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iwlagn: introduce transport layer and implement rx_init
[linux/fpc-iii.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
blob3d971142786e510d4169618577438759b4f5ee39
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-agn.h"
41 #include "iwl-sta.h"
42
43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
44 {
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
47 }
48
49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
50 {
51 status &= TX_STATUS_MSK;
52
53 switch (status) {
54 case TX_STATUS_POSTPONE_DELAY:
55 priv->_agn.reply_tx_stats.pp_delay++;
56 break;
57 case TX_STATUS_POSTPONE_FEW_BYTES:
58 priv->_agn.reply_tx_stats.pp_few_bytes++;
59 break;
60 case TX_STATUS_POSTPONE_BT_PRIO:
61 priv->_agn.reply_tx_stats.pp_bt_prio++;
62 break;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD:
64 priv->_agn.reply_tx_stats.pp_quiet_period++;
65 break;
66 case TX_STATUS_POSTPONE_CALC_TTAK:
67 priv->_agn.reply_tx_stats.pp_calc_ttak++;
68 break;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70 priv->_agn.reply_tx_stats.int_crossed_retry++;
71 break;
72 case TX_STATUS_FAIL_SHORT_LIMIT:
73 priv->_agn.reply_tx_stats.short_limit++;
74 break;
75 case TX_STATUS_FAIL_LONG_LIMIT:
76 priv->_agn.reply_tx_stats.long_limit++;
77 break;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN:
79 priv->_agn.reply_tx_stats.fifo_underrun++;
80 break;
81 case TX_STATUS_FAIL_DRAIN_FLOW:
82 priv->_agn.reply_tx_stats.drain_flow++;
83 break;
84 case TX_STATUS_FAIL_RFKILL_FLUSH:
85 priv->_agn.reply_tx_stats.rfkill_flush++;
86 break;
87 case TX_STATUS_FAIL_LIFE_EXPIRE:
88 priv->_agn.reply_tx_stats.life_expire++;
89 break;
90 case TX_STATUS_FAIL_DEST_PS:
91 priv->_agn.reply_tx_stats.dest_ps++;
92 break;
93 case TX_STATUS_FAIL_HOST_ABORTED:
94 priv->_agn.reply_tx_stats.host_abort++;
95 break;
96 case TX_STATUS_FAIL_BT_RETRY:
97 priv->_agn.reply_tx_stats.bt_retry++;
98 break;
99 case TX_STATUS_FAIL_STA_INVALID:
100 priv->_agn.reply_tx_stats.sta_invalid++;
101 break;
102 case TX_STATUS_FAIL_FRAG_DROPPED:
103 priv->_agn.reply_tx_stats.frag_drop++;
104 break;
105 case TX_STATUS_FAIL_TID_DISABLE:
106 priv->_agn.reply_tx_stats.tid_disable++;
107 break;
108 case TX_STATUS_FAIL_FIFO_FLUSHED:
109 priv->_agn.reply_tx_stats.fifo_flush++;
110 break;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112 priv->_agn.reply_tx_stats.insuff_cf_poll++;
113 break;
114 case TX_STATUS_FAIL_PASSIVE_NO_RX:
115 priv->_agn.reply_tx_stats.fail_hw_drop++;
116 break;
117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
118 priv->_agn.reply_tx_stats.sta_color_mismatch++;
119 break;
120 default:
121 priv->_agn.reply_tx_stats.unknown++;
122 break;
123 }
124 }
125
126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
127 {
128 status &= AGG_TX_STATUS_MSK;
129
130 switch (status) {
131 case AGG_TX_STATE_UNDERRUN_MSK:
132 priv->_agn.reply_agg_tx_stats.underrun++;
133 break;
134 case AGG_TX_STATE_BT_PRIO_MSK:
135 priv->_agn.reply_agg_tx_stats.bt_prio++;
136 break;
137 case AGG_TX_STATE_FEW_BYTES_MSK:
138 priv->_agn.reply_agg_tx_stats.few_bytes++;
139 break;
140 case AGG_TX_STATE_ABORT_MSK:
141 priv->_agn.reply_agg_tx_stats.abort++;
142 break;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK:
144 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
145 break;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
147 priv->_agn.reply_agg_tx_stats.last_sent_try++;
148 break;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
150 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
151 break;
152 case AGG_TX_STATE_SCD_QUERY_MSK:
153 priv->_agn.reply_agg_tx_stats.scd_query++;
154 break;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
156 priv->_agn.reply_agg_tx_stats.bad_crc32++;
157 break;
158 case AGG_TX_STATE_RESPONSE_MSK:
159 priv->_agn.reply_agg_tx_stats.response++;
160 break;
161 case AGG_TX_STATE_DUMP_TX_MSK:
162 priv->_agn.reply_agg_tx_stats.dump_tx++;
163 break;
164 case AGG_TX_STATE_DELAY_TX_MSK:
165 priv->_agn.reply_agg_tx_stats.delay_tx++;
166 break;
167 default:
168 priv->_agn.reply_agg_tx_stats.unknown++;
169 break;
170 }
171 }
172
173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
174 struct ieee80211_tx_info *info,
175 struct iwl_rxon_context *ctx,
176 struct iwlagn_tx_resp *tx_resp,
177 int txq_id, bool is_agg)
178 {
179 u16 status = le16_to_cpu(tx_resp->status.status);
180
181 info->status.rates[0].count = tx_resp->failure_frame + 1;
182 if (is_agg)
183 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
184 info->flags |= iwl_tx_status_to_mac80211(status);
185 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
186 info);
187 if (!iwl_is_tx_success(status))
188 iwlagn_count_tx_err_status(priv, status);
189
190 if (status == TX_STATUS_FAIL_PASSIVE_NO_RX &&
191 iwl_is_associated_ctx(ctx) && ctx->vif &&
192 ctx->vif->type == NL80211_IFTYPE_STATION) {
193 ctx->last_tx_rejected = true;
194 iwl_stop_queue(priv, &priv->txq[txq_id]);
195 }
196
197 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
198 "0x%x retries %d\n",
199 txq_id,
200 iwl_get_tx_fail_reason(status), status,
201 le32_to_cpu(tx_resp->rate_n_flags),
202 tx_resp->failure_frame);
203 }
204
205 #ifdef CONFIG_IWLWIFI_DEBUG
206 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
207
208 const char *iwl_get_agg_tx_fail_reason(u16 status)
209 {
210 status &= AGG_TX_STATUS_MSK;
211 switch (status) {
212 case AGG_TX_STATE_TRANSMITTED:
213 return "SUCCESS";
214 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
215 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
216 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
217 AGG_TX_STATE_FAIL(ABORT_MSK);
218 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
219 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
220 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
221 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
222 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
223 AGG_TX_STATE_FAIL(RESPONSE_MSK);
224 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
225 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
226 }
227
228 return "UNKNOWN";
229 }
230 #endif /* CONFIG_IWLWIFI_DEBUG */
231
232 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
233 struct iwl_ht_agg *agg,
234 struct iwlagn_tx_resp *tx_resp,
235 int txq_id, u16 start_idx)
236 {
237 u16 status;
238 struct agg_tx_status *frame_status = &tx_resp->status;
239 struct ieee80211_hdr *hdr = NULL;
240 int i, sh, idx;
241 u16 seq;
242
243 if (agg->wait_for_ba)
244 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
245
246 agg->frame_count = tx_resp->frame_count;
247 agg->start_idx = start_idx;
248 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
249 agg->bitmap = 0;
250
251 /* # frames attempted by Tx command */
252 if (agg->frame_count == 1) {
253 struct iwl_tx_info *txb;
254
255 /* Only one frame was attempted; no block-ack will arrive */
256 idx = start_idx;
257
258 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
259 agg->frame_count, agg->start_idx, idx);
260 txb = &priv->txq[txq_id].txb[idx];
261 iwlagn_set_tx_status(priv, IEEE80211_SKB_CB(txb->skb),
262 txb->ctx, tx_resp, txq_id, true);
263 agg->wait_for_ba = 0;
264 } else {
265 /* Two or more frames were attempted; expect block-ack */
266 u64 bitmap = 0;
267
268 /*
269 * Start is the lowest frame sent. It may not be the first
270 * frame in the batch; we figure this out dynamically during
271 * the following loop.
272 */
273 int start = agg->start_idx;
274
275 /* Construct bit-map of pending frames within Tx window */
276 for (i = 0; i < agg->frame_count; i++) {
277 u16 sc;
278 status = le16_to_cpu(frame_status[i].status);
279 seq = le16_to_cpu(frame_status[i].sequence);
280 idx = SEQ_TO_INDEX(seq);
281 txq_id = SEQ_TO_QUEUE(seq);
282
283 if (status & AGG_TX_STATUS_MSK)
284 iwlagn_count_agg_tx_err_status(priv, status);
285
286 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
287 AGG_TX_STATE_ABORT_MSK))
288 continue;
289
290 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
291 agg->frame_count, txq_id, idx);
292 IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
293 "try-count (0x%08x)\n",
294 iwl_get_agg_tx_fail_reason(status),
295 status & AGG_TX_STATUS_MSK,
296 status & AGG_TX_TRY_MSK);
297
298 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
299 if (!hdr) {
300 IWL_ERR(priv,
301 "BUG_ON idx doesn't point to valid skb"
302 " idx=%d, txq_id=%d\n", idx, txq_id);
303 return -1;
304 }
305
306 sc = le16_to_cpu(hdr->seq_ctrl);
307 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
308 IWL_ERR(priv,
309 "BUG_ON idx doesn't match seq control"
310 " idx=%d, seq_idx=%d, seq=%d\n",
311 idx, SEQ_TO_SN(sc),
312 hdr->seq_ctrl);
313 return -1;
314 }
315
316 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
317 i, idx, SEQ_TO_SN(sc));
318
319 /*
320 * sh -> how many frames ahead of the starting frame is
321 * the current one?
322 *
323 * Note that all frames sent in the batch must be in a
324 * 64-frame window, so this number should be in [0,63].
325 * If outside of this window, then we've found a new
326 * "first" frame in the batch and need to change start.
327 */
328 sh = idx - start;
329
330 /*
331 * If >= 64, out of window. start must be at the front
332 * of the circular buffer, idx must be near the end of
333 * the buffer, and idx is the new "first" frame. Shift
334 * the indices around.
335 */
336 if (sh >= 64) {
337 /* Shift bitmap by start - idx, wrapped */
338 sh = 0x100 - idx + start;
339 bitmap = bitmap << sh;
340 /* Now idx is the new start so sh = 0 */
341 sh = 0;
342 start = idx;
343 /*
344 * If <= -64 then wraps the 256-pkt circular buffer
345 * (e.g., start = 255 and idx = 0, sh should be 1)
346 */
347 } else if (sh <= -64) {
348 sh = 0x100 - start + idx;
349 /*
350 * If < 0 but > -64, out of window. idx is before start
351 * but not wrapped. Shift the indices around.
352 */
353 } else if (sh < 0) {
354 /* Shift by how far start is ahead of idx */
355 sh = start - idx;
356 bitmap = bitmap << sh;
357 /* Now idx is the new start so sh = 0 */
358 start = idx;
359 sh = 0;
360 }
361 /* Sequence number start + sh was sent in this batch */
362 bitmap |= 1ULL << sh;
363 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
364 start, (unsigned long long)bitmap);
365 }
366
367 /*
368 * Store the bitmap and possibly the new start, if we wrapped
369 * the buffer above
370 */
371 agg->bitmap = bitmap;
372 agg->start_idx = start;
373 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
374 agg->frame_count, agg->start_idx,
375 (unsigned long long)agg->bitmap);
376
377 if (bitmap)
378 agg->wait_for_ba = 1;
379 }
380 return 0;
381 }
382
383 void iwl_check_abort_status(struct iwl_priv *priv,
384 u8 frame_count, u32 status)
385 {
386 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
387 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
388 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
389 queue_work(priv->workqueue, &priv->tx_flush);
390 }
391 }
392
393 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
394 struct iwl_rx_mem_buffer *rxb)
395 {
396 struct iwl_rx_packet *pkt = rxb_addr(rxb);
397 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
398 int txq_id = SEQ_TO_QUEUE(sequence);
399 int index = SEQ_TO_INDEX(sequence);
400 struct iwl_tx_queue *txq = &priv->txq[txq_id];
401 struct ieee80211_tx_info *info;
402 struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
403 struct iwl_tx_info *txb;
404 u32 status = le16_to_cpu(tx_resp->status.status);
405 int tid;
406 int sta_id;
407 int freed;
408 unsigned long flags;
409
410 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
411 IWL_ERR(priv, "%s: Read index for DMA queue txq_id (%d) "
412 "index %d is out of range [0-%d] %d %d\n", __func__,
413 txq_id, index, txq->q.n_bd, txq->q.write_ptr,
414 txq->q.read_ptr);
415 return;
416 }
417
418 txq->time_stamp = jiffies;
419 txb = &txq->txb[txq->q.read_ptr];
420 info = IEEE80211_SKB_CB(txb->skb);
421 memset(&info->status, 0, sizeof(info->status));
422
423 tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
424 IWLAGN_TX_RES_TID_POS;
425 sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
426 IWLAGN_TX_RES_RA_POS;
427
428 spin_lock_irqsave(&priv->sta_lock, flags);
429 if (txq->sched_retry) {
430 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
431 struct iwl_ht_agg *agg;
432
433 agg = &priv->stations[sta_id].tid[tid].agg;
434 /*
435 * If the BT kill count is non-zero, we'll get this
436 * notification again.
437 */
438 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
439 priv->cfg->bt_params &&
440 priv->cfg->bt_params->advanced_bt_coexist) {
441 IWL_DEBUG_COEX(priv, "receive reply tx with bt_kill\n");
442 }
443 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
444
445 /* check if BAR is needed */
446 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
447 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
448
449 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
450 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
451 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
452 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
453 scd_ssn , index, txq_id, txq->swq_id);
454
455 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
456 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
457
458 if (priv->mac80211_registered &&
459 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
460 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
461 iwl_wake_queue(priv, txq);
462 }
463 } else {
464 iwlagn_set_tx_status(priv, info, txb->ctx, tx_resp,
465 txq_id, false);
466 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
467 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
468
469 if (priv->mac80211_registered &&
470 iwl_queue_space(&txq->q) > txq->q.low_mark &&
471 status != TX_STATUS_FAIL_PASSIVE_NO_RX)
472 iwl_wake_queue(priv, txq);
473 }
474
475 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
476
477 iwl_check_abort_status(priv, tx_resp->frame_count, status);
478 spin_unlock_irqrestore(&priv->sta_lock, flags);
479 }
480
481 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
482 {
483 /* init calibration handlers */
484 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
485 iwlagn_rx_calib_result;
486 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
487
488 /* set up notification wait support */
489 spin_lock_init(&priv->_agn.notif_wait_lock);
490 INIT_LIST_HEAD(&priv->_agn.notif_waits);
491 init_waitqueue_head(&priv->_agn.notif_waitq);
492 }
493
494 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
495 {
496 /*
497 * nothing need to be done here anymore
498 * still keep for future use if needed
499 */
500 }
501
502 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
503 {
504 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
505 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
506 }
507
508 int iwlagn_send_tx_power(struct iwl_priv *priv)
509 {
510 struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
511 u8 tx_ant_cfg_cmd;
512
513 if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
514 "TX Power requested while scanning!\n"))
515 return -EAGAIN;
516
517 /* half dBm need to multiply */
518 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
519
520 if (priv->tx_power_lmt_in_half_dbm &&
521 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
522 /*
523 * For the newer devices which using enhanced/extend tx power
524 * table in EEPROM, the format is in half dBm. driver need to
525 * convert to dBm format before report to mac80211.
526 * By doing so, there is a possibility of 1/2 dBm resolution
527 * lost. driver will perform "round-up" operation before
528 * reporting, but it will cause 1/2 dBm tx power over the
529 * regulatory limit. Perform the checking here, if the
530 * "tx_power_user_lmt" is higher than EEPROM value (in
531 * half-dBm format), lower the tx power based on EEPROM
532 */
533 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
534 }
535 tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
536 tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
537
538 if (IWL_UCODE_API(priv->ucode_ver) == 1)
539 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
540 else
541 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
542
543 return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
544 &tx_power_cmd);
545 }
546
547 void iwlagn_temperature(struct iwl_priv *priv)
548 {
549 /* store temperature from correct statistics (in Celsius) */
550 priv->temperature = le32_to_cpu(priv->statistics.common.temperature);
551 iwl_tt_handler(priv);
552 }
553
554 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
555 {
556 struct iwl_eeprom_calib_hdr {
557 u8 version;
558 u8 pa_type;
559 u16 voltage;
560 } *hdr;
561
562 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
563 EEPROM_CALIB_ALL);
564 return hdr->version;
565
566 }
567
568 /*
569 * EEPROM
570 */
571 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
572 {
573 u16 offset = 0;
574
575 if ((address & INDIRECT_ADDRESS) == 0)
576 return address;
577
578 switch (address & INDIRECT_TYPE_MSK) {
579 case INDIRECT_HOST:
580 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
581 break;
582 case INDIRECT_GENERAL:
583 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
584 break;
585 case INDIRECT_REGULATORY:
586 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
587 break;
588 case INDIRECT_TXP_LIMIT:
589 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
590 break;
591 case INDIRECT_TXP_LIMIT_SIZE:
592 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
593 break;
594 case INDIRECT_CALIBRATION:
595 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
596 break;
597 case INDIRECT_PROCESS_ADJST:
598 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
599 break;
600 case INDIRECT_OTHERS:
601 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
602 break;
603 default:
604 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
605 address & INDIRECT_TYPE_MSK);
606 break;
607 }
608
609 /* translate the offset from words to byte */
610 return (address & ADDRESS_MSK) + (offset << 1);
611 }
612
613 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
614 size_t offset)
615 {
616 u32 address = eeprom_indirect_address(priv, offset);
617 BUG_ON(address >= priv->cfg->base_params->eeprom_size);
618 return &priv->eeprom[address];
619 }
620
621 struct iwl_mod_params iwlagn_mod_params = {
622 .amsdu_size_8K = 1,
623 .restart_fw = 1,
624 .plcp_check = true,
625 .bt_coex_active = true,
626 .no_sleep_autoadjust = true,
627 .power_level = IWL_POWER_INDEX_1,
628 /* the rest are 0 by default */
629 };
630
631 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
632 {
633 u32 rb_size;
634 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
635 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
636
637 rb_timeout = RX_RB_TIMEOUT;
638
639 if (iwlagn_mod_params.amsdu_size_8K)
640 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
641 else
642 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
643
644 /* Stop Rx DMA */
645 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
646
647 /* Reset driver's Rx queue write index */
648 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
649
650 /* Tell device where to find RBD circular buffer in DRAM */
651 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
652 (u32)(rxq->bd_dma >> 8));
653
654 /* Tell device where in DRAM to update its Rx status */
655 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
656 rxq->rb_stts_dma >> 4);
657
658 /* Enable Rx DMA
659 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
660 * the credit mechanism in 5000 HW RX FIFO
661 * Direct rx interrupts to hosts
662 * Rx buffer size 4 or 8k
663 * RB timeout 0x10
664 * 256 RBDs
665 */
666 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
667 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
668 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
669 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
670 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
671 rb_size|
672 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
673 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
674
675 /* Set interrupt coalescing timer to default (2048 usecs) */
676 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
677
678 return 0;
679 }
680
681 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
682 {
683 /*
684 * (for documentation purposes)
685 * to set power to V_AUX, do:
686
687 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
688 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
689 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
690 ~APMG_PS_CTRL_MSK_PWR_SRC);
691 */
692
693 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
694 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
695 ~APMG_PS_CTRL_MSK_PWR_SRC);
696 }
697
698 int iwlagn_hw_nic_init(struct iwl_priv *priv)
699 {
700 unsigned long flags;
701 struct iwl_rx_queue *rxq = &priv->rxq;
702 int ret;
703
704 /* nic_init */
705 spin_lock_irqsave(&priv->lock, flags);
706 priv->cfg->ops->lib->apm_ops.init(priv);
707
708 /* Set interrupt coalescing calibration timer to default (512 usecs) */
709 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
710
711 spin_unlock_irqrestore(&priv->lock, flags);
712
713 iwlagn_set_pwr_vmain(priv);
714
715 priv->cfg->ops->lib->apm_ops.config(priv);
716
717 /* Allocate the RX queue, or reset if it is already allocated */
718 priv->trans.ops->rx_init(priv);
719
720 iwlagn_rx_replenish(priv);
721
722 iwlagn_rx_init(priv, rxq);
723
724 spin_lock_irqsave(&priv->lock, flags);
725
726 rxq->need_update = 1;
727 iwl_rx_queue_update_write_ptr(priv, rxq);
728
729 spin_unlock_irqrestore(&priv->lock, flags);
730
731 /* Allocate or reset and init all Tx and Command queues */
732 if (!priv->txq) {
733 ret = iwlagn_txq_ctx_alloc(priv);
734 if (ret)
735 return ret;
736 } else
737 iwlagn_txq_ctx_reset(priv);
738
739 if (priv->cfg->base_params->shadow_reg_enable) {
740 /* enable shadow regs in HW */
741 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
742 0x800FFFFF);
743 }
744
745 set_bit(STATUS_INIT, &priv->status);
746
747 return 0;
748 }
749
750 /**
751 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
752 */
753 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
754 dma_addr_t dma_addr)
755 {
756 return cpu_to_le32((u32)(dma_addr >> 8));
757 }
758
759 /**
760 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
761 *
762 * If there are slots in the RX queue that need to be restocked,
763 * and we have free pre-allocated buffers, fill the ranks as much
764 * as we can, pulling from rx_free.
765 *
766 * This moves the 'write' index forward to catch up with 'processed', and
767 * also updates the memory address in the firmware to reference the new
768 * target buffer.
769 */
770 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
771 {
772 struct iwl_rx_queue *rxq = &priv->rxq;
773 struct list_head *element;
774 struct iwl_rx_mem_buffer *rxb;
775 unsigned long flags;
776
777 spin_lock_irqsave(&rxq->lock, flags);
778 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
779 /* The overwritten rxb must be a used one */
780 rxb = rxq->queue[rxq->write];
781 BUG_ON(rxb && rxb->page);
782
783 /* Get next free Rx buffer, remove from free list */
784 element = rxq->rx_free.next;
785 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
786 list_del(element);
787
788 /* Point to Rx buffer via next RBD in circular buffer */
789 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
790 rxb->page_dma);
791 rxq->queue[rxq->write] = rxb;
792 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
793 rxq->free_count--;
794 }
795 spin_unlock_irqrestore(&rxq->lock, flags);
796 /* If the pre-allocated buffer pool is dropping low, schedule to
797 * refill it */
798 if (rxq->free_count <= RX_LOW_WATERMARK)
799 queue_work(priv->workqueue, &priv->rx_replenish);
800
801
802 /* If we've added more space for the firmware to place data, tell it.
803 * Increment device's write pointer in multiples of 8. */
804 if (rxq->write_actual != (rxq->write & ~0x7)) {
805 spin_lock_irqsave(&rxq->lock, flags);
806 rxq->need_update = 1;
807 spin_unlock_irqrestore(&rxq->lock, flags);
808 iwl_rx_queue_update_write_ptr(priv, rxq);
809 }
810 }
811
812 /**
813 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
814 *
815 * When moving to rx_free an SKB is allocated for the slot.
816 *
817 * Also restock the Rx queue via iwl_rx_queue_restock.
818 * This is called as a scheduled work item (except for during initialization)
819 */
820 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
821 {
822 struct iwl_rx_queue *rxq = &priv->rxq;
823 struct list_head *element;
824 struct iwl_rx_mem_buffer *rxb;
825 struct page *page;
826 unsigned long flags;
827 gfp_t gfp_mask = priority;
828
829 while (1) {
830 spin_lock_irqsave(&rxq->lock, flags);
831 if (list_empty(&rxq->rx_used)) {
832 spin_unlock_irqrestore(&rxq->lock, flags);
833 return;
834 }
835 spin_unlock_irqrestore(&rxq->lock, flags);
836
837 if (rxq->free_count > RX_LOW_WATERMARK)
838 gfp_mask |= __GFP_NOWARN;
839
840 if (priv->hw_params.rx_page_order > 0)
841 gfp_mask |= __GFP_COMP;
842
843 /* Alloc a new receive buffer */
844 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
845 if (!page) {
846 if (net_ratelimit())
847 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
848 "order: %d\n",
849 priv->hw_params.rx_page_order);
850
851 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
852 net_ratelimit())
853 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
854 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
855 rxq->free_count);
856 /* We don't reschedule replenish work here -- we will
857 * call the restock method and if it still needs
858 * more buffers it will schedule replenish */
859 return;
860 }
861
862 spin_lock_irqsave(&rxq->lock, flags);
863
864 if (list_empty(&rxq->rx_used)) {
865 spin_unlock_irqrestore(&rxq->lock, flags);
866 __free_pages(page, priv->hw_params.rx_page_order);
867 return;
868 }
869 element = rxq->rx_used.next;
870 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
871 list_del(element);
872
873 spin_unlock_irqrestore(&rxq->lock, flags);
874
875 BUG_ON(rxb->page);
876 rxb->page = page;
877 /* Get physical address of the RB */
878 rxb->page_dma = dma_map_page(priv->bus.dev, page, 0,
879 PAGE_SIZE << priv->hw_params.rx_page_order,
880 DMA_FROM_DEVICE);
881 /* dma address must be no more than 36 bits */
882 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
883 /* and also 256 byte aligned! */
884 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
885
886 spin_lock_irqsave(&rxq->lock, flags);
887
888 list_add_tail(&rxb->list, &rxq->rx_free);
889 rxq->free_count++;
890
891 spin_unlock_irqrestore(&rxq->lock, flags);
892 }
893 }
894
895 void iwlagn_rx_replenish(struct iwl_priv *priv)
896 {
897 unsigned long flags;
898
899 iwlagn_rx_allocate(priv, GFP_KERNEL);
900
901 spin_lock_irqsave(&priv->lock, flags);
902 iwlagn_rx_queue_restock(priv);
903 spin_unlock_irqrestore(&priv->lock, flags);
904 }
905
906 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
907 {
908 iwlagn_rx_allocate(priv, GFP_ATOMIC);
909
910 iwlagn_rx_queue_restock(priv);
911 }
912
913 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
914 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
915 * This free routine walks the list of POOL entries and if SKB is set to
916 * non NULL it is unmapped and freed
917 */
918 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
919 {
920 int i;
921 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
922 if (rxq->pool[i].page != NULL) {
923 dma_unmap_page(priv->bus.dev, rxq->pool[i].page_dma,
924 PAGE_SIZE << priv->hw_params.rx_page_order,
925 DMA_FROM_DEVICE);
926 __iwl_free_pages(priv, rxq->pool[i].page);
927 rxq->pool[i].page = NULL;
928 }
929 }
930
931 dma_free_coherent(priv->bus.dev, 4 * RX_QUEUE_SIZE,
932 rxq->bd, rxq->bd_dma);
933 dma_free_coherent(priv->bus.dev,
934 sizeof(struct iwl_rb_status),
935 rxq->rb_stts, rxq->rb_stts_dma);
936 rxq->bd = NULL;
937 rxq->rb_stts = NULL;
938 }
939
940 int iwlagn_rxq_stop(struct iwl_priv *priv)
941 {
942
943 /* stop Rx DMA */
944 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
945 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
946 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
947
948 return 0;
949 }
950
951 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
952 {
953 int idx = 0;
954 int band_offset = 0;
955
956 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
957 if (rate_n_flags & RATE_MCS_HT_MSK) {
958 idx = (rate_n_flags & 0xff);
959 return idx;
960 /* Legacy rate format, search for match in table */
961 } else {
962 if (band == IEEE80211_BAND_5GHZ)
963 band_offset = IWL_FIRST_OFDM_RATE;
964 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
965 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
966 return idx - band_offset;
967 }
968
969 return -1;
970 }
971
972 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
973 struct ieee80211_vif *vif,
974 enum ieee80211_band band,
975 struct iwl_scan_channel *scan_ch)
976 {
977 const struct ieee80211_supported_band *sband;
978 u16 passive_dwell = 0;
979 u16 active_dwell = 0;
980 int added = 0;
981 u16 channel = 0;
982
983 sband = iwl_get_hw_mode(priv, band);
984 if (!sband) {
985 IWL_ERR(priv, "invalid band\n");
986 return added;
987 }
988
989 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
990 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
991
992 if (passive_dwell <= active_dwell)
993 passive_dwell = active_dwell + 1;
994
995 channel = iwl_get_single_channel_number(priv, band);
996 if (channel) {
997 scan_ch->channel = cpu_to_le16(channel);
998 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
999 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1000 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1001 /* Set txpower levels to defaults */
1002 scan_ch->dsp_atten = 110;
1003 if (band == IEEE80211_BAND_5GHZ)
1004 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1005 else
1006 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1007 added++;
1008 } else
1009 IWL_ERR(priv, "no valid channel found\n");
1010 return added;
1011 }
1012
1013 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1014 struct ieee80211_vif *vif,
1015 enum ieee80211_band band,
1016 u8 is_active, u8 n_probes,
1017 struct iwl_scan_channel *scan_ch)
1018 {
1019 struct ieee80211_channel *chan;
1020 const struct ieee80211_supported_band *sband;
1021 const struct iwl_channel_info *ch_info;
1022 u16 passive_dwell = 0;
1023 u16 active_dwell = 0;
1024 int added, i;
1025 u16 channel;
1026
1027 sband = iwl_get_hw_mode(priv, band);
1028 if (!sband)
1029 return 0;
1030
1031 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1032 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1033
1034 if (passive_dwell <= active_dwell)
1035 passive_dwell = active_dwell + 1;
1036
1037 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1038 chan = priv->scan_request->channels[i];
1039
1040 if (chan->band != band)
1041 continue;
1042
1043 channel = chan->hw_value;
1044 scan_ch->channel = cpu_to_le16(channel);
1045
1046 ch_info = iwl_get_channel_info(priv, band, channel);
1047 if (!is_channel_valid(ch_info)) {
1048 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1049 channel);
1050 continue;
1051 }
1052
1053 if (!is_active || is_channel_passive(ch_info) ||
1054 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1055 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1056 else
1057 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1058
1059 if (n_probes)
1060 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1061
1062 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1063 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1064
1065 /* Set txpower levels to defaults */
1066 scan_ch->dsp_atten = 110;
1067
1068 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1069 * power level:
1070 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1071 */
1072 if (band == IEEE80211_BAND_5GHZ)
1073 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1074 else
1075 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1076
1077 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1078 channel, le32_to_cpu(scan_ch->type),
1079 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1080 "ACTIVE" : "PASSIVE",
1081 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1082 active_dwell : passive_dwell);
1083
1084 scan_ch++;
1085 added++;
1086 }
1087
1088 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1089 return added;
1090 }
1091
1092 static int iwl_fill_offch_tx(struct iwl_priv *priv, void *data, size_t maxlen)
1093 {
1094 struct sk_buff *skb = priv->_agn.offchan_tx_skb;
1095
1096 if (skb->len < maxlen)
1097 maxlen = skb->len;
1098
1099 memcpy(data, skb->data, maxlen);
1100
1101 return maxlen;
1102 }
1103
1104 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1105 {
1106 struct iwl_host_cmd cmd = {
1107 .id = REPLY_SCAN_CMD,
1108 .len = { sizeof(struct iwl_scan_cmd), },
1109 };
1110 struct iwl_scan_cmd *scan;
1111 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1112 u32 rate_flags = 0;
1113 u16 cmd_len;
1114 u16 rx_chain = 0;
1115 enum ieee80211_band band;
1116 u8 n_probes = 0;
1117 u8 rx_ant = priv->hw_params.valid_rx_ant;
1118 u8 rate;
1119 bool is_active = false;
1120 int chan_mod;
1121 u8 active_chains;
1122 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1123 int ret;
1124
1125 lockdep_assert_held(&priv->mutex);
1126
1127 if (vif)
1128 ctx = iwl_rxon_ctx_from_vif(vif);
1129
1130 if (!priv->scan_cmd) {
1131 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1132 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1133 if (!priv->scan_cmd) {
1134 IWL_DEBUG_SCAN(priv,
1135 "fail to allocate memory for scan\n");
1136 return -ENOMEM;
1137 }
1138 }
1139 scan = priv->scan_cmd;
1140 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1141
1142 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1143 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1144
1145 if (priv->scan_type != IWL_SCAN_OFFCH_TX &&
1146 iwl_is_any_associated(priv)) {
1147 u16 interval = 0;
1148 u32 extra;
1149 u32 suspend_time = 100;
1150 u32 scan_suspend_time = 100;
1151
1152 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1153 switch (priv->scan_type) {
1154 case IWL_SCAN_OFFCH_TX:
1155 WARN_ON(1);
1156 break;
1157 case IWL_SCAN_RADIO_RESET:
1158 interval = 0;
1159 break;
1160 case IWL_SCAN_NORMAL:
1161 interval = vif->bss_conf.beacon_int;
1162 break;
1163 }
1164
1165 scan->suspend_time = 0;
1166 scan->max_out_time = cpu_to_le32(200 * 1024);
1167 if (!interval)
1168 interval = suspend_time;
1169
1170 extra = (suspend_time / interval) << 22;
1171 scan_suspend_time = (extra |
1172 ((suspend_time % interval) * 1024));
1173 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1174 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1175 scan_suspend_time, interval);
1176 } else if (priv->scan_type == IWL_SCAN_OFFCH_TX) {
1177 scan->suspend_time = 0;
1178 scan->max_out_time =
1179 cpu_to_le32(1024 * priv->_agn.offchan_tx_timeout);
1180 }
1181
1182 switch (priv->scan_type) {
1183 case IWL_SCAN_RADIO_RESET:
1184 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1185 break;
1186 case IWL_SCAN_NORMAL:
1187 if (priv->scan_request->n_ssids) {
1188 int i, p = 0;
1189 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1190 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1191 /* always does wildcard anyway */
1192 if (!priv->scan_request->ssids[i].ssid_len)
1193 continue;
1194 scan->direct_scan[p].id = WLAN_EID_SSID;
1195 scan->direct_scan[p].len =
1196 priv->scan_request->ssids[i].ssid_len;
1197 memcpy(scan->direct_scan[p].ssid,
1198 priv->scan_request->ssids[i].ssid,
1199 priv->scan_request->ssids[i].ssid_len);
1200 n_probes++;
1201 p++;
1202 }
1203 is_active = true;
1204 } else
1205 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1206 break;
1207 case IWL_SCAN_OFFCH_TX:
1208 IWL_DEBUG_SCAN(priv, "Start offchannel TX scan.\n");
1209 break;
1210 }
1211
1212 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1213 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1214 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1215
1216 switch (priv->scan_band) {
1217 case IEEE80211_BAND_2GHZ:
1218 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1219 chan_mod = le32_to_cpu(
1220 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1221 RXON_FLG_CHANNEL_MODE_MSK)
1222 >> RXON_FLG_CHANNEL_MODE_POS;
1223 if (chan_mod == CHANNEL_MODE_PURE_40) {
1224 rate = IWL_RATE_6M_PLCP;
1225 } else {
1226 rate = IWL_RATE_1M_PLCP;
1227 rate_flags = RATE_MCS_CCK_MSK;
1228 }
1229 /*
1230 * Internal scans are passive, so we can indiscriminately set
1231 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1232 */
1233 if (priv->cfg->bt_params &&
1234 priv->cfg->bt_params->advanced_bt_coexist)
1235 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1236 break;
1237 case IEEE80211_BAND_5GHZ:
1238 rate = IWL_RATE_6M_PLCP;
1239 break;
1240 default:
1241 IWL_WARN(priv, "Invalid scan band\n");
1242 return -EIO;
1243 }
1244
1245 /*
1246 * If active scanning is requested but a certain channel is
1247 * marked passive, we can do active scanning if we detect
1248 * transmissions.
1249 *
1250 * There is an issue with some firmware versions that triggers
1251 * a sysassert on a "good CRC threshold" of zero (== disabled),
1252 * on a radar channel even though this means that we should NOT
1253 * send probes.
1254 *
1255 * The "good CRC threshold" is the number of frames that we
1256 * need to receive during our dwell time on a channel before
1257 * sending out probes -- setting this to a huge value will
1258 * mean we never reach it, but at the same time work around
1259 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1260 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1261 *
1262 * This was fixed in later versions along with some other
1263 * scan changes, and the threshold behaves as a flag in those
1264 * versions.
1265 */
1266 if (priv->new_scan_threshold_behaviour)
1267 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1268 IWL_GOOD_CRC_TH_DISABLED;
1269 else
1270 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1271 IWL_GOOD_CRC_TH_NEVER;
1272
1273 band = priv->scan_band;
1274
1275 if (priv->cfg->scan_rx_antennas[band])
1276 rx_ant = priv->cfg->scan_rx_antennas[band];
1277
1278 if (band == IEEE80211_BAND_2GHZ &&
1279 priv->cfg->bt_params &&
1280 priv->cfg->bt_params->advanced_bt_coexist) {
1281 /* transmit 2.4 GHz probes only on first antenna */
1282 scan_tx_antennas = first_antenna(scan_tx_antennas);
1283 }
1284
1285 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1286 scan_tx_antennas);
1287 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1288 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1289
1290 /* In power save mode use one chain, otherwise use all chains */
1291 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1292 /* rx_ant has been set to all valid chains previously */
1293 active_chains = rx_ant &
1294 ((u8)(priv->chain_noise_data.active_chains));
1295 if (!active_chains)
1296 active_chains = rx_ant;
1297
1298 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1299 priv->chain_noise_data.active_chains);
1300
1301 rx_ant = first_antenna(active_chains);
1302 }
1303 if (priv->cfg->bt_params &&
1304 priv->cfg->bt_params->advanced_bt_coexist &&
1305 priv->bt_full_concurrent) {
1306 /* operated as 1x1 in full concurrency mode */
1307 rx_ant = first_antenna(rx_ant);
1308 }
1309
1310 /* MIMO is not used here, but value is required */
1311 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1312 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1313 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1314 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1315 scan->rx_chain = cpu_to_le16(rx_chain);
1316 switch (priv->scan_type) {
1317 case IWL_SCAN_NORMAL:
1318 cmd_len = iwl_fill_probe_req(priv,
1319 (struct ieee80211_mgmt *)scan->data,
1320 vif->addr,
1321 priv->scan_request->ie,
1322 priv->scan_request->ie_len,
1323 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1324 break;
1325 case IWL_SCAN_RADIO_RESET:
1326 /* use bcast addr, will not be transmitted but must be valid */
1327 cmd_len = iwl_fill_probe_req(priv,
1328 (struct ieee80211_mgmt *)scan->data,
1329 iwl_bcast_addr, NULL, 0,
1330 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1331 break;
1332 case IWL_SCAN_OFFCH_TX:
1333 cmd_len = iwl_fill_offch_tx(priv, scan->data,
1334 IWL_MAX_SCAN_SIZE
1335 - sizeof(*scan)
1336 - sizeof(struct iwl_scan_channel));
1337 scan->scan_flags |= IWL_SCAN_FLAGS_ACTION_FRAME_TX;
1338 break;
1339 default:
1340 BUG();
1341 }
1342 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1343
1344 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1345 RXON_FILTER_BCON_AWARE_MSK);
1346
1347 switch (priv->scan_type) {
1348 case IWL_SCAN_RADIO_RESET:
1349 scan->channel_count =
1350 iwl_get_single_channel_for_scan(priv, vif, band,
1351 (void *)&scan->data[cmd_len]);
1352 break;
1353 case IWL_SCAN_NORMAL:
1354 scan->channel_count =
1355 iwl_get_channels_for_scan(priv, vif, band,
1356 is_active, n_probes,
1357 (void *)&scan->data[cmd_len]);
1358 break;
1359 case IWL_SCAN_OFFCH_TX: {
1360 struct iwl_scan_channel *scan_ch;
1361
1362 scan->channel_count = 1;
1363
1364 scan_ch = (void *)&scan->data[cmd_len];
1365 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1366 scan_ch->channel =
1367 cpu_to_le16(priv->_agn.offchan_tx_chan->hw_value);
1368 scan_ch->active_dwell =
1369 cpu_to_le16(priv->_agn.offchan_tx_timeout);
1370 scan_ch->passive_dwell = 0;
1371
1372 /* Set txpower levels to defaults */
1373 scan_ch->dsp_atten = 110;
1374
1375 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1376 * power level:
1377 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1378 */
1379 if (priv->_agn.offchan_tx_chan->band == IEEE80211_BAND_5GHZ)
1380 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1381 else
1382 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1383 }
1384 break;
1385 }
1386
1387 if (scan->channel_count == 0) {
1388 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1389 return -EIO;
1390 }
1391
1392 cmd.len[0] += le16_to_cpu(scan->tx_cmd.len) +
1393 scan->channel_count * sizeof(struct iwl_scan_channel);
1394 cmd.data[0] = scan;
1395 cmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY;
1396 scan->len = cpu_to_le16(cmd.len[0]);
1397
1398 /* set scan bit here for PAN params */
1399 set_bit(STATUS_SCAN_HW, &priv->status);
1400
1401 if (priv->cfg->ops->hcmd->set_pan_params) {
1402 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1403 if (ret)
1404 return ret;
1405 }
1406
1407 ret = iwl_send_cmd_sync(priv, &cmd);
1408 if (ret) {
1409 clear_bit(STATUS_SCAN_HW, &priv->status);
1410 if (priv->cfg->ops->hcmd->set_pan_params)
1411 priv->cfg->ops->hcmd->set_pan_params(priv);
1412 }
1413
1414 return ret;
1415 }
1416
1417 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1418 struct ieee80211_vif *vif, bool add)
1419 {
1420 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1421
1422 if (add)
1423 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1424 vif->bss_conf.bssid,
1425 &vif_priv->ibss_bssid_sta_id);
1426 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1427 vif->bss_conf.bssid);
1428 }
1429
1430 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1431 int sta_id, int tid, int freed)
1432 {
1433 lockdep_assert_held(&priv->sta_lock);
1434
1435 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1436 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1437 else {
1438 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1439 priv->stations[sta_id].tid[tid].tfds_in_queue,
1440 freed);
1441 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1442 }
1443 }
1444
1445 #define IWL_FLUSH_WAIT_MS 2000
1446
1447 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1448 {
1449 struct iwl_tx_queue *txq;
1450 struct iwl_queue *q;
1451 int cnt;
1452 unsigned long now = jiffies;
1453 int ret = 0;
1454
1455 /* waiting for all the tx frames complete might take a while */
1456 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1457 if (cnt == priv->cmd_queue)
1458 continue;
1459 txq = &priv->txq[cnt];
1460 q = &txq->q;
1461 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1462 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1463 msleep(1);
1464
1465 if (q->read_ptr != q->write_ptr) {
1466 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1467 ret = -ETIMEDOUT;
1468 break;
1469 }
1470 }
1471 return ret;
1472 }
1473
1474 #define IWL_TX_QUEUE_MSK 0xfffff
1475
1476 /**
1477 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1478 *
1479 * pre-requirements:
1480 * 1. acquire mutex before calling
1481 * 2. make sure rf is on and not in exit state
1482 */
1483 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1484 {
1485 struct iwl_txfifo_flush_cmd flush_cmd;
1486 struct iwl_host_cmd cmd = {
1487 .id = REPLY_TXFIFO_FLUSH,
1488 .len = { sizeof(struct iwl_txfifo_flush_cmd), },
1489 .flags = CMD_SYNC,
1490 .data = { &flush_cmd, },
1491 };
1492
1493 might_sleep();
1494
1495 memset(&flush_cmd, 0, sizeof(flush_cmd));
1496 if (flush_control & BIT(IWL_RXON_CTX_BSS))
1497 flush_cmd.fifo_control = IWL_SCD_VO_MSK | IWL_SCD_VI_MSK |
1498 IWL_SCD_BE_MSK | IWL_SCD_BK_MSK |
1499 IWL_SCD_MGMT_MSK;
1500 if ((flush_control & BIT(IWL_RXON_CTX_PAN)) &&
1501 (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)))
1502 flush_cmd.fifo_control |= IWL_PAN_SCD_VO_MSK |
1503 IWL_PAN_SCD_VI_MSK | IWL_PAN_SCD_BE_MSK |
1504 IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK |
1505 IWL_PAN_SCD_MULTICAST_MSK;
1506
1507 if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
1508 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1509
1510 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1511 flush_cmd.fifo_control);
1512 flush_cmd.flush_control = cpu_to_le16(flush_control);
1513
1514 return iwl_send_cmd(priv, &cmd);
1515 }
1516
1517 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1518 {
1519 mutex_lock(&priv->mutex);
1520 ieee80211_stop_queues(priv->hw);
1521 if (iwlagn_txfifo_flush(priv, IWL_DROP_ALL)) {
1522 IWL_ERR(priv, "flush request fail\n");
1523 goto done;
1524 }
1525 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1526 iwlagn_wait_tx_queue_empty(priv);
1527 done:
1528 ieee80211_wake_queues(priv->hw);
1529 mutex_unlock(&priv->mutex);
1530 }
1531
1532 /*
1533 * BT coex
1534 */
1535 /*
1536 * Macros to access the lookup table.
1537 *
1538 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1539 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1540 *
1541 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1542 *
1543 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1544 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1545 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1546 *
1547 * These macros encode that format.
1548 */
1549 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1550 wifi_txrx, wifi_sh_ant_req) \
1551 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1552 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1553
1554 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1555 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1556 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1557 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1558 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1559 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1560 wifi_sh_ant_req))))
1561 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1562 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1563 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1564 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1565 wifi_sh_ant_req))
1566 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1567 wifi_req, wifi_prio, wifi_txrx, \
1568 wifi_sh_ant_req) \
1569 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1570 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1571 wifi_sh_ant_req))
1572
1573 #define LUT_WLAN_KILL_OP(lut, op, val) \
1574 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1575 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1576 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1577 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1578 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1579 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1580 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1581 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1582 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1583 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1584 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1585 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1586 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1587
1588 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1589 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1590 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1591 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1592 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1593 wifi_req, wifi_prio, wifi_txrx, \
1594 wifi_sh_ant_req))))
1595 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1596 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1597 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1598 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1599 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1600 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1601 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1602 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1603
1604 static const __le32 iwlagn_def_3w_lookup[12] = {
1605 cpu_to_le32(0xaaaaaaaa),
1606 cpu_to_le32(0xaaaaaaaa),
1607 cpu_to_le32(0xaeaaaaaa),
1608 cpu_to_le32(0xaaaaaaaa),
1609 cpu_to_le32(0xcc00ff28),
1610 cpu_to_le32(0x0000aaaa),
1611 cpu_to_le32(0xcc00aaaa),
1612 cpu_to_le32(0x0000aaaa),
1613 cpu_to_le32(0xc0004000),
1614 cpu_to_le32(0x00004000),
1615 cpu_to_le32(0xf0005000),
1616 cpu_to_le32(0xf0005000),
1617 };
1618
1619 static const __le32 iwlagn_concurrent_lookup[12] = {
1620 cpu_to_le32(0xaaaaaaaa),
1621 cpu_to_le32(0xaaaaaaaa),
1622 cpu_to_le32(0xaaaaaaaa),
1623 cpu_to_le32(0xaaaaaaaa),
1624 cpu_to_le32(0xaaaaaaaa),
1625 cpu_to_le32(0xaaaaaaaa),
1626 cpu_to_le32(0xaaaaaaaa),
1627 cpu_to_le32(0xaaaaaaaa),
1628 cpu_to_le32(0x00000000),
1629 cpu_to_le32(0x00000000),
1630 cpu_to_le32(0x00000000),
1631 cpu_to_le32(0x00000000),
1632 };
1633
1634 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1635 {
1636 struct iwl_basic_bt_cmd basic = {
1637 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1638 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1639 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1640 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1641 };
1642 struct iwl6000_bt_cmd bt_cmd_6000;
1643 struct iwl2000_bt_cmd bt_cmd_2000;
1644 int ret;
1645
1646 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1647 sizeof(basic.bt3_lookup_table));
1648
1649 if (priv->cfg->bt_params) {
1650 if (priv->cfg->bt_params->bt_session_2) {
1651 bt_cmd_2000.prio_boost = cpu_to_le32(
1652 priv->cfg->bt_params->bt_prio_boost);
1653 bt_cmd_2000.tx_prio_boost = 0;
1654 bt_cmd_2000.rx_prio_boost = 0;
1655 } else {
1656 bt_cmd_6000.prio_boost =
1657 priv->cfg->bt_params->bt_prio_boost;
1658 bt_cmd_6000.tx_prio_boost = 0;
1659 bt_cmd_6000.rx_prio_boost = 0;
1660 }
1661 } else {
1662 IWL_ERR(priv, "failed to construct BT Coex Config\n");
1663 return;
1664 }
1665
1666 basic.kill_ack_mask = priv->kill_ack_mask;
1667 basic.kill_cts_mask = priv->kill_cts_mask;
1668 basic.valid = priv->bt_valid;
1669
1670 /*
1671 * Configure BT coex mode to "no coexistence" when the
1672 * user disabled BT coexistence, we have no interface
1673 * (might be in monitor mode), or the interface is in
1674 * IBSS mode (no proper uCode support for coex then).
1675 */
1676 if (!iwlagn_mod_params.bt_coex_active ||
1677 priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1678 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_DISABLED;
1679 } else {
1680 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1681 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1682 if (priv->cfg->bt_params &&
1683 priv->cfg->bt_params->bt_sco_disable)
1684 basic.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1685
1686 if (priv->bt_ch_announce)
1687 basic.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1688 IWL_DEBUG_COEX(priv, "BT coex flag: 0X%x\n", basic.flags);
1689 }
1690 priv->bt_enable_flag = basic.flags;
1691 if (priv->bt_full_concurrent)
1692 memcpy(basic.bt3_lookup_table, iwlagn_concurrent_lookup,
1693 sizeof(iwlagn_concurrent_lookup));
1694 else
1695 memcpy(basic.bt3_lookup_table, iwlagn_def_3w_lookup,
1696 sizeof(iwlagn_def_3w_lookup));
1697
1698 IWL_DEBUG_COEX(priv, "BT coex %s in %s mode\n",
1699 basic.flags ? "active" : "disabled",
1700 priv->bt_full_concurrent ?
1701 "full concurrency" : "3-wire");
1702
1703 if (priv->cfg->bt_params->bt_session_2) {
1704 memcpy(&bt_cmd_2000.basic, &basic,
1705 sizeof(basic));
1706 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1707 sizeof(bt_cmd_2000), &bt_cmd_2000);
1708 } else {
1709 memcpy(&bt_cmd_6000.basic, &basic,
1710 sizeof(basic));
1711 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1712 sizeof(bt_cmd_6000), &bt_cmd_6000);
1713 }
1714 if (ret)
1715 IWL_ERR(priv, "failed to send BT Coex Config\n");
1716
1717 }
1718
1719 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1720 {
1721 struct iwl_priv *priv =
1722 container_of(work, struct iwl_priv, bt_traffic_change_work);
1723 struct iwl_rxon_context *ctx;
1724 int smps_request = -1;
1725
1726 if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1727 /* bt coex disabled */
1728 return;
1729 }
1730
1731 /*
1732 * Note: bt_traffic_load can be overridden by scan complete and
1733 * coex profile notifications. Ignore that since only bad consequence
1734 * can be not matching debug print with actual state.
1735 */
1736 IWL_DEBUG_COEX(priv, "BT traffic load changes: %d\n",
1737 priv->bt_traffic_load);
1738
1739 switch (priv->bt_traffic_load) {
1740 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1741 if (priv->bt_status)
1742 smps_request = IEEE80211_SMPS_DYNAMIC;
1743 else
1744 smps_request = IEEE80211_SMPS_AUTOMATIC;
1745 break;
1746 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1747 smps_request = IEEE80211_SMPS_DYNAMIC;
1748 break;
1749 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1750 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1751 smps_request = IEEE80211_SMPS_STATIC;
1752 break;
1753 default:
1754 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1755 priv->bt_traffic_load);
1756 break;
1757 }
1758
1759 mutex_lock(&priv->mutex);
1760
1761 /*
1762 * We can not send command to firmware while scanning. When the scan
1763 * complete we will schedule this work again. We do check with mutex
1764 * locked to prevent new scan request to arrive. We do not check
1765 * STATUS_SCANNING to avoid race when queue_work two times from
1766 * different notifications, but quit and not perform any work at all.
1767 */
1768 if (test_bit(STATUS_SCAN_HW, &priv->status))
1769 goto out;
1770
1771 if (priv->cfg->ops->lib->update_chain_flags)
1772 priv->cfg->ops->lib->update_chain_flags(priv);
1773
1774 if (smps_request != -1) {
1775 priv->current_ht_config.smps = smps_request;
1776 for_each_context(priv, ctx) {
1777 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1778 ieee80211_request_smps(ctx->vif, smps_request);
1779 }
1780 }
1781 out:
1782 mutex_unlock(&priv->mutex);
1783 }
1784
1785 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1786 struct iwl_bt_uart_msg *uart_msg)
1787 {
1788 IWL_DEBUG_COEX(priv, "Message Type = 0x%X, SSN = 0x%X, "
1789 "Update Req = 0x%X",
1790 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1791 BT_UART_MSG_FRAME1MSGTYPE_POS,
1792 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1793 BT_UART_MSG_FRAME1SSN_POS,
1794 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1795 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1796
1797 IWL_DEBUG_COEX(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1798 "Chl_SeqN = 0x%X, In band = 0x%X",
1799 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1800 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1801 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1802 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1803 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1804 BT_UART_MSG_FRAME2CHLSEQN_POS,
1805 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1806 BT_UART_MSG_FRAME2INBAND_POS);
1807
1808 IWL_DEBUG_COEX(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1809 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1810 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1811 BT_UART_MSG_FRAME3SCOESCO_POS,
1812 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1813 BT_UART_MSG_FRAME3SNIFF_POS,
1814 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1815 BT_UART_MSG_FRAME3A2DP_POS,
1816 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1817 BT_UART_MSG_FRAME3ACL_POS,
1818 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1819 BT_UART_MSG_FRAME3MASTER_POS,
1820 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1821 BT_UART_MSG_FRAME3OBEX_POS);
1822
1823 IWL_DEBUG_COEX(priv, "Idle duration = 0x%X",
1824 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1825 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1826
1827 IWL_DEBUG_COEX(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1828 "eSCO Retransmissions = 0x%X",
1829 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1830 BT_UART_MSG_FRAME5TXACTIVITY_POS,
1831 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1832 BT_UART_MSG_FRAME5RXACTIVITY_POS,
1833 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1834 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1835
1836 IWL_DEBUG_COEX(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1837 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1838 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1839 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1840 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1841
1842 IWL_DEBUG_COEX(priv, "Sniff Activity = 0x%X, Page = "
1843 "0x%X, Inquiry = 0x%X, Connectable = 0x%X",
1844 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1845 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1846 (BT_UART_MSG_FRAME7PAGE_MSK & uart_msg->frame7) >>
1847 BT_UART_MSG_FRAME7PAGE_POS,
1848 (BT_UART_MSG_FRAME7INQUIRY_MSK & uart_msg->frame7) >>
1849 BT_UART_MSG_FRAME7INQUIRY_POS,
1850 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1851 BT_UART_MSG_FRAME7CONNECTABLE_POS);
1852 }
1853
1854 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
1855 struct iwl_bt_uart_msg *uart_msg)
1856 {
1857 u8 kill_msk;
1858 static const __le32 bt_kill_ack_msg[2] = {
1859 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
1860 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1861 static const __le32 bt_kill_cts_msg[2] = {
1862 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
1863 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1864
1865 kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
1866 ? 1 : 0;
1867 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
1868 priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
1869 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1870 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
1871 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
1872 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
1873
1874 /* schedule to send runtime bt_config */
1875 queue_work(priv->workqueue, &priv->bt_runtime_config);
1876 }
1877 }
1878
1879 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1880 struct iwl_rx_mem_buffer *rxb)
1881 {
1882 unsigned long flags;
1883 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1884 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1885 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1886
1887 if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1888 /* bt coex disabled */
1889 return;
1890 }
1891
1892 IWL_DEBUG_COEX(priv, "BT Coex notification:\n");
1893 IWL_DEBUG_COEX(priv, " status: %d\n", coex->bt_status);
1894 IWL_DEBUG_COEX(priv, " traffic load: %d\n", coex->bt_traffic_load);
1895 IWL_DEBUG_COEX(priv, " CI compliance: %d\n",
1896 coex->bt_ci_compliance);
1897 iwlagn_print_uartmsg(priv, uart_msg);
1898
1899 priv->last_bt_traffic_load = priv->bt_traffic_load;
1900 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1901 if (priv->bt_status != coex->bt_status ||
1902 priv->last_bt_traffic_load != coex->bt_traffic_load) {
1903 if (coex->bt_status) {
1904 /* BT on */
1905 if (!priv->bt_ch_announce)
1906 priv->bt_traffic_load =
1907 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1908 else
1909 priv->bt_traffic_load =
1910 coex->bt_traffic_load;
1911 } else {
1912 /* BT off */
1913 priv->bt_traffic_load =
1914 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
1915 }
1916 priv->bt_status = coex->bt_status;
1917 queue_work(priv->workqueue,
1918 &priv->bt_traffic_change_work);
1919 }
1920 }
1921
1922 iwlagn_set_kill_msk(priv, uart_msg);
1923
1924 /* FIXME: based on notification, adjust the prio_boost */
1925
1926 spin_lock_irqsave(&priv->lock, flags);
1927 priv->bt_ci_compliance = coex->bt_ci_compliance;
1928 spin_unlock_irqrestore(&priv->lock, flags);
1929 }
1930
1931 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
1932 {
1933 iwlagn_rx_handler_setup(priv);
1934 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
1935 iwlagn_bt_coex_profile_notif;
1936 }
1937
1938 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
1939 {
1940 iwlagn_setup_deferred_work(priv);
1941
1942 INIT_WORK(&priv->bt_traffic_change_work,
1943 iwlagn_bt_traffic_change_work);
1944 }
1945
1946 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
1947 {
1948 cancel_work_sync(&priv->bt_traffic_change_work);
1949 }
1950
1951 static bool is_single_rx_stream(struct iwl_priv *priv)
1952 {
1953 return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1954 priv->current_ht_config.single_chain_sufficient;
1955 }
1956
1957 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
1958 #define IWL_NUM_RX_CHAINS_SINGLE 2
1959 #define IWL_NUM_IDLE_CHAINS_DUAL 2
1960 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
1961
1962 /*
1963 * Determine how many receiver/antenna chains to use.
1964 *
1965 * More provides better reception via diversity. Fewer saves power
1966 * at the expense of throughput, but only when not in powersave to
1967 * start with.
1968 *
1969 * MIMO (dual stream) requires at least 2, but works better with 3.
1970 * This does not determine *which* chains to use, just how many.
1971 */
1972 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
1973 {
1974 if (priv->cfg->bt_params &&
1975 priv->cfg->bt_params->advanced_bt_coexist &&
1976 (priv->bt_full_concurrent ||
1977 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
1978 /*
1979 * only use chain 'A' in bt high traffic load or
1980 * full concurrency mode
1981 */
1982 return IWL_NUM_RX_CHAINS_SINGLE;
1983 }
1984 /* # of Rx chains to use when expecting MIMO. */
1985 if (is_single_rx_stream(priv))
1986 return IWL_NUM_RX_CHAINS_SINGLE;
1987 else
1988 return IWL_NUM_RX_CHAINS_MULTIPLE;
1989 }
1990
1991 /*
1992 * When we are in power saving mode, unless device support spatial
1993 * multiplexing power save, use the active count for rx chain count.
1994 */
1995 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
1996 {
1997 /* # Rx chains when idling, depending on SMPS mode */
1998 switch (priv->current_ht_config.smps) {
1999 case IEEE80211_SMPS_STATIC:
2000 case IEEE80211_SMPS_DYNAMIC:
2001 return IWL_NUM_IDLE_CHAINS_SINGLE;
2002 case IEEE80211_SMPS_OFF:
2003 return active_cnt;
2004 default:
2005 WARN(1, "invalid SMPS mode %d",
2006 priv->current_ht_config.smps);
2007 return active_cnt;
2008 }
2009 }
2010
2011 /* up to 4 chains */
2012 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2013 {
2014 u8 res;
2015 res = (chain_bitmap & BIT(0)) >> 0;
2016 res += (chain_bitmap & BIT(1)) >> 1;
2017 res += (chain_bitmap & BIT(2)) >> 2;
2018 res += (chain_bitmap & BIT(3)) >> 3;
2019 return res;
2020 }
2021
2022 /**
2023 * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2024 *
2025 * Selects how many and which Rx receivers/antennas/chains to use.
2026 * This should not be used for scan command ... it puts data in wrong place.
2027 */
2028 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2029 {
2030 bool is_single = is_single_rx_stream(priv);
2031 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2032 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2033 u32 active_chains;
2034 u16 rx_chain;
2035
2036 /* Tell uCode which antennas are actually connected.
2037 * Before first association, we assume all antennas are connected.
2038 * Just after first association, iwl_chain_noise_calibration()
2039 * checks which antennas actually *are* connected. */
2040 if (priv->chain_noise_data.active_chains)
2041 active_chains = priv->chain_noise_data.active_chains;
2042 else
2043 active_chains = priv->hw_params.valid_rx_ant;
2044
2045 if (priv->cfg->bt_params &&
2046 priv->cfg->bt_params->advanced_bt_coexist &&
2047 (priv->bt_full_concurrent ||
2048 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2049 /*
2050 * only use chain 'A' in bt high traffic load or
2051 * full concurrency mode
2052 */
2053 active_chains = first_antenna(active_chains);
2054 }
2055
2056 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2057
2058 /* How many receivers should we use? */
2059 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2060 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2061
2062
2063 /* correct rx chain count according hw settings
2064 * and chain noise calibration
2065 */
2066 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2067 if (valid_rx_cnt < active_rx_cnt)
2068 active_rx_cnt = valid_rx_cnt;
2069
2070 if (valid_rx_cnt < idle_rx_cnt)
2071 idle_rx_cnt = valid_rx_cnt;
2072
2073 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2074 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
2075
2076 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2077
2078 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2079 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2080 else
2081 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2082
2083 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2084 ctx->staging.rx_chain,
2085 active_rx_cnt, idle_rx_cnt);
2086
2087 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2088 active_rx_cnt < idle_rx_cnt);
2089 }
2090
2091 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2092 {
2093 int i;
2094 u8 ind = ant;
2095
2096 if (priv->band == IEEE80211_BAND_2GHZ &&
2097 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2098 return 0;
2099
2100 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2101 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
2102 if (valid & BIT(ind))
2103 return ind;
2104 }
2105 return ant;
2106 }
2107
2108 static const char *get_csr_string(int cmd)
2109 {
2110 switch (cmd) {
2111 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2112 IWL_CMD(CSR_INT_COALESCING);
2113 IWL_CMD(CSR_INT);
2114 IWL_CMD(CSR_INT_MASK);
2115 IWL_CMD(CSR_FH_INT_STATUS);
2116 IWL_CMD(CSR_GPIO_IN);
2117 IWL_CMD(CSR_RESET);
2118 IWL_CMD(CSR_GP_CNTRL);
2119 IWL_CMD(CSR_HW_REV);
2120 IWL_CMD(CSR_EEPROM_REG);
2121 IWL_CMD(CSR_EEPROM_GP);
2122 IWL_CMD(CSR_OTP_GP_REG);
2123 IWL_CMD(CSR_GIO_REG);
2124 IWL_CMD(CSR_GP_UCODE_REG);
2125 IWL_CMD(CSR_GP_DRIVER_REG);
2126 IWL_CMD(CSR_UCODE_DRV_GP1);
2127 IWL_CMD(CSR_UCODE_DRV_GP2);
2128 IWL_CMD(CSR_LED_REG);
2129 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2130 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2131 IWL_CMD(CSR_ANA_PLL_CFG);
2132 IWL_CMD(CSR_HW_REV_WA_REG);
2133 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2134 default:
2135 return "UNKNOWN";
2136 }
2137 }
2138
2139 void iwl_dump_csr(struct iwl_priv *priv)
2140 {
2141 int i;
2142 static const u32 csr_tbl[] = {
2143 CSR_HW_IF_CONFIG_REG,
2144 CSR_INT_COALESCING,
2145 CSR_INT,
2146 CSR_INT_MASK,
2147 CSR_FH_INT_STATUS,
2148 CSR_GPIO_IN,
2149 CSR_RESET,
2150 CSR_GP_CNTRL,
2151 CSR_HW_REV,
2152 CSR_EEPROM_REG,
2153 CSR_EEPROM_GP,
2154 CSR_OTP_GP_REG,
2155 CSR_GIO_REG,
2156 CSR_GP_UCODE_REG,
2157 CSR_GP_DRIVER_REG,
2158 CSR_UCODE_DRV_GP1,
2159 CSR_UCODE_DRV_GP2,
2160 CSR_LED_REG,
2161 CSR_DRAM_INT_TBL_REG,
2162 CSR_GIO_CHICKEN_BITS,
2163 CSR_ANA_PLL_CFG,
2164 CSR_HW_REV_WA_REG,
2165 CSR_DBG_HPET_MEM_REG
2166 };
2167 IWL_ERR(priv, "CSR values:\n");
2168 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2169 "CSR_INT_PERIODIC_REG)\n");
2170 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2171 IWL_ERR(priv, " %25s: 0X%08x\n",
2172 get_csr_string(csr_tbl[i]),
2173 iwl_read32(priv, csr_tbl[i]));
2174 }
2175 }
2176
2177 static const char *get_fh_string(int cmd)
2178 {
2179 switch (cmd) {
2180 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2181 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2182 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2183 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2184 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2185 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2186 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2187 IWL_CMD(FH_TSSR_TX_STATUS_REG);
2188 IWL_CMD(FH_TSSR_TX_ERROR_REG);
2189 default:
2190 return "UNKNOWN";
2191 }
2192 }
2193
2194 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2195 {
2196 int i;
2197 #ifdef CONFIG_IWLWIFI_DEBUG
2198 int pos = 0;
2199 size_t bufsz = 0;
2200 #endif
2201 static const u32 fh_tbl[] = {
2202 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2203 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2204 FH_RSCSR_CHNL0_WPTR,
2205 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2206 FH_MEM_RSSR_SHARED_CTRL_REG,
2207 FH_MEM_RSSR_RX_STATUS_REG,
2208 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2209 FH_TSSR_TX_STATUS_REG,
2210 FH_TSSR_TX_ERROR_REG
2211 };
2212 #ifdef CONFIG_IWLWIFI_DEBUG
2213 if (display) {
2214 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2215 *buf = kmalloc(bufsz, GFP_KERNEL);
2216 if (!*buf)
2217 return -ENOMEM;
2218 pos += scnprintf(*buf + pos, bufsz - pos,
2219 "FH register values:\n");
2220 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2221 pos += scnprintf(*buf + pos, bufsz - pos,
2222 " %34s: 0X%08x\n",
2223 get_fh_string(fh_tbl[i]),
2224 iwl_read_direct32(priv, fh_tbl[i]));
2225 }
2226 return pos;
2227 }
2228 #endif
2229 IWL_ERR(priv, "FH register values:\n");
2230 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2231 IWL_ERR(priv, " %34s: 0X%08x\n",
2232 get_fh_string(fh_tbl[i]),
2233 iwl_read_direct32(priv, fh_tbl[i]));
2234 }
2235 return 0;
2236 }
2237
2238 /* notification wait support */
2239 void iwlagn_init_notification_wait(struct iwl_priv *priv,
2240 struct iwl_notification_wait *wait_entry,
2241 u8 cmd,
2242 void (*fn)(struct iwl_priv *priv,
2243 struct iwl_rx_packet *pkt,
2244 void *data),
2245 void *fn_data)
2246 {
2247 wait_entry->fn = fn;
2248 wait_entry->fn_data = fn_data;
2249 wait_entry->cmd = cmd;
2250 wait_entry->triggered = false;
2251 wait_entry->aborted = false;
2252
2253 spin_lock_bh(&priv->_agn.notif_wait_lock);
2254 list_add(&wait_entry->list, &priv->_agn.notif_waits);
2255 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2256 }
2257
2258 int iwlagn_wait_notification(struct iwl_priv *priv,
2259 struct iwl_notification_wait *wait_entry,
2260 unsigned long timeout)
2261 {
2262 int ret;
2263
2264 ret = wait_event_timeout(priv->_agn.notif_waitq,
2265 wait_entry->triggered || wait_entry->aborted,
2266 timeout);
2267
2268 spin_lock_bh(&priv->_agn.notif_wait_lock);
2269 list_del(&wait_entry->list);
2270 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2271
2272 if (wait_entry->aborted)
2273 return -EIO;
2274
2275 /* return value is always >= 0 */
2276 if (ret <= 0)
2277 return -ETIMEDOUT;
2278 return 0;
2279 }
2280
2281 void iwlagn_remove_notification(struct iwl_priv *priv,
2282 struct iwl_notification_wait *wait_entry)
2283 {
2284 spin_lock_bh(&priv->_agn.notif_wait_lock);
2285 list_del(&wait_entry->list);
2286 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2287 }
2288
2289 int iwlagn_start_device(struct iwl_priv *priv)
2290 {
2291 int ret;
2292
2293 if ((priv->cfg->sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
2294 iwl_prepare_card_hw(priv)) {
2295 IWL_WARN(priv, "Exit HW not ready\n");
2296 return -EIO;
2297 }
2298
2299 /* If platform's RF_KILL switch is NOT set to KILL */
2300 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2301 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2302 else
2303 set_bit(STATUS_RF_KILL_HW, &priv->status);
2304
2305 if (iwl_is_rfkill(priv)) {
2306 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2307 iwl_enable_interrupts(priv);
2308 return -ERFKILL;
2309 }
2310
2311 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2312
2313 ret = iwlagn_hw_nic_init(priv);
2314 if (ret) {
2315 IWL_ERR(priv, "Unable to init nic\n");
2316 return ret;
2317 }
2318
2319 /* make sure rfkill handshake bits are cleared */
2320 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2321 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2322 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2323
2324 /* clear (again), then enable host interrupts */
2325 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2326 iwl_enable_interrupts(priv);
2327
2328 /* really make sure rfkill handshake bits are cleared */
2329 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2330 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2331
2332 return 0;
2333 }
2334
2335 void iwlagn_stop_device(struct iwl_priv *priv)
2336 {
2337 unsigned long flags;
2338
2339 /* stop and reset the on-board processor */
2340 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2341
2342 /* tell the device to stop sending interrupts */
2343 spin_lock_irqsave(&priv->lock, flags);
2344 iwl_disable_interrupts(priv);
2345 spin_unlock_irqrestore(&priv->lock, flags);
2346 iwl_synchronize_irq(priv);
2347
2348 /* device going down, Stop using ICT table */
2349 iwl_disable_ict(priv);
2350
2351 /*
2352 * If a HW restart happens during firmware loading,
2353 * then the firmware loading might call this function
2354 * and later it might be called again due to the
2355 * restart. So don't process again if the device is
2356 * already dead.
2357 */
2358 if (test_bit(STATUS_DEVICE_ENABLED, &priv->status)) {
2359 iwlagn_txq_ctx_stop(priv);
2360 iwlagn_rxq_stop(priv);
2361
2362 /* Power-down device's busmaster DMA clocks */
2363 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2364 udelay(5);
2365 }
2366
2367 /* Make sure (redundant) we've released our request to stay awake */
2368 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2369
2370 /* Stop the device, and put it in low power state */
2371 iwl_apm_stop(priv);
2372 }
Linux with added FPC-III support