drivers/gpio/gpio-mmio.c

   1 /*
   2  * Generic driver for memory-mapped GPIO controllers.
   3  *
   4  * Copyright 2008 MontaVista Software, Inc.
   5  * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  *
  12  * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
  13  * ...``                                                         ```````..
  14  * ..The simplest form of a GPIO controller that the driver supports is``
  15  *  `.just a single "data" register, where GPIO state can be read and/or `
  16  *    `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
  17  *        `````````
  18                                     ___
  19 _/~~|___/~|   . ```~~~~~~       ___/___\___     ,~.`.`.`.`````.~~...,,,,...
  20 __________|~$@~~~        %~    /o*o*o*o*o*o\   .. Implementing such a GPIO .
  21 o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
  22                                                  `....trivial..'~`.```.```
  23  *                                                    ```````
  24  *  .```````~~~~`..`.``.``.
  25  * .  The driver supports  `...       ,..```.`~~~```````````````....````.``,,
  26  * .   big-endian notation, just`.  .. A bit more sophisticated controllers ,
  27  *  . register the device with -be`. .with a pair of set/clear-bit registers ,
  28  *   `.. suffix.  ```~~`````....`.`   . affecting the data register and the .`
  29  *     ``.`.``...```                  ```.. output pins are also supported.`
  30  *                        ^^             `````.`````````.,``~``~``~~``````
  31  *                                                   .                  ^^
  32  *   ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
  33  * .. The expectation is that in at least some cases .    ,-~~~-,
  34  *  .this will be used with roll-your-own ASIC/FPGA .`     \   /
  35  *  .logic in Verilog or VHDL. ~~~`````````..`````~~`       \ /
  36  *  ..````````......```````````                             \o_
  37  *                                                           |
  38  *                              ^^                          / \
  39  *
  40  *           ...`````~~`.....``.`..........``````.`.``.```........``.
  41  *            `  8, 16, 32 and 64 bits registers are supported, and``.
  42  *            . the number of GPIOs is determined by the width of   ~
  43  *             .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
  44  *               `.......````.```
  45  */
  46
  47 #include <linux/init.h>
  48 #include <linux/err.h>
  49 #include <linux/bug.h>
  50 #include <linux/kernel.h>
  51 #include <linux/module.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/compiler.h>
  54 #include <linux/types.h>
  55 #include <linux/errno.h>
  56 #include <linux/log2.h>
  57 #include <linux/ioport.h>
  58 #include <linux/io.h>
  59 #include <linux/gpio/driver.h>
  60 #include <linux/slab.h>
  61 #include <linux/bitops.h>
  62 #include <linux/platform_device.h>
  63 #include <linux/mod_devicetable.h>
  64 #include <linux/of.h>
  65 #include <linux/of_device.h>
  66
  67 static void bgpio_write8(void __iomem *reg, unsigned long data)
  68 {
  69         writeb(data, reg);
  70 }
  71
  72 static unsigned long bgpio_read8(void __iomem *reg)
  73 {
  74         return readb(reg);
  75 }
  76
  77 static void bgpio_write16(void __iomem *reg, unsigned long data)
  78 {
  79         writew(data, reg);
  80 }
  81
  82 static unsigned long bgpio_read16(void __iomem *reg)
  83 {
  84         return readw(reg);
  85 }
  86
  87 static void bgpio_write32(void __iomem *reg, unsigned long data)
  88 {
  89         writel(data, reg);
  90 }
  91
  92 static unsigned long bgpio_read32(void __iomem *reg)
  93 {
  94         return readl(reg);
  95 }
  96
  97 #if BITS_PER_LONG >= 64
  98 static void bgpio_write64(void __iomem *reg, unsigned long data)
  99 {
 100         writeq(data, reg);
 101 }
 102
 103 static unsigned long bgpio_read64(void __iomem *reg)
 104 {
 105         return readq(reg);
 106 }
 107 #endif /* BITS_PER_LONG >= 64 */
 108
 109 static void bgpio_write16be(void __iomem *reg, unsigned long data)
 110 {
 111         iowrite16be(data, reg);
 112 }
 113
 114 static unsigned long bgpio_read16be(void __iomem *reg)
 115 {
 116         return ioread16be(reg);
 117 }
 118
 119 static void bgpio_write32be(void __iomem *reg, unsigned long data)
 120 {
 121         iowrite32be(data, reg);
 122 }
 123
 124 static unsigned long bgpio_read32be(void __iomem *reg)
 125 {
 126         return ioread32be(reg);
 127 }
 128
 129 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
 130 {
 131         if (gc->be_bits)
 132                 return BIT(gc->bgpio_bits - 1 - line);
 133         return BIT(line);
 134 }
 135
 136 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
 137 {
 138         unsigned long pinmask = bgpio_line2mask(gc, gpio);
 139         bool dir = !!(gc->bgpio_dir & pinmask);
 140
 141         /*
 142          * If the direction is OUT we read the value from the SET
 143          * register, and if the direction is IN we read the value
 144          * from the DAT register.
 145          *
 146          * If the direction bits are inverted, naturally this gets
 147          * inverted too.
 148          */
 149         if (gc->bgpio_dir_inverted)
 150                 dir = !dir;
 151
 152         if (dir)
 153                 return !!(gc->read_reg(gc->reg_set) & pinmask);
 154         else
 155                 return !!(gc->read_reg(gc->reg_dat) & pinmask);
 156 }
 157
 158 /*
 159  * This assumes that the bits in the GPIO register are in native endianness.
 160  * We only assign the function pointer if we have that.
 161  */
 162 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
 163                                   unsigned long *bits)
 164 {
 165         unsigned long get_mask = 0;
 166         unsigned long set_mask = 0;
 167
 168         /* Make sure we first clear any bits that are zero when we read the register */
 169         *bits &= ~*mask;
 170
 171         /* Exploit the fact that we know which directions are set */
 172         if (gc->bgpio_dir_inverted) {
 173                 set_mask = *mask & ~gc->bgpio_dir;
 174                 get_mask = *mask & gc->bgpio_dir;
 175         } else {
 176                 set_mask = *mask & gc->bgpio_dir;
 177                 get_mask = *mask & ~gc->bgpio_dir;
 178         }
 179
 180         if (set_mask)
 181                 *bits |= gc->read_reg(gc->reg_set) & set_mask;
 182         if (get_mask)
 183                 *bits |= gc->read_reg(gc->reg_dat) & get_mask;
 184
 185         return 0;
 186 }
 187
 188 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
 189 {
 190         return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
 191 }
 192
 193 /*
 194  * This only works if the bits in the GPIO register are in native endianness.
 195  */
 196 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
 197                               unsigned long *bits)
 198 {
 199         /* Make sure we first clear any bits that are zero when we read the register */
 200         *bits &= ~*mask;
 201         *bits |= gc->read_reg(gc->reg_dat) & *mask;
 202         return 0;
 203 }
 204
 205 /*
 206  * With big endian mirrored bit order it becomes more tedious.
 207  */
 208 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
 209                                  unsigned long *bits)
 210 {
 211         unsigned long readmask = 0;
 212         unsigned long val;
 213         int bit;
 214
 215         /* Make sure we first clear any bits that are zero when we read the register */
 216         *bits &= ~*mask;
 217
 218         /* Create a mirrored mask */
 219         bit = -1;
 220         while ((bit = find_next_bit(mask, gc->ngpio, bit + 1)) < gc->ngpio)
 221                 readmask |= bgpio_line2mask(gc, bit);
 222
 223         /* Read the register */
 224         val = gc->read_reg(gc->reg_dat) & readmask;
 225
 226         /*
 227          * Mirror the result into the "bits" result, this will give line 0
 228          * in bit 0 ... line 31 in bit 31 for a 32bit register.
 229          */
 230         bit = -1;
 231         while ((bit = find_next_bit(&val, gc->ngpio, bit + 1)) < gc->ngpio)
 232                 *bits |= bgpio_line2mask(gc, bit);
 233
 234         return 0;
 235 }
 236
 237 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
 238 {
 239 }
 240
 241 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 242 {
 243         unsigned long mask = bgpio_line2mask(gc, gpio);
 244         unsigned long flags;
 245
 246         spin_lock_irqsave(&gc->bgpio_lock, flags);
 247
 248         if (val)
 249                 gc->bgpio_data |= mask;
 250         else
 251                 gc->bgpio_data &= ~mask;
 252
 253         gc->write_reg(gc->reg_dat, gc->bgpio_data);
 254
 255         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 256 }
 257
 258 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
 259                                  int val)
 260 {
 261         unsigned long mask = bgpio_line2mask(gc, gpio);
 262
 263         if (val)
 264                 gc->write_reg(gc->reg_set, mask);
 265         else
 266                 gc->write_reg(gc->reg_clr, mask);
 267 }
 268
 269 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
 270 {
 271         unsigned long mask = bgpio_line2mask(gc, gpio);
 272         unsigned long flags;
 273
 274         spin_lock_irqsave(&gc->bgpio_lock, flags);
 275
 276         if (val)
 277                 gc->bgpio_data |= mask;
 278         else
 279                 gc->bgpio_data &= ~mask;
 280
 281         gc->write_reg(gc->reg_set, gc->bgpio_data);
 282
 283         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 284 }
 285
 286 static void bgpio_multiple_get_masks(struct gpio_chip *gc,
 287                                      unsigned long *mask, unsigned long *bits,
 288                                      unsigned long *set_mask,
 289                                      unsigned long *clear_mask)
 290 {
 291         int i;
 292
 293         *set_mask = 0;
 294         *clear_mask = 0;
 295
 296         for (i = 0; i < gc->bgpio_bits; i++) {
 297                 if (*mask == 0)
 298                         break;
 299                 if (__test_and_clear_bit(i, mask)) {
 300                         if (test_bit(i, bits))
 301                                 *set_mask |= bgpio_line2mask(gc, i);
 302                         else
 303                                 *clear_mask |= bgpio_line2mask(gc, i);
 304                 }
 305         }
 306 }
 307
 308 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
 309                                           unsigned long *mask,
 310                                           unsigned long *bits,
 311                                           void __iomem *reg)
 312 {
 313         unsigned long flags;
 314         unsigned long set_mask, clear_mask;
 315
 316         spin_lock_irqsave(&gc->bgpio_lock, flags);
 317
 318         bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
 319
 320         gc->bgpio_data |= set_mask;
 321         gc->bgpio_data &= ~clear_mask;
 322
 323         gc->write_reg(reg, gc->bgpio_data);
 324
 325         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 326 }
 327
 328 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
 329                                unsigned long *bits)
 330 {
 331         bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
 332 }
 333
 334 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
 335                                    unsigned long *bits)
 336 {
 337         bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
 338 }
 339
 340 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
 341                                           unsigned long *mask,
 342                                           unsigned long *bits)
 343 {
 344         unsigned long set_mask, clear_mask;
 345
 346         bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
 347
 348         if (set_mask)
 349                 gc->write_reg(gc->reg_set, set_mask);
 350         if (clear_mask)
 351                 gc->write_reg(gc->reg_clr, clear_mask);
 352 }
 353
 354 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
 355 {
 356         return 0;
 357 }
 358
 359 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
 360                                 int val)
 361 {
 362         return -EINVAL;
 363 }
 364
 365 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
 366                                 int val)
 367 {
 368         gc->set(gc, gpio, val);
 369
 370         return 0;
 371 }
 372
 373 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 374 {
 375         unsigned long flags;
 376
 377         spin_lock_irqsave(&gc->bgpio_lock, flags);
 378
 379         if (gc->bgpio_dir_inverted)
 380                 gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
 381         else
 382                 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
 383         gc->write_reg(gc->reg_dir, gc->bgpio_dir);
 384
 385         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 386
 387         return 0;
 388 }
 389
 390 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
 391 {
 392         /* Return 0 if output, 1 of input */
 393         if (gc->bgpio_dir_inverted)
 394                 return !!(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio));
 395         else
 396                 return !(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio));
 397 }
 398
 399 static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 400 {
 401         unsigned long flags;
 402
 403         gc->set(gc, gpio, val);
 404
 405         spin_lock_irqsave(&gc->bgpio_lock, flags);
 406
 407         if (gc->bgpio_dir_inverted)
 408                 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
 409         else
 410                 gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
 411         gc->write_reg(gc->reg_dir, gc->bgpio_dir);
 412
 413         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 414
 415         return 0;
 416 }
 417
 418 static int bgpio_setup_accessors(struct device *dev,
 419                                  struct gpio_chip *gc,
 420                                  bool byte_be)
 421 {
 422
 423         switch (gc->bgpio_bits) {
 424         case 8:
 425                 gc->read_reg    = bgpio_read8;
 426                 gc->write_reg   = bgpio_write8;
 427                 break;
 428         case 16:
 429                 if (byte_be) {
 430                         gc->read_reg    = bgpio_read16be;
 431                         gc->write_reg   = bgpio_write16be;
 432                 } else {
 433                         gc->read_reg    = bgpio_read16;
 434                         gc->write_reg   = bgpio_write16;
 435                 }
 436                 break;
 437         case 32:
 438                 if (byte_be) {
 439                         gc->read_reg    = bgpio_read32be;
 440                         gc->write_reg   = bgpio_write32be;
 441                 } else {
 442                         gc->read_reg    = bgpio_read32;
 443                         gc->write_reg   = bgpio_write32;
 444                 }
 445                 break;
 446 #if BITS_PER_LONG >= 64
 447         case 64:
 448                 if (byte_be) {
 449                         dev_err(dev,
 450                                 "64 bit big endian byte order unsupported\n");
 451                         return -EINVAL;
 452                 } else {
 453                         gc->read_reg    = bgpio_read64;
 454                         gc->write_reg   = bgpio_write64;
 455                 }
 456                 break;
 457 #endif /* BITS_PER_LONG >= 64 */
 458         default:
 459                 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
 460                 return -EINVAL;
 461         }
 462
 463         return 0;
 464 }
 465
 466 /*
 467  * Create the device and allocate the resources.  For setting GPIO's there are
 468  * three supported configurations:
 469  *
 470  *      - single input/output register resource (named "dat").
 471  *      - set/clear pair (named "set" and "clr").
 472  *      - single output register resource and single input resource ("set" and
 473  *      dat").
 474  *
 475  * For the single output register, this drives a 1 by setting a bit and a zero
 476  * by clearing a bit.  For the set clr pair, this drives a 1 by setting a bit
 477  * in the set register and clears it by setting a bit in the clear register.
 478  * The configuration is detected by which resources are present.
 479  *
 480  * For setting the GPIO direction, there are three supported configurations:
 481  *
 482  *      - simple bidirection GPIO that requires no configuration.
 483  *      - an output direction register (named "dirout") where a 1 bit
 484  *      indicates the GPIO is an output.
 485  *      - an input direction register (named "dirin") where a 1 bit indicates
 486  *      the GPIO is an input.
 487  */
 488 static int bgpio_setup_io(struct gpio_chip *gc,
 489                           void __iomem *dat,
 490                           void __iomem *set,
 491                           void __iomem *clr,
 492                           unsigned long flags)
 493 {
 494
 495         gc->reg_dat = dat;
 496         if (!gc->reg_dat)
 497                 return -EINVAL;
 498
 499         if (set && clr) {
 500                 gc->reg_set = set;
 501                 gc->reg_clr = clr;
 502                 gc->set = bgpio_set_with_clear;
 503                 gc->set_multiple = bgpio_set_multiple_with_clear;
 504         } else if (set && !clr) {
 505                 gc->reg_set = set;
 506                 gc->set = bgpio_set_set;
 507                 gc->set_multiple = bgpio_set_multiple_set;
 508         } else if (flags & BGPIOF_NO_OUTPUT) {
 509                 gc->set = bgpio_set_none;
 510                 gc->set_multiple = NULL;
 511         } else {
 512                 gc->set = bgpio_set;
 513                 gc->set_multiple = bgpio_set_multiple;
 514         }
 515
 516         if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
 517             (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
 518                 gc->get = bgpio_get_set;
 519                 if (!gc->be_bits)
 520                         gc->get_multiple = bgpio_get_set_multiple;
 521                 /*
 522                  * We deliberately avoid assigning the ->get_multiple() call
 523                  * for big endian mirrored registers which are ALSO reflecting
 524                  * their value in the set register when used as output. It is
 525                  * simply too much complexity, let the GPIO core fall back to
 526                  * reading each line individually in that fringe case.
 527                  */
 528         } else {
 529                 gc->get = bgpio_get;
 530                 if (gc->be_bits)
 531                         gc->get_multiple = bgpio_get_multiple_be;
 532                 else
 533                         gc->get_multiple = bgpio_get_multiple;
 534         }
 535
 536         return 0;
 537 }
 538
 539 static int bgpio_setup_direction(struct gpio_chip *gc,
 540                                  void __iomem *dirout,
 541                                  void __iomem *dirin,
 542                                  unsigned long flags)
 543 {
 544         if (dirout && dirin) {
 545                 return -EINVAL;
 546         } else if (dirout) {
 547                 gc->reg_dir = dirout;
 548                 gc->direction_output = bgpio_dir_out;
 549                 gc->direction_input = bgpio_dir_in;
 550                 gc->get_direction = bgpio_get_dir;
 551         } else if (dirin) {
 552                 gc->reg_dir = dirin;
 553                 gc->direction_output = bgpio_dir_out;
 554                 gc->direction_input = bgpio_dir_in;
 555                 gc->get_direction = bgpio_get_dir;
 556                 gc->bgpio_dir_inverted = true;
 557         } else {
 558                 if (flags & BGPIOF_NO_OUTPUT)
 559                         gc->direction_output = bgpio_dir_out_err;
 560                 else
 561                         gc->direction_output = bgpio_simple_dir_out;
 562                 gc->direction_input = bgpio_simple_dir_in;
 563         }
 564
 565         return 0;
 566 }
 567
 568 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
 569 {
 570         if (gpio_pin < chip->ngpio)
 571                 return 0;
 572
 573         return -EINVAL;
 574 }
 575
 576 /**
 577  * bgpio_init() - Initialize generic GPIO accessor functions
 578  * @gc: the GPIO chip to set up
 579  * @dev: the parent device of the new GPIO chip (compulsory)
 580  * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
 581  * @dat: MMIO address for the register to READ the value of the GPIO lines, it
 582  *      is expected that a 1 in the corresponding bit in this register means the
 583  *      line is asserted
 584  * @set: MMIO address for the register to SET the value of the GPIO lines, it is
 585  *      expected that we write the line with 1 in this register to drive the GPIO line
 586  *      high.
 587  * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
 588  *      expected that we write the line with 1 in this register to drive the GPIO line
 589  *      low. It is allowed to leave this address as NULL, in that case the SET register
 590  *      will be assumed to also clear the GPIO lines, by actively writing the line
 591  *      with 0.
 592  * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
 593  *      that setting a line to 1 in this register will turn that line into an
 594  *      output line. Conversely, setting the line to 0 will turn that line into
 595  *      an input. Either this or @dirin can be defined, but never both.
 596  * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
 597  *      that setting a line to 1 in this register will turn that line into an
 598  *      input line. Conversely, setting the line to 0 will turn that line into
 599  *      an output. Either this or @dirout can be defined, but never both.
 600  * @flags: Different flags that will affect the behaviour of the device, such as
 601  *      endianness etc.
 602  */
 603 int bgpio_init(struct gpio_chip *gc, struct device *dev,
 604                unsigned long sz, void __iomem *dat, void __iomem *set,
 605                void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
 606                unsigned long flags)
 607 {
 608         int ret;
 609
 610         if (!is_power_of_2(sz))
 611                 return -EINVAL;
 612
 613         gc->bgpio_bits = sz * 8;
 614         if (gc->bgpio_bits > BITS_PER_LONG)
 615                 return -EINVAL;
 616
 617         spin_lock_init(&gc->bgpio_lock);
 618         gc->parent = dev;
 619         gc->label = dev_name(dev);
 620         gc->base = -1;
 621         gc->ngpio = gc->bgpio_bits;
 622         gc->request = bgpio_request;
 623         gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
 624
 625         ret = bgpio_setup_io(gc, dat, set, clr, flags);
 626         if (ret)
 627                 return ret;
 628
 629         ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
 630         if (ret)
 631                 return ret;
 632
 633         ret = bgpio_setup_direction(gc, dirout, dirin, flags);
 634         if (ret)
 635                 return ret;
 636
 637         gc->bgpio_data = gc->read_reg(gc->reg_dat);
 638         if (gc->set == bgpio_set_set &&
 639                         !(flags & BGPIOF_UNREADABLE_REG_SET))
 640                 gc->bgpio_data = gc->read_reg(gc->reg_set);
 641         if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
 642                 gc->bgpio_dir = gc->read_reg(gc->reg_dir);
 643
 644         return ret;
 645 }
 646 EXPORT_SYMBOL_GPL(bgpio_init);
 647
 648 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
 649
 650 static void __iomem *bgpio_map(struct platform_device *pdev,
 651                                const char *name,
 652                                resource_size_t sane_sz)
 653 {
 654         struct resource *r;
 655         resource_size_t sz;
 656
 657         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
 658         if (!r)
 659                 return NULL;
 660
 661         sz = resource_size(r);
 662         if (sz != sane_sz)
 663                 return IOMEM_ERR_PTR(-EINVAL);
 664
 665         return devm_ioremap_resource(&pdev->dev, r);
 666 }
 667
 668 #ifdef CONFIG_OF
 669 static const struct of_device_id bgpio_of_match[] = {
 670         { .compatible = "brcm,bcm6345-gpio" },
 671         { .compatible = "wd,mbl-gpio" },
 672         { .compatible = "ni,169445-nand-gpio" },
 673         { }
 674 };
 675 MODULE_DEVICE_TABLE(of, bgpio_of_match);
 676
 677 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
 678                                           unsigned long *flags)
 679 {
 680         struct bgpio_pdata *pdata;
 681
 682         if (!of_match_device(bgpio_of_match, &pdev->dev))
 683                 return NULL;
 684
 685         pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
 686                              GFP_KERNEL);
 687         if (!pdata)
 688                 return ERR_PTR(-ENOMEM);
 689
 690         pdata->base = -1;
 691
 692         if (of_device_is_big_endian(pdev->dev.of_node))
 693                 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
 694
 695         if (of_property_read_bool(pdev->dev.of_node, "no-output"))
 696                 *flags |= BGPIOF_NO_OUTPUT;
 697
 698         return pdata;
 699 }
 700 #else
 701 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
 702                                           unsigned long *flags)
 703 {
 704         return NULL;
 705 }
 706 #endif /* CONFIG_OF */
 707
 708 static int bgpio_pdev_probe(struct platform_device *pdev)
 709 {
 710         struct device *dev = &pdev->dev;
 711         struct resource *r;
 712         void __iomem *dat;
 713         void __iomem *set;
 714         void __iomem *clr;
 715         void __iomem *dirout;
 716         void __iomem *dirin;
 717         unsigned long sz;
 718         unsigned long flags = 0;
 719         int err;
 720         struct gpio_chip *gc;
 721         struct bgpio_pdata *pdata;
 722
 723         pdata = bgpio_parse_dt(pdev, &flags);
 724         if (IS_ERR(pdata))
 725                 return PTR_ERR(pdata);
 726
 727         if (!pdata) {
 728                 pdata = dev_get_platdata(dev);
 729                 flags = pdev->id_entry->driver_data;
 730         }
 731
 732         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
 733         if (!r)
 734                 return -EINVAL;
 735
 736         sz = resource_size(r);
 737
 738         dat = bgpio_map(pdev, "dat", sz);
 739         if (IS_ERR(dat))
 740                 return PTR_ERR(dat);
 741
 742         set = bgpio_map(pdev, "set", sz);
 743         if (IS_ERR(set))
 744                 return PTR_ERR(set);
 745
 746         clr = bgpio_map(pdev, "clr", sz);
 747         if (IS_ERR(clr))
 748                 return PTR_ERR(clr);
 749
 750         dirout = bgpio_map(pdev, "dirout", sz);
 751         if (IS_ERR(dirout))
 752                 return PTR_ERR(dirout);
 753
 754         dirin = bgpio_map(pdev, "dirin", sz);
 755         if (IS_ERR(dirin))
 756                 return PTR_ERR(dirin);
 757
 758         gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
 759         if (!gc)
 760                 return -ENOMEM;
 761
 762         err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
 763         if (err)
 764                 return err;
 765
 766         if (pdata) {
 767                 if (pdata->label)
 768                         gc->label = pdata->label;
 769                 gc->base = pdata->base;
 770                 if (pdata->ngpio > 0)
 771                         gc->ngpio = pdata->ngpio;
 772         }
 773
 774         platform_set_drvdata(pdev, gc);
 775
 776         return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
 777 }
 778
 779 static const struct platform_device_id bgpio_id_table[] = {
 780         {
 781                 .name           = "basic-mmio-gpio",
 782                 .driver_data    = 0,
 783         }, {
 784                 .name           = "basic-mmio-gpio-be",
 785                 .driver_data    = BGPIOF_BIG_ENDIAN,
 786         },
 787         { }
 788 };
 789 MODULE_DEVICE_TABLE(platform, bgpio_id_table);
 790
 791 static struct platform_driver bgpio_driver = {
 792         .driver = {
 793                 .name = "basic-mmio-gpio",
 794                 .of_match_table = of_match_ptr(bgpio_of_match),
 795         },
 796         .id_table = bgpio_id_table,
 797         .probe = bgpio_pdev_probe,
 798 };
 799
 800 module_platform_driver(bgpio_driver);
 801
 802 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
 803
 804 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
 805 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
 806 MODULE_LICENSE("GPL");