arch/mips/alchemy/common/time.c

   1 /*
   2  * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
   3  *
   4  * Previous incarnations were:
   5  * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
   6  * Copied and modified Carsten Langgaard's time.c
   7  *
   8  * Carsten Langgaard, carstenl@mips.com
   9  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
  10  *
  11  * ########################################################################
  12  *
  13  *  This program is free software; you can distribute it and/or modify it
  14  *  under the terms of the GNU General Public License (Version 2) as
  15  *  published by the Free Software Foundation.
  16  *
  17  *  This program is distributed in the hope it will be useful, but WITHOUT
  18  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20  *  for more details.
  21  *
  22  *  You should have received a copy of the GNU General Public License along
  23  *  with this program; if not, write to the Free Software Foundation, Inc.,
  24  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  25  *
  26  * ########################################################################
  27  *
  28  * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
  29  * databooks).  Firmware/Board init code must enable the counters in the
  30  * counter control register, otherwise the CP0 counter clocksource/event
  31  * will be installed instead (and use of 'wait' instruction is prohibited).
  32  */
  33
  34 #include <linux/clockchips.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/spinlock.h>
  38
  39 #include <asm/idle.h>
  40 #include <asm/processor.h>
  41 #include <asm/time.h>
  42 #include <asm/mach-au1x00/au1000.h>
  43
  44 /* 32kHz clock enabled and detected */
  45 #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
  46
  47 static cycle_t au1x_counter1_read(struct clocksource *cs)
  48 {
  49         return au_readl(SYS_RTCREAD);
  50 }
  51
  52 static struct clocksource au1x_counter1_clocksource = {
  53         .name           = "alchemy-counter1",
  54         .read           = au1x_counter1_read,
  55         .mask           = CLOCKSOURCE_MASK(32),
  56         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  57         .rating         = 1500,
  58 };
  59
  60 static int au1x_rtcmatch2_set_next_event(unsigned long delta,
  61                                          struct clock_event_device *cd)
  62 {
  63         delta += au_readl(SYS_RTCREAD);
  64         /* wait for register access */
  65         while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21)
  66                 ;
  67         au_writel(delta, SYS_RTCMATCH2);
  68         au_sync();
  69
  70         return 0;
  71 }
  72
  73 static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode,
  74                                     struct clock_event_device *cd)
  75 {
  76 }
  77
  78 static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
  79 {
  80         struct clock_event_device *cd = dev_id;
  81         cd->event_handler(cd);
  82         return IRQ_HANDLED;
  83 }
  84
  85 static struct clock_event_device au1x_rtcmatch2_clockdev = {
  86         .name           = "rtcmatch2",
  87         .features       = CLOCK_EVT_FEAT_ONESHOT,
  88         .rating         = 1500,
  89         .set_next_event = au1x_rtcmatch2_set_next_event,
  90         .set_mode       = au1x_rtcmatch2_set_mode,
  91         .cpumask        = cpu_all_mask,
  92 };
  93
  94 static struct irqaction au1x_rtcmatch2_irqaction = {
  95         .handler        = au1x_rtcmatch2_irq,
  96         .flags          = IRQF_TIMER,
  97         .name           = "timer",
  98         .dev_id         = &au1x_rtcmatch2_clockdev,
  99 };
 100
 101 static int __init alchemy_time_init(unsigned int m2int)
 102 {
 103         struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
 104         unsigned long t;
 105
 106         au1x_rtcmatch2_clockdev.irq = m2int;
 107
 108         /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
 109          * has been detected.  If so install the rtcmatch2 clocksource,
 110          * otherwise don't bother.  Note that both bits being set is by
 111          * no means a definite guarantee that the counters actually work
 112          * (the 32S bit seems to be stuck set to 1 once a single clock-
 113          * edge is detected, hence the timeouts).
 114          */
 115         if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK))
 116                 goto cntr_err;
 117
 118         /*
 119          * setup counter 1 (RTC) to tick at full speed
 120          */
 121         t = 0xffffff;
 122         while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && --t)
 123                 asm volatile ("nop");
 124         if (!t)
 125                 goto cntr_err;
 126
 127         au_writel(0, SYS_RTCTRIM);      /* 32.768 kHz */
 128         au_sync();
 129
 130         t = 0xffffff;
 131         while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
 132                 asm volatile ("nop");
 133         if (!t)
 134                 goto cntr_err;
 135         au_writel(0, SYS_RTCWRITE);
 136         au_sync();
 137
 138         t = 0xffffff;
 139         while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
 140                 asm volatile ("nop");
 141         if (!t)
 142                 goto cntr_err;
 143
 144         /* register counter1 clocksource and event device */
 145         clocksource_register_hz(&au1x_counter1_clocksource, 32768);
 146
 147         cd->shift = 32;
 148         cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
 149         cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
 150         cd->min_delta_ns = clockevent_delta2ns(9, cd);  /* ~0.28ms */
 151         clockevents_register_device(cd);
 152         setup_irq(m2int, &au1x_rtcmatch2_irqaction);
 153
 154         printk(KERN_INFO "Alchemy clocksource installed\n");
 155
 156         return 0;
 157
 158 cntr_err:
 159         return -1;
 160 }
 161
 162 static int alchemy_m2inttab[] __initdata = {
 163         AU1000_RTC_MATCH2_INT,
 164         AU1500_RTC_MATCH2_INT,
 165         AU1100_RTC_MATCH2_INT,
 166         AU1550_RTC_MATCH2_INT,
 167         AU1200_RTC_MATCH2_INT,
 168         AU1300_RTC_MATCH2_INT,
 169 };
 170
 171 void __init plat_time_init(void)
 172 {
 173         int t;
 174
 175         t = alchemy_get_cputype();
 176         if (t == ALCHEMY_CPU_UNKNOWN ||
 177             alchemy_time_init(alchemy_m2inttab[t]))
 178                 cpu_wait = NULL;        /* wait doesn't work with r4k timer */
 179 }