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Linux 3.15-rc1
[linux/fpc-iii.git] / arch / mips / cavium-octeon / octeon-platform.c
blob6df0f4d8f197a867f3dd80befb9fb00a4b8ca4a8
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2011 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
8 */
9
10 #include <linux/init.h>
11 #include <linux/irq.h>
12 #include <linux/i2c.h>
13 #include <linux/usb.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/platform_device.h>
18 #include <linux/of_platform.h>
19 #include <linux/of_fdt.h>
20 #include <linux/libfdt.h>
21
22 #include <asm/octeon/octeon.h>
23 #include <asm/octeon/cvmx-rnm-defs.h>
24 #include <asm/octeon/cvmx-helper.h>
25 #include <asm/octeon/cvmx-helper-board.h>
26
27 /* Octeon Random Number Generator. */
28 static int __init octeon_rng_device_init(void)
29 {
30 struct platform_device *pd;
31 int ret = 0;
32
33 struct resource rng_resources[] = {
34 {
35 .flags = IORESOURCE_MEM,
36 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
37 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
38 }, {
39 .flags = IORESOURCE_MEM,
40 .start = cvmx_build_io_address(8, 0),
41 .end = cvmx_build_io_address(8, 0) + 0x7
42 }
43 };
44
45 pd = platform_device_alloc("octeon_rng", -1);
46 if (!pd) {
47 ret = -ENOMEM;
48 goto out;
49 }
50
51 ret = platform_device_add_resources(pd, rng_resources,
52 ARRAY_SIZE(rng_resources));
53 if (ret)
54 goto fail;
55
56 ret = platform_device_add(pd);
57 if (ret)
58 goto fail;
59
60 return ret;
61 fail:
62 platform_device_put(pd);
63
64 out:
65 return ret;
66 }
67 device_initcall(octeon_rng_device_init);
68
69 #ifdef CONFIG_USB
70
71 static int __init octeon_ehci_device_init(void)
72 {
73 struct platform_device *pd;
74 int ret = 0;
75
76 struct resource usb_resources[] = {
77 {
78 .flags = IORESOURCE_MEM,
79 }, {
80 .flags = IORESOURCE_IRQ,
81 }
82 };
83
84 /* Only Octeon2 has ehci/ohci */
85 if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
86 return 0;
87
88 if (octeon_is_simulation() || usb_disabled())
89 return 0; /* No USB in the simulator. */
90
91 pd = platform_device_alloc("octeon-ehci", 0);
92 if (!pd) {
93 ret = -ENOMEM;
94 goto out;
95 }
96
97 usb_resources[0].start = 0x00016F0000000000ULL;
98 usb_resources[0].end = usb_resources[0].start + 0x100;
99
100 usb_resources[1].start = OCTEON_IRQ_USB0;
101 usb_resources[1].end = OCTEON_IRQ_USB0;
102
103 ret = platform_device_add_resources(pd, usb_resources,
104 ARRAY_SIZE(usb_resources));
105 if (ret)
106 goto fail;
107
108 ret = platform_device_add(pd);
109 if (ret)
110 goto fail;
111
112 return ret;
113 fail:
114 platform_device_put(pd);
115 out:
116 return ret;
117 }
118 device_initcall(octeon_ehci_device_init);
119
120 static int __init octeon_ohci_device_init(void)
121 {
122 struct platform_device *pd;
123 int ret = 0;
124
125 struct resource usb_resources[] = {
126 {
127 .flags = IORESOURCE_MEM,
128 }, {
129 .flags = IORESOURCE_IRQ,
130 }
131 };
132
133 /* Only Octeon2 has ehci/ohci */
134 if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
135 return 0;
136
137 if (octeon_is_simulation() || usb_disabled())
138 return 0; /* No USB in the simulator. */
139
140 pd = platform_device_alloc("octeon-ohci", 0);
141 if (!pd) {
142 ret = -ENOMEM;
143 goto out;
144 }
145
146 usb_resources[0].start = 0x00016F0000000400ULL;
147 usb_resources[0].end = usb_resources[0].start + 0x100;
148
149 usb_resources[1].start = OCTEON_IRQ_USB0;
150 usb_resources[1].end = OCTEON_IRQ_USB0;
151
152 ret = platform_device_add_resources(pd, usb_resources,
153 ARRAY_SIZE(usb_resources));
154 if (ret)
155 goto fail;
156
157 ret = platform_device_add(pd);
158 if (ret)
159 goto fail;
160
161 return ret;
162 fail:
163 platform_device_put(pd);
164 out:
165 return ret;
166 }
167 device_initcall(octeon_ohci_device_init);
168
169 #endif /* CONFIG_USB */
170
171 static struct of_device_id __initdata octeon_ids[] = {
172 { .compatible = "simple-bus", },
173 { .compatible = "cavium,octeon-6335-uctl", },
174 { .compatible = "cavium,octeon-5750-usbn", },
175 { .compatible = "cavium,octeon-3860-bootbus", },
176 { .compatible = "cavium,mdio-mux", },
177 { .compatible = "gpio-leds", },
178 {},
179 };
180
181 static bool __init octeon_has_88e1145(void)
182 {
183 return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
184 !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
185 !OCTEON_IS_MODEL(OCTEON_CN56XX);
186 }
187
188 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
189 {
190 const __be32 *phy_handle;
191 const __be32 *alt_phy_handle;
192 const __be32 *reg;
193 u32 phandle;
194 int phy;
195 int alt_phy;
196 const char *p;
197 int current_len;
198 char new_name[20];
199
200 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
201 if (!phy_handle)
202 return;
203
204 phandle = be32_to_cpup(phy_handle);
205 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
206
207 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
208 if (alt_phy_handle) {
209 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
210 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
211 } else {
212 alt_phy = -1;
213 }
214
215 if (phy_addr < 0 || phy < 0) {
216 /* Delete the PHY things */
217 fdt_nop_property(initial_boot_params, eth, "phy-handle");
218 /* This one may fail */
219 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
220 if (phy >= 0)
221 fdt_nop_node(initial_boot_params, phy);
222 if (alt_phy >= 0)
223 fdt_nop_node(initial_boot_params, alt_phy);
224 return;
225 }
226
227 if (phy_addr >= 256 && alt_phy > 0) {
228 const struct fdt_property *phy_prop;
229 struct fdt_property *alt_prop;
230 u32 phy_handle_name;
231
232 /* Use the alt phy node instead.*/
233 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
234 phy_handle_name = phy_prop->nameoff;
235 fdt_nop_node(initial_boot_params, phy);
236 fdt_nop_property(initial_boot_params, eth, "phy-handle");
237 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
238 alt_prop->nameoff = phy_handle_name;
239 phy = alt_phy;
240 }
241
242 phy_addr &= 0xff;
243
244 if (octeon_has_88e1145()) {
245 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
246 memset(new_name, 0, sizeof(new_name));
247 strcpy(new_name, "marvell,88e1145");
248 p = fdt_getprop(initial_boot_params, phy, "compatible",
249 &current_len);
250 if (p && current_len >= strlen(new_name))
251 fdt_setprop_inplace(initial_boot_params, phy,
252 "compatible", new_name, current_len);
253 }
254
255 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
256 if (phy_addr == be32_to_cpup(reg))
257 return;
258
259 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
260
261 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
262
263 p = fdt_get_name(initial_boot_params, phy, &current_len);
264 if (p && current_len == strlen(new_name))
265 fdt_set_name(initial_boot_params, phy, new_name);
266 else
267 pr_err("Error: could not rename ethernet phy: <%s>", p);
268 }
269
270 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
271 {
272 u8 new_mac[6];
273 u64 mac = *pmac;
274 int r;
275
276 new_mac[0] = (mac >> 40) & 0xff;
277 new_mac[1] = (mac >> 32) & 0xff;
278 new_mac[2] = (mac >> 24) & 0xff;
279 new_mac[3] = (mac >> 16) & 0xff;
280 new_mac[4] = (mac >> 8) & 0xff;
281 new_mac[5] = mac & 0xff;
282
283 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
284 new_mac, sizeof(new_mac));
285
286 if (r) {
287 pr_err("Setting \"local-mac-address\" failed %d", r);
288 return;
289 }
290 *pmac = mac + 1;
291 }
292
293 static void __init octeon_fdt_rm_ethernet(int node)
294 {
295 const __be32 *phy_handle;
296
297 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
298 if (phy_handle) {
299 u32 ph = be32_to_cpup(phy_handle);
300 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
301 if (p >= 0)
302 fdt_nop_node(initial_boot_params, p);
303 }
304 fdt_nop_node(initial_boot_params, node);
305 }
306
307 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac)
308 {
309 char name_buffer[20];
310 int eth;
311 int phy_addr;
312 int ipd_port;
313
314 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
315 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
316 if (eth < 0)
317 return;
318 if (p > max) {
319 pr_debug("Deleting port %x:%x\n", i, p);
320 octeon_fdt_rm_ethernet(eth);
321 return;
322 }
323 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
324 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
325 else
326 ipd_port = 16 * i + p;
327
328 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
329 octeon_fdt_set_phy(eth, phy_addr);
330 octeon_fdt_set_mac_addr(eth, pmac);
331 }
332
333 static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
334 {
335 char name_buffer[20];
336 int iface;
337 int p;
338 int count = 0;
339
340 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
341 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
342 if (iface < 0)
343 return;
344
345 if (cvmx_helper_interface_enumerate(idx) == 0)
346 count = cvmx_helper_ports_on_interface(idx);
347
348 for (p = 0; p < 16; p++)
349 octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
350 }
351
352 int __init octeon_prune_device_tree(void)
353 {
354 int i, max_port, uart_mask;
355 const char *pip_path;
356 const char *alias_prop;
357 char name_buffer[20];
358 int aliases;
359 u64 mac_addr_base;
360
361 if (fdt_check_header(initial_boot_params))
362 panic("Corrupt Device Tree.");
363
364 aliases = fdt_path_offset(initial_boot_params, "/aliases");
365 if (aliases < 0) {
366 pr_err("Error: No /aliases node in device tree.");
367 return -EINVAL;
368 }
369
370
371 mac_addr_base =
372 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
373 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
374 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
375 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
376 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
377 (octeon_bootinfo->mac_addr_base[5] & 0xffull);
378
379 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
380 max_port = 2;
381 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
382 max_port = 1;
383 else
384 max_port = 0;
385
386 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
387 max_port = 0;
388
389 for (i = 0; i < 2; i++) {
390 int mgmt;
391 snprintf(name_buffer, sizeof(name_buffer),
392 "mix%d", i);
393 alias_prop = fdt_getprop(initial_boot_params, aliases,
394 name_buffer, NULL);
395 if (alias_prop) {
396 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
397 if (mgmt < 0)
398 continue;
399 if (i >= max_port) {
400 pr_debug("Deleting mix%d\n", i);
401 octeon_fdt_rm_ethernet(mgmt);
402 fdt_nop_property(initial_boot_params, aliases,
403 name_buffer);
404 } else {
405 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
406 octeon_fdt_set_phy(mgmt, phy_addr);
407 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
408 }
409 }
410 }
411
412 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
413 if (pip_path) {
414 int pip = fdt_path_offset(initial_boot_params, pip_path);
415 if (pip >= 0)
416 for (i = 0; i <= 4; i++)
417 octeon_fdt_pip_iface(pip, i, &mac_addr_base);
418 }
419
420 /* I2C */
421 if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
422 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
423 OCTEON_IS_MODEL(OCTEON_CN68XX) ||
424 OCTEON_IS_MODEL(OCTEON_CN56XX))
425 max_port = 2;
426 else
427 max_port = 1;
428
429 for (i = 0; i < 2; i++) {
430 int i2c;
431 snprintf(name_buffer, sizeof(name_buffer),
432 "twsi%d", i);
433 alias_prop = fdt_getprop(initial_boot_params, aliases,
434 name_buffer, NULL);
435
436 if (alias_prop) {
437 i2c = fdt_path_offset(initial_boot_params, alias_prop);
438 if (i2c < 0)
439 continue;
440 if (i >= max_port) {
441 pr_debug("Deleting twsi%d\n", i);
442 fdt_nop_node(initial_boot_params, i2c);
443 fdt_nop_property(initial_boot_params, aliases,
444 name_buffer);
445 }
446 }
447 }
448
449 /* SMI/MDIO */
450 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
451 max_port = 4;
452 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
453 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
454 OCTEON_IS_MODEL(OCTEON_CN56XX))
455 max_port = 2;
456 else
457 max_port = 1;
458
459 for (i = 0; i < 2; i++) {
460 int i2c;
461 snprintf(name_buffer, sizeof(name_buffer),
462 "smi%d", i);
463 alias_prop = fdt_getprop(initial_boot_params, aliases,
464 name_buffer, NULL);
465
466 if (alias_prop) {
467 i2c = fdt_path_offset(initial_boot_params, alias_prop);
468 if (i2c < 0)
469 continue;
470 if (i >= max_port) {
471 pr_debug("Deleting smi%d\n", i);
472 fdt_nop_node(initial_boot_params, i2c);
473 fdt_nop_property(initial_boot_params, aliases,
474 name_buffer);
475 }
476 }
477 }
478
479 /* Serial */
480 uart_mask = 3;
481
482 /* Right now CN52XX is the only chip with a third uart */
483 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
484 uart_mask |= 4; /* uart2 */
485
486 for (i = 0; i < 3; i++) {
487 int uart;
488 snprintf(name_buffer, sizeof(name_buffer),
489 "uart%d", i);
490 alias_prop = fdt_getprop(initial_boot_params, aliases,
491 name_buffer, NULL);
492
493 if (alias_prop) {
494 uart = fdt_path_offset(initial_boot_params, alias_prop);
495 if (uart_mask & (1 << i)) {
496 __be32 f;
497
498 f = cpu_to_be32(octeon_get_io_clock_rate());
499 fdt_setprop_inplace(initial_boot_params,
500 uart, "clock-frequency",
501 &f, sizeof(f));
502 continue;
503 }
504 pr_debug("Deleting uart%d\n", i);
505 fdt_nop_node(initial_boot_params, uart);
506 fdt_nop_property(initial_boot_params, aliases,
507 name_buffer);
508 }
509 }
510
511 /* Compact Flash */
512 alias_prop = fdt_getprop(initial_boot_params, aliases,
513 "cf0", NULL);
514 if (alias_prop) {
515 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
516 unsigned long base_ptr, region_base, region_size;
517 unsigned long region1_base = 0;
518 unsigned long region1_size = 0;
519 int cs, bootbus;
520 bool is_16bit = false;
521 bool is_true_ide = false;
522 __be32 new_reg[6];
523 __be32 *ranges;
524 int len;
525
526 int cf = fdt_path_offset(initial_boot_params, alias_prop);
527 base_ptr = 0;
528 if (octeon_bootinfo->major_version == 1
529 && octeon_bootinfo->minor_version >= 1) {
530 if (octeon_bootinfo->compact_flash_common_base_addr)
531 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
532 } else {
533 base_ptr = 0x1d000800;
534 }
535
536 if (!base_ptr)
537 goto no_cf;
538
539 /* Find CS0 region. */
540 for (cs = 0; cs < 8; cs++) {
541 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
542 region_base = mio_boot_reg_cfg.s.base << 16;
543 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
544 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
545 && base_ptr < region_base + region_size) {
546 is_16bit = mio_boot_reg_cfg.s.width;
547 break;
548 }
549 }
550 if (cs >= 7) {
551 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
552 goto no_cf;
553 }
554
555 if (!(base_ptr & 0xfffful)) {
556 /*
557 * Boot loader signals availability of DMA (true_ide
558 * mode) by setting low order bits of base_ptr to
559 * zero.
560 */
561
562 /* Asume that CS1 immediately follows. */
563 mio_boot_reg_cfg.u64 =
564 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
565 region1_base = mio_boot_reg_cfg.s.base << 16;
566 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
567 if (!mio_boot_reg_cfg.s.en)
568 goto no_cf;
569 is_true_ide = true;
570
571 } else {
572 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
573 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
574 if (!is_16bit) {
575 __be32 width = cpu_to_be32(8);
576 fdt_setprop_inplace(initial_boot_params, cf,
577 "cavium,bus-width", &width, sizeof(width));
578 }
579 }
580 new_reg[0] = cpu_to_be32(cs);
581 new_reg[1] = cpu_to_be32(0);
582 new_reg[2] = cpu_to_be32(0x10000);
583 new_reg[3] = cpu_to_be32(cs + 1);
584 new_reg[4] = cpu_to_be32(0);
585 new_reg[5] = cpu_to_be32(0x10000);
586 fdt_setprop_inplace(initial_boot_params, cf,
587 "reg", new_reg, sizeof(new_reg));
588
589 bootbus = fdt_parent_offset(initial_boot_params, cf);
590 if (bootbus < 0)
591 goto no_cf;
592 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
593 if (!ranges || len < (5 * 8 * sizeof(__be32)))
594 goto no_cf;
595
596 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
597 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
598 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
599 if (is_true_ide) {
600 cs++;
601 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
602 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
603 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
604 }
605 goto end_cf;
606 no_cf:
607 fdt_nop_node(initial_boot_params, cf);
608
609 end_cf:
610 ;
611 }
612
613 /* 8 char LED */
614 alias_prop = fdt_getprop(initial_boot_params, aliases,
615 "led0", NULL);
616 if (alias_prop) {
617 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
618 unsigned long base_ptr, region_base, region_size;
619 int cs, bootbus;
620 __be32 new_reg[6];
621 __be32 *ranges;
622 int len;
623 int led = fdt_path_offset(initial_boot_params, alias_prop);
624
625 base_ptr = octeon_bootinfo->led_display_base_addr;
626 if (base_ptr == 0)
627 goto no_led;
628 /* Find CS0 region. */
629 for (cs = 0; cs < 8; cs++) {
630 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
631 region_base = mio_boot_reg_cfg.s.base << 16;
632 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
633 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
634 && base_ptr < region_base + region_size)
635 break;
636 }
637
638 if (cs > 7)
639 goto no_led;
640
641 new_reg[0] = cpu_to_be32(cs);
642 new_reg[1] = cpu_to_be32(0x20);
643 new_reg[2] = cpu_to_be32(0x20);
644 new_reg[3] = cpu_to_be32(cs);
645 new_reg[4] = cpu_to_be32(0);
646 new_reg[5] = cpu_to_be32(0x20);
647 fdt_setprop_inplace(initial_boot_params, led,
648 "reg", new_reg, sizeof(new_reg));
649
650 bootbus = fdt_parent_offset(initial_boot_params, led);
651 if (bootbus < 0)
652 goto no_led;
653 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
654 if (!ranges || len < (5 * 8 * sizeof(__be32)))
655 goto no_led;
656
657 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
658 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
659 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
660 goto end_led;
661
662 no_led:
663 fdt_nop_node(initial_boot_params, led);
664 end_led:
665 ;
666 }
667
668 /* OHCI/UHCI USB */
669 alias_prop = fdt_getprop(initial_boot_params, aliases,
670 "uctl", NULL);
671 if (alias_prop) {
672 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
673
674 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
675 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
676 pr_debug("Deleting uctl\n");
677 fdt_nop_node(initial_boot_params, uctl);
678 fdt_nop_property(initial_boot_params, aliases, "uctl");
679 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
680 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
681 /* Missing "refclk-type" defaults to crystal. */
682 fdt_nop_property(initial_boot_params, uctl, "refclk-type");
683 }
684 }
685
686 /* DWC2 USB */
687 alias_prop = fdt_getprop(initial_boot_params, aliases,
688 "usbn", NULL);
689 if (alias_prop) {
690 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
691
692 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
693 !octeon_has_feature(OCTEON_FEATURE_USB))) {
694 pr_debug("Deleting usbn\n");
695 fdt_nop_node(initial_boot_params, usbn);
696 fdt_nop_property(initial_boot_params, aliases, "usbn");
697 } else {
698 __be32 new_f[1];
699 enum cvmx_helper_board_usb_clock_types c;
700 c = __cvmx_helper_board_usb_get_clock_type();
701 switch (c) {
702 case USB_CLOCK_TYPE_REF_48:
703 new_f[0] = cpu_to_be32(48000000);
704 fdt_setprop_inplace(initial_boot_params, usbn,
705 "refclk-frequency", new_f, sizeof(new_f));
706 /* Fall through ...*/
707 case USB_CLOCK_TYPE_REF_12:
708 /* Missing "refclk-type" defaults to external. */
709 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
710 break;
711 default:
712 break;
713 }
714 }
715 }
716
717 return 0;
718 }
719
720 static int __init octeon_publish_devices(void)
721 {
722 return of_platform_bus_probe(NULL, octeon_ids, NULL);
723 }
724 device_initcall(octeon_publish_devices);
725
726 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
727 MODULE_LICENSE("GPL");
728 MODULE_DESCRIPTION("Platform driver for Octeon SOC");
Linux with added FPC-III support