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Linux 3.15-rc1
[linux/fpc-iii.git] / arch / mips / include / asm / gic.h
blob0827166905899db5c49042d0b2fa089810d46ef4
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
7 *
8 * GIC Register Definitions
9 *
10 */
11 #ifndef _ASM_GICREGS_H
12 #define _ASM_GICREGS_H
13
14 #include <linux/bitmap.h>
15 #include <linux/threads.h>
16
17 #undef GICISBYTELITTLEENDIAN
18
19 /* Constants */
20 #define GIC_POL_POS 1
21 #define GIC_POL_NEG 0
22 #define GIC_TRIG_EDGE 1
23 #define GIC_TRIG_LEVEL 0
24
25 #define GIC_NUM_INTRS (24 + NR_CPUS * 2)
26
27 #define MSK(n) ((1 << (n)) - 1)
28 #define REG32(addr) (*(volatile unsigned int *) (addr))
29 #define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
30 #define REGP(base, phys) REG32((unsigned long)(base) + (phys))
31
32 /* Accessors */
33 #define GIC_REG(segment, offset) \
34 REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
35 #define GIC_REG_ADDR(segment, offset) \
36 REG32(_gic_base + segment##_##SECTION_OFS + offset)
37
38 #define GIC_ABS_REG(segment, offset) \
39 (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
40 #define GIC_REG_ABS_ADDR(segment, offset) \
41 (_gic_base + segment##_##SECTION_OFS + offset)
42
43 #ifdef GICISBYTELITTLEENDIAN
44 #define GICREAD(reg, data) ((data) = (reg), (data) = le32_to_cpu(data))
45 #define GICWRITE(reg, data) ((reg) = cpu_to_le32(data))
46 #define GICBIS(reg, bits) \
47 ({unsigned int data; \
48 GICREAD(reg, data); \
49 data |= bits; \
50 GICWRITE(reg, data); \
51 })
52
53 #else
54 #define GICREAD(reg, data) ((data) = (reg))
55 #define GICWRITE(reg, data) ((reg) = (data))
56 #define GICBIS(reg, bits) ((reg) |= (bits))
57 #endif
58
59
60 /* GIC Address Space */
61 #define SHARED_SECTION_OFS 0x0000
62 #define SHARED_SECTION_SIZE 0x8000
63 #define VPE_LOCAL_SECTION_OFS 0x8000
64 #define VPE_LOCAL_SECTION_SIZE 0x4000
65 #define VPE_OTHER_SECTION_OFS 0xc000
66 #define VPE_OTHER_SECTION_SIZE 0x4000
67 #define USM_VISIBLE_SECTION_OFS 0x10000
68 #define USM_VISIBLE_SECTION_SIZE 0x10000
69
70 /* Register Map for Shared Section */
71
72 #define GIC_SH_CONFIG_OFS 0x0000
73
74 /* Shared Global Counter */
75 #define GIC_SH_COUNTER_31_00_OFS 0x0010
76 #define GIC_SH_COUNTER_63_32_OFS 0x0014
77 #define GIC_SH_REVISIONID_OFS 0x0020
78
79 /* Interrupt Polarity */
80 #define GIC_SH_POL_31_0_OFS 0x0100
81 #define GIC_SH_POL_63_32_OFS 0x0104
82 #define GIC_SH_POL_95_64_OFS 0x0108
83 #define GIC_SH_POL_127_96_OFS 0x010c
84 #define GIC_SH_POL_159_128_OFS 0x0110
85 #define GIC_SH_POL_191_160_OFS 0x0114
86 #define GIC_SH_POL_223_192_OFS 0x0118
87 #define GIC_SH_POL_255_224_OFS 0x011c
88
89 /* Edge/Level Triggering */
90 #define GIC_SH_TRIG_31_0_OFS 0x0180
91 #define GIC_SH_TRIG_63_32_OFS 0x0184
92 #define GIC_SH_TRIG_95_64_OFS 0x0188
93 #define GIC_SH_TRIG_127_96_OFS 0x018c
94 #define GIC_SH_TRIG_159_128_OFS 0x0190
95 #define GIC_SH_TRIG_191_160_OFS 0x0194
96 #define GIC_SH_TRIG_223_192_OFS 0x0198
97 #define GIC_SH_TRIG_255_224_OFS 0x019c
98
99 /* Dual Edge Triggering */
100 #define GIC_SH_DUAL_31_0_OFS 0x0200
101 #define GIC_SH_DUAL_63_32_OFS 0x0204
102 #define GIC_SH_DUAL_95_64_OFS 0x0208
103 #define GIC_SH_DUAL_127_96_OFS 0x020c
104 #define GIC_SH_DUAL_159_128_OFS 0x0210
105 #define GIC_SH_DUAL_191_160_OFS 0x0214
106 #define GIC_SH_DUAL_223_192_OFS 0x0218
107 #define GIC_SH_DUAL_255_224_OFS 0x021c
108
109 /* Set/Clear corresponding bit in Edge Detect Register */
110 #define GIC_SH_WEDGE_OFS 0x0280
111
112 /* Reset Mask - Disables Interrupt */
113 #define GIC_SH_RMASK_31_0_OFS 0x0300
114 #define GIC_SH_RMASK_63_32_OFS 0x0304
115 #define GIC_SH_RMASK_95_64_OFS 0x0308
116 #define GIC_SH_RMASK_127_96_OFS 0x030c
117 #define GIC_SH_RMASK_159_128_OFS 0x0310
118 #define GIC_SH_RMASK_191_160_OFS 0x0314
119 #define GIC_SH_RMASK_223_192_OFS 0x0318
120 #define GIC_SH_RMASK_255_224_OFS 0x031c
121
122 /* Set Mask (WO) - Enables Interrupt */
123 #define GIC_SH_SMASK_31_0_OFS 0x0380
124 #define GIC_SH_SMASK_63_32_OFS 0x0384
125 #define GIC_SH_SMASK_95_64_OFS 0x0388
126 #define GIC_SH_SMASK_127_96_OFS 0x038c
127 #define GIC_SH_SMASK_159_128_OFS 0x0390
128 #define GIC_SH_SMASK_191_160_OFS 0x0394
129 #define GIC_SH_SMASK_223_192_OFS 0x0398
130 #define GIC_SH_SMASK_255_224_OFS 0x039c
131
132 /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
133 #define GIC_SH_MASK_31_0_OFS 0x0400
134 #define GIC_SH_MASK_63_32_OFS 0x0404
135 #define GIC_SH_MASK_95_64_OFS 0x0408
136 #define GIC_SH_MASK_127_96_OFS 0x040c
137 #define GIC_SH_MASK_159_128_OFS 0x0410
138 #define GIC_SH_MASK_191_160_OFS 0x0414
139 #define GIC_SH_MASK_223_192_OFS 0x0418
140 #define GIC_SH_MASK_255_224_OFS 0x041c
141
142 /* Pending Global Interrupts (RO) */
143 #define GIC_SH_PEND_31_0_OFS 0x0480
144 #define GIC_SH_PEND_63_32_OFS 0x0484
145 #define GIC_SH_PEND_95_64_OFS 0x0488
146 #define GIC_SH_PEND_127_96_OFS 0x048c
147 #define GIC_SH_PEND_159_128_OFS 0x0490
148 #define GIC_SH_PEND_191_160_OFS 0x0494
149 #define GIC_SH_PEND_223_192_OFS 0x0498
150 #define GIC_SH_PEND_255_224_OFS 0x049c
151
152 #define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
153
154 /* Maps Interrupt X to a Pin */
155 #define GIC_SH_MAP_TO_PIN(intr) \
156 (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
157
158 #define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
159
160 /* Maps Interrupt X to a VPE */
161 #define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
162 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
163 #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
164
165 /* Convert an interrupt number to a byte offset/bit for multi-word registers */
166 #define GIC_INTR_OFS(intr) (((intr) / 32)*4)
167 #define GIC_INTR_BIT(intr) ((intr) % 32)
168
169 /* Polarity : Reset Value is always 0 */
170 #define GIC_SH_SET_POLARITY_OFS 0x0100
171 #define GIC_SET_POLARITY(intr, pol) \
172 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
173 GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
174
175 /* Triggering : Reset Value is always 0 */
176 #define GIC_SH_SET_TRIGGER_OFS 0x0180
177 #define GIC_SET_TRIGGER(intr, trig) \
178 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
179 GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
180
181 /* Mask manipulation */
182 #define GIC_SH_SMASK_OFS 0x0380
183 #define GIC_SET_INTR_MASK(intr) \
184 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
185 GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
186 #define GIC_SH_RMASK_OFS 0x0300
187 #define GIC_CLR_INTR_MASK(intr) \
188 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
189 GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
190
191 /* Register Map for Local Section */
192 #define GIC_VPE_CTL_OFS 0x0000
193 #define GIC_VPE_PEND_OFS 0x0004
194 #define GIC_VPE_MASK_OFS 0x0008
195 #define GIC_VPE_RMASK_OFS 0x000c
196 #define GIC_VPE_SMASK_OFS 0x0010
197 #define GIC_VPE_WD_MAP_OFS 0x0040
198 #define GIC_VPE_COMPARE_MAP_OFS 0x0044
199 #define GIC_VPE_TIMER_MAP_OFS 0x0048
200 #define GIC_VPE_PERFCTR_MAP_OFS 0x0050
201 #define GIC_VPE_SWINT0_MAP_OFS 0x0054
202 #define GIC_VPE_SWINT1_MAP_OFS 0x0058
203 #define GIC_VPE_OTHER_ADDR_OFS 0x0080
204 #define GIC_VPE_WD_CONFIG0_OFS 0x0090
205 #define GIC_VPE_WD_COUNT0_OFS 0x0094
206 #define GIC_VPE_WD_INITIAL0_OFS 0x0098
207 #define GIC_VPE_COMPARE_LO_OFS 0x00a0
208 #define GIC_VPE_COMPARE_HI_OFS 0x00a4
209
210 #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
211 #define GIC_VPE_EIC_SS(intr) \
212 (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))
213
214 #define GIC_VPE_EIC_VEC_BASE 0x0800
215 #define GIC_VPE_EIC_VEC(intr) \
216 (GIC_VPE_EIC_VEC_BASE + (4 * intr))
217
218 #define GIC_VPE_TENABLE_NMI_OFS 0x1000
219 #define GIC_VPE_TENABLE_YQ_OFS 0x1004
220 #define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
221 #define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
222
223 /* User Mode Visible Section Register Map */
224 #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
225 #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
226
227 /* Masks */
228 #define GIC_SH_CONFIG_COUNTSTOP_SHF 28
229 #define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
230
231 #define GIC_SH_CONFIG_COUNTBITS_SHF 24
232 #define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
233
234 #define GIC_SH_CONFIG_NUMINTRS_SHF 16
235 #define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
236
237 #define GIC_SH_CONFIG_NUMVPES_SHF 0
238 #define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
239
240 #define GIC_SH_WEDGE_SET(intr) (intr | (0x1 << 31))
241 #define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
242
243 #define GIC_MAP_TO_PIN_SHF 31
244 #define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
245 #define GIC_MAP_TO_NMI_SHF 30
246 #define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
247 #define GIC_MAP_TO_YQ_SHF 29
248 #define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
249 #define GIC_MAP_SHF 0
250 #define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
251
252 /* GIC_VPE_CTL Masks */
253 #define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
254 #define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
255 #define GIC_VPE_CTL_TIMER_RTBL_SHF 1
256 #define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
257 #define GIC_VPE_CTL_EIC_MODE_SHF 0
258 #define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
259
260 /* GIC_VPE_PEND Masks */
261 #define GIC_VPE_PEND_WD_SHF 0
262 #define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
263 #define GIC_VPE_PEND_CMP_SHF 1
264 #define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
265 #define GIC_VPE_PEND_TIMER_SHF 2
266 #define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
267 #define GIC_VPE_PEND_PERFCOUNT_SHF 3
268 #define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
269 #define GIC_VPE_PEND_SWINT0_SHF 4
270 #define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
271 #define GIC_VPE_PEND_SWINT1_SHF 5
272 #define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
273
274 /* GIC_VPE_RMASK Masks */
275 #define GIC_VPE_RMASK_WD_SHF 0
276 #define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
277 #define GIC_VPE_RMASK_CMP_SHF 1
278 #define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
279 #define GIC_VPE_RMASK_TIMER_SHF 2
280 #define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
281 #define GIC_VPE_RMASK_PERFCNT_SHF 3
282 #define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
283 #define GIC_VPE_RMASK_SWINT0_SHF 4
284 #define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
285 #define GIC_VPE_RMASK_SWINT1_SHF 5
286 #define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
287
288 /* GIC_VPE_SMASK Masks */
289 #define GIC_VPE_SMASK_WD_SHF 0
290 #define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
291 #define GIC_VPE_SMASK_CMP_SHF 1
292 #define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
293 #define GIC_VPE_SMASK_TIMER_SHF 2
294 #define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
295 #define GIC_VPE_SMASK_PERFCNT_SHF 3
296 #define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
297 #define GIC_VPE_SMASK_SWINT0_SHF 4
298 #define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
299 #define GIC_VPE_SMASK_SWINT1_SHF 5
300 #define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
301
302 /*
303 * Set the Mapping of Interrupt X to a VPE.
304 */
305 #define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
306 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
307 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
308
309 struct gic_pcpu_mask {
310 DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
311 };
312
313 struct gic_pending_regs {
314 DECLARE_BITMAP(pending, GIC_NUM_INTRS);
315 };
316
317 struct gic_intrmask_regs {
318 DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
319 };
320
321 /*
322 * Interrupt Meta-data specification. The ipiflag helps
323 * in building ipi_map.
324 */
325 struct gic_intr_map {
326 unsigned int cpunum; /* Directed to this CPU */
327 #define GIC_UNUSED 0xdead /* Dummy data */
328 unsigned int pin; /* Directed to this Pin */
329 unsigned int polarity; /* Polarity : +/- */
330 unsigned int trigtype; /* Trigger : Edge/Levl */
331 unsigned int flags; /* Misc flags */
332 #define GIC_FLAG_IPI 0x01
333 #define GIC_FLAG_TRANSPARENT 0x02
334 };
335
336 /*
337 * This is only used in EIC mode. This helps to figure out which
338 * shared interrupts we need to process when we get a vector interrupt.
339 */
340 #define GIC_MAX_SHARED_INTR 0x5
341 struct gic_shared_intr_map {
342 unsigned int num_shared_intr;
343 unsigned int intr_list[GIC_MAX_SHARED_INTR];
344 unsigned int local_intr_mask;
345 };
346
347 /* GIC nomenclature for Core Interrupt Pins. */
348 #define GIC_CPU_INT0 0 /* Core Interrupt 2 */
349 #define GIC_CPU_INT1 1 /* . */
350 #define GIC_CPU_INT2 2 /* . */
351 #define GIC_CPU_INT3 3 /* . */
352 #define GIC_CPU_INT4 4 /* . */
353 #define GIC_CPU_INT5 5 /* Core Interrupt 7 */
354
355 /* Local GIC interrupts. */
356 #define GIC_INT_TMR (GIC_CPU_INT5)
357 #define GIC_INT_PERFCTR (GIC_CPU_INT5)
358
359 /* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
360 #define GIC_CPU_TO_VEC_OFFSET (2)
361
362 /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
363 #define GIC_PIN_TO_VEC_OFFSET (1)
364
365 #include <linux/clocksource.h>
366 #include <linux/irq.h>
367
368 extern unsigned int gic_present;
369 extern unsigned int gic_frequency;
370 extern unsigned long _gic_base;
371 extern unsigned int gic_irq_base;
372 extern unsigned int gic_irq_flags[];
373 extern struct gic_shared_intr_map gic_shared_intr_map[];
374
375 extern void gic_init(unsigned long gic_base_addr,
376 unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
377 unsigned int intrmap_size, unsigned int irqbase);
378 extern void gic_clocksource_init(unsigned int);
379 extern unsigned int gic_compare_int (void);
380 extern cycle_t gic_read_count(void);
381 extern cycle_t gic_read_compare(void);
382 extern void gic_write_compare(cycle_t cnt);
383 extern void gic_send_ipi(unsigned int intr);
384 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
385 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
386 extern void gic_bind_eic_interrupt(int irq, int set);
387 extern unsigned int gic_get_timer_pending(void);
388 extern unsigned int gic_get_int(void);
389 extern void gic_enable_interrupt(int irq_vec);
390 extern void gic_disable_interrupt(int irq_vec);
391 extern void gic_irq_ack(struct irq_data *d);
392 extern void gic_finish_irq(struct irq_data *d);
393 extern void gic_platform_init(int irqs, struct irq_chip *irq_controller);
394 #endif /* _ASM_GICREGS_H */
Linux with added FPC-III support