Linux 3.15-rc1
[linux/fpc-iii.git] / arch / mips / include / asm / timex.h
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1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 1998, 1999, 2003 by Ralf Baechle
7 */
8 #ifndef _ASM_TIMEX_H
9 #define _ASM_TIMEX_H
11 #ifdef __KERNEL__
13 #include <asm/cpu-features.h>
14 #include <asm/mipsregs.h>
15 #include <asm/cpu-type.h>
18 * This is the clock rate of the i8253 PIT. A MIPS system may not have
19 * a PIT by the symbol is used all over the kernel including some APIs.
20 * So keeping it defined to the number for the PIT is the only sane thing
21 * for now.
23 #define CLOCK_TICK_RATE 1193182
26 * Standard way to access the cycle counter.
27 * Currently only used on SMP for scheduling.
29 * Only the low 32 bits are available as a continuously counting entity.
30 * But this only means we'll force a reschedule every 8 seconds or so,
31 * which isn't an evil thing.
33 * We know that all SMP capable CPUs have cycle counters.
36 typedef unsigned int cycles_t;
39 * On R4000/R4400 before version 5.0 an erratum exists such that if the
40 * cycle counter is read in the exact moment that it is matching the
41 * compare register, no interrupt will be generated.
43 * There is a suggested workaround and also the erratum can't strike if
44 * the compare interrupt isn't being used as the clock source device.
45 * However for now the implementaton of this function doesn't get these
46 * fine details right.
48 static inline cycles_t get_cycles(void)
50 switch (boot_cpu_type()) {
51 case CPU_R4400PC:
52 case CPU_R4400SC:
53 case CPU_R4400MC:
54 if ((read_c0_prid() & 0xff) >= 0x0050)
55 return read_c0_count();
56 break;
58 case CPU_R4000PC:
59 case CPU_R4000SC:
60 case CPU_R4000MC:
61 break;
63 default:
64 if (cpu_has_counter)
65 return read_c0_count();
66 break;
69 return 0; /* no usable counter */
72 #endif /* __KERNEL__ */
74 #endif /* _ASM_TIMEX_H */