arch/mips/kernel/sync-r4k.c

   1 /*
   2  * Count register synchronisation.
   3  *
   4  * All CPUs will have their count registers synchronised to the CPU0 next time
   5  * value. This can cause a small timewarp for CPU0. All other CPU's should
   6  * not have done anything significant (but they may have had interrupts
   7  * enabled briefly - prom_smp_finish() should not be responsible for enabling
   8  * interrupts...)
   9  *
  10  * FIXME: broken for SMTC
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/irqflags.h>
  15 #include <linux/cpumask.h>
  16
  17 #include <asm/r4k-timer.h>
  18 #include <linux/atomic.h>
  19 #include <asm/barrier.h>
  20 #include <asm/mipsregs.h>
  21
  22 static atomic_t count_start_flag = ATOMIC_INIT(0);
  23 static atomic_t count_count_start = ATOMIC_INIT(0);
  24 static atomic_t count_count_stop = ATOMIC_INIT(0);
  25 static atomic_t count_reference = ATOMIC_INIT(0);
  26
  27 #define COUNTON 100
  28 #define NR_LOOPS 5
  29
  30 void synchronise_count_master(int cpu)
  31 {
  32         int i;
  33         unsigned long flags;
  34         unsigned int initcount;
  35
  36 #ifdef CONFIG_MIPS_MT_SMTC
  37         /*
  38          * SMTC needs to synchronise per VPE, not per CPU
  39          * ignore for now
  40          */
  41         return;
  42 #endif
  43
  44         printk(KERN_INFO "Synchronize counters for CPU %u: ", cpu);
  45
  46         local_irq_save(flags);
  47
  48         /*
  49          * Notify the slaves that it's time to start
  50          */
  51         atomic_set(&count_reference, read_c0_count());
  52         atomic_set(&count_start_flag, cpu);
  53         smp_wmb();
  54
  55         /* Count will be initialised to current timer for all CPU's */
  56         initcount = read_c0_count();
  57
  58         /*
  59          * We loop a few times to get a primed instruction cache,
  60          * then the last pass is more or less synchronised and
  61          * the master and slaves each set their cycle counters to a known
  62          * value all at once. This reduces the chance of having random offsets
  63          * between the processors, and guarantees that the maximum
  64          * delay between the cycle counters is never bigger than
  65          * the latency of information-passing (cachelines) between
  66          * two CPUs.
  67          */
  68
  69         for (i = 0; i < NR_LOOPS; i++) {
  70                 /* slaves loop on '!= 2' */
  71                 while (atomic_read(&count_count_start) != 1)
  72                         mb();
  73                 atomic_set(&count_count_stop, 0);
  74                 smp_wmb();
  75
  76                 /* this lets the slaves write their count register */
  77                 atomic_inc(&count_count_start);
  78
  79                 /*
  80                  * Everyone initialises count in the last loop:
  81                  */
  82                 if (i == NR_LOOPS-1)
  83                         write_c0_count(initcount);
  84
  85                 /*
  86                  * Wait for all slaves to leave the synchronization point:
  87                  */
  88                 while (atomic_read(&count_count_stop) != 1)
  89                         mb();
  90                 atomic_set(&count_count_start, 0);
  91                 smp_wmb();
  92                 atomic_inc(&count_count_stop);
  93         }
  94         /* Arrange for an interrupt in a short while */
  95         write_c0_compare(read_c0_count() + COUNTON);
  96         atomic_set(&count_start_flag, 0);
  97
  98         local_irq_restore(flags);
  99
 100         /*
 101          * i386 code reported the skew here, but the
 102          * count registers were almost certainly out of sync
 103          * so no point in alarming people
 104          */
 105         printk("done.\n");
 106 }
 107
 108 void synchronise_count_slave(int cpu)
 109 {
 110         int i;
 111         unsigned int initcount;
 112
 113 #ifdef CONFIG_MIPS_MT_SMTC
 114         /*
 115          * SMTC needs to synchronise per VPE, not per CPU
 116          * ignore for now
 117          */
 118         return;
 119 #endif
 120
 121         /*
 122          * Not every cpu is online at the time this gets called,
 123          * so we first wait for the master to say everyone is ready
 124          */
 125
 126         while (atomic_read(&count_start_flag) != cpu)
 127                 mb();
 128
 129         /* Count will be initialised to next expire for all CPU's */
 130         initcount = atomic_read(&count_reference);
 131
 132         for (i = 0; i < NR_LOOPS; i++) {
 133                 atomic_inc(&count_count_start);
 134                 while (atomic_read(&count_count_start) != 2)
 135                         mb();
 136
 137                 /*
 138                  * Everyone initialises count in the last loop:
 139                  */
 140                 if (i == NR_LOOPS-1)
 141                         write_c0_count(initcount);
 142
 143                 atomic_inc(&count_count_stop);
 144                 while (atomic_read(&count_count_stop) != 2)
 145                         mb();
 146         }
 147         /* Arrange for an interrupt in a short while */
 148         write_c0_compare(read_c0_count() + COUNTON);
 149 }
 150 #undef NR_LOOPS