arch/mips/mti-sead3/sead3-init.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   7  */
   8 #include <linux/init.h>
   9 #include <linux/io.h>
  10
  11 #include <asm/bootinfo.h>
  12 #include <asm/cacheflush.h>
  13 #include <asm/traps.h>
  14 #include <asm/mips-boards/generic.h>
  15 #include <asm/fw/fw.h>
  16
  17 extern char except_vec_nmi;
  18 extern char except_vec_ejtag_debug;
  19
  20 #ifdef CONFIG_SERIAL_8250_CONSOLE
  21 static void __init console_config(void)
  22 {
  23         char console_string[40];
  24         int baud = 0;
  25         char parity = '\0', bits = '\0', flow = '\0';
  26         char *s;
  27
  28         if ((strstr(fw_getcmdline(), "console=")) == NULL) {
  29                 s = fw_getenv("modetty0");
  30                 if (s) {
  31                         while (*s >= '0' && *s <= '9')
  32                                 baud = baud*10 + *s++ - '0';
  33                         if (*s == ',')
  34                                 s++;
  35                         if (*s)
  36                                 parity = *s++;
  37                         if (*s == ',')
  38                                 s++;
  39                         if (*s)
  40                                 bits = *s++;
  41                         if (*s == ',')
  42                                 s++;
  43                         if (*s == 'h')
  44                                 flow = 'r';
  45                 }
  46                 if (baud == 0)
  47                         baud = 38400;
  48                 if (parity != 'n' && parity != 'o' && parity != 'e')
  49                         parity = 'n';
  50                 if (bits != '7' && bits != '8')
  51                         bits = '8';
  52                 if (flow == '\0')
  53                         flow = 'r';
  54                 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud,
  55                         parity, bits, flow);
  56                 strcat(fw_getcmdline(), console_string);
  57         }
  58 }
  59 #endif
  60
  61 static void __init mips_nmi_setup(void)
  62 {
  63         void *base;
  64
  65         base = cpu_has_veic ?
  66                 (void *)(CAC_BASE + 0xa80) :
  67                 (void *)(CAC_BASE + 0x380);
  68 #ifdef CONFIG_CPU_MICROMIPS
  69         /*
  70          * Decrement the exception vector address by one for microMIPS.
  71          */
  72         memcpy(base, (&except_vec_nmi - 1), 0x80);
  73
  74         /*
  75          * This is a hack. We do not know if the boot loader was built with
  76          * microMIPS instructions or not. If it was not, the NMI exception
  77          * code at 0x80000a80 will be taken in MIPS32 mode. The hand coded
  78          * assembly below forces us into microMIPS mode if we are a pure
  79          * microMIPS kernel. The assembly instructions are:
  80          *
  81          *  3C1A8000   lui       k0,0x8000
  82          *  375A0381   ori       k0,k0,0x381
  83          *  03400008   jr        k0
  84          *  00000000   nop
  85          *
  86          * The mode switch occurs by jumping to the unaligned exception
  87          * vector address at 0x80000381 which would have been 0x80000380
  88          * in MIPS32 mode. The jump to the unaligned address transitions
  89          * us into microMIPS mode.
  90          */
  91         if (!cpu_has_veic) {
  92                 void *base2 = (void *)(CAC_BASE + 0xa80);
  93                 *((unsigned int *)base2) = 0x3c1a8000;
  94                 *((unsigned int *)base2 + 1) = 0x375a0381;
  95                 *((unsigned int *)base2 + 2) = 0x03400008;
  96                 *((unsigned int *)base2 + 3) = 0x00000000;
  97                 flush_icache_range((unsigned long)base2,
  98                         (unsigned long)base2 + 0x10);
  99         }
 100 #else
 101         memcpy(base, &except_vec_nmi, 0x80);
 102 #endif
 103         flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
 104 }
 105
 106 static void __init mips_ejtag_setup(void)
 107 {
 108         void *base;
 109
 110         base = cpu_has_veic ?
 111                 (void *)(CAC_BASE + 0xa00) :
 112                 (void *)(CAC_BASE + 0x300);
 113 #ifdef CONFIG_CPU_MICROMIPS
 114         /* Deja vu... */
 115         memcpy(base, (&except_vec_ejtag_debug - 1), 0x80);
 116         if (!cpu_has_veic) {
 117                 void *base2 = (void *)(CAC_BASE + 0xa00);
 118                 *((unsigned int *)base2) = 0x3c1a8000;
 119                 *((unsigned int *)base2 + 1) = 0x375a0301;
 120                 *((unsigned int *)base2 + 2) = 0x03400008;
 121                 *((unsigned int *)base2 + 3) = 0x00000000;
 122                 flush_icache_range((unsigned long)base2,
 123                         (unsigned long)base2 + 0x10);
 124         }
 125 #else
 126         memcpy(base, &except_vec_ejtag_debug, 0x80);
 127 #endif
 128         flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
 129 }
 130
 131 void __init prom_init(void)
 132 {
 133         board_nmi_handler_setup = mips_nmi_setup;
 134         board_ejtag_handler_setup = mips_ejtag_setup;
 135
 136         fw_init_cmdline();
 137 #ifdef CONFIG_EARLY_PRINTK
 138         if ((strstr(fw_getcmdline(), "console=ttyS0")) != NULL)
 139                 fw_init_early_console(0);
 140         else if ((strstr(fw_getcmdline(), "console=ttyS1")) != NULL)
 141                 fw_init_early_console(1);
 142 #endif
 143 #ifdef CONFIG_SERIAL_8250_CONSOLE
 144         if ((strstr(fw_getcmdline(), "console=")) == NULL)
 145                 strcat(fw_getcmdline(), " console=ttyS0,38400n8r");
 146         console_config();
 147 #endif
 148 }
 149
 150 void prom_free_prom_memory(void)
 151 {
 152 }