arch/mips/pci/pci-ar71xx.c

   1 /*
   2  *  Atheros AR71xx PCI host controller driver
   3  *
   4  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/resource.h>
  15 #include <linux/types.h>
  16 #include <linux/delay.h>
  17 #include <linux/bitops.h>
  18 #include <linux/pci.h>
  19 #include <linux/pci_regs.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23
  24 #include <asm/mach-ath79/ar71xx_regs.h>
  25 #include <asm/mach-ath79/ath79.h>
  26
  27 #define AR71XX_PCI_REG_CRP_AD_CBE       0x00
  28 #define AR71XX_PCI_REG_CRP_WRDATA       0x04
  29 #define AR71XX_PCI_REG_CRP_RDDATA       0x08
  30 #define AR71XX_PCI_REG_CFG_AD           0x0c
  31 #define AR71XX_PCI_REG_CFG_CBE          0x10
  32 #define AR71XX_PCI_REG_CFG_WRDATA       0x14
  33 #define AR71XX_PCI_REG_CFG_RDDATA       0x18
  34 #define AR71XX_PCI_REG_PCI_ERR          0x1c
  35 #define AR71XX_PCI_REG_PCI_ERR_ADDR     0x20
  36 #define AR71XX_PCI_REG_AHB_ERR          0x24
  37 #define AR71XX_PCI_REG_AHB_ERR_ADDR     0x28
  38
  39 #define AR71XX_PCI_CRP_CMD_WRITE        0x00010000
  40 #define AR71XX_PCI_CRP_CMD_READ         0x00000000
  41 #define AR71XX_PCI_CFG_CMD_READ         0x0000000a
  42 #define AR71XX_PCI_CFG_CMD_WRITE        0x0000000b
  43
  44 #define AR71XX_PCI_INT_CORE             BIT(4)
  45 #define AR71XX_PCI_INT_DEV2             BIT(2)
  46 #define AR71XX_PCI_INT_DEV1             BIT(1)
  47 #define AR71XX_PCI_INT_DEV0             BIT(0)
  48
  49 #define AR71XX_PCI_IRQ_COUNT            5
  50
  51 struct ar71xx_pci_controller {
  52         void __iomem *cfg_base;
  53         spinlock_t lock;
  54         int irq;
  55         int irq_base;
  56         struct pci_controller pci_ctrl;
  57         struct resource io_res;
  58         struct resource mem_res;
  59 };
  60
  61 /* Byte lane enable bits */
  62 static const u8 ar71xx_pci_ble_table[4][4] = {
  63         {0x0, 0xf, 0xf, 0xf},
  64         {0xe, 0xd, 0xb, 0x7},
  65         {0xc, 0xf, 0x3, 0xf},
  66         {0xf, 0xf, 0xf, 0xf},
  67 };
  68
  69 static const u32 ar71xx_pci_read_mask[8] = {
  70         0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
  71 };
  72
  73 static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
  74 {
  75         u32 t;
  76
  77         t = ar71xx_pci_ble_table[size & 3][where & 3];
  78         BUG_ON(t == 0xf);
  79         t <<= (local) ? 20 : 4;
  80
  81         return t;
  82 }
  83
  84 static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
  85                                       int where)
  86 {
  87         u32 ret;
  88
  89         if (!bus->number) {
  90                 /* type 0 */
  91                 ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
  92                       (where & ~3);
  93         } else {
  94                 /* type 1 */
  95                 ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) |
  96                       (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
  97         }
  98
  99         return ret;
 100 }
 101
 102 static inline struct ar71xx_pci_controller *
 103 pci_bus_to_ar71xx_controller(struct pci_bus *bus)
 104 {
 105         struct pci_controller *hose;
 106
 107         hose = (struct pci_controller *) bus->sysdata;
 108         return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
 109 }
 110
 111 static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
 112 {
 113         void __iomem *base = apc->cfg_base;
 114         u32 pci_err;
 115         u32 ahb_err;
 116
 117         pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
 118         if (pci_err) {
 119                 if (!quiet) {
 120                         u32 addr;
 121
 122                         addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
 123                         pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
 124                                 "PCI", pci_err, addr);
 125                 }
 126
 127                 /* clear PCI error status */
 128                 __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
 129         }
 130
 131         ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
 132         if (ahb_err) {
 133                 if (!quiet) {
 134                         u32 addr;
 135
 136                         addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
 137                         pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
 138                                 "AHB", ahb_err, addr);
 139                 }
 140
 141                 /* clear AHB error status */
 142                 __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);
 143         }
 144
 145         return !!(ahb_err | pci_err);
 146 }
 147
 148 static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
 149                                           int where, int size, u32 value)
 150 {
 151         void __iomem *base = apc->cfg_base;
 152         u32 ad_cbe;
 153
 154         value = value << (8 * (where & 3));
 155
 156         ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3);
 157         ad_cbe |= ar71xx_pci_get_ble(where, size, 1);
 158
 159         __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);
 160         __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);
 161 }
 162
 163 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
 164                                          unsigned int devfn,
 165                                          int where, int size, u32 cmd)
 166 {
 167         struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
 168         void __iomem *base = apc->cfg_base;
 169         u32 addr;
 170
 171         addr = ar71xx_pci_bus_addr(bus, devfn, where);
 172
 173         __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);
 174         __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
 175                      base + AR71XX_PCI_REG_CFG_CBE);
 176
 177         return ar71xx_pci_check_error(apc, 1);
 178 }
 179
 180 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 181                                   int where, int size, u32 *value)
 182 {
 183         struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
 184         void __iomem *base = apc->cfg_base;
 185         unsigned long flags;
 186         u32 data;
 187         int err;
 188         int ret;
 189
 190         ret = PCIBIOS_SUCCESSFUL;
 191         data = ~0;
 192
 193         spin_lock_irqsave(&apc->lock, flags);
 194
 195         err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 196                                      AR71XX_PCI_CFG_CMD_READ);
 197         if (err)
 198                 ret = PCIBIOS_DEVICE_NOT_FOUND;
 199         else
 200                 data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
 201
 202         spin_unlock_irqrestore(&apc->lock, flags);
 203
 204         *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
 205
 206         return ret;
 207 }
 208
 209 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 210                                    int where, int size, u32 value)
 211 {
 212         struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
 213         void __iomem *base = apc->cfg_base;
 214         unsigned long flags;
 215         int err;
 216         int ret;
 217
 218         value = value << (8 * (where & 3));
 219         ret = PCIBIOS_SUCCESSFUL;
 220
 221         spin_lock_irqsave(&apc->lock, flags);
 222
 223         err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 224                                      AR71XX_PCI_CFG_CMD_WRITE);
 225         if (err)
 226                 ret = PCIBIOS_DEVICE_NOT_FOUND;
 227         else
 228                 __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
 229
 230         spin_unlock_irqrestore(&apc->lock, flags);
 231
 232         return ret;
 233 }
 234
 235 static struct pci_ops ar71xx_pci_ops = {
 236         .read   = ar71xx_pci_read_config,
 237         .write  = ar71xx_pci_write_config,
 238 };
 239
 240 static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 241 {
 242         struct ar71xx_pci_controller *apc;
 243         void __iomem *base = ath79_reset_base;
 244         u32 pending;
 245
 246         apc = irq_get_handler_data(irq);
 247
 248         pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
 249                   __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 250
 251         if (pending & AR71XX_PCI_INT_DEV0)
 252                 generic_handle_irq(apc->irq_base + 0);
 253
 254         else if (pending & AR71XX_PCI_INT_DEV1)
 255                 generic_handle_irq(apc->irq_base + 1);
 256
 257         else if (pending & AR71XX_PCI_INT_DEV2)
 258                 generic_handle_irq(apc->irq_base + 2);
 259
 260         else if (pending & AR71XX_PCI_INT_CORE)
 261                 generic_handle_irq(apc->irq_base + 4);
 262
 263         else
 264                 spurious_interrupt();
 265 }
 266
 267 static void ar71xx_pci_irq_unmask(struct irq_data *d)
 268 {
 269         struct ar71xx_pci_controller *apc;
 270         unsigned int irq;
 271         void __iomem *base = ath79_reset_base;
 272         u32 t;
 273
 274         apc = irq_data_get_irq_chip_data(d);
 275         irq = d->irq - apc->irq_base;
 276
 277         t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 278         __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 279
 280         /* flush write */
 281         __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 282 }
 283
 284 static void ar71xx_pci_irq_mask(struct irq_data *d)
 285 {
 286         struct ar71xx_pci_controller *apc;
 287         unsigned int irq;
 288         void __iomem *base = ath79_reset_base;
 289         u32 t;
 290
 291         apc = irq_data_get_irq_chip_data(d);
 292         irq = d->irq - apc->irq_base;
 293
 294         t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 295         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 296
 297         /* flush write */
 298         __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 299 }
 300
 301 static struct irq_chip ar71xx_pci_irq_chip = {
 302         .name           = "AR71XX PCI",
 303         .irq_mask       = ar71xx_pci_irq_mask,
 304         .irq_unmask     = ar71xx_pci_irq_unmask,
 305         .irq_mask_ack   = ar71xx_pci_irq_mask,
 306 };
 307
 308 static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
 309 {
 310         void __iomem *base = ath79_reset_base;
 311         int i;
 312
 313         __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 314         __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
 315
 316         BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
 317
 318         apc->irq_base = ATH79_PCI_IRQ_BASE;
 319         for (i = apc->irq_base;
 320              i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
 321                 irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
 322                                          handle_level_irq);
 323                 irq_set_chip_data(i, apc);
 324         }
 325
 326         irq_set_handler_data(apc->irq, apc);
 327         irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
 328 }
 329
 330 static void ar71xx_pci_reset(void)
 331 {
 332         void __iomem *ddr_base = ath79_ddr_base;
 333
 334         ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
 335         mdelay(100);
 336
 337         ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
 338         mdelay(100);
 339
 340         __raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
 341         __raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
 342         __raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
 343         __raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
 344         __raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
 345         __raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
 346         __raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
 347         __raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);
 348
 349         mdelay(100);
 350 }
 351
 352 static int ar71xx_pci_probe(struct platform_device *pdev)
 353 {
 354         struct ar71xx_pci_controller *apc;
 355         struct resource *res;
 356         u32 t;
 357
 358         apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
 359                            GFP_KERNEL);
 360         if (!apc)
 361                 return -ENOMEM;
 362
 363         spin_lock_init(&apc->lock);
 364
 365         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
 366         apc->cfg_base = devm_ioremap_resource(&pdev->dev, res);
 367         if (IS_ERR(apc->cfg_base))
 368                 return PTR_ERR(apc->cfg_base);
 369
 370         apc->irq = platform_get_irq(pdev, 0);
 371         if (apc->irq < 0)
 372                 return -EINVAL;
 373
 374         res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
 375         if (!res)
 376                 return -EINVAL;
 377
 378         apc->io_res.parent = res;
 379         apc->io_res.name = "PCI IO space";
 380         apc->io_res.start = res->start;
 381         apc->io_res.end = res->end;
 382         apc->io_res.flags = IORESOURCE_IO;
 383
 384         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
 385         if (!res)
 386                 return -EINVAL;
 387
 388         apc->mem_res.parent = res;
 389         apc->mem_res.name = "PCI memory space";
 390         apc->mem_res.start = res->start;
 391         apc->mem_res.end = res->end;
 392         apc->mem_res.flags = IORESOURCE_MEM;
 393
 394         ar71xx_pci_reset();
 395
 396         /* setup COMMAND register */
 397         t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
 398           | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
 399         ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
 400
 401         /* clear bus errors */
 402         ar71xx_pci_check_error(apc, 1);
 403
 404         ar71xx_pci_irq_init(apc);
 405
 406         apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
 407         apc->pci_ctrl.mem_resource = &apc->mem_res;
 408         apc->pci_ctrl.io_resource = &apc->io_res;
 409
 410         register_pci_controller(&apc->pci_ctrl);
 411
 412         return 0;
 413 }
 414
 415 static struct platform_driver ar71xx_pci_driver = {
 416         .probe = ar71xx_pci_probe,
 417         .driver = {
 418                 .name = "ar71xx-pci",
 419                 .owner = THIS_MODULE,
 420         },
 421 };
 422
 423 static int __init ar71xx_pci_init(void)
 424 {
 425         return platform_driver_register(&ar71xx_pci_driver);
 426 }
 427
 428 postcore_initcall(ar71xx_pci_init);