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Linux 3.15-rc1
[linux/fpc-iii.git] / arch / mips / sgi-ip32 / ip32-irq.c
blobe0c7d9e142fa8c3c8b68f86c5990eae2d07506b5
1 /*
2 * Code to handle IP32 IRQs
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Harald Koerfgen
9 * Copyright (C) 2001 Keith M Wesolowski
10 */
11 #include <linux/init.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/bitops.h>
17 #include <linux/kernel.h>
18 #include <linux/mm.h>
19 #include <linux/random.h>
20 #include <linux/sched.h>
21
22 #include <asm/irq_cpu.h>
23 #include <asm/mipsregs.h>
24 #include <asm/signal.h>
25 #include <asm/time.h>
26 #include <asm/ip32/crime.h>
27 #include <asm/ip32/mace.h>
28 #include <asm/ip32/ip32_ints.h>
29
30 /* issue a PIO read to make sure no PIO writes are pending */
31 static void inline flush_crime_bus(void)
32 {
33 crime->control;
34 }
35
36 static void inline flush_mace_bus(void)
37 {
38 mace->perif.ctrl.misc;
39 }
40
41 /*
42 * O2 irq map
43 *
44 * IP0 -> software (ignored)
45 * IP1 -> software (ignored)
46 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
47 * IP3 -> (irq1) X unknown
48 * IP4 -> (irq2) X unknown
49 * IP5 -> (irq3) X unknown
50 * IP6 -> (irq4) X unknown
51 * IP7 -> (irq5) 7 CPU count/compare timer (system timer)
52 *
53 * crime: (C)
54 *
55 * CRIME_INT_STAT 31:0:
56 *
57 * 0 -> 8 Video in 1
58 * 1 -> 9 Video in 2
59 * 2 -> 10 Video out
60 * 3 -> 11 Mace ethernet
61 * 4 -> S SuperIO sub-interrupt
62 * 5 -> M Miscellaneous sub-interrupt
63 * 6 -> A Audio sub-interrupt
64 * 7 -> 15 PCI bridge errors
65 * 8 -> 16 PCI SCSI aic7xxx 0
66 * 9 -> 17 PCI SCSI aic7xxx 1
67 * 10 -> 18 PCI slot 0
68 * 11 -> 19 unused (PCI slot 1)
69 * 12 -> 20 unused (PCI slot 2)
70 * 13 -> 21 unused (PCI shared 0)
71 * 14 -> 22 unused (PCI shared 1)
72 * 15 -> 23 unused (PCI shared 2)
73 * 16 -> 24 GBE0 (E)
74 * 17 -> 25 GBE1 (E)
75 * 18 -> 26 GBE2 (E)
76 * 19 -> 27 GBE3 (E)
77 * 20 -> 28 CPU errors
78 * 21 -> 29 Memory errors
79 * 22 -> 30 RE empty edge (E)
80 * 23 -> 31 RE full edge (E)
81 * 24 -> 32 RE idle edge (E)
82 * 25 -> 33 RE empty level
83 * 26 -> 34 RE full level
84 * 27 -> 35 RE idle level
85 * 28 -> 36 unused (software 0) (E)
86 * 29 -> 37 unused (software 1) (E)
87 * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
88 * 31 -> 39 VICE
89 *
90 * S, M, A: Use the MACE ISA interrupt register
91 * MACE_ISA_INT_STAT 31:0
92 *
93 * 0-7 -> 40-47 Audio
94 * 8 -> 48 RTC
95 * 9 -> 49 Keyboard
96 * 10 -> X Keyboard polled
97 * 11 -> 51 Mouse
98 * 12 -> X Mouse polled
99 * 13-15 -> 53-55 Count/compare timers
100 * 16-19 -> 56-59 Parallel (16 E)
101 * 20-25 -> 60-62 Serial 1 (22 E)
102 * 26-31 -> 66-71 Serial 2 (28 E)
103 *
104 * Note that this means IRQs 12-14, 50, and 52 do not exist. This is a
105 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
106 * is quite different anyway.
107 */
108
109 /* Some initial interrupts to set up */
110 extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
111 extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
112
113 static struct irqaction memerr_irq = {
114 .handler = crime_memerr_intr,
115 .name = "CRIME memory error",
116 };
117
118 static struct irqaction cpuerr_irq = {
119 .handler = crime_cpuerr_intr,
120 .name = "CRIME CPU error",
121 };
122
123 /*
124 * This is for pure CRIME interrupts - ie not MACE. The advantage?
125 * We get to split the register in half and do faster lookups.
126 */
127
128 static uint64_t crime_mask;
129
130 static inline void crime_enable_irq(struct irq_data *d)
131 {
132 unsigned int bit = d->irq - CRIME_IRQ_BASE;
133
134 crime_mask |= 1 << bit;
135 crime->imask = crime_mask;
136 }
137
138 static inline void crime_disable_irq(struct irq_data *d)
139 {
140 unsigned int bit = d->irq - CRIME_IRQ_BASE;
141
142 crime_mask &= ~(1 << bit);
143 crime->imask = crime_mask;
144 flush_crime_bus();
145 }
146
147 static struct irq_chip crime_level_interrupt = {
148 .name = "IP32 CRIME",
149 .irq_mask = crime_disable_irq,
150 .irq_unmask = crime_enable_irq,
151 };
152
153 static void crime_edge_mask_and_ack_irq(struct irq_data *d)
154 {
155 unsigned int bit = d->irq - CRIME_IRQ_BASE;
156 uint64_t crime_int;
157
158 /* Edge triggered interrupts must be cleared. */
159 crime_int = crime->hard_int;
160 crime_int &= ~(1 << bit);
161 crime->hard_int = crime_int;
162
163 crime_disable_irq(d);
164 }
165
166 static struct irq_chip crime_edge_interrupt = {
167 .name = "IP32 CRIME",
168 .irq_ack = crime_edge_mask_and_ack_irq,
169 .irq_mask = crime_disable_irq,
170 .irq_mask_ack = crime_edge_mask_and_ack_irq,
171 .irq_unmask = crime_enable_irq,
172 };
173
174 /*
175 * This is for MACE PCI interrupts. We can decrease bus traffic by masking
176 * as close to the source as possible. This also means we can take the
177 * next chunk of the CRIME register in one piece.
178 */
179
180 static unsigned long macepci_mask;
181
182 static void enable_macepci_irq(struct irq_data *d)
183 {
184 macepci_mask |= MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
185 mace->pci.control = macepci_mask;
186 crime_mask |= 1 << (d->irq - CRIME_IRQ_BASE);
187 crime->imask = crime_mask;
188 }
189
190 static void disable_macepci_irq(struct irq_data *d)
191 {
192 crime_mask &= ~(1 << (d->irq - CRIME_IRQ_BASE));
193 crime->imask = crime_mask;
194 flush_crime_bus();
195 macepci_mask &= ~MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
196 mace->pci.control = macepci_mask;
197 flush_mace_bus();
198 }
199
200 static struct irq_chip ip32_macepci_interrupt = {
201 .name = "IP32 MACE PCI",
202 .irq_mask = disable_macepci_irq,
203 .irq_unmask = enable_macepci_irq,
204 };
205
206 /* This is used for MACE ISA interrupts. That means bits 4-6 in the
207 * CRIME register.
208 */
209
210 #define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \
211 MACEISA_AUDIO_SC_INT | \
212 MACEISA_AUDIO1_DMAT_INT | \
213 MACEISA_AUDIO1_OF_INT | \
214 MACEISA_AUDIO2_DMAT_INT | \
215 MACEISA_AUDIO2_MERR_INT | \
216 MACEISA_AUDIO3_DMAT_INT | \
217 MACEISA_AUDIO3_MERR_INT)
218 #define MACEISA_MISC_INT (MACEISA_RTC_INT | \
219 MACEISA_KEYB_INT | \
220 MACEISA_KEYB_POLL_INT | \
221 MACEISA_MOUSE_INT | \
222 MACEISA_MOUSE_POLL_INT | \
223 MACEISA_TIMER0_INT | \
224 MACEISA_TIMER1_INT | \
225 MACEISA_TIMER2_INT)
226 #define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \
227 MACEISA_PAR_CTXA_INT | \
228 MACEISA_PAR_CTXB_INT | \
229 MACEISA_PAR_MERR_INT | \
230 MACEISA_SERIAL1_INT | \
231 MACEISA_SERIAL1_TDMAT_INT | \
232 MACEISA_SERIAL1_TDMAPR_INT | \
233 MACEISA_SERIAL1_TDMAME_INT | \
234 MACEISA_SERIAL1_RDMAT_INT | \
235 MACEISA_SERIAL1_RDMAOR_INT | \
236 MACEISA_SERIAL2_INT | \
237 MACEISA_SERIAL2_TDMAT_INT | \
238 MACEISA_SERIAL2_TDMAPR_INT | \
239 MACEISA_SERIAL2_TDMAME_INT | \
240 MACEISA_SERIAL2_RDMAT_INT | \
241 MACEISA_SERIAL2_RDMAOR_INT)
242
243 static unsigned long maceisa_mask;
244
245 static void enable_maceisa_irq(struct irq_data *d)
246 {
247 unsigned int crime_int = 0;
248
249 pr_debug("maceisa enable: %u\n", d->irq);
250
251 switch (d->irq) {
252 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
253 crime_int = MACE_AUDIO_INT;
254 break;
255 case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
256 crime_int = MACE_MISC_INT;
257 break;
258 case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
259 crime_int = MACE_SUPERIO_INT;
260 break;
261 }
262 pr_debug("crime_int %08x enabled\n", crime_int);
263 crime_mask |= crime_int;
264 crime->imask = crime_mask;
265 maceisa_mask |= 1 << (d->irq - MACEISA_AUDIO_SW_IRQ);
266 mace->perif.ctrl.imask = maceisa_mask;
267 }
268
269 static void disable_maceisa_irq(struct irq_data *d)
270 {
271 unsigned int crime_int = 0;
272
273 maceisa_mask &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
274 if (!(maceisa_mask & MACEISA_AUDIO_INT))
275 crime_int |= MACE_AUDIO_INT;
276 if (!(maceisa_mask & MACEISA_MISC_INT))
277 crime_int |= MACE_MISC_INT;
278 if (!(maceisa_mask & MACEISA_SUPERIO_INT))
279 crime_int |= MACE_SUPERIO_INT;
280 crime_mask &= ~crime_int;
281 crime->imask = crime_mask;
282 flush_crime_bus();
283 mace->perif.ctrl.imask = maceisa_mask;
284 flush_mace_bus();
285 }
286
287 static void mask_and_ack_maceisa_irq(struct irq_data *d)
288 {
289 unsigned long mace_int;
290
291 /* edge triggered */
292 mace_int = mace->perif.ctrl.istat;
293 mace_int &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
294 mace->perif.ctrl.istat = mace_int;
295
296 disable_maceisa_irq(d);
297 }
298
299 static struct irq_chip ip32_maceisa_level_interrupt = {
300 .name = "IP32 MACE ISA",
301 .irq_mask = disable_maceisa_irq,
302 .irq_unmask = enable_maceisa_irq,
303 };
304
305 static struct irq_chip ip32_maceisa_edge_interrupt = {
306 .name = "IP32 MACE ISA",
307 .irq_ack = mask_and_ack_maceisa_irq,
308 .irq_mask = disable_maceisa_irq,
309 .irq_mask_ack = mask_and_ack_maceisa_irq,
310 .irq_unmask = enable_maceisa_irq,
311 };
312
313 /* This is used for regular non-ISA, non-PCI MACE interrupts. That means
314 * bits 0-3 and 7 in the CRIME register.
315 */
316
317 static void enable_mace_irq(struct irq_data *d)
318 {
319 unsigned int bit = d->irq - CRIME_IRQ_BASE;
320
321 crime_mask |= (1 << bit);
322 crime->imask = crime_mask;
323 }
324
325 static void disable_mace_irq(struct irq_data *d)
326 {
327 unsigned int bit = d->irq - CRIME_IRQ_BASE;
328
329 crime_mask &= ~(1 << bit);
330 crime->imask = crime_mask;
331 flush_crime_bus();
332 }
333
334 static struct irq_chip ip32_mace_interrupt = {
335 .name = "IP32 MACE",
336 .irq_mask = disable_mace_irq,
337 .irq_unmask = enable_mace_irq,
338 };
339
340 static void ip32_unknown_interrupt(void)
341 {
342 printk("Unknown interrupt occurred!\n");
343 printk("cp0_status: %08x\n", read_c0_status());
344 printk("cp0_cause: %08x\n", read_c0_cause());
345 printk("CRIME intr mask: %016lx\n", crime->imask);
346 printk("CRIME intr status: %016lx\n", crime->istat);
347 printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
348 printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
349 printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
350 printk("MACE PCI control register: %08x\n", mace->pci.control);
351
352 printk("Register dump:\n");
353 show_regs(get_irq_regs());
354
355 printk("Please mail this report to linux-mips@linux-mips.org\n");
356 printk("Spinning...");
357 while(1) ;
358 }
359
360 /* CRIME 1.1 appears to deliver all interrupts to this one pin. */
361 /* change this to loop over all edge-triggered irqs, exception masked out ones */
362 static void ip32_irq0(void)
363 {
364 uint64_t crime_int;
365 int irq = 0;
366
367 /*
368 * Sanity check interrupt numbering enum.
369 * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
370 * chained.
371 */
372 BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
373 BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
374
375 crime_int = crime->istat & crime_mask;
376
377 /* crime sometime delivers spurious interrupts, ignore them */
378 if (unlikely(crime_int == 0))
379 return;
380
381 irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
382
383 if (crime_int & CRIME_MACEISA_INT_MASK) {
384 unsigned long mace_int = mace->perif.ctrl.istat;
385 irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
386 }
387
388 pr_debug("*irq %u*\n", irq);
389 do_IRQ(irq);
390 }
391
392 static void ip32_irq1(void)
393 {
394 ip32_unknown_interrupt();
395 }
396
397 static void ip32_irq2(void)
398 {
399 ip32_unknown_interrupt();
400 }
401
402 static void ip32_irq3(void)
403 {
404 ip32_unknown_interrupt();
405 }
406
407 static void ip32_irq4(void)
408 {
409 ip32_unknown_interrupt();
410 }
411
412 static void ip32_irq5(void)
413 {
414 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
415 }
416
417 asmlinkage void plat_irq_dispatch(void)
418 {
419 unsigned int pending = read_c0_status() & read_c0_cause();
420
421 if (likely(pending & IE_IRQ0))
422 ip32_irq0();
423 else if (unlikely(pending & IE_IRQ1))
424 ip32_irq1();
425 else if (unlikely(pending & IE_IRQ2))
426 ip32_irq2();
427 else if (unlikely(pending & IE_IRQ3))
428 ip32_irq3();
429 else if (unlikely(pending & IE_IRQ4))
430 ip32_irq4();
431 else if (likely(pending & IE_IRQ5))
432 ip32_irq5();
433 }
434
435 void __init arch_init_irq(void)
436 {
437 unsigned int irq;
438
439 /* Install our interrupt handler, then clear and disable all
440 * CRIME and MACE interrupts. */
441 crime->imask = 0;
442 crime->hard_int = 0;
443 crime->soft_int = 0;
444 mace->perif.ctrl.istat = 0;
445 mace->perif.ctrl.imask = 0;
446
447 mips_cpu_irq_init();
448 for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
449 switch (irq) {
450 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
451 irq_set_chip_and_handler_name(irq,
452 &ip32_mace_interrupt,
453 handle_level_irq,
454 "level");
455 break;
456
457 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
458 irq_set_chip_and_handler_name(irq,
459 &ip32_macepci_interrupt,
460 handle_level_irq,
461 "level");
462 break;
463
464 case CRIME_CPUERR_IRQ:
465 case CRIME_MEMERR_IRQ:
466 irq_set_chip_and_handler_name(irq,
467 &crime_level_interrupt,
468 handle_level_irq,
469 "level");
470 break;
471
472 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
473 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
474 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
475 case CRIME_VICE_IRQ:
476 irq_set_chip_and_handler_name(irq,
477 &crime_edge_interrupt,
478 handle_edge_irq,
479 "edge");
480 break;
481
482 case MACEISA_PARALLEL_IRQ:
483 case MACEISA_SERIAL1_TDMAPR_IRQ:
484 case MACEISA_SERIAL2_TDMAPR_IRQ:
485 irq_set_chip_and_handler_name(irq,
486 &ip32_maceisa_edge_interrupt,
487 handle_edge_irq,
488 "edge");
489 break;
490
491 default:
492 irq_set_chip_and_handler_name(irq,
493 &ip32_maceisa_level_interrupt,
494 handle_level_irq,
495 "level");
496 break;
497 }
498 }
499 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
500 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
501
502 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
503 change_c0_status(ST0_IM, ALLINTS);
504 }
Linux with added FPC-III support