arch/arm/mach-at91/at91sam9rl.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9rl.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *  Copyright (C) 2007 Atmel Corporation
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file COPYING in the main directory of this archive for
   9  * more details.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/clk/at91_pmc.h>
  14
  15 #include <asm/proc-fns.h>
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/system_misc.h>
  20 #include <mach/cpu.h>
  21 #include <mach/at91_dbgu.h>
  22 #include <mach/at91sam9rl.h>
  23
  24 #include "at91_aic.h"
  25 #include "at91_rstc.h"
  26 #include "soc.h"
  27 #include "generic.h"
  28 #include "clock.h"
  29 #include "sam9_smc.h"
  30 #include "pm.h"
  31
  32 /* --------------------------------------------------------------------
  33  *  Clocks
  34  * -------------------------------------------------------------------- */
  35
  36 /*
  37  * The peripheral clocks.
  38  */
  39 static struct clk pioA_clk = {
  40         .name           = "pioA_clk",
  41         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOA,
  42         .type           = CLK_TYPE_PERIPHERAL,
  43 };
  44 static struct clk pioB_clk = {
  45         .name           = "pioB_clk",
  46         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOB,
  47         .type           = CLK_TYPE_PERIPHERAL,
  48 };
  49 static struct clk pioC_clk = {
  50         .name           = "pioC_clk",
  51         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOC,
  52         .type           = CLK_TYPE_PERIPHERAL,
  53 };
  54 static struct clk pioD_clk = {
  55         .name           = "pioD_clk",
  56         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOD,
  57         .type           = CLK_TYPE_PERIPHERAL,
  58 };
  59 static struct clk usart0_clk = {
  60         .name           = "usart0_clk",
  61         .pmc_mask       = 1 << AT91SAM9RL_ID_US0,
  62         .type           = CLK_TYPE_PERIPHERAL,
  63 };
  64 static struct clk usart1_clk = {
  65         .name           = "usart1_clk",
  66         .pmc_mask       = 1 << AT91SAM9RL_ID_US1,
  67         .type           = CLK_TYPE_PERIPHERAL,
  68 };
  69 static struct clk usart2_clk = {
  70         .name           = "usart2_clk",
  71         .pmc_mask       = 1 << AT91SAM9RL_ID_US2,
  72         .type           = CLK_TYPE_PERIPHERAL,
  73 };
  74 static struct clk usart3_clk = {
  75         .name           = "usart3_clk",
  76         .pmc_mask       = 1 << AT91SAM9RL_ID_US3,
  77         .type           = CLK_TYPE_PERIPHERAL,
  78 };
  79 static struct clk mmc_clk = {
  80         .name           = "mci_clk",
  81         .pmc_mask       = 1 << AT91SAM9RL_ID_MCI,
  82         .type           = CLK_TYPE_PERIPHERAL,
  83 };
  84 static struct clk twi0_clk = {
  85         .name           = "twi0_clk",
  86         .pmc_mask       = 1 << AT91SAM9RL_ID_TWI0,
  87         .type           = CLK_TYPE_PERIPHERAL,
  88 };
  89 static struct clk twi1_clk = {
  90         .name           = "twi1_clk",
  91         .pmc_mask       = 1 << AT91SAM9RL_ID_TWI1,
  92         .type           = CLK_TYPE_PERIPHERAL,
  93 };
  94 static struct clk spi_clk = {
  95         .name           = "spi_clk",
  96         .pmc_mask       = 1 << AT91SAM9RL_ID_SPI,
  97         .type           = CLK_TYPE_PERIPHERAL,
  98 };
  99 static struct clk ssc0_clk = {
 100         .name           = "ssc0_clk",
 101         .pmc_mask       = 1 << AT91SAM9RL_ID_SSC0,
 102         .type           = CLK_TYPE_PERIPHERAL,
 103 };
 104 static struct clk ssc1_clk = {
 105         .name           = "ssc1_clk",
 106         .pmc_mask       = 1 << AT91SAM9RL_ID_SSC1,
 107         .type           = CLK_TYPE_PERIPHERAL,
 108 };
 109 static struct clk tc0_clk = {
 110         .name           = "tc0_clk",
 111         .pmc_mask       = 1 << AT91SAM9RL_ID_TC0,
 112         .type           = CLK_TYPE_PERIPHERAL,
 113 };
 114 static struct clk tc1_clk = {
 115         .name           = "tc1_clk",
 116         .pmc_mask       = 1 << AT91SAM9RL_ID_TC1,
 117         .type           = CLK_TYPE_PERIPHERAL,
 118 };
 119 static struct clk tc2_clk = {
 120         .name           = "tc2_clk",
 121         .pmc_mask       = 1 << AT91SAM9RL_ID_TC2,
 122         .type           = CLK_TYPE_PERIPHERAL,
 123 };
 124 static struct clk pwm_clk = {
 125         .name           = "pwm_clk",
 126         .pmc_mask       = 1 << AT91SAM9RL_ID_PWMC,
 127         .type           = CLK_TYPE_PERIPHERAL,
 128 };
 129 static struct clk tsc_clk = {
 130         .name           = "tsc_clk",
 131         .pmc_mask       = 1 << AT91SAM9RL_ID_TSC,
 132         .type           = CLK_TYPE_PERIPHERAL,
 133 };
 134 static struct clk dma_clk = {
 135         .name           = "dma_clk",
 136         .pmc_mask       = 1 << AT91SAM9RL_ID_DMA,
 137         .type           = CLK_TYPE_PERIPHERAL,
 138 };
 139 static struct clk udphs_clk = {
 140         .name           = "udphs_clk",
 141         .pmc_mask       = 1 << AT91SAM9RL_ID_UDPHS,
 142         .type           = CLK_TYPE_PERIPHERAL,
 143 };
 144 static struct clk lcdc_clk = {
 145         .name           = "lcdc_clk",
 146         .pmc_mask       = 1 << AT91SAM9RL_ID_LCDC,
 147         .type           = CLK_TYPE_PERIPHERAL,
 148 };
 149 static struct clk ac97_clk = {
 150         .name           = "ac97_clk",
 151         .pmc_mask       = 1 << AT91SAM9RL_ID_AC97C,
 152         .type           = CLK_TYPE_PERIPHERAL,
 153 };
 154
 155 static struct clk *periph_clocks[] __initdata = {
 156         &pioA_clk,
 157         &pioB_clk,
 158         &pioC_clk,
 159         &pioD_clk,
 160         &usart0_clk,
 161         &usart1_clk,
 162         &usart2_clk,
 163         &usart3_clk,
 164         &mmc_clk,
 165         &twi0_clk,
 166         &twi1_clk,
 167         &spi_clk,
 168         &ssc0_clk,
 169         &ssc1_clk,
 170         &tc0_clk,
 171         &tc1_clk,
 172         &tc2_clk,
 173         &pwm_clk,
 174         &tsc_clk,
 175         &dma_clk,
 176         &udphs_clk,
 177         &lcdc_clk,
 178         &ac97_clk,
 179         // irq0
 180 };
 181
 182 static struct clk_lookup periph_clocks_lookups[] = {
 183         CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
 184         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
 185         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
 186         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 187         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 188         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 189         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
 190         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
 191         CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
 192         CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
 193         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
 194         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
 195         CLKDEV_CON_ID("pioA", &pioA_clk),
 196         CLKDEV_CON_ID("pioB", &pioB_clk),
 197         CLKDEV_CON_ID("pioC", &pioC_clk),
 198         CLKDEV_CON_ID("pioD", &pioD_clk),
 199 };
 200
 201 static struct clk_lookup usart_clocks_lookups[] = {
 202         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 203         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 204         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 205         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 206         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 207 };
 208
 209 /*
 210  * The two programmable clocks.
 211  * You must configure pin multiplexing to bring these signals out.
 212  */
 213 static struct clk pck0 = {
 214         .name           = "pck0",
 215         .pmc_mask       = AT91_PMC_PCK0,
 216         .type           = CLK_TYPE_PROGRAMMABLE,
 217         .id             = 0,
 218 };
 219 static struct clk pck1 = {
 220         .name           = "pck1",
 221         .pmc_mask       = AT91_PMC_PCK1,
 222         .type           = CLK_TYPE_PROGRAMMABLE,
 223         .id             = 1,
 224 };
 225
 226 static void __init at91sam9rl_register_clocks(void)
 227 {
 228         int i;
 229
 230         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 231                 clk_register(periph_clocks[i]);
 232
 233         clkdev_add_table(periph_clocks_lookups,
 234                          ARRAY_SIZE(periph_clocks_lookups));
 235         clkdev_add_table(usart_clocks_lookups,
 236                          ARRAY_SIZE(usart_clocks_lookups));
 237
 238         clk_register(&pck0);
 239         clk_register(&pck1);
 240 }
 241
 242 /* --------------------------------------------------------------------
 243  *  GPIO
 244  * -------------------------------------------------------------------- */
 245
 246 static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
 247         {
 248                 .id             = AT91SAM9RL_ID_PIOA,
 249                 .regbase        = AT91SAM9RL_BASE_PIOA,
 250         }, {
 251                 .id             = AT91SAM9RL_ID_PIOB,
 252                 .regbase        = AT91SAM9RL_BASE_PIOB,
 253         }, {
 254                 .id             = AT91SAM9RL_ID_PIOC,
 255                 .regbase        = AT91SAM9RL_BASE_PIOC,
 256         }, {
 257                 .id             = AT91SAM9RL_ID_PIOD,
 258                 .regbase        = AT91SAM9RL_BASE_PIOD,
 259         }
 260 };
 261
 262 /* --------------------------------------------------------------------
 263  *  AT91SAM9RL processor initialization
 264  * -------------------------------------------------------------------- */
 265
 266 static void __init at91sam9rl_map_io(void)
 267 {
 268         unsigned long sram_size;
 269
 270         switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
 271                 case AT91_CIDR_SRAMSIZ_32K:
 272                         sram_size = 2 * SZ_16K;
 273                         break;
 274                 case AT91_CIDR_SRAMSIZ_16K:
 275                 default:
 276                         sram_size = SZ_16K;
 277         }
 278
 279         /* Map SRAM */
 280         at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
 281 }
 282
 283 static void __init at91sam9rl_ioremap_registers(void)
 284 {
 285         at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
 286         at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
 287         at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
 288         at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
 289         at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
 290         at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
 291         at91_pm_set_standby(at91sam9_sdram_standby);
 292 }
 293
 294 static void __init at91sam9rl_initialize(void)
 295 {
 296         arm_pm_idle = at91sam9_idle;
 297         arm_pm_restart = at91sam9_alt_restart;
 298
 299         at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
 300         at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
 301
 302         /* Register GPIO subsystem */
 303         at91_gpio_init(at91sam9rl_gpio, 4);
 304 }
 305
 306 /* --------------------------------------------------------------------
 307  *  Interrupt initialization
 308  * -------------------------------------------------------------------- */
 309
 310 /*
 311  * The default interrupt priority levels (0 = lowest, 7 = highest).
 312  */
 313 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
 314         7,      /* Advanced Interrupt Controller */
 315         7,      /* System Peripherals */
 316         1,      /* Parallel IO Controller A */
 317         1,      /* Parallel IO Controller B */
 318         1,      /* Parallel IO Controller C */
 319         1,      /* Parallel IO Controller D */
 320         5,      /* USART 0 */
 321         5,      /* USART 1 */
 322         5,      /* USART 2 */
 323         5,      /* USART 3 */
 324         0,      /* Multimedia Card Interface */
 325         6,      /* Two-Wire Interface 0 */
 326         6,      /* Two-Wire Interface 1 */
 327         5,      /* Serial Peripheral Interface */
 328         4,      /* Serial Synchronous Controller 0 */
 329         4,      /* Serial Synchronous Controller 1 */
 330         0,      /* Timer Counter 0 */
 331         0,      /* Timer Counter 1 */
 332         0,      /* Timer Counter 2 */
 333         0,
 334         0,      /* Touch Screen Controller */
 335         0,      /* DMA Controller */
 336         2,      /* USB Device High speed port */
 337         2,      /* LCD Controller */
 338         6,      /* AC97 Controller */
 339         0,
 340         0,
 341         0,
 342         0,
 343         0,
 344         0,
 345         0,      /* Advanced Interrupt Controller */
 346 };
 347
 348 AT91_SOC_START(at91sam9rl)
 349         .map_io = at91sam9rl_map_io,
 350         .default_irq_priority = at91sam9rl_default_irq_priority,
 351         .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
 352         .ioremap_registers = at91sam9rl_ioremap_registers,
 353         .register_clocks = at91sam9rl_register_clocks,
 354         .init = at91sam9rl_initialize,
 355 AT91_SOC_END