arch/arm/mach-at91/include/mach/at91sam9rl.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/at91sam9260.h
   3  *
   4  *  Copyright (C) 2007 Atmel Corporation
   5  *
   6  * Common definitions.
   7  * Based on AT91SAM9RL datasheet revision A. (Preliminary)
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file COPYING in the main directory of this archive for
  11  * more details.
  12  */
  13
  14 #ifndef AT91SAM9RL_H
  15 #define AT91SAM9RL_H
  16
  17 /*
  18  * Peripheral identifiers/interrupts.
  19  */
  20 #define AT91SAM9RL_ID_PIOA      2       /* Parallel IO Controller A */
  21 #define AT91SAM9RL_ID_PIOB      3       /* Parallel IO Controller B */
  22 #define AT91SAM9RL_ID_PIOC      4       /* Parallel IO Controller C */
  23 #define AT91SAM9RL_ID_PIOD      5       /* Parallel IO Controller D */
  24 #define AT91SAM9RL_ID_US0       6       /* USART 0 */
  25 #define AT91SAM9RL_ID_US1       7       /* USART 1 */
  26 #define AT91SAM9RL_ID_US2       8       /* USART 2 */
  27 #define AT91SAM9RL_ID_US3       9       /* USART 3 */
  28 #define AT91SAM9RL_ID_MCI       10      /* Multimedia Card Interface */
  29 #define AT91SAM9RL_ID_TWI0      11      /* TWI 0 */
  30 #define AT91SAM9RL_ID_TWI1      12      /* TWI 1 */
  31 #define AT91SAM9RL_ID_SPI       13      /* Serial Peripheral Interface */
  32 #define AT91SAM9RL_ID_SSC0      14      /* Serial Synchronous Controller 0 */
  33 #define AT91SAM9RL_ID_SSC1      15      /* Serial Synchronous Controller 1 */
  34 #define AT91SAM9RL_ID_TC0       16      /* Timer Counter 0 */
  35 #define AT91SAM9RL_ID_TC1       17      /* Timer Counter 1 */
  36 #define AT91SAM9RL_ID_TC2       18      /* Timer Counter 2 */
  37 #define AT91SAM9RL_ID_PWMC      19      /* Pulse Width Modulation Controller */
  38 #define AT91SAM9RL_ID_TSC       20      /* Touch Screen Controller */
  39 #define AT91SAM9RL_ID_DMA       21      /* DMA Controller */
  40 #define AT91SAM9RL_ID_UDPHS     22      /* USB Device HS */
  41 #define AT91SAM9RL_ID_LCDC      23      /* LCD Controller */
  42 #define AT91SAM9RL_ID_AC97C     24      /* AC97 Controller */
  43 #define AT91SAM9RL_ID_IRQ0      31      /* Advanced Interrupt Controller (IRQ0) */
  44
  45
  46 /*
  47  * User Peripheral physical base addresses.
  48  */
  49 #define AT91SAM9RL_BASE_TCB0    0xfffa0000
  50 #define AT91SAM9RL_BASE_TC0     0xfffa0000
  51 #define AT91SAM9RL_BASE_TC1     0xfffa0040
  52 #define AT91SAM9RL_BASE_TC2     0xfffa0080
  53 #define AT91SAM9RL_BASE_MCI     0xfffa4000
  54 #define AT91SAM9RL_BASE_TWI0    0xfffa8000
  55 #define AT91SAM9RL_BASE_TWI1    0xfffac000
  56 #define AT91SAM9RL_BASE_US0     0xfffb0000
  57 #define AT91SAM9RL_BASE_US1     0xfffb4000
  58 #define AT91SAM9RL_BASE_US2     0xfffb8000
  59 #define AT91SAM9RL_BASE_US3     0xfffbc000
  60 #define AT91SAM9RL_BASE_SSC0    0xfffc0000
  61 #define AT91SAM9RL_BASE_SSC1    0xfffc4000
  62 #define AT91SAM9RL_BASE_PWMC    0xfffc8000
  63 #define AT91SAM9RL_BASE_SPI     0xfffcc000
  64 #define AT91SAM9RL_BASE_TSC     0xfffd0000
  65 #define AT91SAM9RL_BASE_UDPHS   0xfffd4000
  66 #define AT91SAM9RL_BASE_AC97C   0xfffd8000
  67
  68
  69 /*
  70  * System Peripherals (offset from AT91_BASE_SYS)
  71  */
  72 #define AT91_SCKCR      (0xfffffd50 - AT91_BASE_SYS)
  73
  74 #define AT91SAM9RL_BASE_DMA     0xffffe600
  75 #define AT91SAM9RL_BASE_ECC     0xffffe800
  76 #define AT91SAM9RL_BASE_SDRAMC  0xffffea00
  77 #define AT91SAM9RL_BASE_SMC     0xffffec00
  78 #define AT91SAM9RL_BASE_MATRIX  0xffffee00
  79 #define AT91SAM9RL_BASE_DBGU    AT91_BASE_DBGU0
  80 #define AT91SAM9RL_BASE_PIOA    0xfffff400
  81 #define AT91SAM9RL_BASE_PIOB    0xfffff600
  82 #define AT91SAM9RL_BASE_PIOC    0xfffff800
  83 #define AT91SAM9RL_BASE_PIOD    0xfffffa00
  84 #define AT91SAM9RL_BASE_RSTC    0xfffffd00
  85 #define AT91SAM9RL_BASE_SHDWC   0xfffffd10
  86 #define AT91SAM9RL_BASE_RTT     0xfffffd20
  87 #define AT91SAM9RL_BASE_PIT     0xfffffd30
  88 #define AT91SAM9RL_BASE_WDT     0xfffffd40
  89 #define AT91SAM9RL_BASE_GPBR    0xfffffd60
  90 #define AT91SAM9RL_BASE_RTC     0xfffffe00
  91
  92
  93 /*
  94  * Internal Memory.
  95  */
  96 #define AT91SAM9RL_SRAM_BASE    0x00300000      /* Internal SRAM base address */
  97 #define AT91SAM9RL_SRAM_SIZE    SZ_16K          /* Internal SRAM size (16Kb) */
  98
  99 #define AT91SAM9RL_ROM_BASE     0x00400000      /* Internal ROM base address */
 100 #define AT91SAM9RL_ROM_SIZE     (2 * SZ_16K)    /* Internal ROM size (32Kb) */
 101
 102 #define AT91SAM9RL_LCDC_BASE    0x00500000      /* LCD Controller */
 103 #define AT91SAM9RL_UDPHS_FIFO   0x00600000      /* USB Device HS controller */
 104
 105 #endif