arch/arm/mach-at91/include/mach/at91x40.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/at91x40.h
   3  *
   4  * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #ifndef AT91X40_H
  13 #define AT91X40_H
  14
  15 /*
  16  *      IRQ list.
  17  */
  18 #define AT91X40_ID_USART0       2       /* USART port 0 */
  19 #define AT91X40_ID_USART1       3       /* USART port 1 */
  20 #define AT91X40_ID_TC0          4       /* Timer/Counter 0 */
  21 #define AT91X40_ID_TC1          5       /* Timer/Counter 1*/
  22 #define AT91X40_ID_TC2          6       /* Timer/Counter 2*/
  23 #define AT91X40_ID_WD           7       /* Watchdog? */
  24 #define AT91X40_ID_PIOA         8       /* Parallel IO Controller A */
  25
  26 #define AT91X40_ID_IRQ0         16      /* External IRQ 0 */
  27 #define AT91X40_ID_IRQ1         17      /* External IRQ 1 */
  28 #define AT91X40_ID_IRQ2         18      /* External IRQ 2 */
  29
  30 /*
  31  * System Peripherals
  32  */
  33 #define AT91_BASE_SYS   0xffc00000
  34
  35 #define AT91_EBI        0xffe00000      /* External Bus Interface */
  36 #define AT91_SF         0xfff00000      /* Special Function */
  37 #define AT91_USART1     0xfffcc000      /* USART 1 */
  38 #define AT91_USART0     0xfffd0000      /* USART 0 */
  39 #define AT91_TC         0xfffe0000      /* Timer Counter */
  40 #define AT91_PIOA       0xffff0000      /* PIO Controller A */
  41 #define AT91_PS         0xffff4000      /* Power Save */
  42 #define AT91_WD         0xffff8000      /* Watchdog Timer */
  43
  44 /*
  45  * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
  46  * But it does have a chip identify register and extension ID, so define at
  47  * least these here.
  48  */
  49 #define AT91_DBGU_CIDR  (AT91_SF + 0)   /* CIDR in PS segment */
  50 #define AT91_DBGU_EXID  (AT91_SF + 4)   /* EXID in PS segment */
  51
  52 /*
  53  * Support defines for the simple Power Controller module.
  54  */
  55 #define AT91_PS_CR      (AT91_PS + 0)   /* PS Control register */
  56 #define AT91_PS_CR_CPU  (1 << 0)        /* CPU clock disable bit */
  57
  58 #endif /* AT91X40_H */