arch/arm/mach-ixp4xx/include/mach/io.h

   1 /*
   2  * arch/arm/mach-ixp4xx/include/mach/io.h
   3  *
   4  * Author: Deepak Saxena <dsaxena@plexity.net>
   5  *
   6  * Copyright (C) 2002-2005  MontaVista Software, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ASM_ARM_ARCH_IO_H
  14 #define __ASM_ARM_ARCH_IO_H
  15
  16 #include <linux/bitops.h>
  17
  18 #include <mach/hardware.h>
  19
  20 extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
  21 extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
  22
  23
  24 /*
  25  * IXP4xx provides two methods of accessing PCI memory space:
  26  *
  27  * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB).
  28  *    To access PCI via this space, we simply ioremap() the BAR
  29  *    into the kernel and we can use the standard read[bwl]/write[bwl]
  30  *    macros. This is the preffered method due to speed but it
  31  *    limits the system to just 64MB of PCI memory. This can be
  32  *    problematic if using video cards and other memory-heavy targets.
  33  *
  34  * 2) If > 64MB of memory space is required, the IXP4xx can use indirect
  35  *    registers to access the whole 4 GB of PCI memory space (as we do below
  36  *    for I/O transactions). This allows currently for up to 1 GB (0x10000000
  37  *    to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that
  38  *    every PCI access requires three local register accesses plus a spinlock,
  39  *    but in some cases the performance hit is acceptable. In addition, you
  40  *    cannot mmap() PCI devices in this case.
  41  */
  42 #ifdef  CONFIG_IXP4XX_INDIRECT_PCI
  43
  44 /*
  45  * In the case of using indirect PCI, we simply return the actual PCI
  46  * address and our read/write implementation use that to drive the
  47  * access registers. If something outside of PCI is ioremap'd, we
  48  * fallback to the default.
  49  */
  50
  51 static inline int is_pci_memory(u32 addr)
  52 {
  53         return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF);
  54 }
  55
  56 #define writeb(v, p)                    __indirect_writeb(v, p)
  57 #define writew(v, p)                    __indirect_writew(v, p)
  58 #define writel(v, p)                    __indirect_writel(v, p)
  59
  60 #define writesb(p, v, l)                __indirect_writesb(p, v, l)
  61 #define writesw(p, v, l)                __indirect_writesw(p, v, l)
  62 #define writesl(p, v, l)                __indirect_writesl(p, v, l)
  63
  64 #define readb(p)                        __indirect_readb(p)
  65 #define readw(p)                        __indirect_readw(p)
  66 #define readl(p)                        __indirect_readl(p)
  67
  68 #define readsb(p, v, l)                 __indirect_readsb(p, v, l)
  69 #define readsw(p, v, l)                 __indirect_readsw(p, v, l)
  70 #define readsl(p, v, l)                 __indirect_readsl(p, v, l)
  71
  72 static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
  73 {
  74         u32 addr = (u32)p;
  75         u32 n, byte_enables, data;
  76
  77         if (!is_pci_memory(addr)) {
  78                 __raw_writeb(value, addr);
  79                 return;
  80         }
  81
  82         n = addr % 4;
  83         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
  84         data = value << (8*n);
  85         ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
  86 }
  87
  88 static inline void __indirect_writesb(volatile void __iomem *bus_addr,
  89                                       const u8 *vaddr, int count)
  90 {
  91         while (count--)
  92                 writeb(*vaddr++, bus_addr);
  93 }
  94
  95 static inline void __indirect_writew(u16 value, volatile void __iomem *p)
  96 {
  97         u32 addr = (u32)p;
  98         u32 n, byte_enables, data;
  99
 100         if (!is_pci_memory(addr)) {
 101                 __raw_writew(value, addr);
 102                 return;
 103         }
 104
 105         n = addr % 4;
 106         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 107         data = value << (8*n);
 108         ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
 109 }
 110
 111 static inline void __indirect_writesw(volatile void __iomem *bus_addr,
 112                                       const u16 *vaddr, int count)
 113 {
 114         while (count--)
 115                 writew(*vaddr++, bus_addr);
 116 }
 117
 118 static inline void __indirect_writel(u32 value, volatile void __iomem *p)
 119 {
 120         u32 addr = (__force u32)p;
 121
 122         if (!is_pci_memory(addr)) {
 123                 __raw_writel(value, p);
 124                 return;
 125         }
 126
 127         ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
 128 }
 129
 130 static inline void __indirect_writesl(volatile void __iomem *bus_addr,
 131                                       const u32 *vaddr, int count)
 132 {
 133         while (count--)
 134                 writel(*vaddr++, bus_addr);
 135 }
 136
 137 static inline unsigned char __indirect_readb(const volatile void __iomem *p)
 138 {
 139         u32 addr = (u32)p;
 140         u32 n, byte_enables, data;
 141
 142         if (!is_pci_memory(addr))
 143                 return __raw_readb(addr);
 144
 145         n = addr % 4;
 146         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 147         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
 148                 return 0xff;
 149
 150         return data >> (8*n);
 151 }
 152
 153 static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
 154                                      u8 *vaddr, u32 count)
 155 {
 156         while (count--)
 157                 *vaddr++ = readb(bus_addr);
 158 }
 159
 160 static inline unsigned short __indirect_readw(const volatile void __iomem *p)
 161 {
 162         u32 addr = (u32)p;
 163         u32 n, byte_enables, data;
 164
 165         if (!is_pci_memory(addr))
 166                 return __raw_readw(addr);
 167
 168         n = addr % 4;
 169         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 170         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
 171                 return 0xffff;
 172
 173         return data>>(8*n);
 174 }
 175
 176 static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
 177                                      u16 *vaddr, u32 count)
 178 {
 179         while (count--)
 180                 *vaddr++ = readw(bus_addr);
 181 }
 182
 183 static inline unsigned long __indirect_readl(const volatile void __iomem *p)
 184 {
 185         u32 addr = (__force u32)p;
 186         u32 data;
 187
 188         if (!is_pci_memory(addr))
 189                 return __raw_readl(p);
 190
 191         if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
 192                 return 0xffffffff;
 193
 194         return data;
 195 }
 196
 197 static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
 198                                      u32 *vaddr, u32 count)
 199 {
 200         while (count--)
 201                 *vaddr++ = readl(bus_addr);
 202 }
 203
 204
 205 /*
 206  * We can use the built-in functions b/c they end up calling writeb/readb
 207  */
 208 #define memset_io(c,v,l)                _memset_io((c),(v),(l))
 209 #define memcpy_fromio(a,c,l)            _memcpy_fromio((a),(c),(l))
 210 #define memcpy_toio(c,a,l)              _memcpy_toio((c),(a),(l))
 211
 212 #endif /* CONFIG_IXP4XX_INDIRECT_PCI */
 213
 214 #ifndef CONFIG_PCI
 215
 216 #define __io(v)         __typesafe_io(v)
 217
 218 #else
 219
 220 /*
 221  * IXP4xx does not have a transparent cpu -> PCI I/O translation
 222  * window.  Instead, it has a set of registers that must be tweaked
 223  * with the proper byte lanes, command types, and address for the
 224  * transaction.  This means that we need to override the default
 225  * I/O functions.
 226  */
 227
 228 static inline void outb(u8 value, u32 addr)
 229 {
 230         u32 n, byte_enables, data;
 231         n = addr % 4;
 232         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 233         data = value << (8*n);
 234         ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
 235 }
 236
 237 static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
 238 {
 239         while (count--)
 240                 outb(*vaddr++, io_addr);
 241 }
 242
 243 static inline void outw(u16 value, u32 addr)
 244 {
 245         u32 n, byte_enables, data;
 246         n = addr % 4;
 247         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 248         data = value << (8*n);
 249         ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
 250 }
 251
 252 static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
 253 {
 254         while (count--)
 255                 outw(cpu_to_le16(*vaddr++), io_addr);
 256 }
 257
 258 static inline void outl(u32 value, u32 addr)
 259 {
 260         ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
 261 }
 262
 263 static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
 264 {
 265         while (count--)
 266                 outl(cpu_to_le32(*vaddr++), io_addr);
 267 }
 268
 269 static inline u8 inb(u32 addr)
 270 {
 271         u32 n, byte_enables, data;
 272         n = addr % 4;
 273         byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
 274         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
 275                 return 0xff;
 276
 277         return data >> (8*n);
 278 }
 279
 280 static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
 281 {
 282         while (count--)
 283                 *vaddr++ = inb(io_addr);
 284 }
 285
 286 static inline u16 inw(u32 addr)
 287 {
 288         u32 n, byte_enables, data;
 289         n = addr % 4;
 290         byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
 291         if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
 292                 return 0xffff;
 293
 294         return data>>(8*n);
 295 }
 296
 297 static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
 298 {
 299         while (count--)
 300                 *vaddr++ = le16_to_cpu(inw(io_addr));
 301 }
 302
 303 static inline u32 inl(u32 addr)
 304 {
 305         u32 data;
 306         if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
 307                 return 0xffffffff;
 308
 309         return data;
 310 }
 311
 312 static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
 313 {
 314         while (count--)
 315                 *vaddr++ = le32_to_cpu(inl(io_addr));
 316 }
 317
 318 #define PIO_OFFSET      0x10000UL
 319 #define PIO_MASK        0x0ffffUL
 320
 321 #define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
 322                                         ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
 323
 324 #define ioread8(p)                      ioread8(p)
 325 static inline unsigned int ioread8(const void __iomem *addr)
 326 {
 327         unsigned long port = (unsigned long __force)addr;
 328         if (__is_io_address(port))
 329                 return (unsigned int)inb(port & PIO_MASK);
 330         else
 331 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 332                 return (unsigned int)__raw_readb(addr);
 333 #else
 334                 return (unsigned int)__indirect_readb(addr);
 335 #endif
 336 }
 337
 338 #define ioread8_rep(p, v, c)            ioread8_rep(p, v, c)
 339 static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
 340 {
 341         unsigned long port = (unsigned long __force)addr;
 342         if (__is_io_address(port))
 343                 insb(port & PIO_MASK, vaddr, count);
 344         else
 345 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 346                 __raw_readsb(addr, vaddr, count);
 347 #else
 348                 __indirect_readsb(addr, vaddr, count);
 349 #endif
 350 }
 351
 352 #define ioread16(p)                     ioread16(p)
 353 static inline unsigned int ioread16(const void __iomem *addr)
 354 {
 355         unsigned long port = (unsigned long __force)addr;
 356         if (__is_io_address(port))
 357                 return  (unsigned int)inw(port & PIO_MASK);
 358         else
 359 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 360                 return le16_to_cpu((__force __le16)__raw_readw(addr));
 361 #else
 362                 return (unsigned int)__indirect_readw(addr);
 363 #endif
 364 }
 365
 366 #define ioread16_rep(p, v, c)           ioread16_rep(p, v, c)
 367 static inline void ioread16_rep(const void __iomem *addr, void *vaddr,
 368                                 u32 count)
 369 {
 370         unsigned long port = (unsigned long __force)addr;
 371         if (__is_io_address(port))
 372                 insw(port & PIO_MASK, vaddr, count);
 373         else
 374 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 375                 __raw_readsw(addr, vaddr, count);
 376 #else
 377                 __indirect_readsw(addr, vaddr, count);
 378 #endif
 379 }
 380
 381 #define ioread32(p)                     ioread32(p)
 382 static inline unsigned int ioread32(const void __iomem *addr)
 383 {
 384         unsigned long port = (unsigned long __force)addr;
 385         if (__is_io_address(port))
 386                 return  (unsigned int)inl(port & PIO_MASK);
 387         else {
 388 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 389                 return le32_to_cpu((__force __le32)__raw_readl(addr));
 390 #else
 391                 return (unsigned int)__indirect_readl(addr);
 392 #endif
 393         }
 394 }
 395
 396 #define ioread32_rep(p, v, c)           ioread32_rep(p, v, c)
 397 static inline void ioread32_rep(const void __iomem *addr, void *vaddr,
 398                                 u32 count)
 399 {
 400         unsigned long port = (unsigned long __force)addr;
 401         if (__is_io_address(port))
 402                 insl(port & PIO_MASK, vaddr, count);
 403         else
 404 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 405                 __raw_readsl(addr, vaddr, count);
 406 #else
 407                 __indirect_readsl(addr, vaddr, count);
 408 #endif
 409 }
 410
 411 #define iowrite8(v, p)                  iowrite8(v, p)
 412 static inline void iowrite8(u8 value, void __iomem *addr)
 413 {
 414         unsigned long port = (unsigned long __force)addr;
 415         if (__is_io_address(port))
 416                 outb(value, port & PIO_MASK);
 417         else
 418 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 419                 __raw_writeb(value, addr);
 420 #else
 421                 __indirect_writeb(value, addr);
 422 #endif
 423 }
 424
 425 #define iowrite8_rep(p, v, c)           iowrite8_rep(p, v, c)
 426 static inline void iowrite8_rep(void __iomem *addr, const void *vaddr,
 427                                 u32 count)
 428 {
 429         unsigned long port = (unsigned long __force)addr;
 430         if (__is_io_address(port))
 431                 outsb(port & PIO_MASK, vaddr, count);
 432         else
 433 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 434                 __raw_writesb(addr, vaddr, count);
 435 #else
 436                 __indirect_writesb(addr, vaddr, count);
 437 #endif
 438 }
 439
 440 #define iowrite16(v, p)                 iowrite16(v, p)
 441 static inline void iowrite16(u16 value, void __iomem *addr)
 442 {
 443         unsigned long port = (unsigned long __force)addr;
 444         if (__is_io_address(port))
 445                 outw(value, port & PIO_MASK);
 446         else
 447 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 448                 __raw_writew(cpu_to_le16(value), addr);
 449 #else
 450                 __indirect_writew(value, addr);
 451 #endif
 452 }
 453
 454 #define iowrite16_rep(p, v, c)          iowrite16_rep(p, v, c)
 455 static inline void iowrite16_rep(void __iomem *addr, const void *vaddr,
 456                                  u32 count)
 457 {
 458         unsigned long port = (unsigned long __force)addr;
 459         if (__is_io_address(port))
 460                 outsw(port & PIO_MASK, vaddr, count);
 461         else
 462 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 463                 __raw_writesw(addr, vaddr, count);
 464 #else
 465                 __indirect_writesw(addr, vaddr, count);
 466 #endif
 467 }
 468
 469 #define iowrite32(v, p)                 iowrite32(v, p)
 470 static inline void iowrite32(u32 value, void __iomem *addr)
 471 {
 472         unsigned long port = (unsigned long __force)addr;
 473         if (__is_io_address(port))
 474                 outl(value, port & PIO_MASK);
 475         else
 476 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 477                 __raw_writel((u32 __force)cpu_to_le32(value), addr);
 478 #else
 479                 __indirect_writel(value, addr);
 480 #endif
 481 }
 482
 483 #define iowrite32_rep(p, v, c)          iowrite32_rep(p, v, c)
 484 static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
 485                                  u32 count)
 486 {
 487         unsigned long port = (unsigned long __force)addr;
 488         if (__is_io_address(port))
 489                 outsl(port & PIO_MASK, vaddr, count);
 490         else
 491 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 492                 __raw_writesl(addr, vaddr, count);
 493 #else
 494                 __indirect_writesl(addr, vaddr, count);
 495 #endif
 496 }
 497
 498 #define ioport_map(port, nr)            ((void __iomem*)(port + PIO_OFFSET))
 499 #define ioport_unmap(addr)
 500 #endif /* CONFIG_PCI */
 501
 502 #endif /* __ASM_ARM_ARCH_IO_H */