2 * Copyright (C) ST-Ericsson SA 2011
4 * License terms: GNU General Public License (GPL) version 2
10 #include <asm/cacheflush.h>
11 #include <asm/hardware/cache-l2x0.h>
13 #include "db8500-regs.h"
16 static void __iomem
*l2x0_base
;
18 static int __init
ux500_l2x0_unlock(void)
23 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
24 * apparently locks both caches before jumping to the kernel. The
25 * l2x0 core will not touch the unlock registers if the l2x0 is
26 * already enabled, so we do it right here instead. The PL310 has
27 * 8 sets of registers, one per possible CPU.
29 for (i
= 0; i
< 8; i
++) {
30 writel_relaxed(0x0, l2x0_base
+ L2X0_LOCKDOWN_WAY_D_BASE
+
31 i
* L2X0_LOCKDOWN_STRIDE
);
32 writel_relaxed(0x0, l2x0_base
+ L2X0_LOCKDOWN_WAY_I_BASE
+
33 i
* L2X0_LOCKDOWN_STRIDE
);
38 static int __init
ux500_l2x0_init(void)
40 u32 aux_val
= 0x3e000000;
42 if (cpu_is_u8500_family() || cpu_is_ux540_family())
43 l2x0_base
= __io_address(U8500_L2CC_BASE
);
45 /* Non-Ux500 platform */
48 /* Unlock before init */
51 /* DBx540's L2 has 128KB way size */
52 if (cpu_is_ux540_family())
54 aux_val
|= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT
);
57 aux_val
|= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT
);
59 /* 64KB way size, 8 way associativity, force WA */
60 if (of_have_populated_dt())
61 l2x0_of_init(aux_val
, 0xc0000fff);
63 l2x0_init(l2x0_base
, aux_val
, 0xc0000fff);
66 * We can't disable l2 as we are in non secure mode, currently
67 * this seems be called only during kexec path. So let's
68 * override outer.disable with nasty assignment until we have
69 * some SMI service available.
71 outer_cache
.disable
= NULL
;
72 outer_cache
.set_debug
= NULL
;
77 early_initcall(ux500_l2x0_init
);