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fix a kmap leak in virtio_console
[linux/fpc-iii.git] / drivers / mtd / devices / m25p80.c
blobad19139097025b97839fb7cbe123a1261e6cf876
1 /*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/mutex.h>
25 #include <linux/math64.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h>
29
30 #include <linux/mtd/cfi.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/of_platform.h>
34
35 #include <linux/spi/spi.h>
36 #include <linux/spi/flash.h>
37
38 /* Flash opcodes. */
39 #define OPCODE_WREN 0x06 /* Write enable */
40 #define OPCODE_RDSR 0x05 /* Read status register */
41 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
42 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
43 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
44 #define OPCODE_QUAD_READ 0x6b /* Read data bytes */
45 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
46 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
47 #define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
48 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
49 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
50 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
51 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
52 #define OPCODE_RDCR 0x35 /* Read configuration register */
53
54 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
55 #define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
56 #define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
57 #define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes */
58 #define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
59 #define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
60
61 /* Used for SST flashes only. */
62 #define OPCODE_BP 0x02 /* Byte program */
63 #define OPCODE_WRDI 0x04 /* Write disable */
64 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
65
66 /* Used for Macronix and Winbond flashes. */
67 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
68 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
69
70 /* Used for Spansion flashes only. */
71 #define OPCODE_BRWR 0x17 /* Bank register write */
72
73 /* Status Register bits. */
74 #define SR_WIP 1 /* Write in progress */
75 #define SR_WEL 2 /* Write enable latch */
76 /* meaning of other SR_* bits may differ between vendors */
77 #define SR_BP0 4 /* Block protect 0 */
78 #define SR_BP1 8 /* Block protect 1 */
79 #define SR_BP2 0x10 /* Block protect 2 */
80 #define SR_SRWD 0x80 /* SR write protect */
81
82 #define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
83
84 /* Configuration Register bits. */
85 #define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
86
87 /* Define max times to check status register before we give up. */
88 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
89 #define MAX_CMD_SIZE 6
90
91 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
92
93 /****************************************************************************/
94
95 enum read_type {
96 M25P80_NORMAL = 0,
97 M25P80_FAST,
98 M25P80_QUAD,
99 };
100
101 struct m25p {
102 struct spi_device *spi;
103 struct mutex lock;
104 struct mtd_info mtd;
105 u16 page_size;
106 u16 addr_width;
107 u8 erase_opcode;
108 u8 read_opcode;
109 u8 program_opcode;
110 u8 *command;
111 enum read_type flash_read;
112 };
113
114 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
115 {
116 return container_of(mtd, struct m25p, mtd);
117 }
118
119 /****************************************************************************/
120
121 /*
122 * Internal helper functions
123 */
124
125 /*
126 * Read the status register, returning its value in the location
127 * Return the status register value.
128 * Returns negative if error occurred.
129 */
130 static int read_sr(struct m25p *flash)
131 {
132 ssize_t retval;
133 u8 code = OPCODE_RDSR;
134 u8 val;
135
136 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
137
138 if (retval < 0) {
139 dev_err(&flash->spi->dev, "error %d reading SR\n",
140 (int) retval);
141 return retval;
142 }
143
144 return val;
145 }
146
147 /*
148 * Read configuration register, returning its value in the
149 * location. Return the configuration register value.
150 * Returns negative if error occured.
151 */
152 static int read_cr(struct m25p *flash)
153 {
154 u8 code = OPCODE_RDCR;
155 int ret;
156 u8 val;
157
158 ret = spi_write_then_read(flash->spi, &code, 1, &val, 1);
159 if (ret < 0) {
160 dev_err(&flash->spi->dev, "error %d reading CR\n", ret);
161 return ret;
162 }
163
164 return val;
165 }
166
167 /*
168 * Write status register 1 byte
169 * Returns negative if error occurred.
170 */
171 static int write_sr(struct m25p *flash, u8 val)
172 {
173 flash->command[0] = OPCODE_WRSR;
174 flash->command[1] = val;
175
176 return spi_write(flash->spi, flash->command, 2);
177 }
178
179 /*
180 * Set write enable latch with Write Enable command.
181 * Returns negative if error occurred.
182 */
183 static inline int write_enable(struct m25p *flash)
184 {
185 u8 code = OPCODE_WREN;
186
187 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
188 }
189
190 /*
191 * Send write disble instruction to the chip.
192 */
193 static inline int write_disable(struct m25p *flash)
194 {
195 u8 code = OPCODE_WRDI;
196
197 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
198 }
199
200 /*
201 * Enable/disable 4-byte addressing mode.
202 */
203 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
204 {
205 int status;
206 bool need_wren = false;
207
208 switch (JEDEC_MFR(jedec_id)) {
209 case CFI_MFR_ST: /* Micron, actually */
210 /* Some Micron need WREN command; all will accept it */
211 need_wren = true;
212 case CFI_MFR_MACRONIX:
213 case 0xEF /* winbond */:
214 if (need_wren)
215 write_enable(flash);
216
217 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
218 status = spi_write(flash->spi, flash->command, 1);
219
220 if (need_wren)
221 write_disable(flash);
222
223 return status;
224 default:
225 /* Spansion style */
226 flash->command[0] = OPCODE_BRWR;
227 flash->command[1] = enable << 7;
228 return spi_write(flash->spi, flash->command, 2);
229 }
230 }
231
232 /*
233 * Service routine to read status register until ready, or timeout occurs.
234 * Returns non-zero if error.
235 */
236 static int wait_till_ready(struct m25p *flash)
237 {
238 unsigned long deadline;
239 int sr;
240
241 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
242
243 do {
244 if ((sr = read_sr(flash)) < 0)
245 break;
246 else if (!(sr & SR_WIP))
247 return 0;
248
249 cond_resched();
250
251 } while (!time_after_eq(jiffies, deadline));
252
253 return 1;
254 }
255
256 /*
257 * Write status Register and configuration register with 2 bytes
258 * The first byte will be written to the status register, while the
259 * second byte will be written to the configuration register.
260 * Return negative if error occured.
261 */
262 static int write_sr_cr(struct m25p *flash, u16 val)
263 {
264 flash->command[0] = OPCODE_WRSR;
265 flash->command[1] = val & 0xff;
266 flash->command[2] = (val >> 8);
267
268 return spi_write(flash->spi, flash->command, 3);
269 }
270
271 static int macronix_quad_enable(struct m25p *flash)
272 {
273 int ret, val;
274 u8 cmd[2];
275 cmd[0] = OPCODE_WRSR;
276
277 val = read_sr(flash);
278 cmd[1] = val | SR_QUAD_EN_MX;
279 write_enable(flash);
280
281 spi_write(flash->spi, &cmd, 2);
282
283 if (wait_till_ready(flash))
284 return 1;
285
286 ret = read_sr(flash);
287 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
288 dev_err(&flash->spi->dev, "Macronix Quad bit not set\n");
289 return -EINVAL;
290 }
291
292 return 0;
293 }
294
295 static int spansion_quad_enable(struct m25p *flash)
296 {
297 int ret;
298 int quad_en = CR_QUAD_EN_SPAN << 8;
299
300 write_enable(flash);
301
302 ret = write_sr_cr(flash, quad_en);
303 if (ret < 0) {
304 dev_err(&flash->spi->dev,
305 "error while writing configuration register\n");
306 return -EINVAL;
307 }
308
309 /* read back and check it */
310 ret = read_cr(flash);
311 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
312 dev_err(&flash->spi->dev, "Spansion Quad bit not set\n");
313 return -EINVAL;
314 }
315
316 return 0;
317 }
318
319 static int set_quad_mode(struct m25p *flash, u32 jedec_id)
320 {
321 int status;
322
323 switch (JEDEC_MFR(jedec_id)) {
324 case CFI_MFR_MACRONIX:
325 status = macronix_quad_enable(flash);
326 if (status) {
327 dev_err(&flash->spi->dev,
328 "Macronix quad-read not enabled\n");
329 return -EINVAL;
330 }
331 return status;
332 default:
333 status = spansion_quad_enable(flash);
334 if (status) {
335 dev_err(&flash->spi->dev,
336 "Spansion quad-read not enabled\n");
337 return -EINVAL;
338 }
339 return status;
340 }
341 }
342
343 /*
344 * Erase the whole flash memory
345 *
346 * Returns 0 if successful, non-zero otherwise.
347 */
348 static int erase_chip(struct m25p *flash)
349 {
350 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
351 (long long)(flash->mtd.size >> 10));
352
353 /* Wait until finished previous write command. */
354 if (wait_till_ready(flash))
355 return 1;
356
357 /* Send write enable, then erase commands. */
358 write_enable(flash);
359
360 /* Set up command buffer. */
361 flash->command[0] = OPCODE_CHIP_ERASE;
362
363 spi_write(flash->spi, flash->command, 1);
364
365 return 0;
366 }
367
368 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
369 {
370 /* opcode is in cmd[0] */
371 cmd[1] = addr >> (flash->addr_width * 8 - 8);
372 cmd[2] = addr >> (flash->addr_width * 8 - 16);
373 cmd[3] = addr >> (flash->addr_width * 8 - 24);
374 cmd[4] = addr >> (flash->addr_width * 8 - 32);
375 }
376
377 static int m25p_cmdsz(struct m25p *flash)
378 {
379 return 1 + flash->addr_width;
380 }
381
382 /*
383 * Erase one sector of flash memory at offset ``offset'' which is any
384 * address within the sector which should be erased.
385 *
386 * Returns 0 if successful, non-zero otherwise.
387 */
388 static int erase_sector(struct m25p *flash, u32 offset)
389 {
390 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
391 __func__, flash->mtd.erasesize / 1024, offset);
392
393 /* Wait until finished previous write command. */
394 if (wait_till_ready(flash))
395 return 1;
396
397 /* Send write enable, then erase commands. */
398 write_enable(flash);
399
400 /* Set up command buffer. */
401 flash->command[0] = flash->erase_opcode;
402 m25p_addr2cmd(flash, offset, flash->command);
403
404 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
405
406 return 0;
407 }
408
409 /****************************************************************************/
410
411 /*
412 * MTD implementation
413 */
414
415 /*
416 * Erase an address range on the flash chip. The address range may extend
417 * one or more erase sectors. Return an error is there is a problem erasing.
418 */
419 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
420 {
421 struct m25p *flash = mtd_to_m25p(mtd);
422 u32 addr,len;
423 uint32_t rem;
424
425 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
426 __func__, (long long)instr->addr,
427 (long long)instr->len);
428
429 div_u64_rem(instr->len, mtd->erasesize, &rem);
430 if (rem)
431 return -EINVAL;
432
433 addr = instr->addr;
434 len = instr->len;
435
436 mutex_lock(&flash->lock);
437
438 /* whole-chip erase? */
439 if (len == flash->mtd.size) {
440 if (erase_chip(flash)) {
441 instr->state = MTD_ERASE_FAILED;
442 mutex_unlock(&flash->lock);
443 return -EIO;
444 }
445
446 /* REVISIT in some cases we could speed up erasing large regions
447 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
448 * to use "small sector erase", but that's not always optimal.
449 */
450
451 /* "sector"-at-a-time erase */
452 } else {
453 while (len) {
454 if (erase_sector(flash, addr)) {
455 instr->state = MTD_ERASE_FAILED;
456 mutex_unlock(&flash->lock);
457 return -EIO;
458 }
459
460 addr += mtd->erasesize;
461 len -= mtd->erasesize;
462 }
463 }
464
465 mutex_unlock(&flash->lock);
466
467 instr->state = MTD_ERASE_DONE;
468 mtd_erase_callback(instr);
469
470 return 0;
471 }
472
473 /*
474 * Dummy Cycle calculation for different type of read.
475 * It can be used to support more commands with
476 * different dummy cycle requirements.
477 */
478 static inline int m25p80_dummy_cycles_read(struct m25p *flash)
479 {
480 switch (flash->flash_read) {
481 case M25P80_FAST:
482 case M25P80_QUAD:
483 return 1;
484 case M25P80_NORMAL:
485 return 0;
486 default:
487 dev_err(&flash->spi->dev, "No valid read type supported\n");
488 return -1;
489 }
490 }
491
492 static inline unsigned int m25p80_rx_nbits(const struct m25p *flash)
493 {
494 switch (flash->flash_read) {
495 case M25P80_QUAD:
496 return 4;
497 default:
498 return 0;
499 }
500 }
501
502 /*
503 * Read an address range from the flash chip. The address range
504 * may be any size provided it is within the physical boundaries.
505 */
506 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
507 size_t *retlen, u_char *buf)
508 {
509 struct m25p *flash = mtd_to_m25p(mtd);
510 struct spi_transfer t[2];
511 struct spi_message m;
512 uint8_t opcode;
513 int dummy;
514
515 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
516 __func__, (u32)from, len);
517
518 spi_message_init(&m);
519 memset(t, 0, (sizeof t));
520
521 dummy = m25p80_dummy_cycles_read(flash);
522 if (dummy < 0) {
523 dev_err(&flash->spi->dev, "No valid read command supported\n");
524 return -EINVAL;
525 }
526
527 t[0].tx_buf = flash->command;
528 t[0].len = m25p_cmdsz(flash) + dummy;
529 spi_message_add_tail(&t[0], &m);
530
531 t[1].rx_buf = buf;
532 t[1].rx_nbits = m25p80_rx_nbits(flash);
533 t[1].len = len;
534 spi_message_add_tail(&t[1], &m);
535
536 mutex_lock(&flash->lock);
537
538 /* Wait till previous write/erase is done. */
539 if (wait_till_ready(flash)) {
540 /* REVISIT status return?? */
541 mutex_unlock(&flash->lock);
542 return 1;
543 }
544
545 /* Set up the write data buffer. */
546 opcode = flash->read_opcode;
547 flash->command[0] = opcode;
548 m25p_addr2cmd(flash, from, flash->command);
549
550 spi_sync(flash->spi, &m);
551
552 *retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
553
554 mutex_unlock(&flash->lock);
555
556 return 0;
557 }
558
559 /*
560 * Write an address range to the flash chip. Data must be written in
561 * FLASH_PAGESIZE chunks. The address range may be any size provided
562 * it is within the physical boundaries.
563 */
564 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
565 size_t *retlen, const u_char *buf)
566 {
567 struct m25p *flash = mtd_to_m25p(mtd);
568 u32 page_offset, page_size;
569 struct spi_transfer t[2];
570 struct spi_message m;
571
572 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
573 __func__, (u32)to, len);
574
575 spi_message_init(&m);
576 memset(t, 0, (sizeof t));
577
578 t[0].tx_buf = flash->command;
579 t[0].len = m25p_cmdsz(flash);
580 spi_message_add_tail(&t[0], &m);
581
582 t[1].tx_buf = buf;
583 spi_message_add_tail(&t[1], &m);
584
585 mutex_lock(&flash->lock);
586
587 /* Wait until finished previous write command. */
588 if (wait_till_ready(flash)) {
589 mutex_unlock(&flash->lock);
590 return 1;
591 }
592
593 write_enable(flash);
594
595 /* Set up the opcode in the write buffer. */
596 flash->command[0] = flash->program_opcode;
597 m25p_addr2cmd(flash, to, flash->command);
598
599 page_offset = to & (flash->page_size - 1);
600
601 /* do all the bytes fit onto one page? */
602 if (page_offset + len <= flash->page_size) {
603 t[1].len = len;
604
605 spi_sync(flash->spi, &m);
606
607 *retlen = m.actual_length - m25p_cmdsz(flash);
608 } else {
609 u32 i;
610
611 /* the size of data remaining on the first page */
612 page_size = flash->page_size - page_offset;
613
614 t[1].len = page_size;
615 spi_sync(flash->spi, &m);
616
617 *retlen = m.actual_length - m25p_cmdsz(flash);
618
619 /* write everything in flash->page_size chunks */
620 for (i = page_size; i < len; i += page_size) {
621 page_size = len - i;
622 if (page_size > flash->page_size)
623 page_size = flash->page_size;
624
625 /* write the next page to flash */
626 m25p_addr2cmd(flash, to + i, flash->command);
627
628 t[1].tx_buf = buf + i;
629 t[1].len = page_size;
630
631 wait_till_ready(flash);
632
633 write_enable(flash);
634
635 spi_sync(flash->spi, &m);
636
637 *retlen += m.actual_length - m25p_cmdsz(flash);
638 }
639 }
640
641 mutex_unlock(&flash->lock);
642
643 return 0;
644 }
645
646 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
647 size_t *retlen, const u_char *buf)
648 {
649 struct m25p *flash = mtd_to_m25p(mtd);
650 struct spi_transfer t[2];
651 struct spi_message m;
652 size_t actual;
653 int cmd_sz, ret;
654
655 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
656 __func__, (u32)to, len);
657
658 spi_message_init(&m);
659 memset(t, 0, (sizeof t));
660
661 t[0].tx_buf = flash->command;
662 t[0].len = m25p_cmdsz(flash);
663 spi_message_add_tail(&t[0], &m);
664
665 t[1].tx_buf = buf;
666 spi_message_add_tail(&t[1], &m);
667
668 mutex_lock(&flash->lock);
669
670 /* Wait until finished previous write command. */
671 ret = wait_till_ready(flash);
672 if (ret)
673 goto time_out;
674
675 write_enable(flash);
676
677 actual = to % 2;
678 /* Start write from odd address. */
679 if (actual) {
680 flash->command[0] = OPCODE_BP;
681 m25p_addr2cmd(flash, to, flash->command);
682
683 /* write one byte. */
684 t[1].len = 1;
685 spi_sync(flash->spi, &m);
686 ret = wait_till_ready(flash);
687 if (ret)
688 goto time_out;
689 *retlen += m.actual_length - m25p_cmdsz(flash);
690 }
691 to += actual;
692
693 flash->command[0] = OPCODE_AAI_WP;
694 m25p_addr2cmd(flash, to, flash->command);
695
696 /* Write out most of the data here. */
697 cmd_sz = m25p_cmdsz(flash);
698 for (; actual < len - 1; actual += 2) {
699 t[0].len = cmd_sz;
700 /* write two bytes. */
701 t[1].len = 2;
702 t[1].tx_buf = buf + actual;
703
704 spi_sync(flash->spi, &m);
705 ret = wait_till_ready(flash);
706 if (ret)
707 goto time_out;
708 *retlen += m.actual_length - cmd_sz;
709 cmd_sz = 1;
710 to += 2;
711 }
712 write_disable(flash);
713 ret = wait_till_ready(flash);
714 if (ret)
715 goto time_out;
716
717 /* Write out trailing byte if it exists. */
718 if (actual != len) {
719 write_enable(flash);
720 flash->command[0] = OPCODE_BP;
721 m25p_addr2cmd(flash, to, flash->command);
722 t[0].len = m25p_cmdsz(flash);
723 t[1].len = 1;
724 t[1].tx_buf = buf + actual;
725
726 spi_sync(flash->spi, &m);
727 ret = wait_till_ready(flash);
728 if (ret)
729 goto time_out;
730 *retlen += m.actual_length - m25p_cmdsz(flash);
731 write_disable(flash);
732 }
733
734 time_out:
735 mutex_unlock(&flash->lock);
736 return ret;
737 }
738
739 static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
740 {
741 struct m25p *flash = mtd_to_m25p(mtd);
742 uint32_t offset = ofs;
743 uint8_t status_old, status_new;
744 int res = 0;
745
746 mutex_lock(&flash->lock);
747 /* Wait until finished previous command */
748 if (wait_till_ready(flash)) {
749 res = 1;
750 goto err;
751 }
752
753 status_old = read_sr(flash);
754
755 if (offset < flash->mtd.size-(flash->mtd.size/2))
756 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
757 else if (offset < flash->mtd.size-(flash->mtd.size/4))
758 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
759 else if (offset < flash->mtd.size-(flash->mtd.size/8))
760 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
761 else if (offset < flash->mtd.size-(flash->mtd.size/16))
762 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
763 else if (offset < flash->mtd.size-(flash->mtd.size/32))
764 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
765 else if (offset < flash->mtd.size-(flash->mtd.size/64))
766 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
767 else
768 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
769
770 /* Only modify protection if it will not unlock other areas */
771 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) >
772 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
773 write_enable(flash);
774 if (write_sr(flash, status_new) < 0) {
775 res = 1;
776 goto err;
777 }
778 }
779
780 err: mutex_unlock(&flash->lock);
781 return res;
782 }
783
784 static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
785 {
786 struct m25p *flash = mtd_to_m25p(mtd);
787 uint32_t offset = ofs;
788 uint8_t status_old, status_new;
789 int res = 0;
790
791 mutex_lock(&flash->lock);
792 /* Wait until finished previous command */
793 if (wait_till_ready(flash)) {
794 res = 1;
795 goto err;
796 }
797
798 status_old = read_sr(flash);
799
800 if (offset+len > flash->mtd.size-(flash->mtd.size/64))
801 status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0);
802 else if (offset+len > flash->mtd.size-(flash->mtd.size/32))
803 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
804 else if (offset+len > flash->mtd.size-(flash->mtd.size/16))
805 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
806 else if (offset+len > flash->mtd.size-(flash->mtd.size/8))
807 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
808 else if (offset+len > flash->mtd.size-(flash->mtd.size/4))
809 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
810 else if (offset+len > flash->mtd.size-(flash->mtd.size/2))
811 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
812 else
813 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
814
815 /* Only modify protection if it will not lock other areas */
816 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) <
817 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
818 write_enable(flash);
819 if (write_sr(flash, status_new) < 0) {
820 res = 1;
821 goto err;
822 }
823 }
824
825 err: mutex_unlock(&flash->lock);
826 return res;
827 }
828
829 /****************************************************************************/
830
831 /*
832 * SPI device driver setup and teardown
833 */
834
835 struct flash_info {
836 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
837 * a high byte of zero plus three data bytes: the manufacturer id,
838 * then a two byte device id.
839 */
840 u32 jedec_id;
841 u16 ext_id;
842
843 /* The size listed here is what works with OPCODE_SE, which isn't
844 * necessarily called a "sector" by the vendor.
845 */
846 unsigned sector_size;
847 u16 n_sectors;
848
849 u16 page_size;
850 u16 addr_width;
851
852 u16 flags;
853 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
854 #define M25P_NO_ERASE 0x02 /* No erase command needed */
855 #define SST_WRITE 0x04 /* use SST byte programming */
856 #define M25P_NO_FR 0x08 /* Can't do fastread */
857 #define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */
858 #define M25P80_QUAD_READ 0x20 /* Flash supports Quad Read */
859 };
860
861 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
862 ((kernel_ulong_t)&(struct flash_info) { \
863 .jedec_id = (_jedec_id), \
864 .ext_id = (_ext_id), \
865 .sector_size = (_sector_size), \
866 .n_sectors = (_n_sectors), \
867 .page_size = 256, \
868 .flags = (_flags), \
869 })
870
871 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
872 ((kernel_ulong_t)&(struct flash_info) { \
873 .sector_size = (_sector_size), \
874 .n_sectors = (_n_sectors), \
875 .page_size = (_page_size), \
876 .addr_width = (_addr_width), \
877 .flags = (_flags), \
878 })
879
880 /* NOTE: double check command sets and memory organization when you add
881 * more flash chips. This current list focusses on newer chips, which
882 * have been converging on command sets which including JEDEC ID.
883 */
884 static const struct spi_device_id m25p_ids[] = {
885 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
886 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
887 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
888
889 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
890 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
891 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
892
893 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
894 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
895 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
896 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
897
898 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
899
900 /* EON -- en25xxx */
901 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
902 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
903 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
904 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
905 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
906 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
907
908 /* ESMT */
909 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
910
911 /* Everspin */
912 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, M25P_NO_ERASE | M25P_NO_FR) },
913 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, M25P_NO_ERASE | M25P_NO_FR) },
914
915 /* GigaDevice */
916 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
917 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
918
919 /* Intel/Numonyx -- xxxs33b */
920 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
921 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
922 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
923
924 /* Macronix */
925 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
926 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
927 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
928 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
929 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
930 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
931 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
932 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
933 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
934 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
935 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
936 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, M25P80_QUAD_READ) },
937
938 /* Micron */
939 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
940 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
941 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
942 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
943 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
944
945 /* PMC */
946 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
947 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
948 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
949
950 /* Spansion -- single (large) sector size only, at least
951 * for the chips listed here (without boot sectors).
952 */
953 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) },
954 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
955 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
956 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, M25P80_QUAD_READ) },
957 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, M25P80_QUAD_READ) },
958 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
959 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
960 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
961 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
962 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
963 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
964 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
965 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
966 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
967 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
968 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
969 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
970
971 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
972 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
973 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
974 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
975 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
976 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
977 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
978 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
979 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
980 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
981
982 /* ST Microelectronics -- newer production may have feature updates */
983 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
984 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
985 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
986 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
987 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
988 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
989 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
990 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
991 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
992 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
993
994 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
995 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
996 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
997 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
998 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
999 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
1000 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
1001 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
1002 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
1003
1004 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
1005 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
1006 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
1007
1008 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
1009 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
1010 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
1011
1012 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
1013 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
1014 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
1015 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
1016 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
1017
1018 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1019 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
1020 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
1021 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
1022 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
1023 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
1024 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
1025 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
1026 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
1027 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
1028 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1029 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1030 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
1031 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1032 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1033 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
1034
1035 /* Catalyst / On Semiconductor -- non-JEDEC */
1036 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, M25P_NO_ERASE | M25P_NO_FR) },
1037 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, M25P_NO_ERASE | M25P_NO_FR) },
1038 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
1039 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
1040 { "cat25128", CAT25_INFO(2048, 8, 64, 2, M25P_NO_ERASE | M25P_NO_FR) },
1041 { },
1042 };
1043 MODULE_DEVICE_TABLE(spi, m25p_ids);
1044
1045 static const struct spi_device_id *jedec_probe(struct spi_device *spi)
1046 {
1047 int tmp;
1048 u8 code = OPCODE_RDID;
1049 u8 id[5];
1050 u32 jedec;
1051 u16 ext_jedec;
1052 struct flash_info *info;
1053
1054 /* JEDEC also defines an optional "extended device information"
1055 * string for after vendor-specific data, after the three bytes
1056 * we use here. Supporting some chips might require using it.
1057 */
1058 tmp = spi_write_then_read(spi, &code, 1, id, 5);
1059 if (tmp < 0) {
1060 pr_debug("%s: error %d reading JEDEC ID\n",
1061 dev_name(&spi->dev), tmp);
1062 return ERR_PTR(tmp);
1063 }
1064 jedec = id[0];
1065 jedec = jedec << 8;
1066 jedec |= id[1];
1067 jedec = jedec << 8;
1068 jedec |= id[2];
1069
1070 ext_jedec = id[3] << 8 | id[4];
1071
1072 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
1073 info = (void *)m25p_ids[tmp].driver_data;
1074 if (info->jedec_id == jedec) {
1075 if (info->ext_id != 0 && info->ext_id != ext_jedec)
1076 continue;
1077 return &m25p_ids[tmp];
1078 }
1079 }
1080 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
1081 return ERR_PTR(-ENODEV);
1082 }
1083
1084
1085 /*
1086 * board specific setup should have ensured the SPI clock used here
1087 * matches what the READ command supports, at least until this driver
1088 * understands FAST_READ (for clocks over 25 MHz).
1089 */
1090 static int m25p_probe(struct spi_device *spi)
1091 {
1092 const struct spi_device_id *id = spi_get_device_id(spi);
1093 struct flash_platform_data *data;
1094 struct m25p *flash;
1095 struct flash_info *info;
1096 unsigned i;
1097 struct mtd_part_parser_data ppdata;
1098 struct device_node *np = spi->dev.of_node;
1099 int ret;
1100
1101 /* Platform data helps sort out which chip type we have, as
1102 * well as how this board partitions it. If we don't have
1103 * a chip ID, try the JEDEC id commands; they'll work for most
1104 * newer chips, even if we don't recognize the particular chip.
1105 */
1106 data = dev_get_platdata(&spi->dev);
1107 if (data && data->type) {
1108 const struct spi_device_id *plat_id;
1109
1110 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
1111 plat_id = &m25p_ids[i];
1112 if (strcmp(data->type, plat_id->name))
1113 continue;
1114 break;
1115 }
1116
1117 if (i < ARRAY_SIZE(m25p_ids) - 1)
1118 id = plat_id;
1119 else
1120 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
1121 }
1122
1123 info = (void *)id->driver_data;
1124
1125 if (info->jedec_id) {
1126 const struct spi_device_id *jid;
1127
1128 jid = jedec_probe(spi);
1129 if (IS_ERR(jid)) {
1130 return PTR_ERR(jid);
1131 } else if (jid != id) {
1132 /*
1133 * JEDEC knows better, so overwrite platform ID. We
1134 * can't trust partitions any longer, but we'll let
1135 * mtd apply them anyway, since some partitions may be
1136 * marked read-only, and we don't want to lose that
1137 * information, even if it's not 100% accurate.
1138 */
1139 dev_warn(&spi->dev, "found %s, expected %s\n",
1140 jid->name, id->name);
1141 id = jid;
1142 info = (void *)jid->driver_data;
1143 }
1144 }
1145
1146 flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
1147 if (!flash)
1148 return -ENOMEM;
1149
1150 flash->command = devm_kzalloc(&spi->dev, MAX_CMD_SIZE, GFP_KERNEL);
1151 if (!flash->command)
1152 return -ENOMEM;
1153
1154 flash->spi = spi;
1155 mutex_init(&flash->lock);
1156 spi_set_drvdata(spi, flash);
1157
1158 /*
1159 * Atmel, SST and Intel/Numonyx serial flash tend to power
1160 * up with the software protection bits set
1161 */
1162
1163 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
1164 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
1165 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
1166 write_enable(flash);
1167 write_sr(flash, 0);
1168 }
1169
1170 if (data && data->name)
1171 flash->mtd.name = data->name;
1172 else
1173 flash->mtd.name = dev_name(&spi->dev);
1174
1175 flash->mtd.type = MTD_NORFLASH;
1176 flash->mtd.writesize = 1;
1177 flash->mtd.flags = MTD_CAP_NORFLASH;
1178 flash->mtd.size = info->sector_size * info->n_sectors;
1179 flash->mtd._erase = m25p80_erase;
1180 flash->mtd._read = m25p80_read;
1181
1182 /* flash protection support for STmicro chips */
1183 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
1184 flash->mtd._lock = m25p80_lock;
1185 flash->mtd._unlock = m25p80_unlock;
1186 }
1187
1188 /* sst flash chips use AAI word program */
1189 if (info->flags & SST_WRITE)
1190 flash->mtd._write = sst_write;
1191 else
1192 flash->mtd._write = m25p80_write;
1193
1194 /* prefer "small sector" erase if possible */
1195 if (info->flags & SECT_4K) {
1196 flash->erase_opcode = OPCODE_BE_4K;
1197 flash->mtd.erasesize = 4096;
1198 } else if (info->flags & SECT_4K_PMC) {
1199 flash->erase_opcode = OPCODE_BE_4K_PMC;
1200 flash->mtd.erasesize = 4096;
1201 } else {
1202 flash->erase_opcode = OPCODE_SE;
1203 flash->mtd.erasesize = info->sector_size;
1204 }
1205
1206 if (info->flags & M25P_NO_ERASE)
1207 flash->mtd.flags |= MTD_NO_ERASE;
1208
1209 ppdata.of_node = spi->dev.of_node;
1210 flash->mtd.dev.parent = &spi->dev;
1211 flash->page_size = info->page_size;
1212 flash->mtd.writebufsize = flash->page_size;
1213
1214 if (np) {
1215 /* If we were instantiated by DT, use it */
1216 if (of_property_read_bool(np, "m25p,fast-read"))
1217 flash->flash_read = M25P80_FAST;
1218 else
1219 flash->flash_read = M25P80_NORMAL;
1220 } else {
1221 /* If we weren't instantiated by DT, default to fast-read */
1222 flash->flash_read = M25P80_FAST;
1223 }
1224
1225 /* Some devices cannot do fast-read, no matter what DT tells us */
1226 if (info->flags & M25P_NO_FR)
1227 flash->flash_read = M25P80_NORMAL;
1228
1229 /* Quad-read mode takes precedence over fast/normal */
1230 if (spi->mode & SPI_RX_QUAD && info->flags & M25P80_QUAD_READ) {
1231 ret = set_quad_mode(flash, info->jedec_id);
1232 if (ret) {
1233 dev_err(&flash->spi->dev, "quad mode not supported\n");
1234 return ret;
1235 }
1236 flash->flash_read = M25P80_QUAD;
1237 }
1238
1239 /* Default commands */
1240 switch (flash->flash_read) {
1241 case M25P80_QUAD:
1242 flash->read_opcode = OPCODE_QUAD_READ;
1243 break;
1244 case M25P80_FAST:
1245 flash->read_opcode = OPCODE_FAST_READ;
1246 break;
1247 case M25P80_NORMAL:
1248 flash->read_opcode = OPCODE_NORM_READ;
1249 break;
1250 default:
1251 dev_err(&flash->spi->dev, "No Read opcode defined\n");
1252 return -EINVAL;
1253 }
1254
1255 flash->program_opcode = OPCODE_PP;
1256
1257 if (info->addr_width)
1258 flash->addr_width = info->addr_width;
1259 else if (flash->mtd.size > 0x1000000) {
1260 /* enable 4-byte addressing if the device exceeds 16MiB */
1261 flash->addr_width = 4;
1262 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
1263 /* Dedicated 4-byte command set */
1264 switch (flash->flash_read) {
1265 case M25P80_QUAD:
1266 flash->read_opcode = OPCODE_QUAD_READ_4B;
1267 break;
1268 case M25P80_FAST:
1269 flash->read_opcode = OPCODE_FAST_READ_4B;
1270 break;
1271 case M25P80_NORMAL:
1272 flash->read_opcode = OPCODE_NORM_READ_4B;
1273 break;
1274 }
1275 flash->program_opcode = OPCODE_PP_4B;
1276 /* No small sector erase for 4-byte command set */
1277 flash->erase_opcode = OPCODE_SE_4B;
1278 flash->mtd.erasesize = info->sector_size;
1279 } else
1280 set_4byte(flash, info->jedec_id, 1);
1281 } else {
1282 flash->addr_width = 3;
1283 }
1284
1285 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
1286 (long long)flash->mtd.size >> 10);
1287
1288 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
1289 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1290 flash->mtd.name,
1291 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
1292 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
1293 flash->mtd.numeraseregions);
1294
1295 if (flash->mtd.numeraseregions)
1296 for (i = 0; i < flash->mtd.numeraseregions; i++)
1297 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
1298 ".erasesize = 0x%.8x (%uKiB), "
1299 ".numblocks = %d }\n",
1300 i, (long long)flash->mtd.eraseregions[i].offset,
1301 flash->mtd.eraseregions[i].erasesize,
1302 flash->mtd.eraseregions[i].erasesize / 1024,
1303 flash->mtd.eraseregions[i].numblocks);
1304
1305
1306 /* partitions should match sector boundaries; and it may be good to
1307 * use readonly partitions for writeprotected sectors (BP2..BP0).
1308 */
1309 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
1310 data ? data->parts : NULL,
1311 data ? data->nr_parts : 0);
1312 }
1313
1314
1315 static int m25p_remove(struct spi_device *spi)
1316 {
1317 struct m25p *flash = spi_get_drvdata(spi);
1318
1319 /* Clean up MTD stuff. */
1320 return mtd_device_unregister(&flash->mtd);
1321 }
1322
1323
1324 static struct spi_driver m25p80_driver = {
1325 .driver = {
1326 .name = "m25p80",
1327 .owner = THIS_MODULE,
1328 },
1329 .id_table = m25p_ids,
1330 .probe = m25p_probe,
1331 .remove = m25p_remove,
1332
1333 /* REVISIT: many of these chips have deep power-down modes, which
1334 * should clearly be entered on suspend() to minimize power use.
1335 * And also when they're otherwise idle...
1336 */
1337 };
1338
1339 module_spi_driver(m25p80_driver);
1340
1341 MODULE_LICENSE("GPL");
1342 MODULE_AUTHOR("Mike Lavender");
1343 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
Linux with added FPC-III support