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fix a kmap leak in virtio_console
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / init.c
blobc36de303c8f38d9545ecdb74b575e176ec1b1d25
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/ath9k_platform.h>
22 #include <linux/module.h>
23 #include <linux/relay.h>
24 #include <net/ieee80211_radiotap.h>
25
26 #include "ath9k.h"
27
28 struct ath9k_eeprom_ctx {
29 struct completion complete;
30 struct ath_hw *ah;
31 };
32
33 static char *dev_info = "ath9k";
34
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
39
40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
41 module_param_named(debug, ath9k_debug, uint, 0);
42 MODULE_PARM_DESC(debug, "Debugging mask");
43
44 int ath9k_modparam_nohwcrypt;
45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
47
48 int led_blink;
49 module_param_named(blink, led_blink, int, 0444);
50 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
51
52 static int ath9k_btcoex_enable;
53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
55
56 static int ath9k_bt_ant_diversity;
57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
59
60 bool is_ath9k_unloaded;
61 /* We use the hw_value as an index into our private channel structure */
62
63 #define CHAN2G(_freq, _idx) { \
64 .band = IEEE80211_BAND_2GHZ, \
65 .center_freq = (_freq), \
66 .hw_value = (_idx), \
67 .max_power = 20, \
68 }
69
70 #define CHAN5G(_freq, _idx) { \
71 .band = IEEE80211_BAND_5GHZ, \
72 .center_freq = (_freq), \
73 .hw_value = (_idx), \
74 .max_power = 20, \
75 }
76
77 /* Some 2 GHz radios are actually tunable on 2312-2732
78 * on 5 MHz steps, we support the channels which we know
79 * we have calibration data for all cards though to make
80 * this static */
81 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
82 CHAN2G(2412, 0), /* Channel 1 */
83 CHAN2G(2417, 1), /* Channel 2 */
84 CHAN2G(2422, 2), /* Channel 3 */
85 CHAN2G(2427, 3), /* Channel 4 */
86 CHAN2G(2432, 4), /* Channel 5 */
87 CHAN2G(2437, 5), /* Channel 6 */
88 CHAN2G(2442, 6), /* Channel 7 */
89 CHAN2G(2447, 7), /* Channel 8 */
90 CHAN2G(2452, 8), /* Channel 9 */
91 CHAN2G(2457, 9), /* Channel 10 */
92 CHAN2G(2462, 10), /* Channel 11 */
93 CHAN2G(2467, 11), /* Channel 12 */
94 CHAN2G(2472, 12), /* Channel 13 */
95 CHAN2G(2484, 13), /* Channel 14 */
96 };
97
98 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
99 * on 5 MHz steps, we support the channels which we know
100 * we have calibration data for all cards though to make
101 * this static */
102 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
103 /* _We_ call this UNII 1 */
104 CHAN5G(5180, 14), /* Channel 36 */
105 CHAN5G(5200, 15), /* Channel 40 */
106 CHAN5G(5220, 16), /* Channel 44 */
107 CHAN5G(5240, 17), /* Channel 48 */
108 /* _We_ call this UNII 2 */
109 CHAN5G(5260, 18), /* Channel 52 */
110 CHAN5G(5280, 19), /* Channel 56 */
111 CHAN5G(5300, 20), /* Channel 60 */
112 CHAN5G(5320, 21), /* Channel 64 */
113 /* _We_ call this "Middle band" */
114 CHAN5G(5500, 22), /* Channel 100 */
115 CHAN5G(5520, 23), /* Channel 104 */
116 CHAN5G(5540, 24), /* Channel 108 */
117 CHAN5G(5560, 25), /* Channel 112 */
118 CHAN5G(5580, 26), /* Channel 116 */
119 CHAN5G(5600, 27), /* Channel 120 */
120 CHAN5G(5620, 28), /* Channel 124 */
121 CHAN5G(5640, 29), /* Channel 128 */
122 CHAN5G(5660, 30), /* Channel 132 */
123 CHAN5G(5680, 31), /* Channel 136 */
124 CHAN5G(5700, 32), /* Channel 140 */
125 /* _We_ call this UNII 3 */
126 CHAN5G(5745, 33), /* Channel 149 */
127 CHAN5G(5765, 34), /* Channel 153 */
128 CHAN5G(5785, 35), /* Channel 157 */
129 CHAN5G(5805, 36), /* Channel 161 */
130 CHAN5G(5825, 37), /* Channel 165 */
131 };
132
133 /* Atheros hardware rate code addition for short premble */
134 #define SHPCHECK(__hw_rate, __flags) \
135 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
136
137 #define RATE(_bitrate, _hw_rate, _flags) { \
138 .bitrate = (_bitrate), \
139 .flags = (_flags), \
140 .hw_value = (_hw_rate), \
141 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
142 }
143
144 static struct ieee80211_rate ath9k_legacy_rates[] = {
145 RATE(10, 0x1b, 0),
146 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
147 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
148 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
149 RATE(60, 0x0b, (IEEE80211_RATE_SUPPORTS_5MHZ |
150 IEEE80211_RATE_SUPPORTS_10MHZ)),
151 RATE(90, 0x0f, (IEEE80211_RATE_SUPPORTS_5MHZ |
152 IEEE80211_RATE_SUPPORTS_10MHZ)),
153 RATE(120, 0x0a, (IEEE80211_RATE_SUPPORTS_5MHZ |
154 IEEE80211_RATE_SUPPORTS_10MHZ)),
155 RATE(180, 0x0e, (IEEE80211_RATE_SUPPORTS_5MHZ |
156 IEEE80211_RATE_SUPPORTS_10MHZ)),
157 RATE(240, 0x09, (IEEE80211_RATE_SUPPORTS_5MHZ |
158 IEEE80211_RATE_SUPPORTS_10MHZ)),
159 RATE(360, 0x0d, (IEEE80211_RATE_SUPPORTS_5MHZ |
160 IEEE80211_RATE_SUPPORTS_10MHZ)),
161 RATE(480, 0x08, (IEEE80211_RATE_SUPPORTS_5MHZ |
162 IEEE80211_RATE_SUPPORTS_10MHZ)),
163 RATE(540, 0x0c, (IEEE80211_RATE_SUPPORTS_5MHZ |
164 IEEE80211_RATE_SUPPORTS_10MHZ)),
165 };
166
167 #ifdef CONFIG_MAC80211_LEDS
168 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
169 { .throughput = 0 * 1024, .blink_time = 334 },
170 { .throughput = 1 * 1024, .blink_time = 260 },
171 { .throughput = 5 * 1024, .blink_time = 220 },
172 { .throughput = 10 * 1024, .blink_time = 190 },
173 { .throughput = 20 * 1024, .blink_time = 170 },
174 { .throughput = 50 * 1024, .blink_time = 150 },
175 { .throughput = 70 * 1024, .blink_time = 130 },
176 { .throughput = 100 * 1024, .blink_time = 110 },
177 { .throughput = 200 * 1024, .blink_time = 80 },
178 { .throughput = 300 * 1024, .blink_time = 50 },
179 };
180 #endif
181
182 static void ath9k_deinit_softc(struct ath_softc *sc);
183
184 /*
185 * Read and write, they both share the same lock. We do this to serialize
186 * reads and writes on Atheros 802.11n PCI devices only. This is required
187 * as the FIFO on these devices can only accept sanely 2 requests.
188 */
189
190 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
191 {
192 struct ath_hw *ah = (struct ath_hw *) hw_priv;
193 struct ath_common *common = ath9k_hw_common(ah);
194 struct ath_softc *sc = (struct ath_softc *) common->priv;
195
196 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
197 unsigned long flags;
198 spin_lock_irqsave(&sc->sc_serial_rw, flags);
199 iowrite32(val, sc->mem + reg_offset);
200 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
201 } else
202 iowrite32(val, sc->mem + reg_offset);
203 }
204
205 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
206 {
207 struct ath_hw *ah = (struct ath_hw *) hw_priv;
208 struct ath_common *common = ath9k_hw_common(ah);
209 struct ath_softc *sc = (struct ath_softc *) common->priv;
210 u32 val;
211
212 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
213 unsigned long flags;
214 spin_lock_irqsave(&sc->sc_serial_rw, flags);
215 val = ioread32(sc->mem + reg_offset);
216 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
217 } else
218 val = ioread32(sc->mem + reg_offset);
219 return val;
220 }
221
222 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
223 u32 set, u32 clr)
224 {
225 u32 val;
226
227 val = ioread32(sc->mem + reg_offset);
228 val &= ~clr;
229 val |= set;
230 iowrite32(val, sc->mem + reg_offset);
231
232 return val;
233 }
234
235 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
236 {
237 struct ath_hw *ah = (struct ath_hw *) hw_priv;
238 struct ath_common *common = ath9k_hw_common(ah);
239 struct ath_softc *sc = (struct ath_softc *) common->priv;
240 unsigned long uninitialized_var(flags);
241 u32 val;
242
243 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
244 spin_lock_irqsave(&sc->sc_serial_rw, flags);
245 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
246 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
247 } else
248 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
249
250 return val;
251 }
252
253 /**************************/
254 /* Initialization */
255 /**************************/
256
257 static void setup_ht_cap(struct ath_softc *sc,
258 struct ieee80211_sta_ht_cap *ht_info)
259 {
260 struct ath_hw *ah = sc->sc_ah;
261 struct ath_common *common = ath9k_hw_common(ah);
262 u8 tx_streams, rx_streams;
263 int i, max_streams;
264
265 ht_info->ht_supported = true;
266 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
267 IEEE80211_HT_CAP_SM_PS |
268 IEEE80211_HT_CAP_SGI_40 |
269 IEEE80211_HT_CAP_DSSSCCK40;
270
271 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
272 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
273
274 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
275 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
276
277 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
278 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
279
280 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))
281 max_streams = 1;
282 else if (AR_SREV_9462(ah))
283 max_streams = 2;
284 else if (AR_SREV_9300_20_OR_LATER(ah))
285 max_streams = 3;
286 else
287 max_streams = 2;
288
289 if (AR_SREV_9280_20_OR_LATER(ah)) {
290 if (max_streams >= 2)
291 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
292 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
293 }
294
295 /* set up supported mcs set */
296 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
297 tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams);
298 rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams);
299
300 ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
301 tx_streams, rx_streams);
302
303 if (tx_streams != rx_streams) {
304 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
305 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
306 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
307 }
308
309 for (i = 0; i < rx_streams; i++)
310 ht_info->mcs.rx_mask[i] = 0xff;
311
312 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
313 }
314
315 static void ath9k_reg_notifier(struct wiphy *wiphy,
316 struct regulatory_request *request)
317 {
318 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
319 struct ath_softc *sc = hw->priv;
320 struct ath_hw *ah = sc->sc_ah;
321 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
322
323 ath_reg_notifier_apply(wiphy, request, reg);
324
325 /* Set tx power */
326 if (ah->curchan) {
327 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power;
328 ath9k_ps_wakeup(sc);
329 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
330 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
331 /* synchronize DFS detector if regulatory domain changed */
332 if (sc->dfs_detector != NULL)
333 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
334 request->dfs_region);
335 ath9k_ps_restore(sc);
336 }
337 }
338
339 /*
340 * This function will allocate both the DMA descriptor structure, and the
341 * buffers it contains. These are used to contain the descriptors used
342 * by the system.
343 */
344 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
345 struct list_head *head, const char *name,
346 int nbuf, int ndesc, bool is_tx)
347 {
348 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
349 u8 *ds;
350 int i, bsize, desc_len;
351
352 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
353 name, nbuf, ndesc);
354
355 INIT_LIST_HEAD(head);
356
357 if (is_tx)
358 desc_len = sc->sc_ah->caps.tx_desc_len;
359 else
360 desc_len = sizeof(struct ath_desc);
361
362 /* ath_desc must be a multiple of DWORDs */
363 if ((desc_len % 4) != 0) {
364 ath_err(common, "ath_desc not DWORD aligned\n");
365 BUG_ON((desc_len % 4) != 0);
366 return -ENOMEM;
367 }
368
369 dd->dd_desc_len = desc_len * nbuf * ndesc;
370
371 /*
372 * Need additional DMA memory because we can't use
373 * descriptors that cross the 4K page boundary. Assume
374 * one skipped descriptor per 4K page.
375 */
376 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
377 u32 ndesc_skipped =
378 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
379 u32 dma_len;
380
381 while (ndesc_skipped) {
382 dma_len = ndesc_skipped * desc_len;
383 dd->dd_desc_len += dma_len;
384
385 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
386 }
387 }
388
389 /* allocate descriptors */
390 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
391 &dd->dd_desc_paddr, GFP_KERNEL);
392 if (!dd->dd_desc)
393 return -ENOMEM;
394
395 ds = (u8 *) dd->dd_desc;
396 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
397 name, ds, (u32) dd->dd_desc_len,
398 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
399
400 /* allocate buffers */
401 if (is_tx) {
402 struct ath_buf *bf;
403
404 bsize = sizeof(struct ath_buf) * nbuf;
405 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
406 if (!bf)
407 return -ENOMEM;
408
409 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
410 bf->bf_desc = ds;
411 bf->bf_daddr = DS2PHYS(dd, ds);
412
413 if (!(sc->sc_ah->caps.hw_caps &
414 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
415 /*
416 * Skip descriptor addresses which can cause 4KB
417 * boundary crossing (addr + length) with a 32 dword
418 * descriptor fetch.
419 */
420 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
421 BUG_ON((caddr_t) bf->bf_desc >=
422 ((caddr_t) dd->dd_desc +
423 dd->dd_desc_len));
424
425 ds += (desc_len * ndesc);
426 bf->bf_desc = ds;
427 bf->bf_daddr = DS2PHYS(dd, ds);
428 }
429 }
430 list_add_tail(&bf->list, head);
431 }
432 } else {
433 struct ath_rxbuf *bf;
434
435 bsize = sizeof(struct ath_rxbuf) * nbuf;
436 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
437 if (!bf)
438 return -ENOMEM;
439
440 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
441 bf->bf_desc = ds;
442 bf->bf_daddr = DS2PHYS(dd, ds);
443
444 if (!(sc->sc_ah->caps.hw_caps &
445 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
446 /*
447 * Skip descriptor addresses which can cause 4KB
448 * boundary crossing (addr + length) with a 32 dword
449 * descriptor fetch.
450 */
451 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
452 BUG_ON((caddr_t) bf->bf_desc >=
453 ((caddr_t) dd->dd_desc +
454 dd->dd_desc_len));
455
456 ds += (desc_len * ndesc);
457 bf->bf_desc = ds;
458 bf->bf_daddr = DS2PHYS(dd, ds);
459 }
460 }
461 list_add_tail(&bf->list, head);
462 }
463 }
464 return 0;
465 }
466
467 static int ath9k_init_queues(struct ath_softc *sc)
468 {
469 int i = 0;
470
471 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
472 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
473 ath_cabq_update(sc);
474
475 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
476
477 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
478 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
479 sc->tx.txq_map[i]->mac80211_qnum = i;
480 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
481 }
482 return 0;
483 }
484
485 static int ath9k_init_channels_rates(struct ath_softc *sc)
486 {
487 void *channels;
488
489 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
490 ARRAY_SIZE(ath9k_5ghz_chantable) !=
491 ATH9K_NUM_CHANNELS);
492
493 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
494 channels = devm_kzalloc(sc->dev,
495 sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
496 if (!channels)
497 return -ENOMEM;
498
499 memcpy(channels, ath9k_2ghz_chantable,
500 sizeof(ath9k_2ghz_chantable));
501 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
502 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
503 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
504 ARRAY_SIZE(ath9k_2ghz_chantable);
505 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
506 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
507 ARRAY_SIZE(ath9k_legacy_rates);
508 }
509
510 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
511 channels = devm_kzalloc(sc->dev,
512 sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
513 if (!channels)
514 return -ENOMEM;
515
516 memcpy(channels, ath9k_5ghz_chantable,
517 sizeof(ath9k_5ghz_chantable));
518 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
519 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
520 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
521 ARRAY_SIZE(ath9k_5ghz_chantable);
522 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
523 ath9k_legacy_rates + 4;
524 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
525 ARRAY_SIZE(ath9k_legacy_rates) - 4;
526 }
527 return 0;
528 }
529
530 static void ath9k_init_misc(struct ath_softc *sc)
531 {
532 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
533 int i = 0;
534
535 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
536
537 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
538 sc->config.txpowlimit = ATH_TXPOWER_MAX;
539 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
540 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
541
542 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
543 sc->beacon.bslot[i] = NULL;
544
545 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
546 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
547
548 sc->spec_config.enabled = 0;
549 sc->spec_config.short_repeat = true;
550 sc->spec_config.count = 8;
551 sc->spec_config.endless = false;
552 sc->spec_config.period = 0xFF;
553 sc->spec_config.fft_period = 0xF;
554 }
555
556 static void ath9k_init_pcoem_platform(struct ath_softc *sc)
557 {
558 struct ath_hw *ah = sc->sc_ah;
559 struct ath9k_hw_capabilities *pCap = &ah->caps;
560 struct ath_common *common = ath9k_hw_common(ah);
561
562 if (common->bus_ops->ath_bus_type != ATH_PCI)
563 return;
564
565 if (sc->driver_data & (ATH9K_PCI_CUS198 |
566 ATH9K_PCI_CUS230)) {
567 ah->config.xlna_gpio = 9;
568 ah->config.xatten_margin_cfg = true;
569 ah->config.alt_mingainidx = true;
570 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
571 sc->ant_comb.low_rssi_thresh = 20;
572 sc->ant_comb.fast_div_bias = 3;
573
574 ath_info(common, "Set parameters for %s\n",
575 (sc->driver_data & ATH9K_PCI_CUS198) ?
576 "CUS198" : "CUS230");
577 }
578
579 if (sc->driver_data & ATH9K_PCI_CUS217)
580 ath_info(common, "CUS217 card detected\n");
581
582 if (sc->driver_data & ATH9K_PCI_CUS252)
583 ath_info(common, "CUS252 card detected\n");
584
585 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
586 ath_info(common, "WB335 1-ANT card detected\n");
587
588 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
589 ath_info(common, "WB335 2-ANT card detected\n");
590
591 if (sc->driver_data & ATH9K_PCI_KILLER)
592 ath_info(common, "Killer Wireless card detected\n");
593
594 /*
595 * Some WB335 cards do not support antenna diversity. Since
596 * we use a hardcoded value for AR9565 instead of using the
597 * EEPROM/OTP data, remove the combining feature from
598 * the HW capabilities bitmap.
599 */
600 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
601 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
602 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
603 }
604
605 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
606 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
607 ath_info(common, "Set BT/WLAN RX diversity capability\n");
608 }
609
610 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
611 ah->config.pcie_waen = 0x0040473b;
612 ath_info(common, "Enable WAR for ASPM D3/L1\n");
613 }
614
615 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
616 ah->config.no_pll_pwrsave = true;
617 ath_info(common, "Disable PLL PowerSave\n");
618 }
619 }
620
621 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
622 void *ctx)
623 {
624 struct ath9k_eeprom_ctx *ec = ctx;
625
626 if (eeprom_blob)
627 ec->ah->eeprom_blob = eeprom_blob;
628
629 complete(&ec->complete);
630 }
631
632 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
633 {
634 struct ath9k_eeprom_ctx ec;
635 struct ath_hw *ah = ah = sc->sc_ah;
636 int err;
637
638 /* try to load the EEPROM content asynchronously */
639 init_completion(&ec.complete);
640 ec.ah = sc->sc_ah;
641
642 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
643 &ec, ath9k_eeprom_request_cb);
644 if (err < 0) {
645 ath_err(ath9k_hw_common(ah),
646 "EEPROM request failed\n");
647 return err;
648 }
649
650 wait_for_completion(&ec.complete);
651
652 if (!ah->eeprom_blob) {
653 ath_err(ath9k_hw_common(ah),
654 "Unable to load EEPROM file %s\n", name);
655 return -EINVAL;
656 }
657
658 return 0;
659 }
660
661 static void ath9k_eeprom_release(struct ath_softc *sc)
662 {
663 release_firmware(sc->sc_ah->eeprom_blob);
664 }
665
666 static int ath9k_init_soc_platform(struct ath_softc *sc)
667 {
668 struct ath9k_platform_data *pdata = sc->dev->platform_data;
669 struct ath_hw *ah = sc->sc_ah;
670 int ret = 0;
671
672 if (!pdata)
673 return 0;
674
675 if (pdata->eeprom_name) {
676 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
677 if (ret)
678 return ret;
679 }
680
681 if (pdata->tx_gain_buffalo)
682 ah->config.tx_gain_buffalo = true;
683
684 return ret;
685 }
686
687 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
688 const struct ath_bus_ops *bus_ops)
689 {
690 struct ath9k_platform_data *pdata = sc->dev->platform_data;
691 struct ath_hw *ah = NULL;
692 struct ath9k_hw_capabilities *pCap;
693 struct ath_common *common;
694 int ret = 0, i;
695 int csz = 0;
696
697 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
698 if (!ah)
699 return -ENOMEM;
700
701 ah->dev = sc->dev;
702 ah->hw = sc->hw;
703 ah->hw_version.devid = devid;
704 ah->reg_ops.read = ath9k_ioread32;
705 ah->reg_ops.write = ath9k_iowrite32;
706 ah->reg_ops.rmw = ath9k_reg_rmw;
707 sc->sc_ah = ah;
708 pCap = &ah->caps;
709
710 common = ath9k_hw_common(ah);
711 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
712 sc->tx99_power = MAX_RATE_POWER + 1;
713 init_waitqueue_head(&sc->tx_wait);
714
715 if (!pdata) {
716 ah->ah_flags |= AH_USE_EEPROM;
717 sc->sc_ah->led_pin = -1;
718 } else {
719 sc->sc_ah->gpio_mask = pdata->gpio_mask;
720 sc->sc_ah->gpio_val = pdata->gpio_val;
721 sc->sc_ah->led_pin = pdata->led_pin;
722 ah->is_clk_25mhz = pdata->is_clk_25mhz;
723 ah->get_mac_revision = pdata->get_mac_revision;
724 ah->external_reset = pdata->external_reset;
725 }
726
727 common->ops = &ah->reg_ops;
728 common->bus_ops = bus_ops;
729 common->ah = ah;
730 common->hw = sc->hw;
731 common->priv = sc;
732 common->debug_mask = ath9k_debug;
733 common->btcoex_enabled = ath9k_btcoex_enable == 1;
734 common->disable_ani = false;
735
736 /*
737 * Platform quirks.
738 */
739 ath9k_init_pcoem_platform(sc);
740
741 ret = ath9k_init_soc_platform(sc);
742 if (ret)
743 return ret;
744
745 /*
746 * Enable WLAN/BT RX Antenna diversity only when:
747 *
748 * - BTCOEX is disabled.
749 * - the user manually requests the feature.
750 * - the HW cap is set using the platform data.
751 */
752 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
753 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
754 common->bt_ant_diversity = 1;
755
756 spin_lock_init(&common->cc_lock);
757 spin_lock_init(&sc->sc_serial_rw);
758 spin_lock_init(&sc->sc_pm_lock);
759 mutex_init(&sc->mutex);
760 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
761 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
762 (unsigned long)sc);
763
764 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
765 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
766 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
767 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
768
769 /*
770 * Cache line size is used to size and align various
771 * structures used to communicate with the hardware.
772 */
773 ath_read_cachesize(common, &csz);
774 common->cachelsz = csz << 2; /* convert to bytes */
775
776 /* Initializes the hardware for all supported chipsets */
777 ret = ath9k_hw_init(ah);
778 if (ret)
779 goto err_hw;
780
781 if (pdata && pdata->macaddr)
782 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
783
784 ret = ath9k_init_queues(sc);
785 if (ret)
786 goto err_queues;
787
788 ret = ath9k_init_btcoex(sc);
789 if (ret)
790 goto err_btcoex;
791
792 ret = ath9k_init_channels_rates(sc);
793 if (ret)
794 goto err_btcoex;
795
796 ath9k_cmn_init_crypto(sc->sc_ah);
797 ath9k_init_misc(sc);
798 ath_fill_led_pin(sc);
799
800 if (common->bus_ops->aspm_init)
801 common->bus_ops->aspm_init(common);
802
803 return 0;
804
805 err_btcoex:
806 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
807 if (ATH_TXQ_SETUP(sc, i))
808 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
809 err_queues:
810 ath9k_hw_deinit(ah);
811 err_hw:
812 ath9k_eeprom_release(sc);
813 dev_kfree_skb_any(sc->tx99_skb);
814 return ret;
815 }
816
817 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
818 {
819 struct ieee80211_supported_band *sband;
820 struct ieee80211_channel *chan;
821 struct ath_hw *ah = sc->sc_ah;
822 struct cfg80211_chan_def chandef;
823 int i;
824
825 sband = &sc->sbands[band];
826 for (i = 0; i < sband->n_channels; i++) {
827 chan = &sband->channels[i];
828 ah->curchan = &ah->channels[chan->hw_value];
829 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
830 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
831 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
832 }
833 }
834
835 static void ath9k_init_txpower_limits(struct ath_softc *sc)
836 {
837 struct ath_hw *ah = sc->sc_ah;
838 struct ath9k_channel *curchan = ah->curchan;
839
840 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
841 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
842 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
843 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
844
845 ah->curchan = curchan;
846 }
847
848 void ath9k_reload_chainmask_settings(struct ath_softc *sc)
849 {
850 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT))
851 return;
852
853 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
854 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
855 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
856 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
857 }
858
859 static const struct ieee80211_iface_limit if_limits[] = {
860 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) |
861 BIT(NL80211_IFTYPE_P2P_CLIENT) |
862 BIT(NL80211_IFTYPE_WDS) },
863 { .max = 8, .types =
864 #ifdef CONFIG_MAC80211_MESH
865 BIT(NL80211_IFTYPE_MESH_POINT) |
866 #endif
867 BIT(NL80211_IFTYPE_AP) |
868 BIT(NL80211_IFTYPE_P2P_GO) },
869 };
870
871 static const struct ieee80211_iface_limit if_dfs_limits[] = {
872 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) |
873 #ifdef CONFIG_MAC80211_MESH
874 BIT(NL80211_IFTYPE_MESH_POINT) |
875 #endif
876 BIT(NL80211_IFTYPE_ADHOC) },
877 };
878
879 static const struct ieee80211_iface_combination if_comb[] = {
880 {
881 .limits = if_limits,
882 .n_limits = ARRAY_SIZE(if_limits),
883 .max_interfaces = 2048,
884 .num_different_channels = 1,
885 .beacon_int_infra_match = true,
886 },
887 {
888 .limits = if_dfs_limits,
889 .n_limits = ARRAY_SIZE(if_dfs_limits),
890 .max_interfaces = 1,
891 .num_different_channels = 1,
892 .beacon_int_infra_match = true,
893 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
894 BIT(NL80211_CHAN_WIDTH_20),
895 }
896 };
897
898 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
899 {
900 struct ath_hw *ah = sc->sc_ah;
901 struct ath_common *common = ath9k_hw_common(ah);
902
903 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
904 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
905 IEEE80211_HW_SIGNAL_DBM |
906 IEEE80211_HW_SUPPORTS_PS |
907 IEEE80211_HW_PS_NULLFUNC_STACK |
908 IEEE80211_HW_SPECTRUM_MGMT |
909 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
910 IEEE80211_HW_SUPPORTS_RC_TABLE |
911 IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
912
913 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
914 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
915
916 if (AR_SREV_9280_20_OR_LATER(ah))
917 hw->radiotap_mcs_details |=
918 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
919 }
920
921 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
922 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
923
924 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR;
925
926 if (!config_enabled(CONFIG_ATH9K_TX99)) {
927 hw->wiphy->interface_modes =
928 BIT(NL80211_IFTYPE_P2P_GO) |
929 BIT(NL80211_IFTYPE_P2P_CLIENT) |
930 BIT(NL80211_IFTYPE_AP) |
931 BIT(NL80211_IFTYPE_WDS) |
932 BIT(NL80211_IFTYPE_STATION) |
933 BIT(NL80211_IFTYPE_ADHOC) |
934 BIT(NL80211_IFTYPE_MESH_POINT);
935 hw->wiphy->iface_combinations = if_comb;
936 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
937 }
938
939 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
940
941 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
942 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
943 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
944 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
945 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
946
947 hw->queues = 4;
948 hw->max_rates = 4;
949 hw->max_listen_interval = 1;
950 hw->max_rate_tries = 10;
951 hw->sta_data_size = sizeof(struct ath_node);
952 hw->vif_data_size = sizeof(struct ath_vif);
953
954 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
955 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
956
957 /* single chain devices with rx diversity */
958 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
959 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
960
961 sc->ant_rx = hw->wiphy->available_antennas_rx;
962 sc->ant_tx = hw->wiphy->available_antennas_tx;
963
964 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
965 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
966 &sc->sbands[IEEE80211_BAND_2GHZ];
967 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
968 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
969 &sc->sbands[IEEE80211_BAND_5GHZ];
970
971 ath9k_init_wow(hw);
972 ath9k_reload_chainmask_settings(sc);
973
974 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
975 }
976
977 int ath9k_init_device(u16 devid, struct ath_softc *sc,
978 const struct ath_bus_ops *bus_ops)
979 {
980 struct ieee80211_hw *hw = sc->hw;
981 struct ath_common *common;
982 struct ath_hw *ah;
983 int error = 0;
984 struct ath_regulatory *reg;
985
986 /* Bring up device */
987 error = ath9k_init_softc(devid, sc, bus_ops);
988 if (error)
989 return error;
990
991 ah = sc->sc_ah;
992 common = ath9k_hw_common(ah);
993 ath9k_set_hw_capab(sc, hw);
994
995 /* Initialize regulatory */
996 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
997 ath9k_reg_notifier);
998 if (error)
999 goto deinit;
1000
1001 reg = &common->regulatory;
1002
1003 /* Setup TX DMA */
1004 error = ath_tx_init(sc, ATH_TXBUF);
1005 if (error != 0)
1006 goto deinit;
1007
1008 /* Setup RX DMA */
1009 error = ath_rx_init(sc, ATH_RXBUF);
1010 if (error != 0)
1011 goto deinit;
1012
1013 ath9k_init_txpower_limits(sc);
1014
1015 #ifdef CONFIG_MAC80211_LEDS
1016 /* must be initialized before ieee80211_register_hw */
1017 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
1018 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
1019 ARRAY_SIZE(ath9k_tpt_blink));
1020 #endif
1021
1022 /* Register with mac80211 */
1023 error = ieee80211_register_hw(hw);
1024 if (error)
1025 goto rx_cleanup;
1026
1027 error = ath9k_init_debug(ah);
1028 if (error) {
1029 ath_err(common, "Unable to create debugfs files\n");
1030 goto unregister;
1031 }
1032
1033 /* Handle world regulatory */
1034 if (!ath_is_world_regd(reg)) {
1035 error = regulatory_hint(hw->wiphy, reg->alpha2);
1036 if (error)
1037 goto debug_cleanup;
1038 }
1039
1040 ath_init_leds(sc);
1041 ath_start_rfkill_poll(sc);
1042
1043 return 0;
1044
1045 debug_cleanup:
1046 ath9k_deinit_debug(sc);
1047 unregister:
1048 ieee80211_unregister_hw(hw);
1049 rx_cleanup:
1050 ath_rx_cleanup(sc);
1051 deinit:
1052 ath9k_deinit_softc(sc);
1053 return error;
1054 }
1055
1056 /*****************************/
1057 /* De-Initialization */
1058 /*****************************/
1059
1060 static void ath9k_deinit_softc(struct ath_softc *sc)
1061 {
1062 int i = 0;
1063
1064 ath9k_deinit_btcoex(sc);
1065
1066 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1067 if (ATH_TXQ_SETUP(sc, i))
1068 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1069
1070 del_timer_sync(&sc->sleep_timer);
1071 ath9k_hw_deinit(sc->sc_ah);
1072 if (sc->dfs_detector != NULL)
1073 sc->dfs_detector->exit(sc->dfs_detector);
1074
1075 ath9k_eeprom_release(sc);
1076 }
1077
1078 void ath9k_deinit_device(struct ath_softc *sc)
1079 {
1080 struct ieee80211_hw *hw = sc->hw;
1081
1082 ath9k_ps_wakeup(sc);
1083
1084 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1085 ath_deinit_leds(sc);
1086
1087 ath9k_ps_restore(sc);
1088
1089 ath9k_deinit_debug(sc);
1090 ieee80211_unregister_hw(hw);
1091 ath_rx_cleanup(sc);
1092 ath9k_deinit_softc(sc);
1093 }
1094
1095 /************************/
1096 /* Module Hooks */
1097 /************************/
1098
1099 static int __init ath9k_init(void)
1100 {
1101 int error;
1102
1103 /* Register rate control algorithm */
1104 error = ath_rate_control_register();
1105 if (error != 0) {
1106 pr_err("Unable to register rate control algorithm: %d\n",
1107 error);
1108 goto err_out;
1109 }
1110
1111 error = ath_pci_init();
1112 if (error < 0) {
1113 pr_err("No PCI devices found, driver not installed\n");
1114 error = -ENODEV;
1115 goto err_rate_unregister;
1116 }
1117
1118 error = ath_ahb_init();
1119 if (error < 0) {
1120 error = -ENODEV;
1121 goto err_pci_exit;
1122 }
1123
1124 return 0;
1125
1126 err_pci_exit:
1127 ath_pci_exit();
1128
1129 err_rate_unregister:
1130 ath_rate_control_unregister();
1131 err_out:
1132 return error;
1133 }
1134 module_init(ath9k_init);
1135
1136 static void __exit ath9k_exit(void)
1137 {
1138 is_ath9k_unloaded = true;
1139 ath_ahb_exit();
1140 ath_pci_exit();
1141 ath_rate_control_unregister();
1142 pr_info("%s: Driver unloaded\n", dev_info);
1143 }
1144 module_exit(ath9k_exit);
Linux with added FPC-III support