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fix a kmap leak in virtio_console
[linux/fpc-iii.git] / drivers / net / wireless / rtlwifi / rtl8723ae / phy.c
blob5d318a85eda4047100eeec7c5297412c15d615fd
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../pci.h"
32 #include "../ps.h"
33 #include "reg.h"
34 #include "def.h"
35 #include "phy.h"
36 #include "rf.h"
37 #include "dm.h"
38 #include "table.h"
39
40 /* static forward definitions */
41 static u32 _phy_fw_rf_serial_read(struct ieee80211_hw *hw,
42 enum radio_path rfpath, u32 offset);
43 static void _phy_fw_rf_serial_write(struct ieee80211_hw *hw,
44 enum radio_path rfpath,
45 u32 offset, u32 data);
46 static u32 _phy_rf_serial_read(struct ieee80211_hw *hw,
47 enum radio_path rfpath, u32 offset);
48 static void _phy_rf_serial_write(struct ieee80211_hw *hw,
49 enum radio_path rfpath, u32 offset, u32 data);
50 static u32 _phy_calculate_bit_shift(u32 bitmask);
51 static bool _phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
52 static bool _phy_cfg_mac_w_header(struct ieee80211_hw *hw);
53 static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype);
54 static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype);
55 static void _phy_init_bb_rf_reg_def(struct ieee80211_hw *hw);
56 static bool _phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
57 u32 cmdtableidx, u32 cmdtablesz,
58 enum swchnlcmd_id cmdid,
59 u32 para1, u32 para2,
60 u32 msdelay);
61 static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
62 u8 *stage, u8 *step, u32 *delay);
63 static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
64 enum wireless_mode wirelessmode,
65 long power_indbm);
66 static long _phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
67 enum wireless_mode wirelessmode, u8 txpwridx);
68 static void rtl8723ae_phy_set_io(struct ieee80211_hw *hw);
69
70 u32 rtl8723ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
71 u32 bitmask)
72 {
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 u32 returnvalue, originalvalue, bitshift;
75
76 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
77 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
78 originalvalue = rtl_read_dword(rtlpriv, regaddr);
79 bitshift = _phy_calculate_bit_shift(bitmask);
80 returnvalue = (originalvalue & bitmask) >> bitshift;
81
82 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
83 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask, regaddr,
84 originalvalue);
85
86 return returnvalue;
87 }
88
89 void rtl8723ae_phy_set_bb_reg(struct ieee80211_hw *hw,
90 u32 regaddr, u32 bitmask, u32 data)
91 {
92 struct rtl_priv *rtlpriv = rtl_priv(hw);
93 u32 originalvalue, bitshift;
94
95 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
96 "regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr,
97 bitmask, data);
98
99 if (bitmask != MASKDWORD) {
100 originalvalue = rtl_read_dword(rtlpriv, regaddr);
101 bitshift = _phy_calculate_bit_shift(bitmask);
102 data = ((originalvalue & (~bitmask)) | (data << bitshift));
103 }
104
105 rtl_write_dword(rtlpriv, regaddr, data);
106
107 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
108 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
109 regaddr, bitmask, data);
110 }
111
112 u32 rtl8723ae_phy_query_rf_reg(struct ieee80211_hw *hw,
113 enum radio_path rfpath, u32 regaddr, u32 bitmask)
114 {
115 struct rtl_priv *rtlpriv = rtl_priv(hw);
116 u32 original_value, readback_value, bitshift;
117 struct rtl_phy *rtlphy = &(rtlpriv->phy);
118 unsigned long flags;
119
120 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
121 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
122 regaddr, rfpath, bitmask);
123
124 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
125
126 if (rtlphy->rf_mode != RF_OP_BY_FW)
127 original_value = _phy_rf_serial_read(hw, rfpath, regaddr);
128 else
129 original_value = _phy_fw_rf_serial_read(hw, rfpath, regaddr);
130
131 bitshift = _phy_calculate_bit_shift(bitmask);
132 readback_value = (original_value & bitmask) >> bitshift;
133
134 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
135
136 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
137 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
138 regaddr, rfpath, bitmask, original_value);
139
140 return readback_value;
141 }
142
143 void rtl8723ae_phy_set_rf_reg(struct ieee80211_hw *hw,
144 enum radio_path rfpath,
145 u32 regaddr, u32 bitmask, u32 data)
146 {
147 struct rtl_priv *rtlpriv = rtl_priv(hw);
148 struct rtl_phy *rtlphy = &(rtlpriv->phy);
149 u32 original_value, bitshift;
150 unsigned long flags;
151
152 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
153 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
154 regaddr, bitmask, data, rfpath);
155
156 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
157
158 if (rtlphy->rf_mode != RF_OP_BY_FW) {
159 if (bitmask != RFREG_OFFSET_MASK) {
160 original_value = _phy_rf_serial_read(hw, rfpath,
161 regaddr);
162 bitshift = _phy_calculate_bit_shift(bitmask);
163 data = ((original_value & (~bitmask)) |
164 (data << bitshift));
165 }
166
167 _phy_rf_serial_write(hw, rfpath, regaddr, data);
168 } else {
169 if (bitmask != RFREG_OFFSET_MASK) {
170 original_value = _phy_fw_rf_serial_read(hw, rfpath,
171 regaddr);
172 bitshift = _phy_calculate_bit_shift(bitmask);
173 data = ((original_value & (~bitmask)) |
174 (data << bitshift));
175 }
176 _phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
177 }
178
179 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
180
181 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
182 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
183 regaddr, bitmask, data, rfpath);
184 }
185
186 static u32 _phy_fw_rf_serial_read(struct ieee80211_hw *hw,
187 enum radio_path rfpath, u32 offset)
188 {
189 RT_ASSERT(false, "deprecated!\n");
190 return 0;
191 }
192
193 static void _phy_fw_rf_serial_write(struct ieee80211_hw *hw,
194 enum radio_path rfpath,
195 u32 offset, u32 data)
196 {
197 RT_ASSERT(false, "deprecated!\n");
198 }
199
200 static u32 _phy_rf_serial_read(struct ieee80211_hw *hw,
201 enum radio_path rfpath, u32 offset)
202 {
203 struct rtl_priv *rtlpriv = rtl_priv(hw);
204 struct rtl_phy *rtlphy = &(rtlpriv->phy);
205 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
206 u32 newoffset;
207 u32 tmplong, tmplong2;
208 u8 rfpi_enable = 0;
209 u32 retvalue;
210
211 offset &= 0x3f;
212 newoffset = offset;
213 if (RT_CANNOT_IO(hw)) {
214 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
215 return 0xFFFFFFFF;
216 }
217 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
218 if (rfpath == RF90_PATH_A)
219 tmplong2 = tmplong;
220 else
221 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
222 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
223 (newoffset << 23) | BLSSIREADEDGE;
224 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
225 tmplong & (~BLSSIREADEDGE));
226 mdelay(1);
227 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
228 mdelay(1);
229 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
230 tmplong | BLSSIREADEDGE);
231 mdelay(1);
232 if (rfpath == RF90_PATH_A)
233 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
234 BIT(8));
235 else if (rfpath == RF90_PATH_B)
236 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
237 BIT(8));
238 if (rfpi_enable)
239 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
240 BLSSIREADBACKDATA);
241 else
242 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
243 BLSSIREADBACKDATA);
244 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
245 rfpath, pphyreg->rf_rb, retvalue);
246 return retvalue;
247 }
248
249 static void _phy_rf_serial_write(struct ieee80211_hw *hw,
250 enum radio_path rfpath, u32 offset, u32 data)
251 {
252 u32 data_and_addr;
253 u32 newoffset;
254 struct rtl_priv *rtlpriv = rtl_priv(hw);
255 struct rtl_phy *rtlphy = &(rtlpriv->phy);
256 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
257
258 if (RT_CANNOT_IO(hw)) {
259 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
260 return;
261 }
262 offset &= 0x3f;
263 newoffset = offset;
264 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
265 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
266 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
267 rfpath, pphyreg->rf3wire_offset, data_and_addr);
268 }
269
270 static u32 _phy_calculate_bit_shift(u32 bitmask)
271 {
272 u32 i;
273
274 for (i = 0; i <= 31; i++) {
275 if (((bitmask >> i) & 0x1) == 1)
276 break;
277 }
278 return i;
279 }
280
281 static void _rtl8723ae_phy_bb_config_1t(struct ieee80211_hw *hw)
282 {
283 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
284 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
285 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
286 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
287 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
288 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
289 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
290 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
291 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
292 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
293 }
294
295 bool rtl8723ae_phy_mac_config(struct ieee80211_hw *hw)
296 {
297 struct rtl_priv *rtlpriv = rtl_priv(hw);
298 bool rtstatus = _phy_cfg_mac_w_header(hw);
299 rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
300 return rtstatus;
301 }
302
303 bool rtl8723ae_phy_bb_config(struct ieee80211_hw *hw)
304 {
305 bool rtstatus = true;
306 struct rtl_priv *rtlpriv = rtl_priv(hw);
307 u8 tmpu1b;
308 u8 reg_hwparafile = 1;
309
310 _phy_init_bb_rf_reg_def(hw);
311
312 /* 1. 0x28[1] = 1 */
313 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_PLL_CTRL);
314 udelay(2);
315 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, (tmpu1b|BIT(1)));
316 udelay(2);
317 /* 2. 0x29[7:0] = 0xFF */
318 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL+1, 0xff);
319 udelay(2);
320
321 /* 3. 0x02[1:0] = 2b'11 */
322 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
323 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmpu1b |
324 FEN_BB_GLB_RSTn | FEN_BBRSTB));
325
326 /* 4. 0x25[6] = 0 */
327 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+1);
328 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+1, (tmpu1b&(~BIT(6))));
329
330 /* 5. 0x24[20] = 0 Advised by SD3 Alex Wang. 2011.02.09. */
331 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2);
332 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, (tmpu1b&(~BIT(4))));
333
334 /* 6. 0x1f[7:0] = 0x07 */
335 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07);
336
337 if (reg_hwparafile == 1)
338 rtstatus = _phy_bb8192c_config_parafile(hw);
339 return rtstatus;
340 }
341
342 bool rtl8723ae_phy_rf_config(struct ieee80211_hw *hw)
343 {
344 return rtl8723ae_phy_rf6052_config(hw);
345 }
346
347 static bool _phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
348 {
349 struct rtl_priv *rtlpriv = rtl_priv(hw);
350 struct rtl_phy *rtlphy = &(rtlpriv->phy);
351 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
352 bool rtstatus;
353
354 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
355 rtstatus = _phy_cfg_bb_w_header(hw, BASEBAND_CONFIG_PHY_REG);
356 if (rtstatus != true) {
357 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!");
358 return false;
359 }
360
361 if (rtlphy->rf_type == RF_1T2R) {
362 _rtl8723ae_phy_bb_config_1t(hw);
363 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
364 }
365 if (rtlefuse->autoload_failflag == false) {
366 rtlphy->pwrgroup_cnt = 0;
367 rtstatus = _phy_cfg_bb_w_pgheader(hw, BASEBAND_CONFIG_PHY_REG);
368 }
369 if (rtstatus != true) {
370 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
371 return false;
372 }
373 rtstatus = _phy_cfg_bb_w_header(hw, BASEBAND_CONFIG_AGC_TAB);
374 if (rtstatus != true) {
375 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
376 return false;
377 }
378 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
379 RFPGA0_XA_HSSIPARAMETER2, 0x200));
380 return true;
381 }
382
383 static bool _phy_cfg_mac_w_header(struct ieee80211_hw *hw)
384 {
385 struct rtl_priv *rtlpriv = rtl_priv(hw);
386 u32 i;
387 u32 arraylength;
388 u32 *ptrarray;
389
390 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl723MACPHY_Array\n");
391 arraylength = RTL8723E_MACARRAYLENGTH;
392 ptrarray = RTL8723EMAC_ARRAY;
393
394 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
395 "Img:RTL8192CEMAC_2T_ARRAY\n");
396 for (i = 0; i < arraylength; i = i + 2)
397 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
398 return true;
399 }
400
401 static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype)
402 {
403 int i;
404 u32 *phy_regarray_table;
405 u32 *agctab_array_table;
406 u16 phy_reg_arraylen, agctab_arraylen;
407 struct rtl_priv *rtlpriv = rtl_priv(hw);
408
409 agctab_arraylen = RTL8723E_AGCTAB_1TARRAYLENGTH;
410 agctab_array_table = RTL8723EAGCTAB_1TARRAY;
411 phy_reg_arraylen = RTL8723E_PHY_REG_1TARRAY_LENGTH;
412 phy_regarray_table = RTL8723EPHY_REG_1TARRAY;
413 if (configtype == BASEBAND_CONFIG_PHY_REG) {
414 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
415 if (phy_regarray_table[i] == 0xfe)
416 mdelay(50);
417 else if (phy_regarray_table[i] == 0xfd)
418 mdelay(5);
419 else if (phy_regarray_table[i] == 0xfc)
420 mdelay(1);
421 else if (phy_regarray_table[i] == 0xfb)
422 udelay(50);
423 else if (phy_regarray_table[i] == 0xfa)
424 udelay(5);
425 else if (phy_regarray_table[i] == 0xf9)
426 udelay(1);
427 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
428 phy_regarray_table[i + 1]);
429 udelay(1);
430 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
431 "The phy_regarray_table[0] is %x"
432 " Rtl819XPHY_REGArray[1] is %x\n",
433 phy_regarray_table[i],
434 phy_regarray_table[i + 1]);
435 }
436 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
437 for (i = 0; i < agctab_arraylen; i = i + 2) {
438 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
439 agctab_array_table[i + 1]);
440 udelay(1);
441 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
442 "The agctab_array_table[0] is "
443 "%x Rtl819XPHY_REGArray[1] is %x\n",
444 agctab_array_table[i],
445 agctab_array_table[i + 1]);
446 }
447 }
448 return true;
449 }
450
451 static void _st_pwrIdx_dfrate_off(struct ieee80211_hw *hw, u32 regaddr,
452 u32 bitmask, u32 data)
453 {
454 struct rtl_priv *rtlpriv = rtl_priv(hw);
455 struct rtl_phy *rtlphy = &(rtlpriv->phy);
456
457 switch (regaddr) {
458 case RTXAGC_A_RATE18_06:
459 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0] = data;
460 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
461 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
462 rtlphy->pwrgroup_cnt,
463 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0]);
464 break;
465 case RTXAGC_A_RATE54_24:
466 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1] = data;
467 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
468 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
469 rtlphy->pwrgroup_cnt,
470 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1]);
471 break;
472 case RTXAGC_A_CCK1_MCS32:
473 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6] = data;
474 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
475 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
476 rtlphy->pwrgroup_cnt,
477 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6]);
478 break;
479 case RTXAGC_B_CCK11_A_CCK2_11:
480 if (bitmask == 0xffffff00) {
481 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7] = data;
482 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
483 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
484 rtlphy->pwrgroup_cnt,
485 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7]);
486 }
487 if (bitmask == 0x000000ff) {
488 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15] = data;
489 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
490 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
491 rtlphy->pwrgroup_cnt,
492 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15]);
493 }
494 break;
495 case RTXAGC_A_MCS03_MCS00:
496 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2] = data;
497 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
498 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
499 rtlphy->pwrgroup_cnt,
500 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2]);
501 break;
502 case RTXAGC_A_MCS07_MCS04:
503 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3] = data;
504 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
505 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
506 rtlphy->pwrgroup_cnt,
507 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3]);
508 break;
509 case RTXAGC_A_MCS11_MCS08:
510 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4] = data;
511 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
512 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
513 rtlphy->pwrgroup_cnt,
514 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4]);
515 break;
516 case RTXAGC_A_MCS15_MCS12:
517 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5] = data;
518 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
519 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
520 rtlphy->pwrgroup_cnt,
521 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5]);
522 break;
523 case RTXAGC_B_RATE18_06:
524 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8] = data;
525 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
526 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
527 rtlphy->pwrgroup_cnt,
528 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8]);
529 break;
530 case RTXAGC_B_RATE54_24:
531 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9] = data;
532 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
533 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
534 rtlphy->pwrgroup_cnt,
535 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9]);
536 break;
537 case RTXAGC_B_CCK1_55_MCS32:
538 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14] = data;
539 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
540 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
541 rtlphy->pwrgroup_cnt,
542 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14]);
543 break;
544 case RTXAGC_B_MCS03_MCS00:
545 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10] = data;
546 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
547 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
548 rtlphy->pwrgroup_cnt,
549 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10]);
550 break;
551 case RTXAGC_B_MCS07_MCS04:
552 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11] = data;
553 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
554 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
555 rtlphy->pwrgroup_cnt,
556 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11]);
557 break;
558 case RTXAGC_B_MCS11_MCS08:
559 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12] = data;
560 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
561 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
562 rtlphy->pwrgroup_cnt,
563 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12]);
564 break;
565 case RTXAGC_B_MCS15_MCS12:
566 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13] = data;
567 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
568 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
569 rtlphy->pwrgroup_cnt,
570 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13]);
571 rtlphy->pwrgroup_cnt++;
572 break;
573 }
574 }
575
576 static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype)
577 {
578 struct rtl_priv *rtlpriv = rtl_priv(hw);
579 int i;
580 u32 *phy_regarray_table_pg;
581 u16 phy_regarray_pg_len;
582
583 phy_regarray_pg_len = RTL8723E_PHY_REG_ARRAY_PGLENGTH;
584 phy_regarray_table_pg = RTL8723EPHY_REG_ARRAY_PG;
585
586 if (configtype == BASEBAND_CONFIG_PHY_REG) {
587 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
588 if (phy_regarray_table_pg[i] == 0xfe)
589 mdelay(50);
590 else if (phy_regarray_table_pg[i] == 0xfd)
591 mdelay(5);
592 else if (phy_regarray_table_pg[i] == 0xfc)
593 mdelay(1);
594 else if (phy_regarray_table_pg[i] == 0xfb)
595 udelay(50);
596 else if (phy_regarray_table_pg[i] == 0xfa)
597 udelay(5);
598 else if (phy_regarray_table_pg[i] == 0xf9)
599 udelay(1);
600
601 _st_pwrIdx_dfrate_off(hw, phy_regarray_table_pg[i],
602 phy_regarray_table_pg[i + 1],
603 phy_regarray_table_pg[i + 2]);
604 }
605 } else {
606 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
607 "configtype != BaseBand_Config_PHY_REG\n");
608 }
609 return true;
610 }
611
612 bool rtl8723ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
613 enum radio_path rfpath)
614 {
615 struct rtl_priv *rtlpriv = rtl_priv(hw);
616 int i;
617 u32 *radioa_array_table;
618 u16 radioa_arraylen;
619
620 radioa_arraylen = Rtl8723ERADIOA_1TARRAYLENGTH;
621 radioa_array_table = RTL8723E_RADIOA_1TARRAY;
622
623 switch (rfpath) {
624 case RF90_PATH_A:
625 for (i = 0; i < radioa_arraylen; i = i + 2) {
626 if (radioa_array_table[i] == 0xfe)
627 mdelay(50);
628 else if (radioa_array_table[i] == 0xfd)
629 mdelay(5);
630 else if (radioa_array_table[i] == 0xfc)
631 mdelay(1);
632 else if (radioa_array_table[i] == 0xfb)
633 udelay(50);
634 else if (radioa_array_table[i] == 0xfa)
635 udelay(5);
636 else if (radioa_array_table[i] == 0xf9)
637 udelay(1);
638 else {
639 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
640 RFREG_OFFSET_MASK,
641 radioa_array_table[i + 1]);
642 udelay(1);
643 }
644 }
645 break;
646 case RF90_PATH_B:
647 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
648 "switch case not process\n");
649 break;
650 case RF90_PATH_C:
651 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
652 "switch case not process\n");
653 break;
654 case RF90_PATH_D:
655 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
656 "switch case not process\n");
657 break;
658 }
659 return true;
660 }
661
662 void rtl8723ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
663 {
664 struct rtl_priv *rtlpriv = rtl_priv(hw);
665 struct rtl_phy *rtlphy = &(rtlpriv->phy);
666
667 rtlphy->default_initialgain[0] =
668 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
669 rtlphy->default_initialgain[1] =
670 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
671 rtlphy->default_initialgain[2] =
672 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
673 rtlphy->default_initialgain[3] =
674 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
675
676 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
677 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
678 rtlphy->default_initialgain[0],
679 rtlphy->default_initialgain[1],
680 rtlphy->default_initialgain[2],
681 rtlphy->default_initialgain[3]);
682
683 rtlphy->framesync = (u8) rtl_get_bbreg(hw,
684 ROFDM0_RXDETECTOR3, MASKBYTE0);
685 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
686 ROFDM0_RXDETECTOR2, MASKDWORD);
687
688 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
689 "Default framesync (0x%x) = 0x%x\n",
690 ROFDM0_RXDETECTOR3, rtlphy->framesync);
691 }
692
693 static void _phy_init_bb_rf_reg_def(struct ieee80211_hw *hw)
694 {
695 struct rtl_priv *rtlpriv = rtl_priv(hw);
696 struct rtl_phy *rtlphy = &(rtlpriv->phy);
697
698 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
699 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
700 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
701 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
702
703 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
704 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
705 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
706 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
707
708 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
709 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
710
711 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
712 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
713
714 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
715 RFPGA0_XA_LSSIPARAMETER;
716 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
717 RFPGA0_XB_LSSIPARAMETER;
718
719 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
720 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
721 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
722 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
723
724 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
725 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
726 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
727 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
728
729 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
730 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
731
732 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
733 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
734
735 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
736 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
737 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
738 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
739
740 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
741 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
742 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
743 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
744
745 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
746 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
747 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
748 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
749
750 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
751 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
752 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
753 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
754
755 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
756 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
757 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
758 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
759
760 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
761 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
762 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
763 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
764
765 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
766 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
767 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
768 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
769
770 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
771 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
772 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
773 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
774
775 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
776 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
777 }
778
779 void rtl8723ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
780 {
781 struct rtl_priv *rtlpriv = rtl_priv(hw);
782 struct rtl_phy *rtlphy = &(rtlpriv->phy);
783 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
784 u8 txpwr_level;
785 long txpwr_dbm;
786
787 txpwr_level = rtlphy->cur_cck_txpwridx;
788 txpwr_dbm = _phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B, txpwr_level);
789 txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
790 rtlefuse->legacy_ht_txpowerdiff;
791 if (_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) > txpwr_dbm)
792 txpwr_dbm = _phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
793 txpwr_level);
794 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
795 if (_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, txpwr_level) >
796 txpwr_dbm)
797 txpwr_dbm = _phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
798 txpwr_level);
799 *powerlevel = txpwr_dbm;
800 }
801
802 static void _rtl8723ae_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
803 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
804 {
805 struct rtl_priv *rtlpriv = rtl_priv(hw);
806 struct rtl_phy *rtlphy = &(rtlpriv->phy);
807 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
808 u8 index = (channel - 1);
809
810 cckpowerlevel[RF90_PATH_A] =
811 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
812 cckpowerlevel[RF90_PATH_B] =
813 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
814 if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
815 ofdmpowerlevel[RF90_PATH_A] =
816 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
817 ofdmpowerlevel[RF90_PATH_B] =
818 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
819 } else if (get_rf_type(rtlphy) == RF_2T2R) {
820 ofdmpowerlevel[RF90_PATH_A] =
821 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
822 ofdmpowerlevel[RF90_PATH_B] =
823 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
824 }
825 }
826
827 static void _rtl8723ae_ccxpower_index_check(struct ieee80211_hw *hw,
828 u8 channel, u8 *cckpowerlevel,
829 u8 *ofdmpowerlevel)
830 {
831 struct rtl_priv *rtlpriv = rtl_priv(hw);
832 struct rtl_phy *rtlphy = &(rtlpriv->phy);
833
834 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
835 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
836 }
837
838 void rtl8723ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
839 {
840 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
841 u8 cckpowerlevel[2], ofdmpowerlevel[2];
842
843 if (rtlefuse->txpwr_fromeprom == false)
844 return;
845 _rtl8723ae_get_txpower_index(hw, channel, &cckpowerlevel[0],
846 &ofdmpowerlevel[0]);
847 _rtl8723ae_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
848 &ofdmpowerlevel[0]);
849 rtl8723ae_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
850 rtl8723ae_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
851 }
852
853 bool rtl8723ae_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
854 {
855 struct rtl_priv *rtlpriv = rtl_priv(hw);
856 struct rtl_phy *rtlphy = &(rtlpriv->phy);
857 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
858 u8 idx;
859 u8 rf_path;
860 u8 ccktxpwridx = _phy_dbm_to_txpwr_Idx(hw, WIRELESS_MODE_B,
861 power_indbm);
862 u8 ofdmtxpwridx = _phy_dbm_to_txpwr_Idx(hw, WIRELESS_MODE_N_24G,
863 power_indbm);
864 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
865 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
866 else
867 ofdmtxpwridx = 0;
868 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
869 "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
870 power_indbm, ccktxpwridx, ofdmtxpwridx);
871 for (idx = 0; idx < 14; idx++) {
872 for (rf_path = 0; rf_path < 2; rf_path++) {
873 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
874 rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
875 ofdmtxpwridx;
876 rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
877 ofdmtxpwridx;
878 }
879 }
880 rtl8723ae_phy_set_txpower_level(hw, rtlphy->current_channel);
881 return true;
882 }
883
884 static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
885 enum wireless_mode wirelessmode,
886 long power_indbm)
887 {
888 u8 txpwridx;
889 long offset;
890
891 switch (wirelessmode) {
892 case WIRELESS_MODE_B:
893 offset = -7;
894 break;
895 case WIRELESS_MODE_G:
896 case WIRELESS_MODE_N_24G:
897 offset = -8;
898 break;
899 default:
900 offset = -8;
901 break;
902 }
903
904 if ((power_indbm - offset) > 0)
905 txpwridx = (u8) ((power_indbm - offset) * 2);
906 else
907 txpwridx = 0;
908
909 if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
910 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
911
912 return txpwridx;
913 }
914
915 static long _phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
916 enum wireless_mode wirelessmode, u8 txpwridx)
917 {
918 long offset;
919 long pwrout_dbm;
920
921 switch (wirelessmode) {
922 case WIRELESS_MODE_B:
923 offset = -7;
924 break;
925 case WIRELESS_MODE_G:
926 case WIRELESS_MODE_N_24G:
927 offset = -8;
928 break;
929 default:
930 offset = -8;
931 break;
932 }
933 pwrout_dbm = txpwridx / 2 + offset;
934 return pwrout_dbm;
935 }
936
937 void rtl8723ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
938 {
939 struct rtl_priv *rtlpriv = rtl_priv(hw);
940 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
941 struct rtl_phy *rtlphy = &(rtlpriv->phy);
942 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
943 u8 reg_bw_opmode;
944 u8 reg_prsr_rsc;
945
946 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
947 "Switch to %s bandwidth\n",
948 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
949 "20MHz" : "40MHz");
950
951 if (is_hal_stop(rtlhal)) {
952 rtlphy->set_bwmode_inprogress = false;
953 return;
954 }
955
956 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
957 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
958
959 switch (rtlphy->current_chan_bw) {
960 case HT_CHANNEL_WIDTH_20:
961 reg_bw_opmode |= BW_OPMODE_20MHZ;
962 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
963 break;
964 case HT_CHANNEL_WIDTH_20_40:
965 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
966 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
967 reg_prsr_rsc =
968 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
969 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
970 break;
971 default:
972 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
973 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
974 break;
975 }
976
977 switch (rtlphy->current_chan_bw) {
978 case HT_CHANNEL_WIDTH_20:
979 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
980 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
981 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
982 break;
983 case HT_CHANNEL_WIDTH_20_40:
984 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
985 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
986
987 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
988 (mac->cur_40_prime_sc >> 1));
989 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
990 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
991
992 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
993 (mac->cur_40_prime_sc ==
994 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
995 break;
996 default:
997 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
998 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
999 break;
1000 }
1001 rtl8723ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1002 rtlphy->set_bwmode_inprogress = false;
1003 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1004 }
1005
1006 void rtl8723ae_phy_set_bw_mode(struct ieee80211_hw *hw,
1007 enum nl80211_channel_type ch_type)
1008 {
1009 struct rtl_priv *rtlpriv = rtl_priv(hw);
1010 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1011 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1012 u8 tmp_bw = rtlphy->current_chan_bw;
1013
1014 if (rtlphy->set_bwmode_inprogress)
1015 return;
1016 rtlphy->set_bwmode_inprogress = true;
1017 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1018 rtl8723ae_phy_set_bw_mode_callback(hw);
1019 } else {
1020 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1021 "FALSE driver sleep or unload\n");
1022 rtlphy->set_bwmode_inprogress = false;
1023 rtlphy->current_chan_bw = tmp_bw;
1024 }
1025 }
1026
1027 void rtl8723ae_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1028 {
1029 struct rtl_priv *rtlpriv = rtl_priv(hw);
1030 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1031 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1032 u32 delay;
1033
1034 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1035 "switch to channel%d\n", rtlphy->current_channel);
1036 if (is_hal_stop(rtlhal))
1037 return;
1038 do {
1039 if (!rtlphy->sw_chnl_inprogress)
1040 break;
1041 if (!_phy_sw_chnl_step_by_step
1042 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1043 &rtlphy->sw_chnl_step, &delay)) {
1044 if (delay > 0)
1045 mdelay(delay);
1046 else
1047 continue;
1048 } else {
1049 rtlphy->sw_chnl_inprogress = false;
1050 }
1051 break;
1052 } while (true);
1053 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1054 }
1055
1056 u8 rtl8723ae_phy_sw_chnl(struct ieee80211_hw *hw)
1057 {
1058 struct rtl_priv *rtlpriv = rtl_priv(hw);
1059 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1060 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1061
1062 if (rtlphy->sw_chnl_inprogress)
1063 return 0;
1064 if (rtlphy->set_bwmode_inprogress)
1065 return 0;
1066 RT_ASSERT((rtlphy->current_channel <= 14),
1067 "WIRELESS_MODE_G but channel>14");
1068 rtlphy->sw_chnl_inprogress = true;
1069 rtlphy->sw_chnl_stage = 0;
1070 rtlphy->sw_chnl_step = 0;
1071 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1072 rtl8723ae_phy_sw_chnl_callback(hw);
1073 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1074 "sw_chnl_inprogress false schedule workitem\n");
1075 rtlphy->sw_chnl_inprogress = false;
1076 } else {
1077 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1078 "sw_chnl_inprogress false driver sleep or unload\n");
1079 rtlphy->sw_chnl_inprogress = false;
1080 }
1081 return 1;
1082 }
1083
1084 static void _rtl8723ae_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
1085 {
1086 struct rtl_priv *rtlpriv = rtl_priv(hw);
1087 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1088 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1089
1090 if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
1091 if (channel == 6 && rtlphy->current_chan_bw ==
1092 HT_CHANNEL_WIDTH_20)
1093 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
1094 0x00255);
1095 else{
1096 u32 backupRF0x1A = (u32)rtl_get_rfreg(hw, RF90_PATH_A,
1097 RF_RX_G1, RFREG_OFFSET_MASK);
1098 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
1099 backupRF0x1A);
1100 }
1101 }
1102 }
1103
1104 static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
1105 u8 *stage, u8 *step, u32 *delay)
1106 {
1107 struct rtl_priv *rtlpriv = rtl_priv(hw);
1108 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1109 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1110 u32 precommoncmdcnt;
1111 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
1112 u32 postcommoncmdcnt;
1113 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
1114 u32 rfdependcmdcnt;
1115 struct swchnlcmd *currentcmd = NULL;
1116 u8 rfpath;
1117 u8 num_total_rfpath = rtlphy->num_total_rfpath;
1118
1119 precommoncmdcnt = 0;
1120 _phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1121 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL,
1122 0, 0, 0);
1123 _phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1124 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1125 postcommoncmdcnt = 0;
1126
1127 _phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1128 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
1129 rfdependcmdcnt = 0;
1130
1131 RT_ASSERT((channel >= 1 && channel <= 14),
1132 "illegal channel for Zebra: %d\n", channel);
1133
1134 _phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1135 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
1136 RF_CHNLBW, channel, 10);
1137
1138 _phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1139 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
1140
1141 do {
1142 switch (*stage) {
1143 case 0:
1144 currentcmd = &precommoncmd[*step];
1145 break;
1146 case 1:
1147 currentcmd = &rfdependcmd[*step];
1148 break;
1149 case 2:
1150 currentcmd = &postcommoncmd[*step];
1151 break;
1152 }
1153
1154 if (currentcmd->cmdid == CMDID_END) {
1155 if ((*stage) == 2) {
1156 return true;
1157 } else {
1158 (*stage)++;
1159 (*step) = 0;
1160 continue;
1161 }
1162 }
1163
1164 switch (currentcmd->cmdid) {
1165 case CMDID_SET_TXPOWEROWER_LEVEL:
1166 rtl8723ae_phy_set_txpower_level(hw, channel);
1167 break;
1168 case CMDID_WRITEPORT_ULONG:
1169 rtl_write_dword(rtlpriv, currentcmd->para1,
1170 currentcmd->para2);
1171 break;
1172 case CMDID_WRITEPORT_USHORT:
1173 rtl_write_word(rtlpriv, currentcmd->para1,
1174 (u16) currentcmd->para2);
1175 break;
1176 case CMDID_WRITEPORT_UCHAR:
1177 rtl_write_byte(rtlpriv, currentcmd->para1,
1178 (u8) currentcmd->para2);
1179 break;
1180 case CMDID_RF_WRITEREG:
1181 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1182 rtlphy->rfreg_chnlval[rfpath] =
1183 ((rtlphy->rfreg_chnlval[rfpath] &
1184 0xfffffc00) | currentcmd->para2);
1185
1186 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1187 currentcmd->para1,
1188 RFREG_OFFSET_MASK,
1189 rtlphy->rfreg_chnlval[rfpath]);
1190 }
1191 _rtl8723ae_phy_sw_rf_seting(hw, channel);
1192 break;
1193 default:
1194 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1195 "switch case not process\n");
1196 break;
1197 }
1198
1199 break;
1200 } while (true);
1201
1202 (*delay) = currentcmd->msdelay;
1203 (*step)++;
1204 return false;
1205 }
1206
1207 static bool _phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
1208 u32 cmdtableidx, u32 cmdtablesz,
1209 enum swchnlcmd_id cmdid, u32 para1,
1210 u32 para2, u32 msdelay)
1211 {
1212 struct swchnlcmd *pcmd;
1213
1214 if (cmdtable == NULL) {
1215 RT_ASSERT(false, "cmdtable cannot be NULL.\n");
1216 return false;
1217 }
1218
1219 if (cmdtableidx >= cmdtablesz)
1220 return false;
1221
1222 pcmd = cmdtable + cmdtableidx;
1223 pcmd->cmdid = cmdid;
1224 pcmd->para1 = para1;
1225 pcmd->para2 = para2;
1226 pcmd->msdelay = msdelay;
1227 return true;
1228 }
1229
1230 static u8 _rtl8723ae_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1231 {
1232 u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
1233 u8 result = 0x00;
1234
1235 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1236 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1237 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1238 rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
1239 config_pathb ? 0x28160202 : 0x28160502);
1240
1241 if (config_pathb) {
1242 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1243 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1244 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1245 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
1246 }
1247
1248 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
1249 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1250 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1251
1252 mdelay(IQK_DELAY_TIME);
1253
1254 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1255 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1256 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1257 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1258
1259 if (!(reg_eac & BIT(28)) &&
1260 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1261 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1262 result |= 0x01;
1263 else
1264 return result;
1265
1266 if (!(reg_eac & BIT(27)) &&
1267 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1268 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1269 result |= 0x02;
1270 return result;
1271 }
1272
1273 static u8 _rtl8723ae_phy_path_b_iqk(struct ieee80211_hw *hw)
1274 {
1275 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1276 u8 result = 0x00;
1277
1278 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1279 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1280 mdelay(IQK_DELAY_TIME);
1281 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1282 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1283 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1284 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1285 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1286
1287 if (!(reg_eac & BIT(31)) &&
1288 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1289 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1290 result |= 0x01;
1291 else
1292 return result;
1293 if (!(reg_eac & BIT(30)) &&
1294 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1295 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1296 result |= 0x02;
1297 return result;
1298 }
1299
1300 static void phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, bool iqk_ok,
1301 long result[][8], u8 final_candidate,
1302 bool btxonly)
1303 {
1304 u32 oldval_0, x, tx0_a, reg;
1305 long y, tx0_c;
1306
1307 if (final_candidate == 0xFF) {
1308 return;
1309 } else if (iqk_ok) {
1310 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1311 MASKDWORD) >> 22) & 0x3FF;
1312 x = result[final_candidate][0];
1313 if ((x & 0x00000200) != 0)
1314 x = x | 0xFFFFFC00;
1315 tx0_a = (x * oldval_0) >> 8;
1316 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1317 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1318 ((x * oldval_0 >> 7) & 0x1));
1319 y = result[final_candidate][1];
1320 if ((y & 0x00000200) != 0)
1321 y = y | 0xFFFFFC00;
1322 tx0_c = (y * oldval_0) >> 8;
1323 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1324 ((tx0_c & 0x3C0) >> 6));
1325 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1326 (tx0_c & 0x3F));
1327 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1328 ((y * oldval_0 >> 7) & 0x1));
1329 if (btxonly)
1330 return;
1331 reg = result[final_candidate][2];
1332 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1333 reg = result[final_candidate][3] & 0x3F;
1334 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1335 reg = (result[final_candidate][3] >> 6) & 0xF;
1336 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1337 }
1338 }
1339
1340 static void phy_save_adda_regs(struct ieee80211_hw *hw,
1341 u32 *addareg, u32 *addabackup,
1342 u32 registernum)
1343 {
1344 u32 i;
1345
1346 for (i = 0; i < registernum; i++)
1347 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1348 }
1349
1350 static void phy_save_mac_regs(struct ieee80211_hw *hw, u32 *macreg,
1351 u32 *macbackup)
1352 {
1353 struct rtl_priv *rtlpriv = rtl_priv(hw);
1354 u32 i;
1355
1356 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1357 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1358 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1359 }
1360
1361 static void phy_reload_adda_regs(struct ieee80211_hw *hw, u32 *addareg,
1362 u32 *addabackup, u32 regiesternum)
1363 {
1364 u32 i;
1365
1366 for (i = 0; i < regiesternum; i++)
1367 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1368 }
1369
1370 static void phy_reload_mac_regs(struct ieee80211_hw *hw, u32 *macreg,
1371 u32 *macbackup)
1372 {
1373 struct rtl_priv *rtlpriv = rtl_priv(hw);
1374 u32 i;
1375
1376 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1377 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1378 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1379 }
1380
1381 static void _rtl8723ae_phy_path_adda_on(struct ieee80211_hw *hw,
1382 u32 *addareg, bool is_patha_on,
1383 bool is2t)
1384 {
1385 u32 pathOn;
1386 u32 i;
1387
1388 pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1389 if (false == is2t) {
1390 pathOn = 0x0bdb25a0;
1391 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1392 } else {
1393 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1394 }
1395
1396 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1397 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1398 }
1399
1400 static void _rtl8723ae_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1401 u32 *macreg, u32 *macbackup)
1402 {
1403 struct rtl_priv *rtlpriv = rtl_priv(hw);
1404 u32 i = 0;
1405
1406 rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1407
1408 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1409 rtl_write_byte(rtlpriv, macreg[i],
1410 (u8) (macbackup[i] & (~BIT(3))));
1411 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1412 }
1413
1414 static void _rtl8723ae_phy_path_a_standby(struct ieee80211_hw *hw)
1415 {
1416 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1417 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1418 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1419 }
1420
1421 static void _rtl8723ae_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1422 {
1423 u32 mode;
1424
1425 mode = pi_mode ? 0x01000100 : 0x01000000;
1426 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1427 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1428 }
1429
1430 static bool phy_simularity_comp(struct ieee80211_hw *hw, long result[][8],
1431 u8 c1, u8 c2)
1432 {
1433 u32 i, j, diff, simularity_bitmap, bound;
1434
1435 u8 final_candidate[2] = { 0xFF, 0xFF };
1436 bool bresult = true;
1437
1438 bound = 4;
1439
1440 simularity_bitmap = 0;
1441
1442 for (i = 0; i < bound; i++) {
1443 diff = (result[c1][i] > result[c2][i]) ?
1444 (result[c1][i] - result[c2][i]) :
1445 (result[c2][i] - result[c1][i]);
1446
1447 if (diff > MAX_TOLERANCE) {
1448 if ((i == 2 || i == 6) && !simularity_bitmap) {
1449 if (result[c1][i] + result[c1][i + 1] == 0)
1450 final_candidate[(i / 4)] = c2;
1451 else if (result[c2][i] + result[c2][i + 1] == 0)
1452 final_candidate[(i / 4)] = c1;
1453 else
1454 simularity_bitmap = simularity_bitmap |
1455 (1 << i);
1456 } else
1457 simularity_bitmap =
1458 simularity_bitmap | (1 << i);
1459 }
1460 }
1461
1462 if (simularity_bitmap == 0) {
1463 for (i = 0; i < (bound / 4); i++) {
1464 if (final_candidate[i] != 0xFF) {
1465 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1466 result[3][j] =
1467 result[final_candidate[i]][j];
1468 bresult = false;
1469 }
1470 }
1471 return bresult;
1472 } else if (!(simularity_bitmap & 0x0F)) {
1473 for (i = 0; i < 4; i++)
1474 result[3][i] = result[c1][i];
1475 return false;
1476 } else {
1477 return false;
1478 }
1479
1480 }
1481
1482 static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1483 long result[][8], u8 t, bool is2t)
1484 {
1485 struct rtl_priv *rtlpriv = rtl_priv(hw);
1486 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1487 u32 i;
1488 u8 patha_ok, pathb_ok;
1489 u32 adda_reg[IQK_ADDA_REG_NUM] = {
1490 0x85c, 0xe6c, 0xe70, 0xe74,
1491 0xe78, 0xe7c, 0xe80, 0xe84,
1492 0xe88, 0xe8c, 0xed0, 0xed4,
1493 0xed8, 0xedc, 0xee0, 0xeec
1494 };
1495 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1496 0x522, 0x550, 0x551, 0x040
1497 };
1498 const u32 retrycount = 2;
1499
1500 if (t == 0) {
1501 phy_save_adda_regs(hw, adda_reg, rtlphy->adda_backup, 16);
1502 phy_save_mac_regs(hw, iqk_mac_reg, rtlphy->iqk_mac_backup);
1503 }
1504 _rtl8723ae_phy_path_adda_on(hw, adda_reg, true, is2t);
1505 if (t == 0) {
1506 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1507 RFPGA0_XA_HSSIPARAMETER1,
1508 BIT(8));
1509 }
1510
1511 if (!rtlphy->rfpi_enable)
1512 _rtl8723ae_phy_pi_mode_switch(hw, true);
1513 if (t == 0) {
1514 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1515 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1516 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1517 }
1518 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1519 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1520 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1521 if (is2t) {
1522 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1523 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1524 }
1525 _rtl8723ae_phy_mac_setting_calibration(hw, iqk_mac_reg,
1526 rtlphy->iqk_mac_backup);
1527 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1528 if (is2t)
1529 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1530 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1531 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1532 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1533 for (i = 0; i < retrycount; i++) {
1534 patha_ok = _rtl8723ae_phy_path_a_iqk(hw, is2t);
1535 if (patha_ok == 0x03) {
1536 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1537 0x3FF0000) >> 16;
1538 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1539 0x3FF0000) >> 16;
1540 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1541 0x3FF0000) >> 16;
1542 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1543 0x3FF0000) >> 16;
1544 break;
1545 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1546
1547 result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1548 MASKDWORD) & 0x3FF0000) >> 16;
1549 result[t][1] =
1550 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1551
1552 }
1553
1554 if (is2t) {
1555 _rtl8723ae_phy_path_a_standby(hw);
1556 _rtl8723ae_phy_path_adda_on(hw, adda_reg, false, is2t);
1557 for (i = 0; i < retrycount; i++) {
1558 pathb_ok = _rtl8723ae_phy_path_b_iqk(hw);
1559 if (pathb_ok == 0x03) {
1560 result[t][4] =
1561 (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
1562 0x3FF0000) >> 16;
1563 result[t][5] =
1564 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1565 0x3FF0000) >> 16;
1566 result[t][6] =
1567 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1568 0x3FF0000) >> 16;
1569 result[t][7] =
1570 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1571 0x3FF0000) >> 16;
1572 break;
1573 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1574 result[t][4] =
1575 (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
1576 0x3FF0000) >> 16;
1577 }
1578 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1579 0x3FF0000) >> 16;
1580 }
1581 }
1582 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1583 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1584 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1585 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1586 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1587 if (is2t)
1588 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1589 if (t != 0) {
1590 if (!rtlphy->rfpi_enable)
1591 _rtl8723ae_phy_pi_mode_switch(hw, false);
1592 phy_reload_adda_regs(hw, adda_reg, rtlphy->adda_backup, 16);
1593 phy_reload_mac_regs(hw, iqk_mac_reg, rtlphy->iqk_mac_backup);
1594 }
1595 }
1596
1597 static void _rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1598 {
1599 struct rtl_priv *rtlpriv = rtl_priv(hw);
1600 u8 tmpreg;
1601 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1602
1603 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1604
1605 if ((tmpreg & 0x70) != 0)
1606 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
1607 else
1608 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1609
1610 if ((tmpreg & 0x70) != 0) {
1611 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
1612
1613 if (is2t)
1614 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
1615 MASK12BITS);
1616
1617 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
1618 (rf_a_mode & 0x8FFFF) | 0x10000);
1619
1620 if (is2t)
1621 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1622 (rf_b_mode & 0x8FFFF) | 0x10000);
1623 }
1624 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
1625
1626 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
1627
1628 mdelay(100);
1629
1630 if ((tmpreg & 0x70) != 0) {
1631 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
1632 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
1633
1634 if (is2t)
1635 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1636 rf_b_mode);
1637 } else {
1638 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1639 }
1640 }
1641
1642 static void _rtl8723ae_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1643 bool bmain, bool is2t)
1644 {
1645 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1646
1647 if (is_hal_stop(rtlhal)) {
1648 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1649 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1650 }
1651 if (is2t) {
1652 if (bmain)
1653 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1654 BIT(5) | BIT(6), 0x1);
1655 else
1656 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1657 BIT(5) | BIT(6), 0x2);
1658 } else {
1659 if (bmain)
1660 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1661 else
1662 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1663
1664 }
1665 }
1666
1667 #undef IQK_ADDA_REG_NUM
1668 #undef IQK_DELAY_TIME
1669
1670 void rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1671 {
1672 struct rtl_priv *rtlpriv = rtl_priv(hw);
1673 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1674 long result[4][8];
1675 u8 i, final_candidate;
1676 bool patha_ok, pathb_ok;
1677 long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_tmp = 0;
1678 bool is12simular, is13simular, is23simular;
1679 bool start_conttx = false, singletone = false;
1680 u32 iqk_bb_reg[10] = {
1681 ROFDM0_XARXIQIMBALANCE,
1682 ROFDM0_XBRXIQIMBALANCE,
1683 ROFDM0_ECCATHRESHOLD,
1684 ROFDM0_AGCRSSITABLE,
1685 ROFDM0_XATXIQIMBALANCE,
1686 ROFDM0_XBTXIQIMBALANCE,
1687 ROFDM0_XCTXIQIMBALANCE,
1688 ROFDM0_XCTXAFE,
1689 ROFDM0_XDTXAFE,
1690 ROFDM0_RXIQEXTANTA
1691 };
1692
1693 if (recovery) {
1694 phy_reload_adda_regs(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 10);
1695 return;
1696 }
1697 if (start_conttx || singletone)
1698 return;
1699 for (i = 0; i < 8; i++) {
1700 result[0][i] = 0;
1701 result[1][i] = 0;
1702 result[2][i] = 0;
1703 result[3][i] = 0;
1704 }
1705 final_candidate = 0xff;
1706 patha_ok = false;
1707 pathb_ok = false;
1708 is12simular = false;
1709 is23simular = false;
1710 is13simular = false;
1711 for (i = 0; i < 3; i++) {
1712 _rtl8723ae_phy_iq_calibrate(hw, result, i, false);
1713 if (i == 1) {
1714 is12simular = phy_simularity_comp(hw, result, 0, 1);
1715 if (is12simular) {
1716 final_candidate = 0;
1717 break;
1718 }
1719 }
1720 if (i == 2) {
1721 is13simular = phy_simularity_comp(hw, result, 0, 2);
1722 if (is13simular) {
1723 final_candidate = 0;
1724 break;
1725 }
1726 is23simular = phy_simularity_comp(hw, result, 1, 2);
1727 if (is23simular) {
1728 final_candidate = 1;
1729 } else {
1730 for (i = 0; i < 8; i++)
1731 reg_tmp += result[3][i];
1732
1733 if (reg_tmp != 0)
1734 final_candidate = 3;
1735 else
1736 final_candidate = 0xFF;
1737 }
1738 }
1739 }
1740 for (i = 0; i < 4; i++) {
1741 reg_e94 = result[i][0];
1742 reg_e9c = result[i][1];
1743 reg_ea4 = result[i][2];
1744 reg_eb4 = result[i][4];
1745 reg_ebc = result[i][5];
1746 }
1747 if (final_candidate != 0xff) {
1748 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1749 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1750 reg_ea4 = result[final_candidate][2];
1751 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1752 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1753 patha_ok = pathb_ok = true;
1754 } else {
1755 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1756 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1757 }
1758 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1759 phy_path_a_fill_iqk_matrix(hw, patha_ok, result,
1760 final_candidate, (reg_ea4 == 0));
1761 phy_save_adda_regs(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 10);
1762 }
1763
1764 void rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw)
1765 {
1766 bool start_conttx = false, singletone = false;
1767
1768 if (start_conttx || singletone)
1769 return;
1770 _rtl8723ae_phy_lc_calibrate(hw, false);
1771 }
1772
1773 void rtl8723ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1774 {
1775 _rtl8723ae_phy_set_rfpath_switch(hw, bmain, false);
1776 }
1777
1778 bool rtl8723ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1779 {
1780 struct rtl_priv *rtlpriv = rtl_priv(hw);
1781 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1782 bool postprocessing = false;
1783
1784 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1785 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1786 iotype, rtlphy->set_io_inprogress);
1787 do {
1788 switch (iotype) {
1789 case IO_CMD_RESUME_DM_BY_SCAN:
1790 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1791 "[IO CMD] Resume DM after scan.\n");
1792 postprocessing = true;
1793 break;
1794 case IO_CMD_PAUSE_DM_BY_SCAN:
1795 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1796 "[IO CMD] Pause DM before scan.\n");
1797 postprocessing = true;
1798 break;
1799 default:
1800 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1801 "switch case not process\n");
1802 break;
1803 }
1804 } while (false);
1805 if (postprocessing && !rtlphy->set_io_inprogress) {
1806 rtlphy->set_io_inprogress = true;
1807 rtlphy->current_io_type = iotype;
1808 } else {
1809 return false;
1810 }
1811 rtl8723ae_phy_set_io(hw);
1812 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
1813 return true;
1814 }
1815
1816 static void rtl8723ae_phy_set_io(struct ieee80211_hw *hw)
1817 {
1818 struct rtl_priv *rtlpriv = rtl_priv(hw);
1819 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1820 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1821
1822 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1823 "--->Cmd(%#x), set_io_inprogress(%d)\n",
1824 rtlphy->current_io_type, rtlphy->set_io_inprogress);
1825 switch (rtlphy->current_io_type) {
1826 case IO_CMD_RESUME_DM_BY_SCAN:
1827 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1828 rtl8723ae_dm_write_dig(hw);
1829 rtl8723ae_phy_set_txpower_level(hw, rtlphy->current_channel);
1830 break;
1831 case IO_CMD_PAUSE_DM_BY_SCAN:
1832 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1833 dm_digtable->cur_igvalue = 0x17;
1834 rtl8723ae_dm_write_dig(hw);
1835 break;
1836 default:
1837 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1838 "switch case not process\n");
1839 break;
1840 }
1841 rtlphy->set_io_inprogress = false;
1842 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1843 "<---(%#x)\n", rtlphy->current_io_type);
1844 }
1845
1846 static void rtl8723ae_phy_set_rf_on(struct ieee80211_hw *hw)
1847 {
1848 struct rtl_priv *rtlpriv = rtl_priv(hw);
1849
1850 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1851 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1852 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1853 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1854 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1855 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1856 }
1857
1858 static void _rtl8723ae_phy_set_rf_sleep(struct ieee80211_hw *hw)
1859 {
1860 struct rtl_priv *rtlpriv = rtl_priv(hw);
1861 u32 u4b_tmp;
1862 u8 delay = 5;
1863
1864 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1865 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1866 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1867 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1868 while (u4b_tmp != 0 && delay > 0) {
1869 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
1870 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1871 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1872 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1873 delay--;
1874 }
1875 if (delay == 0) {
1876 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1877 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1878 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1879 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1880 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1881 "Switch RF timeout !!!.\n");
1882 return;
1883 }
1884 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1885 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1886 }
1887
1888 static bool _rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
1889 enum rf_pwrstate rfpwr_state)
1890 {
1891 struct rtl_priv *rtlpriv = rtl_priv(hw);
1892 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1893 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1894 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1895 struct rtl8192_tx_ring *ring = NULL;
1896 bool bresult = true;
1897 u8 i, queue_id;
1898
1899 switch (rfpwr_state) {
1900 case ERFON:
1901 if ((ppsc->rfpwr_state == ERFOFF) &&
1902 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
1903 bool rtstatus;
1904 u32 InitializeCount = 0;
1905 do {
1906 InitializeCount++;
1907 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1908 "IPS Set eRf nic enable\n");
1909 rtstatus = rtl_ps_enable_nic(hw);
1910 } while ((rtstatus != true) && (InitializeCount < 10));
1911 RT_CLEAR_PS_LEVEL(ppsc,
1912 RT_RF_OFF_LEVL_HALT_NIC);
1913 } else {
1914 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1915 "Set ERFON sleeped:%d ms\n",
1916 jiffies_to_msecs(jiffies -
1917 ppsc->last_sleep_jiffies));
1918 ppsc->last_awake_jiffies = jiffies;
1919 rtl8723ae_phy_set_rf_on(hw);
1920 }
1921 if (mac->link_state == MAC80211_LINKED) {
1922 rtlpriv->cfg->ops->led_control(hw,
1923 LED_CTL_LINK);
1924 } else {
1925 rtlpriv->cfg->ops->led_control(hw,
1926 LED_CTL_NO_LINK);
1927 }
1928 break;
1929 case ERFOFF:
1930 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
1931 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1932 "IPS Set eRf nic disable\n");
1933 rtl_ps_disable_nic(hw);
1934 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1935 } else {
1936 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
1937 rtlpriv->cfg->ops->led_control(hw,
1938 LED_CTL_NO_LINK);
1939 } else {
1940 rtlpriv->cfg->ops->led_control(hw,
1941 LED_CTL_POWER_OFF);
1942 }
1943 }
1944 break;
1945 case ERFSLEEP:
1946 if (ppsc->rfpwr_state == ERFOFF)
1947 break;
1948 for (queue_id = 0, i = 0;
1949 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
1950 ring = &pcipriv->dev.tx_ring[queue_id];
1951 if (skb_queue_len(&ring->queue) == 0) {
1952 queue_id++;
1953 continue;
1954 } else {
1955 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1956 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
1957 (i + 1), queue_id,
1958 skb_queue_len(&ring->queue));
1959
1960 udelay(10);
1961 i++;
1962 }
1963 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1964 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1965 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
1966 MAX_DOZE_WAITING_TIMES_9x,
1967 queue_id,
1968 skb_queue_len(&ring->queue));
1969 break;
1970 }
1971 }
1972 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1973 "Set ERFSLEEP awaked:%d ms\n",
1974 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
1975 ppsc->last_sleep_jiffies = jiffies;
1976 _rtl8723ae_phy_set_rf_sleep(hw);
1977 break;
1978 default:
1979 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1980 "switch case not processed\n");
1981 bresult = false;
1982 break;
1983 }
1984 if (bresult)
1985 ppsc->rfpwr_state = rfpwr_state;
1986 return bresult;
1987 }
1988
1989 bool rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
1990 enum rf_pwrstate rfpwr_state)
1991 {
1992 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1993 bool bresult = false;
1994
1995 if (rfpwr_state == ppsc->rfpwr_state)
1996 return bresult;
1997 bresult = _rtl8723ae_phy_set_rf_power_state(hw, rfpwr_state);
1998 return bresult;
1999 }
Linux with added FPC-III support