2 * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/rtc.h>
21 /* These register offsets are relative to LP (Low Power) range */
22 #define SNVS_LPCR 0x04
23 #define SNVS_LPSR 0x18
24 #define SNVS_LPSRTCMR 0x1c
25 #define SNVS_LPSRTCLR 0x20
26 #define SNVS_LPTAR 0x24
27 #define SNVS_LPPGDR 0x30
29 #define SNVS_LPCR_SRTC_ENV (1 << 0)
30 #define SNVS_LPCR_LPTA_EN (1 << 1)
31 #define SNVS_LPCR_LPWUI_EN (1 << 3)
32 #define SNVS_LPSR_LPTA (1 << 0)
34 #define SNVS_LPPGDR_INIT 0x41736166
35 #define CNTR_TO_SECS_SH 15
37 struct snvs_rtc_data
{
38 struct rtc_device
*rtc
;
44 static u32
rtc_read_lp_counter(void __iomem
*ioaddr
)
49 read1
= readl(ioaddr
+ SNVS_LPSRTCMR
);
51 read1
|= readl(ioaddr
+ SNVS_LPSRTCLR
);
53 read2
= readl(ioaddr
+ SNVS_LPSRTCMR
);
55 read2
|= readl(ioaddr
+ SNVS_LPSRTCLR
);
56 } while (read1
!= read2
);
58 /* Convert 47-bit counter to 32-bit raw second count */
59 return (u32
) (read1
>> CNTR_TO_SECS_SH
);
62 static void rtc_write_sync_lp(void __iomem
*ioaddr
)
64 u32 count1
, count2
, count3
;
67 /* Wait for 3 CKIL cycles */
68 for (i
= 0; i
< 3; i
++) {
70 count1
= readl(ioaddr
+ SNVS_LPSRTCLR
);
71 count2
= readl(ioaddr
+ SNVS_LPSRTCLR
);
72 } while (count1
!= count2
);
74 /* Now wait until counter value changes */
77 count2
= readl(ioaddr
+ SNVS_LPSRTCLR
);
78 count3
= readl(ioaddr
+ SNVS_LPSRTCLR
);
79 } while (count2
!= count3
);
80 } while (count3
== count1
);
84 static int snvs_rtc_enable(struct snvs_rtc_data
*data
, bool enable
)
90 spin_lock_irqsave(&data
->lock
, flags
);
92 lpcr
= readl(data
->ioaddr
+ SNVS_LPCR
);
94 lpcr
|= SNVS_LPCR_SRTC_ENV
;
96 lpcr
&= ~SNVS_LPCR_SRTC_ENV
;
97 writel(lpcr
, data
->ioaddr
+ SNVS_LPCR
);
99 spin_unlock_irqrestore(&data
->lock
, flags
);
102 lpcr
= readl(data
->ioaddr
+ SNVS_LPCR
);
105 if (lpcr
& SNVS_LPCR_SRTC_ENV
)
108 if (!(lpcr
& SNVS_LPCR_SRTC_ENV
))
119 static int snvs_rtc_read_time(struct device
*dev
, struct rtc_time
*tm
)
121 struct snvs_rtc_data
*data
= dev_get_drvdata(dev
);
122 unsigned long time
= rtc_read_lp_counter(data
->ioaddr
);
124 rtc_time_to_tm(time
, tm
);
129 static int snvs_rtc_set_time(struct device
*dev
, struct rtc_time
*tm
)
131 struct snvs_rtc_data
*data
= dev_get_drvdata(dev
);
134 rtc_tm_to_time(tm
, &time
);
136 /* Disable RTC first */
137 snvs_rtc_enable(data
, false);
139 /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
140 writel(time
<< CNTR_TO_SECS_SH
, data
->ioaddr
+ SNVS_LPSRTCLR
);
141 writel(time
>> (32 - CNTR_TO_SECS_SH
), data
->ioaddr
+ SNVS_LPSRTCMR
);
143 /* Enable RTC again */
144 snvs_rtc_enable(data
, true);
149 static int snvs_rtc_read_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
151 struct snvs_rtc_data
*data
= dev_get_drvdata(dev
);
154 lptar
= readl(data
->ioaddr
+ SNVS_LPTAR
);
155 rtc_time_to_tm(lptar
, &alrm
->time
);
157 lpsr
= readl(data
->ioaddr
+ SNVS_LPSR
);
158 alrm
->pending
= (lpsr
& SNVS_LPSR_LPTA
) ? 1 : 0;
163 static int snvs_rtc_alarm_irq_enable(struct device
*dev
, unsigned int enable
)
165 struct snvs_rtc_data
*data
= dev_get_drvdata(dev
);
169 spin_lock_irqsave(&data
->lock
, flags
);
171 lpcr
= readl(data
->ioaddr
+ SNVS_LPCR
);
173 lpcr
|= (SNVS_LPCR_LPTA_EN
| SNVS_LPCR_LPWUI_EN
);
175 lpcr
&= ~(SNVS_LPCR_LPTA_EN
| SNVS_LPCR_LPWUI_EN
);
176 writel(lpcr
, data
->ioaddr
+ SNVS_LPCR
);
178 spin_unlock_irqrestore(&data
->lock
, flags
);
180 rtc_write_sync_lp(data
->ioaddr
);
185 static int snvs_rtc_set_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
187 struct snvs_rtc_data
*data
= dev_get_drvdata(dev
);
188 struct rtc_time
*alrm_tm
= &alrm
->time
;
193 rtc_tm_to_time(alrm_tm
, &time
);
195 spin_lock_irqsave(&data
->lock
, flags
);
197 /* Have to clear LPTA_EN before programming new alarm time in LPTAR */
198 lpcr
= readl(data
->ioaddr
+ SNVS_LPCR
);
199 lpcr
&= ~SNVS_LPCR_LPTA_EN
;
200 writel(lpcr
, data
->ioaddr
+ SNVS_LPCR
);
202 spin_unlock_irqrestore(&data
->lock
, flags
);
204 writel(time
, data
->ioaddr
+ SNVS_LPTAR
);
206 /* Clear alarm interrupt status bit */
207 writel(SNVS_LPSR_LPTA
, data
->ioaddr
+ SNVS_LPSR
);
209 return snvs_rtc_alarm_irq_enable(dev
, alrm
->enabled
);
212 static const struct rtc_class_ops snvs_rtc_ops
= {
213 .read_time
= snvs_rtc_read_time
,
214 .set_time
= snvs_rtc_set_time
,
215 .read_alarm
= snvs_rtc_read_alarm
,
216 .set_alarm
= snvs_rtc_set_alarm
,
217 .alarm_irq_enable
= snvs_rtc_alarm_irq_enable
,
220 static irqreturn_t
snvs_rtc_irq_handler(int irq
, void *dev_id
)
222 struct device
*dev
= dev_id
;
223 struct snvs_rtc_data
*data
= dev_get_drvdata(dev
);
227 lpsr
= readl(data
->ioaddr
+ SNVS_LPSR
);
229 if (lpsr
& SNVS_LPSR_LPTA
) {
230 events
|= (RTC_AF
| RTC_IRQF
);
232 /* RTC alarm should be one-shot */
233 snvs_rtc_alarm_irq_enable(dev
, 0);
235 rtc_update_irq(data
->rtc
, 1, events
);
238 /* clear interrupt status */
239 writel(lpsr
, data
->ioaddr
+ SNVS_LPSR
);
241 return events
? IRQ_HANDLED
: IRQ_NONE
;
244 static int snvs_rtc_probe(struct platform_device
*pdev
)
246 struct snvs_rtc_data
*data
;
247 struct resource
*res
;
250 data
= devm_kzalloc(&pdev
->dev
, sizeof(*data
), GFP_KERNEL
);
254 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
255 data
->ioaddr
= devm_ioremap_resource(&pdev
->dev
, res
);
256 if (IS_ERR(data
->ioaddr
))
257 return PTR_ERR(data
->ioaddr
);
259 data
->irq
= platform_get_irq(pdev
, 0);
263 platform_set_drvdata(pdev
, data
);
265 spin_lock_init(&data
->lock
);
267 /* Initialize glitch detect */
268 writel(SNVS_LPPGDR_INIT
, data
->ioaddr
+ SNVS_LPPGDR
);
270 /* Clear interrupt status */
271 writel(0xffffffff, data
->ioaddr
+ SNVS_LPSR
);
274 snvs_rtc_enable(data
, true);
276 device_init_wakeup(&pdev
->dev
, true);
278 ret
= devm_request_irq(&pdev
->dev
, data
->irq
, snvs_rtc_irq_handler
,
279 IRQF_SHARED
, "rtc alarm", &pdev
->dev
);
281 dev_err(&pdev
->dev
, "failed to request irq %d: %d\n",
286 data
->rtc
= devm_rtc_device_register(&pdev
->dev
, pdev
->name
,
287 &snvs_rtc_ops
, THIS_MODULE
);
288 if (IS_ERR(data
->rtc
)) {
289 ret
= PTR_ERR(data
->rtc
);
290 dev_err(&pdev
->dev
, "failed to register rtc: %d\n", ret
);
297 #ifdef CONFIG_PM_SLEEP
298 static int snvs_rtc_suspend(struct device
*dev
)
300 struct snvs_rtc_data
*data
= dev_get_drvdata(dev
);
302 if (device_may_wakeup(dev
))
303 enable_irq_wake(data
->irq
);
308 static int snvs_rtc_resume(struct device
*dev
)
310 struct snvs_rtc_data
*data
= dev_get_drvdata(dev
);
312 if (device_may_wakeup(dev
))
313 disable_irq_wake(data
->irq
);
319 static SIMPLE_DEV_PM_OPS(snvs_rtc_pm_ops
, snvs_rtc_suspend
, snvs_rtc_resume
);
321 static const struct of_device_id snvs_dt_ids
[] = {
322 { .compatible
= "fsl,sec-v4.0-mon-rtc-lp", },
325 MODULE_DEVICE_TABLE(of
, snvs_dt_ids
);
327 static struct platform_driver snvs_rtc_driver
= {
330 .owner
= THIS_MODULE
,
331 .pm
= &snvs_rtc_pm_ops
,
332 .of_match_table
= snvs_dt_ids
,
334 .probe
= snvs_rtc_probe
,
336 module_platform_driver(snvs_rtc_driver
);
338 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
339 MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
340 MODULE_LICENSE("GPL");