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fix a kmap leak in virtio_console
[linux/fpc-iii.git] / drivers / scsi / qla4xxx / ql4_def.h
blobaa67bb9a442618cb40c89d3e38ec5742c5d82b35
1 /*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8 #ifndef __QL4_DEF_H
9 #define __QL4_DEF_H
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/module.h>
15 #include <linux/list.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/sched.h>
19 #include <linux/slab.h>
20 #include <linux/dmapool.h>
21 #include <linux/mempool.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/mutex.h>
27 #include <linux/aer.h>
28 #include <linux/bsg-lib.h>
29
30 #include <net/tcp.h>
31 #include <scsi/scsi.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/scsi_device.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <scsi/scsi_transport.h>
36 #include <scsi/scsi_transport_iscsi.h>
37 #include <scsi/scsi_bsg_iscsi.h>
38 #include <scsi/scsi_netlink.h>
39 #include <scsi/libiscsi.h>
40
41 #include "ql4_dbg.h"
42 #include "ql4_nx.h"
43 #include "ql4_fw.h"
44 #include "ql4_nvram.h"
45 #include "ql4_83xx.h"
46
47 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
48 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
49 #endif
50
51 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
52 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
53 #endif
54
55 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
56 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
57 #endif
58
59 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
60 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
61 #endif
62
63 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8324
64 #define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032
65 #endif
66
67 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8042
68 #define PCI_DEVICE_ID_QLOGIC_ISP8042 0x8042
69 #endif
70
71 #define ISP4XXX_PCI_FN_1 0x1
72 #define ISP4XXX_PCI_FN_2 0x3
73
74 #define QLA_SUCCESS 0
75 #define QLA_ERROR 1
76 #define STATUS(status) status == QLA_ERROR ? "FAILED" : "SUCCEEDED"
77
78 /*
79 * Data bit definitions
80 */
81 #define BIT_0 0x1
82 #define BIT_1 0x2
83 #define BIT_2 0x4
84 #define BIT_3 0x8
85 #define BIT_4 0x10
86 #define BIT_5 0x20
87 #define BIT_6 0x40
88 #define BIT_7 0x80
89 #define BIT_8 0x100
90 #define BIT_9 0x200
91 #define BIT_10 0x400
92 #define BIT_11 0x800
93 #define BIT_12 0x1000
94 #define BIT_13 0x2000
95 #define BIT_14 0x4000
96 #define BIT_15 0x8000
97 #define BIT_16 0x10000
98 #define BIT_17 0x20000
99 #define BIT_18 0x40000
100 #define BIT_19 0x80000
101 #define BIT_20 0x100000
102 #define BIT_21 0x200000
103 #define BIT_22 0x400000
104 #define BIT_23 0x800000
105 #define BIT_24 0x1000000
106 #define BIT_25 0x2000000
107 #define BIT_26 0x4000000
108 #define BIT_27 0x8000000
109 #define BIT_28 0x10000000
110 #define BIT_29 0x20000000
111 #define BIT_30 0x40000000
112 #define BIT_31 0x80000000
113
114 /**
115 * Macros to help code, maintain, etc.
116 **/
117 #define ql4_printk(level, ha, format, arg...) \
118 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
119
120
121 /*
122 * Host adapter default definitions
123 ***********************************/
124 #define MAX_HBAS 16
125 #define MAX_BUSES 1
126 #define MAX_TARGETS MAX_DEV_DB_ENTRIES
127 #define MAX_LUNS 0xffff
128 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
129 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
130 #define MAX_PDU_ENTRIES 32
131 #define INVALID_ENTRY 0xFFFF
132 #define MAX_CMDS_TO_RISC 1024
133 #define MAX_SRBS MAX_CMDS_TO_RISC
134 #define MBOX_AEN_REG_COUNT 8
135 #define MAX_INIT_RETRIES 5
136
137 /*
138 * Buffer sizes
139 */
140 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
141 #define RESPONSE_QUEUE_DEPTH 64
142 #define QUEUE_SIZE 64
143 #define DMA_BUFFER_SIZE 512
144 #define IOCB_HIWAT_CUSHION 4
145
146 /*
147 * Misc
148 */
149 #define MAC_ADDR_LEN 6 /* in bytes */
150 #define IP_ADDR_LEN 4 /* in bytes */
151 #define IPv6_ADDR_LEN 16 /* IPv6 address size */
152 #define DRIVER_NAME "qla4xxx"
153
154 #define MAX_LINKED_CMDS_PER_LUN 3
155 #define MAX_REQS_SERVICED_PER_INTR 1
156
157 #define ISCSI_IPADDR_SIZE 4 /* IP address size */
158 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
159 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
160
161 #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */
162 /* recovery timeout */
163
164 #define LSDW(x) ((u32)((u64)(x)))
165 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
166
167 #define DEV_DB_NON_PERSISTENT 0
168 #define DEV_DB_PERSISTENT 1
169
170 #define COPY_ISID(dst_isid, src_isid) { \
171 int i, j; \
172 for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;) \
173 dst_isid[i++] = src_isid[j--]; \
174 }
175
176 #define SET_BITVAL(o, n, v) { \
177 if (o) \
178 n |= v; \
179 else \
180 n &= ~v; \
181 }
182
183 #define OP_STATE(o, f, p) { \
184 p = (o & f) ? "enable" : "disable"; \
185 }
186
187 /*
188 * Retry & Timeout Values
189 */
190 #define MBOX_TOV 60
191 #define SOFT_RESET_TOV 30
192 #define RESET_INTR_TOV 3
193 #define SEMAPHORE_TOV 10
194 #define ADAPTER_INIT_TOV 30
195 #define ADAPTER_RESET_TOV 180
196 #define EXTEND_CMD_TOV 60
197 #define WAIT_CMD_TOV 30
198 #define EH_WAIT_CMD_TOV 120
199 #define FIRMWARE_UP_TOV 60
200 #define RESET_FIRMWARE_TOV 30
201 #define LOGOUT_TOV 10
202 #define IOCB_TOV_MARGIN 10
203 #define RELOGIN_TOV 18
204 #define ISNS_DEREG_TOV 5
205 #define HBA_ONLINE_TOV 30
206 #define DISABLE_ACB_TOV 30
207 #define IP_CONFIG_TOV 30
208 #define LOGIN_TOV 12
209 #define BOOT_LOGIN_RESP_TOV 60
210
211 #define MAX_RESET_HA_RETRIES 2
212 #define FW_ALIVE_WAIT_TOV 3
213 #define IDC_EXTEND_TOV 8
214 #define IDC_COMP_TOV 5
215 #define LINK_UP_COMP_TOV 30
216
217 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
218
219 /*
220 * SCSI Request Block structure (srb) that is placed
221 * on cmd->SCp location of every I/O [We have 22 bytes available]
222 */
223 struct srb {
224 struct list_head list; /* (8) */
225 struct scsi_qla_host *ha; /* HA the SP is queued on */
226 struct ddb_entry *ddb;
227 uint16_t flags; /* (1) Status flags. */
228
229 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
230 #define SRB_GOT_SENSE BIT_4 /* sense data received. */
231 uint8_t state; /* (1) Status flags. */
232
233 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
234 #define SRB_FREE_STATE 1
235 #define SRB_ACTIVE_STATE 3
236 #define SRB_ACTIVE_TIMEOUT_STATE 4
237 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
238
239 struct scsi_cmnd *cmd; /* (4) SCSI command block */
240 dma_addr_t dma_handle; /* (4) for unmap of single transfers */
241 struct kref srb_ref; /* reference count for this srb */
242 uint8_t err_id; /* error id */
243 #define SRB_ERR_PORT 1 /* Request failed because "port down" */
244 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
245 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
246 #define SRB_ERR_OTHER 4
247
248 uint16_t reserved;
249 uint16_t iocb_tov;
250 uint16_t iocb_cnt; /* Number of used iocbs */
251 uint16_t cc_stat;
252
253 /* Used for extended sense / status continuation */
254 uint8_t *req_sense_ptr;
255 uint16_t req_sense_len;
256 uint16_t reserved2;
257 };
258
259 /* Mailbox request block structure */
260 struct mrb {
261 struct scsi_qla_host *ha;
262 struct mbox_cmd_iocb *mbox;
263 uint32_t mbox_cmd;
264 uint16_t iocb_cnt; /* Number of used iocbs */
265 uint32_t pid;
266 };
267
268 /*
269 * Asynchronous Event Queue structure
270 */
271 struct aen {
272 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
273 };
274
275 struct ql4_aen_log {
276 int count;
277 struct aen entry[MAX_AEN_ENTRIES];
278 };
279
280 /*
281 * Device Database (DDB) structure
282 */
283 struct ddb_entry {
284 struct scsi_qla_host *ha;
285 struct iscsi_cls_session *sess;
286 struct iscsi_cls_conn *conn;
287
288 uint16_t fw_ddb_index; /* DDB firmware index */
289 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
290 uint16_t ddb_type;
291 #define FLASH_DDB 0x01
292
293 struct dev_db_entry fw_ddb_entry;
294 int (*unblock_sess)(struct iscsi_cls_session *cls_session);
295 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
296 struct ddb_entry *ddb_entry, uint32_t state);
297
298 /* Driver Re-login */
299 unsigned long flags; /* DDB Flags */
300 uint16_t default_relogin_timeout; /* Max time to wait for
301 * relogin to complete */
302 atomic_t retry_relogin_timer; /* Min Time between relogins
303 * (4000 only) */
304 atomic_t relogin_timer; /* Max Time to wait for
305 * relogin to complete */
306 atomic_t relogin_retry_count; /* Num of times relogin has been
307 * retried */
308 uint32_t default_time2wait; /* Default Min time between
309 * relogins (+aens) */
310 uint16_t chap_tbl_idx;
311 };
312
313 struct qla_ddb_index {
314 struct list_head list;
315 uint16_t fw_ddb_idx;
316 uint16_t flash_ddb_idx;
317 struct dev_db_entry fw_ddb;
318 uint8_t flash_isid[6];
319 };
320
321 #define DDB_IPADDR_LEN 64
322
323 struct ql4_tuple_ddb {
324 int port;
325 int tpgt;
326 char ip_addr[DDB_IPADDR_LEN];
327 char iscsi_name[ISCSI_NAME_SIZE];
328 uint16_t options;
329 #define DDB_OPT_IPV6 0x0e0e
330 #define DDB_OPT_IPV4 0x0f0f
331 uint8_t isid[6];
332 };
333
334 /*
335 * DDB states.
336 */
337 #define DDB_STATE_DEAD 0 /* We can no longer talk to
338 * this device */
339 #define DDB_STATE_ONLINE 1 /* Device ready to accept
340 * commands */
341 #define DDB_STATE_MISSING 2 /* Device logged off, trying
342 * to re-login */
343
344 /*
345 * DDB flags.
346 */
347 #define DF_RELOGIN 0 /* Relogin to device */
348 #define DF_BOOT_TGT 1 /* Boot target entry */
349 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
350 #define DF_FO_MASKED 3
351 #define DF_DISABLE_RELOGIN 4 /* Disable relogin to device */
352
353 enum qla4_work_type {
354 QLA4_EVENT_AEN,
355 QLA4_EVENT_PING_STATUS,
356 };
357
358 struct qla4_work_evt {
359 struct list_head list;
360 enum qla4_work_type type;
361 union {
362 struct {
363 enum iscsi_host_event_code code;
364 uint32_t data_size;
365 uint8_t data[0];
366 } aen;
367 struct {
368 uint32_t status;
369 uint32_t pid;
370 uint32_t data_size;
371 uint8_t data[0];
372 } ping;
373 } u;
374 };
375
376 struct ql82xx_hw_data {
377 /* Offsets for flash/nvram access (set to ~0 if not used). */
378 uint32_t flash_conf_off;
379 uint32_t flash_data_off;
380
381 uint32_t fdt_wrt_disable;
382 uint32_t fdt_erase_cmd;
383 uint32_t fdt_block_size;
384 uint32_t fdt_unprotect_sec_cmd;
385 uint32_t fdt_protect_sec_cmd;
386
387 uint32_t flt_region_flt;
388 uint32_t flt_region_fdt;
389 uint32_t flt_region_boot;
390 uint32_t flt_region_bootload;
391 uint32_t flt_region_fw;
392
393 uint32_t flt_iscsi_param;
394 uint32_t flt_region_chap;
395 uint32_t flt_chap_size;
396 uint32_t flt_region_ddb;
397 uint32_t flt_ddb_size;
398 };
399
400 struct qla4_8xxx_legacy_intr_set {
401 uint32_t int_vec_bit;
402 uint32_t tgt_status_reg;
403 uint32_t tgt_mask_reg;
404 uint32_t pci_int_reg;
405 };
406
407 /* MSI-X Support */
408
409 #define QLA_MSIX_DEFAULT 0x00
410 #define QLA_MSIX_RSP_Q 0x01
411
412 #define QLA_MSIX_ENTRIES 2
413 #define QLA_MIDX_DEFAULT 0
414 #define QLA_MIDX_RSP_Q 1
415
416 struct ql4_msix_entry {
417 int have_irq;
418 uint16_t msix_vector;
419 uint16_t msix_entry;
420 };
421
422 /*
423 * ISP Operations
424 */
425 struct isp_operations {
426 int (*iospace_config) (struct scsi_qla_host *ha);
427 void (*pci_config) (struct scsi_qla_host *);
428 void (*disable_intrs) (struct scsi_qla_host *);
429 void (*enable_intrs) (struct scsi_qla_host *);
430 int (*start_firmware) (struct scsi_qla_host *);
431 int (*restart_firmware) (struct scsi_qla_host *);
432 irqreturn_t (*intr_handler) (int , void *);
433 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
434 int (*need_reset) (struct scsi_qla_host *);
435 int (*reset_chip) (struct scsi_qla_host *);
436 int (*reset_firmware) (struct scsi_qla_host *);
437 void (*queue_iocb) (struct scsi_qla_host *);
438 void (*complete_iocb) (struct scsi_qla_host *);
439 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
440 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
441 int (*get_sys_info) (struct scsi_qla_host *);
442 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
443 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
444 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
445 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
446 int (*idc_lock) (struct scsi_qla_host *);
447 void (*idc_unlock) (struct scsi_qla_host *);
448 void (*rom_lock_recovery) (struct scsi_qla_host *);
449 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
450 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int);
451 };
452
453 struct ql4_mdump_size_table {
454 uint32_t size;
455 uint32_t size_cmask_02;
456 uint32_t size_cmask_04;
457 uint32_t size_cmask_08;
458 uint32_t size_cmask_10;
459 uint32_t size_cmask_FF;
460 uint32_t version;
461 };
462
463 /*qla4xxx ipaddress configuration details */
464 struct ipaddress_config {
465 uint16_t ipv4_options;
466 uint16_t tcp_options;
467 uint16_t ipv4_vlan_tag;
468 uint8_t ipv4_addr_state;
469 uint8_t ip_address[IP_ADDR_LEN];
470 uint8_t subnet_mask[IP_ADDR_LEN];
471 uint8_t gateway[IP_ADDR_LEN];
472 uint32_t ipv6_options;
473 uint32_t ipv6_addl_options;
474 uint8_t ipv6_link_local_state;
475 uint8_t ipv6_addr0_state;
476 uint8_t ipv6_addr1_state;
477 uint8_t ipv6_default_router_state;
478 uint16_t ipv6_vlan_tag;
479 struct in6_addr ipv6_link_local_addr;
480 struct in6_addr ipv6_addr0;
481 struct in6_addr ipv6_addr1;
482 struct in6_addr ipv6_default_router_addr;
483 uint16_t eth_mtu_size;
484 uint16_t ipv4_port;
485 uint16_t ipv6_port;
486 uint8_t control;
487 uint16_t ipv6_tcp_options;
488 uint8_t tcp_wsf;
489 uint8_t ipv6_tcp_wsf;
490 uint8_t ipv4_tos;
491 uint8_t ipv4_cache_id;
492 uint8_t ipv6_cache_id;
493 uint8_t ipv4_alt_cid_len;
494 uint8_t ipv4_alt_cid[11];
495 uint8_t ipv4_vid_len;
496 uint8_t ipv4_vid[11];
497 uint8_t ipv4_ttl;
498 uint16_t ipv6_flow_lbl;
499 uint8_t ipv6_traffic_class;
500 uint8_t ipv6_hop_limit;
501 uint32_t ipv6_nd_reach_time;
502 uint32_t ipv6_nd_rexmit_timer;
503 uint32_t ipv6_nd_stale_timeout;
504 uint8_t ipv6_dup_addr_detect_count;
505 uint32_t ipv6_gw_advrt_mtu;
506 uint16_t def_timeout;
507 uint8_t abort_timer;
508 uint16_t iscsi_options;
509 uint16_t iscsi_max_pdu_size;
510 uint16_t iscsi_first_burst_len;
511 uint16_t iscsi_max_outstnd_r2t;
512 uint16_t iscsi_max_burst_len;
513 uint8_t iscsi_name[224];
514 };
515
516 #define QL4_CHAP_MAX_NAME_LEN 256
517 #define QL4_CHAP_MAX_SECRET_LEN 100
518 #define LOCAL_CHAP 0
519 #define BIDI_CHAP 1
520
521 struct ql4_chap_format {
522 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
523 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN];
524 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN];
525 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN];
526 u16 intr_chap_name_length;
527 u16 intr_secret_length;
528 u16 target_chap_name_length;
529 u16 target_secret_length;
530 };
531
532 struct ip_address_format {
533 u8 ip_type;
534 u8 ip_address[16];
535 };
536
537 struct ql4_conn_info {
538 u16 dest_port;
539 struct ip_address_format dest_ipaddr;
540 struct ql4_chap_format chap;
541 };
542
543 struct ql4_boot_session_info {
544 u8 target_name[224];
545 struct ql4_conn_info conn_list[1];
546 };
547
548 struct ql4_boot_tgt_info {
549 struct ql4_boot_session_info boot_pri_sess;
550 struct ql4_boot_session_info boot_sec_sess;
551 };
552
553 /*
554 * Linux Host Adapter structure
555 */
556 struct scsi_qla_host {
557 /* Linux adapter configuration data */
558 unsigned long flags;
559
560 #define AF_ONLINE 0 /* 0x00000001 */
561 #define AF_INIT_DONE 1 /* 0x00000002 */
562 #define AF_MBOX_COMMAND 2 /* 0x00000004 */
563 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
564 #define AF_ST_DISCOVERY_IN_PROGRESS 4 /* 0x00000010 */
565 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */
566 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
567 #define AF_LINK_UP 8 /* 0x00000100 */
568 #define AF_LOOPBACK 9 /* 0x00000200 */
569 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */
570 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
571 #define AF_HA_REMOVAL 12 /* 0x00001000 */
572 #define AF_INTx_ENABLED 15 /* 0x00008000 */
573 #define AF_MSI_ENABLED 16 /* 0x00010000 */
574 #define AF_MSIX_ENABLED 17 /* 0x00020000 */
575 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
576 #define AF_FW_RECOVERY 19 /* 0x00080000 */
577 #define AF_EEH_BUSY 20 /* 0x00100000 */
578 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
579 #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */
580 #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */
581 #define AF_8XXX_RST_OWNER 25 /* 0x02000000 */
582 #define AF_82XX_DUMP_READING 26 /* 0x04000000 */
583 #define AF_83XX_NO_FW_DUMP 27 /* 0x08000000 */
584 #define AF_83XX_IOCB_INTR_ON 28 /* 0x10000000 */
585 #define AF_83XX_MBOX_INTR_ON 29 /* 0x20000000 */
586
587 unsigned long dpc_flags;
588
589 #define DPC_RESET_HA 1 /* 0x00000002 */
590 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
591 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
592 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
593 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */
594 #define DPC_ISNS_RESTART 7 /* 0x00000080 */
595 #define DPC_AEN 9 /* 0x00000200 */
596 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
597 #define DPC_LINK_CHANGED 18 /* 0x00040000 */
598 #define DPC_RESET_ACTIVE 20 /* 0x00040000 */
599 #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
600 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
601 #define DPC_POST_IDC_ACK 23 /* 0x00200000 */
602 #define DPC_RESTORE_ACB 24 /* 0x01000000 */
603
604 struct Scsi_Host *host; /* pointer to host data */
605 uint32_t tot_ddbs;
606
607 uint16_t iocb_cnt;
608 uint16_t iocb_hiwat;
609
610 /* SRB cache. */
611 #define SRB_MIN_REQ 128
612 mempool_t *srb_mempool;
613
614 /* pci information */
615 struct pci_dev *pdev;
616
617 struct isp_reg __iomem *reg; /* Base I/O address */
618 unsigned long pio_address;
619 unsigned long pio_length;
620 #define MIN_IOBASE_LEN 0x100
621
622 uint16_t req_q_count;
623
624 unsigned long host_no;
625
626 /* NVRAM registers */
627 struct eeprom_data *nvram;
628 spinlock_t hardware_lock ____cacheline_aligned;
629 uint32_t eeprom_cmd_data;
630
631 /* Counters for general statistics */
632 uint64_t isr_count;
633 uint64_t adapter_error_count;
634 uint64_t device_error_count;
635 uint64_t total_io_count;
636 uint64_t total_mbytes_xferred;
637 uint64_t link_failure_count;
638 uint64_t invalid_crc_count;
639 uint32_t bytes_xfered;
640 uint32_t spurious_int_count;
641 uint32_t aborted_io_count;
642 uint32_t io_timeout_count;
643 uint32_t mailbox_timeout_count;
644 uint32_t seconds_since_last_intr;
645 uint32_t seconds_since_last_heartbeat;
646 uint32_t mac_index;
647
648 /* Info Needed for Management App */
649 /* --- From GetFwVersion --- */
650 uint32_t firmware_version[2];
651 uint32_t patch_number;
652 uint32_t build_number;
653 uint32_t board_id;
654
655 /* --- From Init_FW --- */
656 /* init_cb_t *init_cb; */
657 uint16_t firmware_options;
658 uint8_t alias[32];
659 uint8_t name_string[256];
660 uint8_t heartbeat_interval;
661
662 /* --- From FlashSysInfo --- */
663 uint8_t my_mac[MAC_ADDR_LEN];
664 uint8_t serial_number[16];
665 uint16_t port_num;
666 /* --- From GetFwState --- */
667 uint32_t firmware_state;
668 uint32_t addl_fw_state;
669
670 /* Linux kernel thread */
671 struct workqueue_struct *dpc_thread;
672 struct work_struct dpc_work;
673
674 /* Linux timer thread */
675 struct timer_list timer;
676 uint32_t timer_active;
677
678 /* Recovery Timers */
679 atomic_t check_relogin_timeouts;
680 uint32_t retry_reset_ha_cnt;
681 uint32_t isp_reset_timer; /* reset test timer */
682 uint32_t nic_reset_timer; /* simulated nic reset test timer */
683 int eh_start;
684 struct list_head free_srb_q;
685 uint16_t free_srb_q_count;
686 uint16_t num_srbs_allocated;
687
688 /* DMA Memory Block */
689 void *queues;
690 dma_addr_t queues_dma;
691 unsigned long queues_len;
692
693 #define MEM_ALIGN_VALUE \
694 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
695 sizeof(struct queue_entry))
696 /* request and response queue variables */
697 dma_addr_t request_dma;
698 struct queue_entry *request_ring;
699 struct queue_entry *request_ptr;
700 dma_addr_t response_dma;
701 struct queue_entry *response_ring;
702 struct queue_entry *response_ptr;
703 dma_addr_t shadow_regs_dma;
704 struct shadow_regs *shadow_regs;
705 uint16_t request_in; /* Current indexes. */
706 uint16_t request_out;
707 uint16_t response_in;
708 uint16_t response_out;
709
710 /* aen queue variables */
711 uint16_t aen_q_count; /* Number of available aen_q entries */
712 uint16_t aen_in; /* Current indexes */
713 uint16_t aen_out;
714 struct aen aen_q[MAX_AEN_ENTRIES];
715
716 struct ql4_aen_log aen_log;/* tracks all aens */
717
718 /* This mutex protects several threads to do mailbox commands
719 * concurrently.
720 */
721 struct mutex mbox_sem;
722
723 /* temporary mailbox status registers */
724 volatile uint8_t mbox_status_count;
725 volatile uint32_t mbox_status[MBOX_REG_COUNT];
726
727 /* FW ddb index map */
728 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
729
730 /* Saved srb for status continuation entry processing */
731 struct srb *status_srb;
732
733 uint8_t acb_version;
734
735 /* qla82xx specific fields */
736 struct device_reg_82xx __iomem *qla4_82xx_reg; /* Base I/O address */
737 unsigned long nx_pcibase; /* Base I/O address */
738 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
739 unsigned long nx_db_wr_ptr; /* Door bell write pointer */
740 unsigned long first_page_group_start;
741 unsigned long first_page_group_end;
742
743 uint32_t crb_win;
744 uint32_t curr_window;
745 uint32_t ddr_mn_window;
746 unsigned long mn_win_crb;
747 unsigned long ms_win_crb;
748 int qdr_sn_window;
749 rwlock_t hw_lock;
750 uint16_t func_num;
751 int link_width;
752
753 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
754 u32 nx_crb_mask;
755
756 uint8_t revision_id;
757 uint32_t fw_heartbeat_counter;
758
759 struct isp_operations *isp_ops;
760 struct ql82xx_hw_data hw;
761
762 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
763
764 uint32_t nx_dev_init_timeout;
765 uint32_t nx_reset_timeout;
766 void *fw_dump;
767 uint32_t fw_dump_size;
768 uint32_t fw_dump_capture_mask;
769 void *fw_dump_tmplt_hdr;
770 uint32_t fw_dump_tmplt_size;
771
772 struct completion mbx_intr_comp;
773
774 struct ipaddress_config ip_config;
775 struct iscsi_iface *iface_ipv4;
776 struct iscsi_iface *iface_ipv6_0;
777 struct iscsi_iface *iface_ipv6_1;
778
779 /* --- From About Firmware --- */
780 struct about_fw_info fw_info;
781 uint32_t fw_uptime_secs; /* seconds elapsed since fw bootup */
782 uint32_t fw_uptime_msecs; /* milliseconds beyond elapsed seconds */
783 uint16_t def_timeout; /* Default login timeout */
784
785 uint32_t flash_state;
786 #define QLFLASH_WAITING 0
787 #define QLFLASH_READING 1
788 #define QLFLASH_WRITING 2
789 struct dma_pool *chap_dma_pool;
790 uint8_t *chap_list; /* CHAP table cache */
791 struct mutex chap_sem;
792
793 #define CHAP_DMA_BLOCK_SIZE 512
794 struct workqueue_struct *task_wq;
795 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
796 #define SYSFS_FLAG_FW_SEL_BOOT 2
797 struct iscsi_boot_kset *boot_kset;
798 struct ql4_boot_tgt_info boot_tgt;
799 uint16_t phy_port_num;
800 uint16_t phy_port_cnt;
801 uint16_t iscsi_pci_func_cnt;
802 uint8_t model_name[16];
803 struct completion disable_acb_comp;
804 struct dma_pool *fw_ddb_dma_pool;
805 #define DDB_DMA_BLOCK_SIZE 512
806 uint16_t pri_ddb_idx;
807 uint16_t sec_ddb_idx;
808 int is_reset;
809 uint16_t temperature;
810
811 /* event work list */
812 struct list_head work_list;
813 spinlock_t work_lock;
814
815 /* mbox iocb */
816 #define MAX_MRB 128
817 struct mrb *active_mrb_array[MAX_MRB];
818 uint32_t mrb_index;
819
820 uint32_t *reg_tbl;
821 struct qla4_83xx_reset_template reset_tmplt;
822 struct device_reg_83xx __iomem *qla4_83xx_reg; /* Base I/O address
823 for ISP8324 and
824 and ISP8042 */
825 uint32_t pf_bit;
826 struct qla4_83xx_idc_information idc_info;
827 struct addr_ctrl_blk *saved_acb;
828 int notify_idc_comp;
829 int notify_link_up_comp;
830 int idc_extend_tmo;
831 struct completion idc_comp;
832 struct completion link_up_comp;
833 };
834
835 struct ql4_task_data {
836 struct scsi_qla_host *ha;
837 uint8_t iocb_req_cnt;
838 dma_addr_t data_dma;
839 void *req_buffer;
840 dma_addr_t req_dma;
841 uint32_t req_len;
842 void *resp_buffer;
843 dma_addr_t resp_dma;
844 uint32_t resp_len;
845 struct iscsi_task *task;
846 struct passthru_status sts;
847 struct work_struct task_work;
848 };
849
850 struct qla_endpoint {
851 struct Scsi_Host *host;
852 struct sockaddr_storage dst_addr;
853 };
854
855 struct qla_conn {
856 struct qla_endpoint *qla_ep;
857 };
858
859 static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
860 {
861 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
862 }
863
864 static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
865 {
866 return ((ha->ip_config.ipv6_options &
867 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
868 }
869
870 static inline int is_qla4010(struct scsi_qla_host *ha)
871 {
872 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
873 }
874
875 static inline int is_qla4022(struct scsi_qla_host *ha)
876 {
877 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
878 }
879
880 static inline int is_qla4032(struct scsi_qla_host *ha)
881 {
882 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
883 }
884
885 static inline int is_qla40XX(struct scsi_qla_host *ha)
886 {
887 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
888 }
889
890 static inline int is_qla8022(struct scsi_qla_host *ha)
891 {
892 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
893 }
894
895 static inline int is_qla8032(struct scsi_qla_host *ha)
896 {
897 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324;
898 }
899
900 static inline int is_qla8042(struct scsi_qla_host *ha)
901 {
902 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042;
903 }
904
905 static inline int is_qla80XX(struct scsi_qla_host *ha)
906 {
907 return is_qla8022(ha) || is_qla8032(ha) || is_qla8042(ha);
908 }
909
910 static inline int is_aer_supported(struct scsi_qla_host *ha)
911 {
912 return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) ||
913 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324));
914 }
915
916 static inline int adapter_up(struct scsi_qla_host *ha)
917 {
918 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
919 (test_bit(AF_LINK_UP, &ha->flags) != 0) &&
920 (!test_bit(AF_LOOPBACK, &ha->flags));
921 }
922
923 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
924 {
925 return (struct scsi_qla_host *)iscsi_host_priv(shost);
926 }
927
928 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
929 {
930 return (is_qla4010(ha) ?
931 &ha->reg->u1.isp4010.nvram :
932 &ha->reg->u1.isp4022.semaphore);
933 }
934
935 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
936 {
937 return (is_qla4010(ha) ?
938 &ha->reg->u1.isp4010.nvram :
939 &ha->reg->u1.isp4022.nvram);
940 }
941
942 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
943 {
944 return (is_qla4010(ha) ?
945 &ha->reg->u2.isp4010.ext_hw_conf :
946 &ha->reg->u2.isp4022.p0.ext_hw_conf);
947 }
948
949 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
950 {
951 return (is_qla4010(ha) ?
952 &ha->reg->u2.isp4010.port_status :
953 &ha->reg->u2.isp4022.p0.port_status);
954 }
955
956 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
957 {
958 return (is_qla4010(ha) ?
959 &ha->reg->u2.isp4010.port_ctrl :
960 &ha->reg->u2.isp4022.p0.port_ctrl);
961 }
962
963 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
964 {
965 return (is_qla4010(ha) ?
966 &ha->reg->u2.isp4010.port_err_status :
967 &ha->reg->u2.isp4022.p0.port_err_status);
968 }
969
970 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
971 {
972 return (is_qla4010(ha) ?
973 &ha->reg->u2.isp4010.gp_out :
974 &ha->reg->u2.isp4022.p0.gp_out);
975 }
976
977 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
978 {
979 return (is_qla4010(ha) ?
980 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
981 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
982 }
983
984 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
985 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
986 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
987
988 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
989 {
990 if (is_qla4010(a))
991 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
992 QL4010_FLASH_SEM_BITS);
993 else
994 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
995 (QL4022_RESOURCE_BITS_BASE_CODE |
996 (a->mac_index)) << 13);
997 }
998
999 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
1000 {
1001 if (is_qla4010(a))
1002 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
1003 else
1004 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
1005 }
1006
1007 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
1008 {
1009 if (is_qla4010(a))
1010 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
1011 QL4010_NVRAM_SEM_BITS);
1012 else
1013 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
1014 (QL4022_RESOURCE_BITS_BASE_CODE |
1015 (a->mac_index)) << 10);
1016 }
1017
1018 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
1019 {
1020 if (is_qla4010(a))
1021 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
1022 else
1023 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
1024 }
1025
1026 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
1027 {
1028 if (is_qla4010(a))
1029 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
1030 QL4010_DRVR_SEM_BITS);
1031 else
1032 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
1033 (QL4022_RESOURCE_BITS_BASE_CODE |
1034 (a->mac_index)) << 1);
1035 }
1036
1037 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
1038 {
1039 if (is_qla4010(a))
1040 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
1041 else
1042 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
1043 }
1044
1045 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
1046 {
1047 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
1048 test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
1049 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
1050 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
1051 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
1052 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
1053
1054 }
1055
1056 static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha,
1057 const uint32_t crb_reg)
1058 {
1059 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]);
1060 }
1061
1062 static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha,
1063 const uint32_t crb_reg,
1064 const uint32_t value)
1065 {
1066 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value);
1067 }
1068
1069 /*---------------------------------------------------------------------------*/
1070
1071 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
1072
1073 #define INIT_ADAPTER 0
1074 #define RESET_ADAPTER 1
1075
1076 #define PRESERVE_DDB_LIST 0
1077 #define REBUILD_DDB_LIST 1
1078
1079 /* Defines for process_aen() */
1080 #define PROCESS_ALL_AENS 0
1081 #define FLUSH_DDB_CHANGED_AENS 1
1082
1083 /* Defines for udev events */
1084 #define QL4_UEVENT_CODE_FW_DUMP 0
1085
1086 #endif /*_QLA4XXX_H */
Linux with added FPC-III support