drivers/staging/imx-drm/ipuv3-plane.c

   1 /*
   2  * i.MX IPUv3 DP Overlay Planes
   3  *
   4  * Copyright (C) 2013 Philipp Zabel, Pengutronix
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <drm/drmP.h>
  17 #include <drm/drm_fb_cma_helper.h>
  18 #include <drm/drm_gem_cma_helper.h>
  19
  20 #include "ipu-v3/imx-ipu-v3.h"
  21 #include "ipuv3-plane.h"
  22
  23 #define to_ipu_plane(x) container_of(x, struct ipu_plane, base)
  24
  25 static const uint32_t ipu_plane_formats[] = {
  26         DRM_FORMAT_XRGB1555,
  27         DRM_FORMAT_XBGR1555,
  28         DRM_FORMAT_ARGB8888,
  29         DRM_FORMAT_XRGB8888,
  30         DRM_FORMAT_ABGR8888,
  31         DRM_FORMAT_XBGR8888,
  32         DRM_FORMAT_YUYV,
  33         DRM_FORMAT_YVYU,
  34         DRM_FORMAT_YUV420,
  35         DRM_FORMAT_YVU420,
  36 };
  37
  38 int ipu_plane_irq(struct ipu_plane *ipu_plane)
  39 {
  40         return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
  41                                      IPU_IRQ_EOF);
  42 }
  43
  44 static int calc_vref(struct drm_display_mode *mode)
  45 {
  46         unsigned long htotal, vtotal;
  47
  48         htotal = mode->htotal;
  49         vtotal = mode->vtotal;
  50
  51         if (!htotal || !vtotal)
  52                 return 60;
  53
  54         return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
  55 }
  56
  57 static inline int calc_bandwidth(int width, int height, unsigned int vref)
  58 {
  59         return width * height * vref;
  60 }
  61
  62 int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
  63                        int x, int y)
  64 {
  65         struct ipu_ch_param __iomem *cpmem;
  66         struct drm_gem_cma_object *cma_obj;
  67         unsigned long eba;
  68
  69         cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
  70         if (!cma_obj) {
  71                 DRM_LOG_KMS("entry is null.\n");
  72                 return -EFAULT;
  73         }
  74
  75         dev_dbg(ipu_plane->base.dev->dev, "phys = 0x%x, x = %d, y = %d",
  76                 cma_obj->paddr, x, y);
  77
  78         cpmem = ipu_get_cpmem(ipu_plane->ipu_ch);
  79         ipu_cpmem_set_stride(cpmem, fb->pitches[0]);
  80
  81         eba = cma_obj->paddr + fb->offsets[0] +
  82               fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
  83         ipu_cpmem_set_buffer(cpmem, 0, eba);
  84         ipu_cpmem_set_buffer(cpmem, 1, eba);
  85
  86         /* cache offsets for subsequent pageflips */
  87         ipu_plane->x = x;
  88         ipu_plane->y = y;
  89
  90         return 0;
  91 }
  92
  93 int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
  94                        struct drm_display_mode *mode,
  95                        struct drm_framebuffer *fb, int crtc_x, int crtc_y,
  96                        unsigned int crtc_w, unsigned int crtc_h,
  97                        uint32_t src_x, uint32_t src_y,
  98                        uint32_t src_w, uint32_t src_h)
  99 {
 100         struct ipu_ch_param __iomem *cpmem;
 101         struct device *dev = ipu_plane->base.dev->dev;
 102         int ret;
 103
 104         /* no scaling */
 105         if (src_w != crtc_w || src_h != crtc_h)
 106                 return -EINVAL;
 107
 108         /* clip to crtc bounds */
 109         if (crtc_x < 0) {
 110                 if (-crtc_x > crtc_w)
 111                         return -EINVAL;
 112                 src_x += -crtc_x;
 113                 src_w -= -crtc_x;
 114                 crtc_w -= -crtc_x;
 115                 crtc_x = 0;
 116         }
 117         if (crtc_y < 0) {
 118                 if (-crtc_y > crtc_h)
 119                         return -EINVAL;
 120                 src_y += -crtc_y;
 121                 src_h -= -crtc_y;
 122                 crtc_h -= -crtc_y;
 123                 crtc_y = 0;
 124         }
 125         if (crtc_x + crtc_w > mode->hdisplay) {
 126                 if (crtc_x > mode->hdisplay)
 127                         return -EINVAL;
 128                 crtc_w = mode->hdisplay - crtc_x;
 129                 src_w = crtc_w;
 130         }
 131         if (crtc_y + crtc_h > mode->vdisplay) {
 132                 if (crtc_y > mode->vdisplay)
 133                         return -EINVAL;
 134                 crtc_h = mode->vdisplay - crtc_y;
 135                 src_h = crtc_h;
 136         }
 137         /* full plane minimum width is 13 pixels */
 138         if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
 139                 return -EINVAL;
 140         if (crtc_h < 2)
 141                 return -EINVAL;
 142
 143         switch (ipu_plane->dp_flow) {
 144         case IPU_DP_FLOW_SYNC_BG:
 145                 ret = ipu_dp_setup_channel(ipu_plane->dp,
 146                                 IPUV3_COLORSPACE_RGB,
 147                                 IPUV3_COLORSPACE_RGB);
 148                 if (ret) {
 149                         dev_err(dev,
 150                                 "initializing display processor failed with %d\n",
 151                                 ret);
 152                         return ret;
 153                 }
 154                 ipu_dp_set_global_alpha(ipu_plane->dp, 1, 0, 1);
 155                 break;
 156         case IPU_DP_FLOW_SYNC_FG:
 157                 ipu_dp_setup_channel(ipu_plane->dp,
 158                                 ipu_drm_fourcc_to_colorspace(fb->pixel_format),
 159                                 IPUV3_COLORSPACE_UNKNOWN);
 160                 ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
 161                 break;
 162         }
 163
 164         ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
 165         if (ret) {
 166                 dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
 167                 return ret;
 168         }
 169
 170         ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
 171                         calc_bandwidth(crtc_w, crtc_h,
 172                                        calc_vref(mode)), 64);
 173         if (ret) {
 174                 dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
 175                 return ret;
 176         }
 177
 178         cpmem = ipu_get_cpmem(ipu_plane->ipu_ch);
 179         ipu_ch_param_zero(cpmem);
 180         ipu_cpmem_set_resolution(cpmem, src_w, src_h);
 181         ret = ipu_cpmem_set_fmt(cpmem, fb->pixel_format);
 182         if (ret < 0) {
 183                 dev_err(dev, "unsupported pixel format 0x%08x\n",
 184                         fb->pixel_format);
 185                 return ret;
 186         }
 187         ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
 188
 189         ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
 190         if (ret < 0)
 191                 return ret;
 192
 193         return 0;
 194 }
 195
 196 void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
 197 {
 198         if (!IS_ERR_OR_NULL(ipu_plane->dp))
 199                 ipu_dp_put(ipu_plane->dp);
 200         if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
 201                 ipu_dmfc_put(ipu_plane->dmfc);
 202         if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
 203                 ipu_idmac_put(ipu_plane->ipu_ch);
 204 }
 205
 206 int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
 207 {
 208         int ret;
 209
 210         ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
 211         if (IS_ERR(ipu_plane->ipu_ch)) {
 212                 ret = PTR_ERR(ipu_plane->ipu_ch);
 213                 DRM_ERROR("failed to get idmac channel: %d\n", ret);
 214                 return ret;
 215         }
 216
 217         ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
 218         if (IS_ERR(ipu_plane->dmfc)) {
 219                 ret = PTR_ERR(ipu_plane->dmfc);
 220                 DRM_ERROR("failed to get dmfc: ret %d\n", ret);
 221                 goto err_out;
 222         }
 223
 224         if (ipu_plane->dp_flow >= 0) {
 225                 ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
 226                 if (IS_ERR(ipu_plane->dp)) {
 227                         ret = PTR_ERR(ipu_plane->dp);
 228                         DRM_ERROR("failed to get dp flow: %d\n", ret);
 229                         goto err_out;
 230                 }
 231         }
 232
 233         return 0;
 234 err_out:
 235         ipu_plane_put_resources(ipu_plane);
 236
 237         return ret;
 238 }
 239
 240 void ipu_plane_enable(struct ipu_plane *ipu_plane)
 241 {
 242         ipu_dmfc_enable_channel(ipu_plane->dmfc);
 243         ipu_idmac_enable_channel(ipu_plane->ipu_ch);
 244         if (ipu_plane->dp)
 245                 ipu_dp_enable_channel(ipu_plane->dp);
 246
 247         ipu_plane->enabled = true;
 248 }
 249
 250 void ipu_plane_disable(struct ipu_plane *ipu_plane)
 251 {
 252         ipu_plane->enabled = false;
 253
 254         ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
 255
 256         if (ipu_plane->dp)
 257                 ipu_dp_disable_channel(ipu_plane->dp);
 258         ipu_idmac_disable_channel(ipu_plane->ipu_ch);
 259         ipu_dmfc_disable_channel(ipu_plane->dmfc);
 260 }
 261
 262 static void ipu_plane_dpms(struct ipu_plane *ipu_plane, int mode)
 263 {
 264         bool enable;
 265
 266         DRM_DEBUG_KMS("mode = %d", mode);
 267
 268         enable = (mode == DRM_MODE_DPMS_ON);
 269
 270         if (enable == ipu_plane->enabled)
 271                 return;
 272
 273         if (enable) {
 274                 ipu_plane_enable(ipu_plane);
 275         } else {
 276                 ipu_plane_disable(ipu_plane);
 277
 278                 ipu_idmac_put(ipu_plane->ipu_ch);
 279                 ipu_dmfc_put(ipu_plane->dmfc);
 280                 ipu_dp_put(ipu_plane->dp);
 281         }
 282 }
 283
 284 /*
 285  * drm_plane API
 286  */
 287
 288 static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 289                             struct drm_framebuffer *fb, int crtc_x, int crtc_y,
 290                             unsigned int crtc_w, unsigned int crtc_h,
 291                             uint32_t src_x, uint32_t src_y,
 292                             uint32_t src_w, uint32_t src_h)
 293 {
 294         struct ipu_plane *ipu_plane = to_ipu_plane(plane);
 295         int ret = 0;
 296
 297         DRM_DEBUG_KMS("plane - %p\n", plane);
 298
 299         if (!ipu_plane->enabled)
 300                 ret = ipu_plane_get_resources(ipu_plane);
 301         if (ret < 0)
 302                 return ret;
 303
 304         ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
 305                         crtc_x, crtc_y, crtc_w, crtc_h,
 306                         src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16);
 307         if (ret < 0) {
 308                 ipu_plane_put_resources(ipu_plane);
 309                 return ret;
 310         }
 311
 312         if (crtc != plane->crtc)
 313                 dev_info(plane->dev->dev, "crtc change: %p -> %p\n",
 314                                 plane->crtc, crtc);
 315         plane->crtc = crtc;
 316
 317         ipu_plane_dpms(ipu_plane, DRM_MODE_DPMS_ON);
 318
 319         return 0;
 320 }
 321
 322 static int ipu_disable_plane(struct drm_plane *plane)
 323 {
 324         struct ipu_plane *ipu_plane = to_ipu_plane(plane);
 325
 326         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 327
 328         ipu_plane_dpms(ipu_plane, DRM_MODE_DPMS_OFF);
 329
 330         ipu_plane_put_resources(ipu_plane);
 331
 332         return 0;
 333 }
 334
 335 static void ipu_plane_destroy(struct drm_plane *plane)
 336 {
 337         struct ipu_plane *ipu_plane = to_ipu_plane(plane);
 338
 339         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 340
 341         ipu_disable_plane(plane);
 342         drm_plane_cleanup(plane);
 343         kfree(ipu_plane);
 344 }
 345
 346 static struct drm_plane_funcs ipu_plane_funcs = {
 347         .update_plane   = ipu_update_plane,
 348         .disable_plane  = ipu_disable_plane,
 349         .destroy        = ipu_plane_destroy,
 350 };
 351
 352 struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
 353                                  int dma, int dp, unsigned int possible_crtcs,
 354                                  bool priv)
 355 {
 356         struct ipu_plane *ipu_plane;
 357         int ret;
 358
 359         DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
 360                       dma, dp, possible_crtcs);
 361
 362         ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
 363         if (!ipu_plane) {
 364                 DRM_ERROR("failed to allocate plane\n");
 365                 return ERR_PTR(-ENOMEM);
 366         }
 367
 368         ipu_plane->ipu = ipu;
 369         ipu_plane->dma = dma;
 370         ipu_plane->dp_flow = dp;
 371
 372         ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs,
 373                              &ipu_plane_funcs, ipu_plane_formats,
 374                              ARRAY_SIZE(ipu_plane_formats),
 375                              priv);
 376         if (ret) {
 377                 DRM_ERROR("failed to initialize plane\n");
 378                 kfree(ipu_plane);
 379                 return ERR_PTR(ret);
 380         }
 381
 382         return ipu_plane;
 383 }