drivers/video/omap2/dss/dispc.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.h
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  * Author: Archit Taneja <archit@ti.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef __OMAP2_DISPC_REG_H
  22 #define __OMAP2_DISPC_REG_H
  23
  24 /* DISPC common registers */
  25 #define DISPC_REVISION                  0x0000
  26 #define DISPC_SYSCONFIG                 0x0010
  27 #define DISPC_SYSSTATUS                 0x0014
  28 #define DISPC_IRQSTATUS                 0x0018
  29 #define DISPC_IRQENABLE                 0x001C
  30 #define DISPC_CONTROL                   0x0040
  31 #define DISPC_CONFIG                    0x0044
  32 #define DISPC_CAPABLE                   0x0048
  33 #define DISPC_LINE_STATUS               0x005C
  34 #define DISPC_LINE_NUMBER               0x0060
  35 #define DISPC_GLOBAL_ALPHA              0x0074
  36 #define DISPC_CONTROL2                  0x0238
  37 #define DISPC_CONFIG2                   0x0620
  38 #define DISPC_DIVISOR                   0x0804
  39 #define DISPC_GLOBAL_BUFFER             0x0800
  40 #define DISPC_CONTROL3                  0x0848
  41 #define DISPC_CONFIG3                   0x084C
  42 #define DISPC_MSTANDBY_CTRL             0x0858
  43 #define DISPC_GLOBAL_MFLAG_ATTRIBUTE    0x085C
  44
  45 /* DISPC overlay registers */
  46 #define DISPC_OVL_BA0(n)                (DISPC_OVL_BASE(n) + \
  47                                         DISPC_BA0_OFFSET(n))
  48 #define DISPC_OVL_BA1(n)                (DISPC_OVL_BASE(n) + \
  49                                         DISPC_BA1_OFFSET(n))
  50 #define DISPC_OVL_BA0_UV(n)             (DISPC_OVL_BASE(n) + \
  51                                         DISPC_BA0_UV_OFFSET(n))
  52 #define DISPC_OVL_BA1_UV(n)             (DISPC_OVL_BASE(n) + \
  53                                         DISPC_BA1_UV_OFFSET(n))
  54 #define DISPC_OVL_POSITION(n)           (DISPC_OVL_BASE(n) + \
  55                                         DISPC_POS_OFFSET(n))
  56 #define DISPC_OVL_SIZE(n)               (DISPC_OVL_BASE(n) + \
  57                                         DISPC_SIZE_OFFSET(n))
  58 #define DISPC_OVL_ATTRIBUTES(n)         (DISPC_OVL_BASE(n) + \
  59                                         DISPC_ATTR_OFFSET(n))
  60 #define DISPC_OVL_ATTRIBUTES2(n)        (DISPC_OVL_BASE(n) + \
  61                                         DISPC_ATTR2_OFFSET(n))
  62 #define DISPC_OVL_FIFO_THRESHOLD(n)     (DISPC_OVL_BASE(n) + \
  63                                         DISPC_FIFO_THRESH_OFFSET(n))
  64 #define DISPC_OVL_FIFO_SIZE_STATUS(n)   (DISPC_OVL_BASE(n) + \
  65                                         DISPC_FIFO_SIZE_STATUS_OFFSET(n))
  66 #define DISPC_OVL_ROW_INC(n)            (DISPC_OVL_BASE(n) + \
  67                                         DISPC_ROW_INC_OFFSET(n))
  68 #define DISPC_OVL_PIXEL_INC(n)          (DISPC_OVL_BASE(n) + \
  69                                         DISPC_PIX_INC_OFFSET(n))
  70 #define DISPC_OVL_WINDOW_SKIP(n)        (DISPC_OVL_BASE(n) + \
  71                                         DISPC_WINDOW_SKIP_OFFSET(n))
  72 #define DISPC_OVL_TABLE_BA(n)           (DISPC_OVL_BASE(n) + \
  73                                         DISPC_TABLE_BA_OFFSET(n))
  74 #define DISPC_OVL_FIR(n)                (DISPC_OVL_BASE(n) + \
  75                                         DISPC_FIR_OFFSET(n))
  76 #define DISPC_OVL_FIR2(n)               (DISPC_OVL_BASE(n) + \
  77                                         DISPC_FIR2_OFFSET(n))
  78 #define DISPC_OVL_PICTURE_SIZE(n)       (DISPC_OVL_BASE(n) + \
  79                                         DISPC_PIC_SIZE_OFFSET(n))
  80 #define DISPC_OVL_ACCU0(n)              (DISPC_OVL_BASE(n) + \
  81                                         DISPC_ACCU0_OFFSET(n))
  82 #define DISPC_OVL_ACCU1(n)              (DISPC_OVL_BASE(n) + \
  83                                         DISPC_ACCU1_OFFSET(n))
  84 #define DISPC_OVL_ACCU2_0(n)            (DISPC_OVL_BASE(n) + \
  85                                         DISPC_ACCU2_0_OFFSET(n))
  86 #define DISPC_OVL_ACCU2_1(n)            (DISPC_OVL_BASE(n) + \
  87                                         DISPC_ACCU2_1_OFFSET(n))
  88 #define DISPC_OVL_FIR_COEF_H(n, i)      (DISPC_OVL_BASE(n) + \
  89                                         DISPC_FIR_COEF_H_OFFSET(n, i))
  90 #define DISPC_OVL_FIR_COEF_HV(n, i)     (DISPC_OVL_BASE(n) + \
  91                                         DISPC_FIR_COEF_HV_OFFSET(n, i))
  92 #define DISPC_OVL_FIR_COEF_H2(n, i)     (DISPC_OVL_BASE(n) + \
  93                                         DISPC_FIR_COEF_H2_OFFSET(n, i))
  94 #define DISPC_OVL_FIR_COEF_HV2(n, i)    (DISPC_OVL_BASE(n) + \
  95                                         DISPC_FIR_COEF_HV2_OFFSET(n, i))
  96 #define DISPC_OVL_CONV_COEF(n, i)       (DISPC_OVL_BASE(n) + \
  97                                         DISPC_CONV_COEF_OFFSET(n, i))
  98 #define DISPC_OVL_FIR_COEF_V(n, i)      (DISPC_OVL_BASE(n) + \
  99                                         DISPC_FIR_COEF_V_OFFSET(n, i))
 100 #define DISPC_OVL_FIR_COEF_V2(n, i)     (DISPC_OVL_BASE(n) + \
 101                                         DISPC_FIR_COEF_V2_OFFSET(n, i))
 102 #define DISPC_OVL_PRELOAD(n)            (DISPC_OVL_BASE(n) + \
 103                                         DISPC_PRELOAD_OFFSET(n))
 104 #define DISPC_OVL_MFLAG_THRESHOLD(n)    (DISPC_OVL_BASE(n) + \
 105                                         DISPC_MFLAG_THRESHOLD_OFFSET(n))
 106
 107 /* DISPC up/downsampling FIR filter coefficient structure */
 108 struct dispc_coef {
 109         s8 hc4_vc22;
 110         s8 hc3_vc2;
 111         u8 hc2_vc1;
 112         s8 hc1_vc0;
 113         s8 hc0_vc00;
 114 };
 115
 116 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
 117
 118 /* DISPC manager/channel specific registers */
 119 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
 120 {
 121         switch (channel) {
 122         case OMAP_DSS_CHANNEL_LCD:
 123                 return 0x004C;
 124         case OMAP_DSS_CHANNEL_DIGIT:
 125                 return 0x0050;
 126         case OMAP_DSS_CHANNEL_LCD2:
 127                 return 0x03AC;
 128         case OMAP_DSS_CHANNEL_LCD3:
 129                 return 0x0814;
 130         default:
 131                 BUG();
 132                 return 0;
 133         }
 134 }
 135
 136 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
 137 {
 138         switch (channel) {
 139         case OMAP_DSS_CHANNEL_LCD:
 140                 return 0x0054;
 141         case OMAP_DSS_CHANNEL_DIGIT:
 142                 return 0x0058;
 143         case OMAP_DSS_CHANNEL_LCD2:
 144                 return 0x03B0;
 145         case OMAP_DSS_CHANNEL_LCD3:
 146                 return 0x0818;
 147         default:
 148                 BUG();
 149                 return 0;
 150         }
 151 }
 152
 153 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
 154 {
 155         switch (channel) {
 156         case OMAP_DSS_CHANNEL_LCD:
 157                 return 0x0064;
 158         case OMAP_DSS_CHANNEL_DIGIT:
 159                 BUG();
 160                 return 0;
 161         case OMAP_DSS_CHANNEL_LCD2:
 162                 return 0x0400;
 163         case OMAP_DSS_CHANNEL_LCD3:
 164                 return 0x0840;
 165         default:
 166                 BUG();
 167                 return 0;
 168         }
 169 }
 170
 171 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
 172 {
 173         switch (channel) {
 174         case OMAP_DSS_CHANNEL_LCD:
 175                 return 0x0068;
 176         case OMAP_DSS_CHANNEL_DIGIT:
 177                 BUG();
 178                 return 0;
 179         case OMAP_DSS_CHANNEL_LCD2:
 180                 return 0x0404;
 181         case OMAP_DSS_CHANNEL_LCD3:
 182                 return 0x0844;
 183         default:
 184                 BUG();
 185                 return 0;
 186         }
 187 }
 188
 189 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
 190 {
 191         switch (channel) {
 192         case OMAP_DSS_CHANNEL_LCD:
 193                 return 0x006C;
 194         case OMAP_DSS_CHANNEL_DIGIT:
 195                 BUG();
 196                 return 0;
 197         case OMAP_DSS_CHANNEL_LCD2:
 198                 return 0x0408;
 199         case OMAP_DSS_CHANNEL_LCD3:
 200                 return 0x083C;
 201         default:
 202                 BUG();
 203                 return 0;
 204         }
 205 }
 206
 207 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
 208 {
 209         switch (channel) {
 210         case OMAP_DSS_CHANNEL_LCD:
 211                 return 0x0070;
 212         case OMAP_DSS_CHANNEL_DIGIT:
 213                 BUG();
 214                 return 0;
 215         case OMAP_DSS_CHANNEL_LCD2:
 216                 return 0x040C;
 217         case OMAP_DSS_CHANNEL_LCD3:
 218                 return 0x0838;
 219         default:
 220                 BUG();
 221                 return 0;
 222         }
 223 }
 224
 225 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
 226 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
 227 {
 228         switch (channel) {
 229         case OMAP_DSS_CHANNEL_LCD:
 230                 return 0x007C;
 231         case OMAP_DSS_CHANNEL_DIGIT:
 232                 return 0x0078;
 233         case OMAP_DSS_CHANNEL_LCD2:
 234                 return 0x03CC;
 235         case OMAP_DSS_CHANNEL_LCD3:
 236                 return 0x0834;
 237         default:
 238                 BUG();
 239                 return 0;
 240         }
 241 }
 242
 243 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
 244 {
 245         switch (channel) {
 246         case OMAP_DSS_CHANNEL_LCD:
 247                 return 0x01D4;
 248         case OMAP_DSS_CHANNEL_DIGIT:
 249                 BUG();
 250                 return 0;
 251         case OMAP_DSS_CHANNEL_LCD2:
 252                 return 0x03C0;
 253         case OMAP_DSS_CHANNEL_LCD3:
 254                 return 0x0828;
 255         default:
 256                 BUG();
 257                 return 0;
 258         }
 259 }
 260
 261 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
 262 {
 263         switch (channel) {
 264         case OMAP_DSS_CHANNEL_LCD:
 265                 return 0x01D8;
 266         case OMAP_DSS_CHANNEL_DIGIT:
 267                 BUG();
 268                 return 0;
 269         case OMAP_DSS_CHANNEL_LCD2:
 270                 return 0x03C4;
 271         case OMAP_DSS_CHANNEL_LCD3:
 272                 return 0x082C;
 273         default:
 274                 BUG();
 275                 return 0;
 276         }
 277 }
 278
 279 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
 280 {
 281         switch (channel) {
 282         case OMAP_DSS_CHANNEL_LCD:
 283                 return 0x01DC;
 284         case OMAP_DSS_CHANNEL_DIGIT:
 285                 BUG();
 286                 return 0;
 287         case OMAP_DSS_CHANNEL_LCD2:
 288                 return 0x03C8;
 289         case OMAP_DSS_CHANNEL_LCD3:
 290                 return 0x0830;
 291         default:
 292                 BUG();
 293                 return 0;
 294         }
 295 }
 296
 297 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
 298 {
 299         switch (channel) {
 300         case OMAP_DSS_CHANNEL_LCD:
 301                 return 0x0220;
 302         case OMAP_DSS_CHANNEL_DIGIT:
 303                 BUG();
 304                 return 0;
 305         case OMAP_DSS_CHANNEL_LCD2:
 306                 return 0x03BC;
 307         case OMAP_DSS_CHANNEL_LCD3:
 308                 return 0x0824;
 309         default:
 310                 BUG();
 311                 return 0;
 312         }
 313 }
 314
 315 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
 316 {
 317         switch (channel) {
 318         case OMAP_DSS_CHANNEL_LCD:
 319                 return 0x0224;
 320         case OMAP_DSS_CHANNEL_DIGIT:
 321                 BUG();
 322                 return 0;
 323         case OMAP_DSS_CHANNEL_LCD2:
 324                 return 0x03B8;
 325         case OMAP_DSS_CHANNEL_LCD3:
 326                 return 0x0820;
 327         default:
 328                 BUG();
 329                 return 0;
 330         }
 331 }
 332
 333 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
 334 {
 335         switch (channel) {
 336         case OMAP_DSS_CHANNEL_LCD:
 337                 return 0x0228;
 338         case OMAP_DSS_CHANNEL_DIGIT:
 339                 BUG();
 340                 return 0;
 341         case OMAP_DSS_CHANNEL_LCD2:
 342                 return 0x03B4;
 343         case OMAP_DSS_CHANNEL_LCD3:
 344                 return 0x081C;
 345         default:
 346                 BUG();
 347                 return 0;
 348         }
 349 }
 350
 351 /* DISPC overlay register base addresses */
 352 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
 353 {
 354         switch (plane) {
 355         case OMAP_DSS_GFX:
 356                 return 0x0080;
 357         case OMAP_DSS_VIDEO1:
 358                 return 0x00BC;
 359         case OMAP_DSS_VIDEO2:
 360                 return 0x014C;
 361         case OMAP_DSS_VIDEO3:
 362                 return 0x0300;
 363         case OMAP_DSS_WB:
 364                 return 0x0500;
 365         default:
 366                 BUG();
 367                 return 0;
 368         }
 369 }
 370
 371 /* DISPC overlay register offsets */
 372 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
 373 {
 374         switch (plane) {
 375         case OMAP_DSS_GFX:
 376         case OMAP_DSS_VIDEO1:
 377         case OMAP_DSS_VIDEO2:
 378                 return 0x0000;
 379         case OMAP_DSS_VIDEO3:
 380         case OMAP_DSS_WB:
 381                 return 0x0008;
 382         default:
 383                 BUG();
 384                 return 0;
 385         }
 386 }
 387
 388 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
 389 {
 390         switch (plane) {
 391         case OMAP_DSS_GFX:
 392         case OMAP_DSS_VIDEO1:
 393         case OMAP_DSS_VIDEO2:
 394                 return 0x0004;
 395         case OMAP_DSS_VIDEO3:
 396         case OMAP_DSS_WB:
 397                 return 0x000C;
 398         default:
 399                 BUG();
 400                 return 0;
 401         }
 402 }
 403
 404 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
 405 {
 406         switch (plane) {
 407         case OMAP_DSS_GFX:
 408                 BUG();
 409                 return 0;
 410         case OMAP_DSS_VIDEO1:
 411                 return 0x0544;
 412         case OMAP_DSS_VIDEO2:
 413                 return 0x04BC;
 414         case OMAP_DSS_VIDEO3:
 415                 return 0x0310;
 416         case OMAP_DSS_WB:
 417                 return 0x0118;
 418         default:
 419                 BUG();
 420                 return 0;
 421         }
 422 }
 423
 424 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
 425 {
 426         switch (plane) {
 427         case OMAP_DSS_GFX:
 428                 BUG();
 429                 return 0;
 430         case OMAP_DSS_VIDEO1:
 431                 return 0x0548;
 432         case OMAP_DSS_VIDEO2:
 433                 return 0x04C0;
 434         case OMAP_DSS_VIDEO3:
 435                 return 0x0314;
 436         case OMAP_DSS_WB:
 437                 return 0x011C;
 438         default:
 439                 BUG();
 440                 return 0;
 441         }
 442 }
 443
 444 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
 445 {
 446         switch (plane) {
 447         case OMAP_DSS_GFX:
 448         case OMAP_DSS_VIDEO1:
 449         case OMAP_DSS_VIDEO2:
 450                 return 0x0008;
 451         case OMAP_DSS_VIDEO3:
 452                 return 0x009C;
 453         default:
 454                 BUG();
 455                 return 0;
 456         }
 457 }
 458
 459 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
 460 {
 461         switch (plane) {
 462         case OMAP_DSS_GFX:
 463         case OMAP_DSS_VIDEO1:
 464         case OMAP_DSS_VIDEO2:
 465                 return 0x000C;
 466         case OMAP_DSS_VIDEO3:
 467         case OMAP_DSS_WB:
 468                 return 0x00A8;
 469         default:
 470                 BUG();
 471                 return 0;
 472         }
 473 }
 474
 475 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
 476 {
 477         switch (plane) {
 478         case OMAP_DSS_GFX:
 479                 return 0x0020;
 480         case OMAP_DSS_VIDEO1:
 481         case OMAP_DSS_VIDEO2:
 482                 return 0x0010;
 483         case OMAP_DSS_VIDEO3:
 484         case OMAP_DSS_WB:
 485                 return 0x0070;
 486         default:
 487                 BUG();
 488                 return 0;
 489         }
 490 }
 491
 492 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
 493 {
 494         switch (plane) {
 495         case OMAP_DSS_GFX:
 496                 BUG();
 497                 return 0;
 498         case OMAP_DSS_VIDEO1:
 499                 return 0x0568;
 500         case OMAP_DSS_VIDEO2:
 501                 return 0x04DC;
 502         case OMAP_DSS_VIDEO3:
 503                 return 0x032C;
 504         case OMAP_DSS_WB:
 505                 return 0x0310;
 506         default:
 507                 BUG();
 508                 return 0;
 509         }
 510 }
 511
 512 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
 513 {
 514         switch (plane) {
 515         case OMAP_DSS_GFX:
 516                 return 0x0024;
 517         case OMAP_DSS_VIDEO1:
 518         case OMAP_DSS_VIDEO2:
 519                 return 0x0014;
 520         case OMAP_DSS_VIDEO3:
 521         case OMAP_DSS_WB:
 522                 return 0x008C;
 523         default:
 524                 BUG();
 525                 return 0;
 526         }
 527 }
 528
 529 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
 530 {
 531         switch (plane) {
 532         case OMAP_DSS_GFX:
 533                 return 0x0028;
 534         case OMAP_DSS_VIDEO1:
 535         case OMAP_DSS_VIDEO2:
 536                 return 0x0018;
 537         case OMAP_DSS_VIDEO3:
 538         case OMAP_DSS_WB:
 539                 return 0x0088;
 540         default:
 541                 BUG();
 542                 return 0;
 543         }
 544 }
 545
 546 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
 547 {
 548         switch (plane) {
 549         case OMAP_DSS_GFX:
 550                 return 0x002C;
 551         case OMAP_DSS_VIDEO1:
 552         case OMAP_DSS_VIDEO2:
 553                 return 0x001C;
 554         case OMAP_DSS_VIDEO3:
 555         case OMAP_DSS_WB:
 556                 return 0x00A4;
 557         default:
 558                 BUG();
 559                 return 0;
 560         }
 561 }
 562
 563 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
 564 {
 565         switch (plane) {
 566         case OMAP_DSS_GFX:
 567                 return 0x0030;
 568         case OMAP_DSS_VIDEO1:
 569         case OMAP_DSS_VIDEO2:
 570                 return 0x0020;
 571         case OMAP_DSS_VIDEO3:
 572         case OMAP_DSS_WB:
 573                 return 0x0098;
 574         default:
 575                 BUG();
 576                 return 0;
 577         }
 578 }
 579
 580 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
 581 {
 582         switch (plane) {
 583         case OMAP_DSS_GFX:
 584                 return 0x0034;
 585         case OMAP_DSS_VIDEO1:
 586         case OMAP_DSS_VIDEO2:
 587         case OMAP_DSS_VIDEO3:
 588                 BUG();
 589                 return 0;
 590         default:
 591                 BUG();
 592                 return 0;
 593         }
 594 }
 595
 596 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
 597 {
 598         switch (plane) {
 599         case OMAP_DSS_GFX:
 600                 return 0x0038;
 601         case OMAP_DSS_VIDEO1:
 602         case OMAP_DSS_VIDEO2:
 603         case OMAP_DSS_VIDEO3:
 604                 BUG();
 605                 return 0;
 606         default:
 607                 BUG();
 608                 return 0;
 609         }
 610 }
 611
 612 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
 613 {
 614         switch (plane) {
 615         case OMAP_DSS_GFX:
 616                 BUG();
 617                 return 0;
 618         case OMAP_DSS_VIDEO1:
 619         case OMAP_DSS_VIDEO2:
 620                 return 0x0024;
 621         case OMAP_DSS_VIDEO3:
 622         case OMAP_DSS_WB:
 623                 return 0x0090;
 624         default:
 625                 BUG();
 626                 return 0;
 627         }
 628 }
 629
 630 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
 631 {
 632         switch (plane) {
 633         case OMAP_DSS_GFX:
 634                 BUG();
 635                 return 0;
 636         case OMAP_DSS_VIDEO1:
 637                 return 0x0580;
 638         case OMAP_DSS_VIDEO2:
 639                 return 0x055C;
 640         case OMAP_DSS_VIDEO3:
 641                 return 0x0424;
 642         case OMAP_DSS_WB:
 643                 return 0x290;
 644         default:
 645                 BUG();
 646                 return 0;
 647         }
 648 }
 649
 650 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
 651 {
 652         switch (plane) {
 653         case OMAP_DSS_GFX:
 654                 BUG();
 655                 return 0;
 656         case OMAP_DSS_VIDEO1:
 657         case OMAP_DSS_VIDEO2:
 658                 return 0x0028;
 659         case OMAP_DSS_VIDEO3:
 660         case OMAP_DSS_WB:
 661                 return 0x0094;
 662         default:
 663                 BUG();
 664                 return 0;
 665         }
 666 }
 667
 668
 669 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
 670 {
 671         switch (plane) {
 672         case OMAP_DSS_GFX:
 673                 BUG();
 674                 return 0;
 675         case OMAP_DSS_VIDEO1:
 676         case OMAP_DSS_VIDEO2:
 677                 return 0x002C;
 678         case OMAP_DSS_VIDEO3:
 679         case OMAP_DSS_WB:
 680                 return 0x0000;
 681         default:
 682                 BUG();
 683                 return 0;
 684         }
 685 }
 686
 687 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
 688 {
 689         switch (plane) {
 690         case OMAP_DSS_GFX:
 691                 BUG();
 692                 return 0;
 693         case OMAP_DSS_VIDEO1:
 694                 return 0x0584;
 695         case OMAP_DSS_VIDEO2:
 696                 return 0x0560;
 697         case OMAP_DSS_VIDEO3:
 698                 return 0x0428;
 699         case OMAP_DSS_WB:
 700                 return 0x0294;
 701         default:
 702                 BUG();
 703                 return 0;
 704         }
 705 }
 706
 707 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
 708 {
 709         switch (plane) {
 710         case OMAP_DSS_GFX:
 711                 BUG();
 712                 return 0;
 713         case OMAP_DSS_VIDEO1:
 714         case OMAP_DSS_VIDEO2:
 715                 return 0x0030;
 716         case OMAP_DSS_VIDEO3:
 717         case OMAP_DSS_WB:
 718                 return 0x0004;
 719         default:
 720                 BUG();
 721                 return 0;
 722         }
 723 }
 724
 725 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
 726 {
 727         switch (plane) {
 728         case OMAP_DSS_GFX:
 729                 BUG();
 730                 return 0;
 731         case OMAP_DSS_VIDEO1:
 732                 return 0x0588;
 733         case OMAP_DSS_VIDEO2:
 734                 return 0x0564;
 735         case OMAP_DSS_VIDEO3:
 736                 return 0x042C;
 737         case OMAP_DSS_WB:
 738                 return 0x0298;
 739         default:
 740                 BUG();
 741                 return 0;
 742         }
 743 }
 744
 745 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 746 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
 747 {
 748         switch (plane) {
 749         case OMAP_DSS_GFX:
 750                 BUG();
 751                 return 0;
 752         case OMAP_DSS_VIDEO1:
 753         case OMAP_DSS_VIDEO2:
 754                 return 0x0034 + i * 0x8;
 755         case OMAP_DSS_VIDEO3:
 756         case OMAP_DSS_WB:
 757                 return 0x0010 + i * 0x8;
 758         default:
 759                 BUG();
 760                 return 0;
 761         }
 762 }
 763
 764 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 765 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
 766 {
 767         switch (plane) {
 768         case OMAP_DSS_GFX:
 769                 BUG();
 770                 return 0;
 771         case OMAP_DSS_VIDEO1:
 772                 return 0x058C + i * 0x8;
 773         case OMAP_DSS_VIDEO2:
 774                 return 0x0568 + i * 0x8;
 775         case OMAP_DSS_VIDEO3:
 776                 return 0x0430 + i * 0x8;
 777         case OMAP_DSS_WB:
 778                 return 0x02A0 + i * 0x8;
 779         default:
 780                 BUG();
 781                 return 0;
 782         }
 783 }
 784
 785 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 786 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
 787 {
 788         switch (plane) {
 789         case OMAP_DSS_GFX:
 790                 BUG();
 791                 return 0;
 792         case OMAP_DSS_VIDEO1:
 793         case OMAP_DSS_VIDEO2:
 794                 return 0x0038 + i * 0x8;
 795         case OMAP_DSS_VIDEO3:
 796         case OMAP_DSS_WB:
 797                 return 0x0014 + i * 0x8;
 798         default:
 799                 BUG();
 800                 return 0;
 801         }
 802 }
 803
 804 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 805 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
 806 {
 807         switch (plane) {
 808         case OMAP_DSS_GFX:
 809                 BUG();
 810                 return 0;
 811         case OMAP_DSS_VIDEO1:
 812                 return 0x0590 + i * 8;
 813         case OMAP_DSS_VIDEO2:
 814                 return 0x056C + i * 0x8;
 815         case OMAP_DSS_VIDEO3:
 816                 return 0x0434 + i * 0x8;
 817         case OMAP_DSS_WB:
 818                 return 0x02A4 + i * 0x8;
 819         default:
 820                 BUG();
 821                 return 0;
 822         }
 823 }
 824
 825 /* coef index i = {0, 1, 2, 3, 4,} */
 826 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
 827 {
 828         switch (plane) {
 829         case OMAP_DSS_GFX:
 830                 BUG();
 831                 return 0;
 832         case OMAP_DSS_VIDEO1:
 833         case OMAP_DSS_VIDEO2:
 834         case OMAP_DSS_VIDEO3:
 835         case OMAP_DSS_WB:
 836                 return 0x0074 + i * 0x4;
 837         default:
 838                 BUG();
 839                 return 0;
 840         }
 841 }
 842
 843 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 844 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
 845 {
 846         switch (plane) {
 847         case OMAP_DSS_GFX:
 848                 BUG();
 849                 return 0;
 850         case OMAP_DSS_VIDEO1:
 851                 return 0x0124 + i * 0x4;
 852         case OMAP_DSS_VIDEO2:
 853                 return 0x00B4 + i * 0x4;
 854         case OMAP_DSS_VIDEO3:
 855         case OMAP_DSS_WB:
 856                 return 0x0050 + i * 0x4;
 857         default:
 858                 BUG();
 859                 return 0;
 860         }
 861 }
 862
 863 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 864 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
 865 {
 866         switch (plane) {
 867         case OMAP_DSS_GFX:
 868                 BUG();
 869                 return 0;
 870         case OMAP_DSS_VIDEO1:
 871                 return 0x05CC + i * 0x4;
 872         case OMAP_DSS_VIDEO2:
 873                 return 0x05A8 + i * 0x4;
 874         case OMAP_DSS_VIDEO3:
 875                 return 0x0470 + i * 0x4;
 876         case OMAP_DSS_WB:
 877                 return 0x02E0 + i * 0x4;
 878         default:
 879                 BUG();
 880                 return 0;
 881         }
 882 }
 883
 884 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
 885 {
 886         switch (plane) {
 887         case OMAP_DSS_GFX:
 888                 return 0x01AC;
 889         case OMAP_DSS_VIDEO1:
 890                 return 0x0174;
 891         case OMAP_DSS_VIDEO2:
 892                 return 0x00E8;
 893         case OMAP_DSS_VIDEO3:
 894                 return 0x00A0;
 895         default:
 896                 BUG();
 897                 return 0;
 898         }
 899 }
 900
 901 static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane)
 902 {
 903         switch (plane) {
 904         case OMAP_DSS_GFX:
 905                 return 0x0860;
 906         case OMAP_DSS_VIDEO1:
 907                 return 0x0864;
 908         case OMAP_DSS_VIDEO2:
 909                 return 0x0868;
 910         case OMAP_DSS_VIDEO3:
 911                 return 0x086c;
 912         default:
 913                 BUG();
 914                 return 0;
 915         }
 916 }
 917 #endif