drivers/video/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #include <linux/interrupt.h>
  27
  28 #ifdef pr_fmt
  29 #undef pr_fmt
  30 #endif
  31
  32 #ifdef DSS_SUBSYS_NAME
  33 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
  34 #else
  35 #define pr_fmt(fmt) fmt
  36 #endif
  37
  38 #define DSSDBG(format, ...) \
  39         pr_debug(format, ## __VA_ARGS__)
  40
  41 #ifdef DSS_SUBSYS_NAME
  42 #define DSSERR(format, ...) \
  43         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  44         ## __VA_ARGS__)
  45 #else
  46 #define DSSERR(format, ...) \
  47         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  48 #endif
  49
  50 #ifdef DSS_SUBSYS_NAME
  51 #define DSSINFO(format, ...) \
  52         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  53         ## __VA_ARGS__)
  54 #else
  55 #define DSSINFO(format, ...) \
  56         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  57 #endif
  58
  59 #ifdef DSS_SUBSYS_NAME
  60 #define DSSWARN(format, ...) \
  61         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  62         ## __VA_ARGS__)
  63 #else
  64 #define DSSWARN(format, ...) \
  65         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  66 #endif
  67
  68 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  69    number. For example 7:0 */
  70 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  71 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  72 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  73 #define FLD_MOD(orig, val, start, end) \
  74         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  75
  76 enum dss_io_pad_mode {
  77         DSS_IO_PAD_MODE_RESET,
  78         DSS_IO_PAD_MODE_RFBI,
  79         DSS_IO_PAD_MODE_BYPASS,
  80 };
  81
  82 enum dss_hdmi_venc_clk_source_select {
  83         DSS_VENC_TV_CLK = 0,
  84         DSS_HDMI_M_PCLK = 1,
  85 };
  86
  87 enum dss_dsi_content_type {
  88         DSS_DSI_CONTENT_DCS,
  89         DSS_DSI_CONTENT_GENERIC,
  90 };
  91
  92 enum dss_writeback_channel {
  93         DSS_WB_LCD1_MGR =       0,
  94         DSS_WB_LCD2_MGR =       1,
  95         DSS_WB_TV_MGR =         2,
  96         DSS_WB_OVL0 =           3,
  97         DSS_WB_OVL1 =           4,
  98         DSS_WB_OVL2 =           5,
  99         DSS_WB_OVL3 =           6,
 100         DSS_WB_LCD3_MGR =       7,
 101 };
 102
 103 struct dispc_clock_info {
 104         /* rates that we get with dividers below */
 105         unsigned long lck;
 106         unsigned long pck;
 107
 108         /* dividers */
 109         u16 lck_div;
 110         u16 pck_div;
 111 };
 112
 113 struct dsi_clock_info {
 114         /* rates that we get with dividers below */
 115         unsigned long fint;
 116         unsigned long clkin4ddr;
 117         unsigned long clkin;
 118         unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
 119                                                  * OMAP4: PLLx_CLK1 */
 120         unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
 121                                                  * OMAP4: PLLx_CLK2 */
 122         unsigned long lp_clk;
 123
 124         /* dividers */
 125         u16 regn;
 126         u16 regm;
 127         u16 regm_dispc; /* OMAP3: REGM3
 128                          * OMAP4: REGM4 */
 129         u16 regm_dsi;   /* OMAP3: REGM4
 130                          * OMAP4: REGM5 */
 131         u16 lp_clk_div;
 132 };
 133
 134 struct reg_field {
 135         u16 reg;
 136         u8 high;
 137         u8 low;
 138 };
 139
 140 struct dss_lcd_mgr_config {
 141         enum dss_io_pad_mode io_pad_mode;
 142
 143         bool stallmode;
 144         bool fifohandcheck;
 145
 146         struct dispc_clock_info clock_info;
 147
 148         int video_port_width;
 149
 150         int lcden_sig_polarity;
 151 };
 152
 153 struct seq_file;
 154 struct platform_device;
 155
 156 /* core */
 157 struct platform_device *dss_get_core_pdev(void);
 158 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
 159 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
 160 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
 161 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
 162
 163 /* display */
 164 int dss_suspend_all_devices(void);
 165 int dss_resume_all_devices(void);
 166 void dss_disable_all_devices(void);
 167
 168 int display_init_sysfs(struct platform_device *pdev);
 169 void display_uninit_sysfs(struct platform_device *pdev);
 170
 171 /* manager */
 172 int dss_init_overlay_managers(void);
 173 void dss_uninit_overlay_managers(void);
 174 int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
 175 void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
 176 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
 177                 const struct omap_overlay_manager_info *info);
 178 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
 179                 const struct omap_video_timings *timings);
 180 int dss_mgr_check(struct omap_overlay_manager *mgr,
 181                 struct omap_overlay_manager_info *info,
 182                 const struct omap_video_timings *mgr_timings,
 183                 const struct dss_lcd_mgr_config *config,
 184                 struct omap_overlay_info **overlay_infos);
 185
 186 static inline bool dss_mgr_is_lcd(enum omap_channel id)
 187 {
 188         if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
 189                         id == OMAP_DSS_CHANNEL_LCD3)
 190                 return true;
 191         else
 192                 return false;
 193 }
 194
 195 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
 196                 struct platform_device *pdev);
 197 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
 198
 199 /* overlay */
 200 void dss_init_overlays(struct platform_device *pdev);
 201 void dss_uninit_overlays(struct platform_device *pdev);
 202 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 203 int dss_ovl_simple_check(struct omap_overlay *ovl,
 204                 const struct omap_overlay_info *info);
 205 int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
 206                 const struct omap_video_timings *mgr_timings);
 207 bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
 208                 enum omap_color_mode mode);
 209 int dss_overlay_kobj_init(struct omap_overlay *ovl,
 210                 struct platform_device *pdev);
 211 void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
 212
 213 /* DSS */
 214 int dss_init_platform_driver(void) __init;
 215 void dss_uninit_platform_driver(void);
 216
 217 unsigned long dss_get_dispc_clk_rate(void);
 218 int dss_dpi_select_source(enum omap_channel channel);
 219 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 220 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
 221 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 222 void dss_dump_clocks(struct seq_file *s);
 223
 224 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
 225 void dss_debug_dump_clocks(struct seq_file *s);
 226 #endif
 227
 228 int dss_get_ctx_loss_count(void);
 229
 230 void dss_sdi_init(int datapairs);
 231 int dss_sdi_enable(void);
 232 void dss_sdi_disable(void);
 233
 234 void dss_select_dsi_clk_source(int dsi_module,
 235                 enum omap_dss_clk_source clk_src);
 236 void dss_select_lcd_clk_source(enum omap_channel channel,
 237                 enum omap_dss_clk_source clk_src);
 238 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 239 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 240 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 241
 242 void dss_set_venc_output(enum omap_dss_venc_type type);
 243 void dss_set_dac_pwrdn_bgz(bool enable);
 244
 245 int dss_set_fck_rate(unsigned long rate);
 246
 247 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
 248 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
 249                 dss_div_calc_func func, void *data);
 250
 251 /* SDI */
 252 int sdi_init_platform_driver(void) __init;
 253 void sdi_uninit_platform_driver(void) __exit;
 254
 255 /* DSI */
 256
 257 typedef bool (*dsi_pll_calc_func)(int regn, int regm, unsigned long fint,
 258                 unsigned long pll, void *data);
 259 typedef bool (*dsi_hsdiv_calc_func)(int regm_dispc, unsigned long dispc,
 260                 void *data);
 261
 262 #ifdef CONFIG_OMAP2_DSS_DSI
 263
 264 struct dentry;
 265 struct file_operations;
 266
 267 int dsi_init_platform_driver(void) __init;
 268 void dsi_uninit_platform_driver(void) __exit;
 269
 270 int dsi_runtime_get(struct platform_device *dsidev);
 271 void dsi_runtime_put(struct platform_device *dsidev);
 272
 273 void dsi_dump_clocks(struct seq_file *s);
 274
 275 void dsi_irq_handler(void);
 276 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
 277
 278 unsigned long dsi_get_pll_clkin(struct platform_device *dsidev);
 279
 280 bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
 281                 unsigned long out_min, dsi_hsdiv_calc_func func, void *data);
 282 bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
 283                 unsigned long pll_min, unsigned long pll_max,
 284                 dsi_pll_calc_func func, void *data);
 285
 286 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
 287 int dsi_pll_set_clock_div(struct platform_device *dsidev,
 288                 struct dsi_clock_info *cinfo);
 289 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
 290                 bool enable_hsdiv);
 291 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
 292 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
 293 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
 294 struct platform_device *dsi_get_dsidev_from_id(int module);
 295 #else
 296 static inline int dsi_runtime_get(struct platform_device *dsidev)
 297 {
 298         return 0;
 299 }
 300 static inline void dsi_runtime_put(struct platform_device *dsidev)
 301 {
 302 }
 303 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 304 {
 305         WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
 306         return 0;
 307 }
 308 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
 309 {
 310         WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
 311         return 0;
 312 }
 313 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
 314                 struct dsi_clock_info *cinfo)
 315 {
 316         WARN("%s: DSI not compiled in\n", __func__);
 317         return -ENODEV;
 318 }
 319 static inline int dsi_pll_init(struct platform_device *dsidev,
 320                 bool enable_hsclk, bool enable_hsdiv)
 321 {
 322         WARN("%s: DSI not compiled in\n", __func__);
 323         return -ENODEV;
 324 }
 325 static inline void dsi_pll_uninit(struct platform_device *dsidev,
 326                 bool disconnect_lanes)
 327 {
 328 }
 329 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
 330 {
 331 }
 332 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
 333 {
 334 }
 335 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
 336 {
 337         return NULL;
 338 }
 339
 340 static inline unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
 341 {
 342         return 0;
 343 }
 344
 345 static inline bool dsi_hsdiv_calc(struct platform_device *dsidev,
 346                 unsigned long pll, unsigned long out_min,
 347                 dsi_hsdiv_calc_func func, void *data)
 348 {
 349         return false;
 350 }
 351
 352 static inline bool dsi_pll_calc(struct platform_device *dsidev,
 353                 unsigned long clkin,
 354                 unsigned long pll_min, unsigned long pll_max,
 355                 dsi_pll_calc_func func, void *data)
 356 {
 357         return false;
 358 }
 359
 360 #endif
 361
 362 /* DPI */
 363 int dpi_init_platform_driver(void) __init;
 364 void dpi_uninit_platform_driver(void) __exit;
 365
 366 /* DISPC */
 367 int dispc_init_platform_driver(void) __init;
 368 void dispc_uninit_platform_driver(void) __exit;
 369 void dispc_dump_clocks(struct seq_file *s);
 370
 371 void dispc_enable_sidle(void);
 372 void dispc_disable_sidle(void);
 373
 374 void dispc_lcd_enable_signal(bool enable);
 375 void dispc_pck_free_enable(bool enable);
 376 void dispc_enable_fifomerge(bool enable);
 377 void dispc_enable_gamma_table(bool enable);
 378 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 379
 380 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
 381                 unsigned long pck, void *data);
 382 bool dispc_div_calc(unsigned long dispc,
 383                 unsigned long pck_min, unsigned long pck_max,
 384                 dispc_div_calc_func func, void *data);
 385
 386 bool dispc_mgr_timings_ok(enum omap_channel channel,
 387                 const struct omap_video_timings *timings);
 388 unsigned long dispc_fclk_rate(void);
 389 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 390                 struct dispc_clock_info *cinfo);
 391
 392
 393 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
 394 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
 395                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
 396                 bool manual_update);
 397
 398 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 399 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 400 unsigned long dispc_core_clk_rate(void);
 401 void dispc_mgr_set_clock_div(enum omap_channel channel,
 402                 const struct dispc_clock_info *cinfo);
 403 int dispc_mgr_get_clock_div(enum omap_channel channel,
 404                 struct dispc_clock_info *cinfo);
 405 void dispc_set_tv_pclk(unsigned long pclk);
 406
 407 u32 dispc_wb_get_framedone_irq(void);
 408 bool dispc_wb_go_busy(void);
 409 void dispc_wb_go(void);
 410 void dispc_wb_enable(bool enable);
 411 bool dispc_wb_is_enabled(void);
 412 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
 413 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
 414                 bool mem_to_mem, const struct omap_video_timings *timings);
 415
 416 /* VENC */
 417 int venc_init_platform_driver(void) __init;
 418 void venc_uninit_platform_driver(void) __exit;
 419
 420 /* HDMI */
 421 int hdmi4_init_platform_driver(void) __init;
 422 void hdmi4_uninit_platform_driver(void) __exit;
 423
 424 /* RFBI */
 425 int rfbi_init_platform_driver(void) __init;
 426 void rfbi_uninit_platform_driver(void) __exit;
 427
 428
 429 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 430 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 431 {
 432         int b;
 433         for (b = 0; b < 32; ++b) {
 434                 if (irqstatus & (1 << b))
 435                         irq_arr[b]++;
 436         }
 437 }
 438 #endif
 439
 440 #endif