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PM / sleep: Make pm_prepare_console() return void
[linux/fpc-iii.git] / drivers / pci / host / pcie-designware.c
blobaafd766546f38737d3845339944bbaee29883ec5
1 /*
2 * Synopsys Designware PCIe host controller driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/pci_regs.h>
23 #include <linux/platform_device.h>
24 #include <linux/types.h>
25 #include <linux/delay.h>
26
27 #include "pcie-designware.h"
28
29 /* Synopsis specific PCIE configuration registers */
30 #define PCIE_PORT_LINK_CONTROL 0x710
31 #define PORT_LINK_MODE_MASK (0x3f << 16)
32 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
33 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
34 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
35 #define PORT_LINK_MODE_8_LANES (0xf << 16)
36
37 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
38 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
39 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
40 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
41 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
42 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
43 #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
44
45 #define PCIE_MSI_ADDR_LO 0x820
46 #define PCIE_MSI_ADDR_HI 0x824
47 #define PCIE_MSI_INTR0_ENABLE 0x828
48 #define PCIE_MSI_INTR0_MASK 0x82C
49 #define PCIE_MSI_INTR0_STATUS 0x830
50
51 #define PCIE_ATU_VIEWPORT 0x900
52 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
53 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
54 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
55 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
56 #define PCIE_ATU_CR1 0x904
57 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
58 #define PCIE_ATU_TYPE_IO (0x2 << 0)
59 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
60 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
61 #define PCIE_ATU_CR2 0x908
62 #define PCIE_ATU_ENABLE (0x1 << 31)
63 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
64 #define PCIE_ATU_LOWER_BASE 0x90C
65 #define PCIE_ATU_UPPER_BASE 0x910
66 #define PCIE_ATU_LIMIT 0x914
67 #define PCIE_ATU_LOWER_TARGET 0x918
68 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
69 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
70 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
71 #define PCIE_ATU_UPPER_TARGET 0x91C
72
73 /* PCIe Port Logic registers */
74 #define PLR_OFFSET 0x700
75 #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
76 #define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
77
78 static struct pci_ops dw_pcie_ops;
79
80 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
81 {
82 if ((uintptr_t)addr & (size - 1)) {
83 *val = 0;
84 return PCIBIOS_BAD_REGISTER_NUMBER;
85 }
86
87 if (size == 4)
88 *val = readl(addr);
89 else if (size == 2)
90 *val = readw(addr);
91 else if (size == 1)
92 *val = readb(addr);
93 else {
94 *val = 0;
95 return PCIBIOS_BAD_REGISTER_NUMBER;
96 }
97
98 return PCIBIOS_SUCCESSFUL;
99 }
100
101 int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
102 {
103 if ((uintptr_t)addr & (size - 1))
104 return PCIBIOS_BAD_REGISTER_NUMBER;
105
106 if (size == 4)
107 writel(val, addr);
108 else if (size == 2)
109 writew(val, addr);
110 else if (size == 1)
111 writeb(val, addr);
112 else
113 return PCIBIOS_BAD_REGISTER_NUMBER;
114
115 return PCIBIOS_SUCCESSFUL;
116 }
117
118 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
119 {
120 if (pp->ops->readl_rc)
121 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
122 else
123 *val = readl(pp->dbi_base + reg);
124 }
125
126 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
127 {
128 if (pp->ops->writel_rc)
129 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
130 else
131 writel(val, pp->dbi_base + reg);
132 }
133
134 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
135 u32 *val)
136 {
137 if (pp->ops->rd_own_conf)
138 return pp->ops->rd_own_conf(pp, where, size, val);
139
140 return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
141 }
142
143 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
144 u32 val)
145 {
146 if (pp->ops->wr_own_conf)
147 return pp->ops->wr_own_conf(pp, where, size, val);
148
149 return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
150 }
151
152 static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
153 int type, u64 cpu_addr, u64 pci_addr, u32 size)
154 {
155 u32 val;
156
157 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
158 PCIE_ATU_VIEWPORT);
159 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
160 dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
161 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
162 PCIE_ATU_LIMIT);
163 dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
164 dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
165 dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
166 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
167
168 /*
169 * Make sure ATU enable takes effect before any subsequent config
170 * and I/O accesses.
171 */
172 dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
173 }
174
175 static struct irq_chip dw_msi_irq_chip = {
176 .name = "PCI-MSI",
177 .irq_enable = pci_msi_unmask_irq,
178 .irq_disable = pci_msi_mask_irq,
179 .irq_mask = pci_msi_mask_irq,
180 .irq_unmask = pci_msi_unmask_irq,
181 };
182
183 /* MSI int handler */
184 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
185 {
186 unsigned long val;
187 int i, pos, irq;
188 irqreturn_t ret = IRQ_NONE;
189
190 for (i = 0; i < MAX_MSI_CTRLS; i++) {
191 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
192 (u32 *)&val);
193 if (val) {
194 ret = IRQ_HANDLED;
195 pos = 0;
196 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
197 irq = irq_find_mapping(pp->irq_domain,
198 i * 32 + pos);
199 dw_pcie_wr_own_conf(pp,
200 PCIE_MSI_INTR0_STATUS + i * 12,
201 4, 1 << pos);
202 generic_handle_irq(irq);
203 pos++;
204 }
205 }
206 }
207
208 return ret;
209 }
210
211 void dw_pcie_msi_init(struct pcie_port *pp)
212 {
213 u64 msi_target;
214
215 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
216 msi_target = virt_to_phys((void *)pp->msi_data);
217
218 /* program the msi_data */
219 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
220 (u32)(msi_target & 0xffffffff));
221 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
222 (u32)(msi_target >> 32 & 0xffffffff));
223 }
224
225 static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
226 {
227 unsigned int res, bit, val;
228
229 res = (irq / 32) * 12;
230 bit = irq % 32;
231 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
232 val &= ~(1 << bit);
233 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
234 }
235
236 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
237 unsigned int nvec, unsigned int pos)
238 {
239 unsigned int i;
240
241 for (i = 0; i < nvec; i++) {
242 irq_set_msi_desc_off(irq_base, i, NULL);
243 /* Disable corresponding interrupt on MSI controller */
244 if (pp->ops->msi_clear_irq)
245 pp->ops->msi_clear_irq(pp, pos + i);
246 else
247 dw_pcie_msi_clear_irq(pp, pos + i);
248 }
249
250 bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
251 }
252
253 static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
254 {
255 unsigned int res, bit, val;
256
257 res = (irq / 32) * 12;
258 bit = irq % 32;
259 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
260 val |= 1 << bit;
261 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
262 }
263
264 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
265 {
266 int irq, pos0, i;
267 struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(desc);
268
269 pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
270 order_base_2(no_irqs));
271 if (pos0 < 0)
272 goto no_valid_irq;
273
274 irq = irq_find_mapping(pp->irq_domain, pos0);
275 if (!irq)
276 goto no_valid_irq;
277
278 /*
279 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
280 * descs so there is no need to allocate descs here. We can therefore
281 * assume that if irq_find_mapping above returns non-zero, then the
282 * descs are also successfully allocated.
283 */
284
285 for (i = 0; i < no_irqs; i++) {
286 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
287 clear_irq_range(pp, irq, i, pos0);
288 goto no_valid_irq;
289 }
290 /*Enable corresponding interrupt in MSI interrupt controller */
291 if (pp->ops->msi_set_irq)
292 pp->ops->msi_set_irq(pp, pos0 + i);
293 else
294 dw_pcie_msi_set_irq(pp, pos0 + i);
295 }
296
297 *pos = pos0;
298 desc->nvec_used = no_irqs;
299 desc->msi_attrib.multiple = order_base_2(no_irqs);
300
301 return irq;
302
303 no_valid_irq:
304 *pos = pos0;
305 return -ENOSPC;
306 }
307
308 static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
309 {
310 struct msi_msg msg;
311 u64 msi_target;
312
313 if (pp->ops->get_msi_addr)
314 msi_target = pp->ops->get_msi_addr(pp);
315 else
316 msi_target = virt_to_phys((void *)pp->msi_data);
317
318 msg.address_lo = (u32)(msi_target & 0xffffffff);
319 msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
320
321 if (pp->ops->get_msi_data)
322 msg.data = pp->ops->get_msi_data(pp, pos);
323 else
324 msg.data = pos;
325
326 pci_write_msi_msg(irq, &msg);
327 }
328
329 static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
330 struct msi_desc *desc)
331 {
332 int irq, pos;
333 struct pcie_port *pp = pdev->bus->sysdata;
334
335 if (desc->msi_attrib.is_msix)
336 return -EINVAL;
337
338 irq = assign_irq(1, desc, &pos);
339 if (irq < 0)
340 return irq;
341
342 dw_msi_setup_msg(pp, irq, pos);
343
344 return 0;
345 }
346
347 static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
348 int nvec, int type)
349 {
350 #ifdef CONFIG_PCI_MSI
351 int irq, pos;
352 struct msi_desc *desc;
353 struct pcie_port *pp = pdev->bus->sysdata;
354
355 /* MSI-X interrupts are not supported */
356 if (type == PCI_CAP_ID_MSIX)
357 return -EINVAL;
358
359 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
360 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
361
362 irq = assign_irq(nvec, desc, &pos);
363 if (irq < 0)
364 return irq;
365
366 dw_msi_setup_msg(pp, irq, pos);
367
368 return 0;
369 #else
370 return -EINVAL;
371 #endif
372 }
373
374 static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
375 {
376 struct irq_data *data = irq_get_irq_data(irq);
377 struct msi_desc *msi = irq_data_get_msi_desc(data);
378 struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
379
380 clear_irq_range(pp, irq, 1, data->hwirq);
381 }
382
383 static struct msi_controller dw_pcie_msi_chip = {
384 .setup_irq = dw_msi_setup_irq,
385 .setup_irqs = dw_msi_setup_irqs,
386 .teardown_irq = dw_msi_teardown_irq,
387 };
388
389 int dw_pcie_wait_for_link(struct pcie_port *pp)
390 {
391 int retries;
392
393 /* check if the link is up or not */
394 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
395 if (dw_pcie_link_up(pp)) {
396 dev_info(pp->dev, "link up\n");
397 return 0;
398 }
399 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
400 }
401
402 dev_err(pp->dev, "phy link never came up\n");
403
404 return -ETIMEDOUT;
405 }
406
407 int dw_pcie_link_up(struct pcie_port *pp)
408 {
409 u32 val;
410
411 if (pp->ops->link_up)
412 return pp->ops->link_up(pp);
413
414 val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
415 return val & PCIE_PHY_DEBUG_R1_LINK_UP;
416 }
417
418 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
419 irq_hw_number_t hwirq)
420 {
421 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
422 irq_set_chip_data(irq, domain->host_data);
423
424 return 0;
425 }
426
427 static const struct irq_domain_ops msi_domain_ops = {
428 .map = dw_pcie_msi_map,
429 };
430
431 int dw_pcie_host_init(struct pcie_port *pp)
432 {
433 struct device_node *np = pp->dev->of_node;
434 struct platform_device *pdev = to_platform_device(pp->dev);
435 struct pci_bus *bus, *child;
436 struct resource *cfg_res;
437 int i, ret;
438 LIST_HEAD(res);
439 struct resource_entry *win;
440
441 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
442 if (cfg_res) {
443 pp->cfg0_size = resource_size(cfg_res)/2;
444 pp->cfg1_size = resource_size(cfg_res)/2;
445 pp->cfg0_base = cfg_res->start;
446 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
447 } else if (!pp->va_cfg0_base) {
448 dev_err(pp->dev, "missing *config* reg space\n");
449 }
450
451 ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
452 if (ret)
453 return ret;
454
455 /* Get the I/O and memory ranges from DT */
456 resource_list_for_each_entry(win, &res) {
457 switch (resource_type(win->res)) {
458 case IORESOURCE_IO:
459 pp->io = win->res;
460 pp->io->name = "I/O";
461 pp->io_size = resource_size(pp->io);
462 pp->io_bus_addr = pp->io->start - win->offset;
463 ret = pci_remap_iospace(pp->io, pp->io_base);
464 if (ret) {
465 dev_warn(pp->dev, "error %d: failed to map resource %pR\n",
466 ret, pp->io);
467 continue;
468 }
469 break;
470 case IORESOURCE_MEM:
471 pp->mem = win->res;
472 pp->mem->name = "MEM";
473 pp->mem_size = resource_size(pp->mem);
474 pp->mem_bus_addr = pp->mem->start - win->offset;
475 break;
476 case 0:
477 pp->cfg = win->res;
478 pp->cfg0_size = resource_size(pp->cfg)/2;
479 pp->cfg1_size = resource_size(pp->cfg)/2;
480 pp->cfg0_base = pp->cfg->start;
481 pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
482 break;
483 case IORESOURCE_BUS:
484 pp->busn = win->res;
485 break;
486 default:
487 continue;
488 }
489 }
490
491 if (!pp->dbi_base) {
492 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start,
493 resource_size(pp->cfg));
494 if (!pp->dbi_base) {
495 dev_err(pp->dev, "error with ioremap\n");
496 return -ENOMEM;
497 }
498 }
499
500 pp->mem_base = pp->mem->start;
501
502 if (!pp->va_cfg0_base) {
503 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
504 pp->cfg0_size);
505 if (!pp->va_cfg0_base) {
506 dev_err(pp->dev, "error with ioremap in function\n");
507 return -ENOMEM;
508 }
509 }
510
511 if (!pp->va_cfg1_base) {
512 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
513 pp->cfg1_size);
514 if (!pp->va_cfg1_base) {
515 dev_err(pp->dev, "error with ioremap\n");
516 return -ENOMEM;
517 }
518 }
519
520 ret = of_property_read_u32(np, "num-lanes", &pp->lanes);
521 if (ret)
522 pp->lanes = 0;
523
524 if (IS_ENABLED(CONFIG_PCI_MSI)) {
525 if (!pp->ops->msi_host_init) {
526 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
527 MAX_MSI_IRQS, &msi_domain_ops,
528 &dw_pcie_msi_chip);
529 if (!pp->irq_domain) {
530 dev_err(pp->dev, "irq domain init failed\n");
531 return -ENXIO;
532 }
533
534 for (i = 0; i < MAX_MSI_IRQS; i++)
535 irq_create_mapping(pp->irq_domain, i);
536 } else {
537 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
538 if (ret < 0)
539 return ret;
540 }
541 }
542
543 if (pp->ops->host_init)
544 pp->ops->host_init(pp);
545
546 pp->root_bus_nr = pp->busn->start;
547 if (IS_ENABLED(CONFIG_PCI_MSI)) {
548 bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
549 &dw_pcie_ops, pp, &res,
550 &dw_pcie_msi_chip);
551 dw_pcie_msi_chip.dev = pp->dev;
552 } else
553 bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops,
554 pp, &res);
555 if (!bus)
556 return -ENOMEM;
557
558 if (pp->ops->scan_bus)
559 pp->ops->scan_bus(pp);
560
561 #ifdef CONFIG_ARM
562 /* support old dtbs that incorrectly describe IRQs */
563 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
564 #endif
565
566 pci_bus_size_bridges(bus);
567 pci_bus_assign_resources(bus);
568
569 list_for_each_entry(child, &bus->children, node)
570 pcie_bus_configure_settings(child);
571
572 pci_bus_add_devices(bus);
573 return 0;
574 }
575
576 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
577 u32 devfn, int where, int size, u32 *val)
578 {
579 int ret, type;
580 u32 busdev, cfg_size;
581 u64 cpu_addr;
582 void __iomem *va_cfg_base;
583
584 if (pp->ops->rd_other_conf)
585 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
586
587 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
588 PCIE_ATU_FUNC(PCI_FUNC(devfn));
589
590 if (bus->parent->number == pp->root_bus_nr) {
591 type = PCIE_ATU_TYPE_CFG0;
592 cpu_addr = pp->cfg0_base;
593 cfg_size = pp->cfg0_size;
594 va_cfg_base = pp->va_cfg0_base;
595 } else {
596 type = PCIE_ATU_TYPE_CFG1;
597 cpu_addr = pp->cfg1_base;
598 cfg_size = pp->cfg1_size;
599 va_cfg_base = pp->va_cfg1_base;
600 }
601
602 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
603 type, cpu_addr,
604 busdev, cfg_size);
605 ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
606 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
607 PCIE_ATU_TYPE_IO, pp->io_base,
608 pp->io_bus_addr, pp->io_size);
609
610 return ret;
611 }
612
613 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
614 u32 devfn, int where, int size, u32 val)
615 {
616 int ret, type;
617 u32 busdev, cfg_size;
618 u64 cpu_addr;
619 void __iomem *va_cfg_base;
620
621 if (pp->ops->wr_other_conf)
622 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
623
624 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
625 PCIE_ATU_FUNC(PCI_FUNC(devfn));
626
627 if (bus->parent->number == pp->root_bus_nr) {
628 type = PCIE_ATU_TYPE_CFG0;
629 cpu_addr = pp->cfg0_base;
630 cfg_size = pp->cfg0_size;
631 va_cfg_base = pp->va_cfg0_base;
632 } else {
633 type = PCIE_ATU_TYPE_CFG1;
634 cpu_addr = pp->cfg1_base;
635 cfg_size = pp->cfg1_size;
636 va_cfg_base = pp->va_cfg1_base;
637 }
638
639 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
640 type, cpu_addr,
641 busdev, cfg_size);
642 ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
643 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
644 PCIE_ATU_TYPE_IO, pp->io_base,
645 pp->io_bus_addr, pp->io_size);
646
647 return ret;
648 }
649
650 static int dw_pcie_valid_config(struct pcie_port *pp,
651 struct pci_bus *bus, int dev)
652 {
653 /* If there is no link, then there is no device */
654 if (bus->number != pp->root_bus_nr) {
655 if (!dw_pcie_link_up(pp))
656 return 0;
657 }
658
659 /* access only one slot on each root port */
660 if (bus->number == pp->root_bus_nr && dev > 0)
661 return 0;
662
663 /*
664 * do not read more than one device on the bus directly attached
665 * to RC's (Virtual Bridge's) DS side.
666 */
667 if (bus->primary == pp->root_bus_nr && dev > 0)
668 return 0;
669
670 return 1;
671 }
672
673 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
674 int size, u32 *val)
675 {
676 struct pcie_port *pp = bus->sysdata;
677
678 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
679 *val = 0xffffffff;
680 return PCIBIOS_DEVICE_NOT_FOUND;
681 }
682
683 if (bus->number == pp->root_bus_nr)
684 return dw_pcie_rd_own_conf(pp, where, size, val);
685
686 return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
687 }
688
689 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
690 int where, int size, u32 val)
691 {
692 struct pcie_port *pp = bus->sysdata;
693
694 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
695 return PCIBIOS_DEVICE_NOT_FOUND;
696
697 if (bus->number == pp->root_bus_nr)
698 return dw_pcie_wr_own_conf(pp, where, size, val);
699
700 return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
701 }
702
703 static struct pci_ops dw_pcie_ops = {
704 .read = dw_pcie_rd_conf,
705 .write = dw_pcie_wr_conf,
706 };
707
708 void dw_pcie_setup_rc(struct pcie_port *pp)
709 {
710 u32 val;
711
712 /* set the number of lanes */
713 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
714 val &= ~PORT_LINK_MODE_MASK;
715 switch (pp->lanes) {
716 case 1:
717 val |= PORT_LINK_MODE_1_LANES;
718 break;
719 case 2:
720 val |= PORT_LINK_MODE_2_LANES;
721 break;
722 case 4:
723 val |= PORT_LINK_MODE_4_LANES;
724 break;
725 case 8:
726 val |= PORT_LINK_MODE_8_LANES;
727 break;
728 default:
729 dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes);
730 return;
731 }
732 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
733
734 /* set link width speed control register */
735 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
736 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
737 switch (pp->lanes) {
738 case 1:
739 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
740 break;
741 case 2:
742 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
743 break;
744 case 4:
745 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
746 break;
747 case 8:
748 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
749 break;
750 }
751 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
752
753 /* setup RC BARs */
754 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
755 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
756
757 /* setup interrupt pins */
758 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
759 val &= 0xffff00ff;
760 val |= 0x00000100;
761 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
762
763 /* setup bus numbers */
764 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
765 val &= 0xff000000;
766 val |= 0x00010100;
767 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
768
769 /* setup command register */
770 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
771 val &= 0xffff0000;
772 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
773 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
774 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
775
776 /*
777 * If the platform provides ->rd_other_conf, it means the platform
778 * uses its own address translation component rather than ATU, so
779 * we should not program the ATU here.
780 */
781 if (!pp->ops->rd_other_conf)
782 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
783 PCIE_ATU_TYPE_MEM, pp->mem_base,
784 pp->mem_bus_addr, pp->mem_size);
785
786 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
787
788 /* program correct class for RC */
789 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
790
791 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
792 val |= PORT_LOGIC_SPEED_CHANGE;
793 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
794 }
795
796 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
797 MODULE_DESCRIPTION("Designware PCIe host controller driver");
798 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support