Staging: remove wusbcore and UWB from the kernel tree.
[linux/fpc-iii.git] / arch / microblaze / kernel / cpu / cpuinfo.c
blobcd9b4450763b0b91ba8152d45f38c48c81d1bd46
1 /*
2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
4 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
11 #include <linux/clk.h>
12 #include <linux/init.h>
13 #include <asm/cpuinfo.h>
14 #include <asm/pvr.h>
16 const struct cpu_ver_key cpu_ver_lookup[] = {
17 /* These key value are as per MBV field in PVR0 */
18 {"5.00.a", 0x01},
19 {"5.00.b", 0x02},
20 {"5.00.c", 0x03},
21 {"6.00.a", 0x04},
22 {"6.00.b", 0x06},
23 {"7.00.a", 0x05},
24 {"7.00.b", 0x07},
25 {"7.10.a", 0x08},
26 {"7.10.b", 0x09},
27 {"7.10.c", 0x0a},
28 {"7.10.d", 0x0b},
29 {"7.20.a", 0x0c},
30 {"7.20.b", 0x0d},
31 {"7.20.c", 0x0e},
32 {"7.20.d", 0x0f},
33 {"7.30.a", 0x10},
34 {"7.30.b", 0x11},
35 {"8.00.a", 0x12},
36 {"8.00.b", 0x13},
37 {"8.10.a", 0x14},
38 {"8.20.a", 0x15},
39 {"8.20.b", 0x16},
40 {"8.30.a", 0x17},
41 {"8.40.a", 0x18},
42 {"8.40.b", 0x19},
43 {"8.50.a", 0x1a},
44 {"8.50.b", 0x1c},
45 {"8.50.c", 0x1e},
46 {"9.0", 0x1b},
47 {"9.1", 0x1d},
48 {"9.2", 0x1f},
49 {"9.3", 0x20},
50 {"9.4", 0x21},
51 {"9.5", 0x22},
52 {"9.6", 0x23},
53 {"10.0", 0x24},
54 {"11.0", 0x25},
55 {NULL, 0},
59 * FIXME Not sure if the actual key is defined by Xilinx in the PVR
61 const struct family_string_key family_string_lookup[] = {
62 {"virtex2", 0x4},
63 {"virtex2pro", 0x5},
64 {"spartan3", 0x6},
65 {"virtex4", 0x7},
66 {"virtex5", 0x8},
67 {"spartan3e", 0x9},
68 {"spartan3a", 0xa},
69 {"spartan3an", 0xb},
70 {"spartan3adsp", 0xc},
71 {"spartan6", 0xd},
72 {"virtex6", 0xe},
73 {"virtex7", 0xf},
74 /* FIXME There is no key code defined for spartan2 */
75 {"spartan2", 0xf0},
76 {"kintex7", 0x10},
77 {"artix7", 0x11},
78 {"zynq7000", 0x12},
79 {"UltraScale Virtex", 0x13},
80 {"UltraScale Kintex", 0x14},
81 {"UltraScale+ Zynq", 0x15},
82 {"UltraScale+ Virtex", 0x16},
83 {"UltraScale+ Kintex", 0x17},
84 {"Spartan7", 0x18},
85 {NULL, 0},
88 struct cpuinfo cpuinfo;
89 static struct device_node *cpu;
91 void __init setup_cpuinfo(void)
93 cpu = of_get_cpu_node(0, NULL);
94 if (!cpu)
95 pr_err("You don't have cpu or are missing cpu reg property!!!\n");
97 pr_info("%s: initialising\n", __func__);
99 switch (cpu_has_pvr()) {
100 case 0:
101 pr_warn("%s: No PVR support. Using static CPU info from FDT\n",
102 __func__);
103 set_cpuinfo_static(&cpuinfo, cpu);
104 break;
105 /* FIXME I found weird behavior with MB 7.00.a/b 7.10.a
106 * please do not use FULL PVR with MMU */
107 case 1:
108 pr_info("%s: Using full CPU PVR support\n",
109 __func__);
110 set_cpuinfo_static(&cpuinfo, cpu);
111 set_cpuinfo_pvr_full(&cpuinfo, cpu);
112 break;
113 default:
114 pr_warn("%s: Unsupported PVR setting\n", __func__);
115 set_cpuinfo_static(&cpuinfo, cpu);
118 if (cpuinfo.mmu_privins)
119 pr_warn("%s: Stream instructions enabled"
120 " - USERSPACE CAN LOCK THIS KERNEL!\n", __func__);
122 of_node_put(cpu);
125 void __init setup_cpuinfo_clk(void)
127 struct clk *clk;
129 clk = of_clk_get(cpu, 0);
130 if (IS_ERR(clk)) {
131 pr_err("ERROR: CPU CCF input clock not found\n");
132 /* take timebase-frequency from DTS */
133 cpuinfo.cpu_clock_freq = fcpu(cpu, "timebase-frequency");
134 } else {
135 cpuinfo.cpu_clock_freq = clk_get_rate(clk);
138 if (!cpuinfo.cpu_clock_freq) {
139 pr_err("ERROR: CPU clock frequency not setup\n");
140 BUG();