include/asm-m32r/smp.h

   1 #ifndef _ASM_M32R_SMP_H
   2 #define _ASM_M32R_SMP_H
   3
   4 /* $Id$ */
   5
   6 #include <linux/config.h>
   7
   8 #ifdef CONFIG_SMP
   9 #ifndef __ASSEMBLY__
  10
  11 #include <linux/cpumask.h>
  12 #include <linux/spinlock.h>
  13 #include <linux/threads.h>
  14 #include <asm/m32r.h>
  15
  16 #define PHYSID_ARRAY_SIZE       1
  17
  18 struct physid_mask
  19 {
  20         unsigned long mask[PHYSID_ARRAY_SIZE];
  21 };
  22
  23 typedef struct physid_mask physid_mask_t;
  24
  25 #define physid_set(physid, map)                 set_bit(physid, (map).mask)
  26 #define physid_clear(physid, map)               clear_bit(physid, (map).mask)
  27 #define physid_isset(physid, map)               test_bit(physid, (map).mask)
  28 #define physid_test_and_set(physid, map)        test_and_set_bit(physid, (map).mask)
  29
  30 #define physids_and(dst, src1, src2)            bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
  31 #define physids_or(dst, src1, src2)             bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
  32 #define physids_clear(map)                      bitmap_zero((map).mask, MAX_APICS)
  33 #define physids_complement(dst, src)            bitmap_complement((dst).mask,(src).mask, MAX_APICS)
  34 #define physids_empty(map)                      bitmap_empty((map).mask, MAX_APICS)
  35 #define physids_equal(map1, map2)               bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
  36 #define physids_weight(map)                     bitmap_weight((map).mask, MAX_APICS)
  37 #define physids_shift_right(d, s, n)            bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
  38 #define physids_shift_left(d, s, n)             bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
  39 #define physids_coerce(map)                     ((map).mask[0])
  40
  41 #define physids_promote(physids)                                        \
  42         ({                                                              \
  43                 physid_mask_t __physid_mask = PHYSID_MASK_NONE;         \
  44                 __physid_mask.mask[0] = physids;                        \
  45                 __physid_mask;                                          \
  46         })
  47
  48 #define physid_mask_of_physid(physid)                                   \
  49         ({                                                              \
  50                 physid_mask_t __physid_mask = PHYSID_MASK_NONE;         \
  51                 physid_set(physid, __physid_mask);                      \
  52                 __physid_mask;                                          \
  53         })
  54
  55 #define PHYSID_MASK_ALL         { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
  56 #define PHYSID_MASK_NONE        { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
  57
  58 extern physid_mask_t phys_cpu_present_map;
  59
  60 /*
  61  * Some lowlevel functions might want to know about
  62  * the real CPU ID <-> CPU # mapping.
  63  */
  64 extern volatile int physid_2_cpu[NR_CPUS];
  65 extern volatile int cpu_2_physid[NR_CPUS];
  66 #define physid_to_cpu(physid)   physid_2_cpu[physid]
  67 #define cpu_to_physid(cpu_id)   cpu_2_physid[cpu_id]
  68
  69 #define raw_smp_processor_id()  (current_thread_info()->cpu)
  70
  71 extern cpumask_t cpu_callout_map;
  72 #define cpu_possible_map cpu_callout_map
  73
  74 static __inline__ int hard_smp_processor_id(void)
  75 {
  76         return (int)*(volatile long *)M32R_CPUID_PORTL;
  77 }
  78
  79 static __inline__ int cpu_logical_map(int cpu)
  80 {
  81         return cpu;
  82 }
  83
  84 static __inline__ int cpu_number_map(int cpu)
  85 {
  86         return cpu;
  87 }
  88
  89 static __inline__ unsigned int num_booting_cpus(void)
  90 {
  91         return cpus_weight(cpu_callout_map);
  92 }
  93
  94 extern void smp_send_timer(void);
  95 extern unsigned long send_IPI_mask_phys(cpumask_t, int, int);
  96
  97 #endif  /* not __ASSEMBLY__ */
  98
  99 #define NO_PROC_ID (0xff)       /* No processor magic marker */
 100
 101 #define PROC_CHANGE_PENALTY     (15)    /* Schedule penalty */
 102
 103 /*
 104  * M32R-mp IPI
 105  */
 106 #define RESCHEDULE_IPI          (M32R_IRQ_IPI0-M32R_IRQ_IPI0)
 107 #define INVALIDATE_TLB_IPI      (M32R_IRQ_IPI1-M32R_IRQ_IPI0)
 108 #define CALL_FUNCTION_IPI       (M32R_IRQ_IPI2-M32R_IRQ_IPI0)
 109 #define LOCAL_TIMER_IPI         (M32R_IRQ_IPI3-M32R_IRQ_IPI0)
 110 #define INVALIDATE_CACHE_IPI    (M32R_IRQ_IPI4-M32R_IRQ_IPI0)
 111 #define CPU_BOOT_IPI            (M32R_IRQ_IPI5-M32R_IRQ_IPI0)
 112
 113 #define IPI_SHIFT       (0)
 114 #define NR_IPIS         (8)
 115
 116 #endif  /* CONFIG_SMP */
 117
 118 #endif  /* _ASM_M32R_SMP_H */