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usb: fsl_udc_core: Fix scheduling while atomic dump message
[linux/fpc-iii.git] / drivers / usb / gadget / fsl_udc_core.c
blob530838103d485ea283ba66e404a7a15fa3897e78
1 /*
2 * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * Author: Li Yang <leoli@freescale.com>
6 * Jiang Bo <tanya.jiang@freescale.com>
7 *
8 * Description:
9 * Freescale high-speed USB SOC DR module device controller driver.
10 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
11 * The driver is previously named as mpc_udc. Based on bare board
12 * code from Dave Liu and Shlomi Gridish.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20 #undef VERBOSE
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/ioport.h>
25 #include <linux/types.h>
26 #include <linux/errno.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/list.h>
30 #include <linux/interrupt.h>
31 #include <linux/proc_fs.h>
32 #include <linux/mm.h>
33 #include <linux/moduleparam.h>
34 #include <linux/device.h>
35 #include <linux/usb/ch9.h>
36 #include <linux/usb/gadget.h>
37 #include <linux/usb/otg.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/platform_device.h>
40 #include <linux/fsl_devices.h>
41 #include <linux/dmapool.h>
42 #include <linux/delay.h>
43
44 #include <asm/byteorder.h>
45 #include <asm/io.h>
46 #include <asm/system.h>
47 #include <asm/unaligned.h>
48 #include <asm/dma.h>
49
50 #include "fsl_usb2_udc.h"
51
52 #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
53 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
54 #define DRIVER_VERSION "Apr 20, 2007"
55
56 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
57
58 static const char driver_name[] = "fsl-usb2-udc";
59 static const char driver_desc[] = DRIVER_DESC;
60
61 static struct usb_dr_device *dr_regs;
62 #ifndef CONFIG_ARCH_MXC
63 static struct usb_sys_interface *usb_sys_regs;
64 #endif
65
66 /* it is initialized in probe() */
67 static struct fsl_udc *udc_controller = NULL;
68
69 static const struct usb_endpoint_descriptor
70 fsl_ep0_desc = {
71 .bLength = USB_DT_ENDPOINT_SIZE,
72 .bDescriptorType = USB_DT_ENDPOINT,
73 .bEndpointAddress = 0,
74 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
75 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
76 };
77
78 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
79
80 #ifdef CONFIG_PPC32
81 /*
82 * On some SoCs, the USB controller registers can be big or little endian,
83 * depending on the version of the chip. In order to be able to run the
84 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
85 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
86 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
87 * call through those pointers. Platform code for SoCs that have BE USB
88 * registers should set pdata->big_endian_mmio flag.
89 *
90 * This also applies to controller-to-cpu accessors for the USB descriptors,
91 * since their endianness is also SoC dependant. Platform code for SoCs that
92 * have BE USB descriptors should set pdata->big_endian_desc flag.
93 */
94 static u32 _fsl_readl_be(const unsigned __iomem *p)
95 {
96 return in_be32(p);
97 }
98
99 static u32 _fsl_readl_le(const unsigned __iomem *p)
100 {
101 return in_le32(p);
102 }
103
104 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
105 {
106 out_be32(p, v);
107 }
108
109 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
110 {
111 out_le32(p, v);
112 }
113
114 static u32 (*_fsl_readl)(const unsigned __iomem *p);
115 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
116
117 #define fsl_readl(p) (*_fsl_readl)((p))
118 #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
119
120 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
121 {
122 if (pdata->big_endian_mmio) {
123 _fsl_readl = _fsl_readl_be;
124 _fsl_writel = _fsl_writel_be;
125 } else {
126 _fsl_readl = _fsl_readl_le;
127 _fsl_writel = _fsl_writel_le;
128 }
129 }
130
131 static inline u32 cpu_to_hc32(const u32 x)
132 {
133 return udc_controller->pdata->big_endian_desc
134 ? (__force u32)cpu_to_be32(x)
135 : (__force u32)cpu_to_le32(x);
136 }
137
138 static inline u32 hc32_to_cpu(const u32 x)
139 {
140 return udc_controller->pdata->big_endian_desc
141 ? be32_to_cpu((__force __be32)x)
142 : le32_to_cpu((__force __le32)x);
143 }
144 #else /* !CONFIG_PPC32 */
145 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
146
147 #define fsl_readl(addr) readl(addr)
148 #define fsl_writel(val32, addr) writel(val32, addr)
149 #define cpu_to_hc32(x) cpu_to_le32(x)
150 #define hc32_to_cpu(x) le32_to_cpu(x)
151 #endif /* CONFIG_PPC32 */
152
153 /********************************************************************
154 * Internal Used Function
155 ********************************************************************/
156 /*-----------------------------------------------------------------
157 * done() - retire a request; caller blocked irqs
158 * @status : request status to be set, only works when
159 * request is still in progress.
160 *--------------------------------------------------------------*/
161 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
162 {
163 struct fsl_udc *udc = NULL;
164 unsigned char stopped = ep->stopped;
165 struct ep_td_struct *curr_td, *next_td;
166 int j;
167
168 udc = (struct fsl_udc *)ep->udc;
169 /* Removed the req from fsl_ep->queue */
170 list_del_init(&req->queue);
171
172 /* req.status should be set as -EINPROGRESS in ep_queue() */
173 if (req->req.status == -EINPROGRESS)
174 req->req.status = status;
175 else
176 status = req->req.status;
177
178 /* Free dtd for the request */
179 next_td = req->head;
180 for (j = 0; j < req->dtd_count; j++) {
181 curr_td = next_td;
182 if (j != req->dtd_count - 1) {
183 next_td = curr_td->next_td_virt;
184 }
185 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
186 }
187
188 if (req->mapped) {
189 dma_unmap_single(ep->udc->gadget.dev.parent,
190 req->req.dma, req->req.length,
191 ep_is_in(ep)
192 ? DMA_TO_DEVICE
193 : DMA_FROM_DEVICE);
194 req->req.dma = DMA_ADDR_INVALID;
195 req->mapped = 0;
196 } else
197 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
198 req->req.dma, req->req.length,
199 ep_is_in(ep)
200 ? DMA_TO_DEVICE
201 : DMA_FROM_DEVICE);
202
203 if (status && (status != -ESHUTDOWN))
204 VDBG("complete %s req %p stat %d len %u/%u",
205 ep->ep.name, &req->req, status,
206 req->req.actual, req->req.length);
207
208 ep->stopped = 1;
209
210 spin_unlock(&ep->udc->lock);
211 /* complete() is from gadget layer,
212 * eg fsg->bulk_in_complete() */
213 if (req->req.complete)
214 req->req.complete(&ep->ep, &req->req);
215
216 spin_lock(&ep->udc->lock);
217 ep->stopped = stopped;
218 }
219
220 /*-----------------------------------------------------------------
221 * nuke(): delete all requests related to this ep
222 * called with spinlock held
223 *--------------------------------------------------------------*/
224 static void nuke(struct fsl_ep *ep, int status)
225 {
226 ep->stopped = 1;
227
228 /* Flush fifo */
229 fsl_ep_fifo_flush(&ep->ep);
230
231 /* Whether this eq has request linked */
232 while (!list_empty(&ep->queue)) {
233 struct fsl_req *req = NULL;
234
235 req = list_entry(ep->queue.next, struct fsl_req, queue);
236 done(ep, req, status);
237 }
238 }
239
240 /*------------------------------------------------------------------
241 Internal Hardware related function
242 ------------------------------------------------------------------*/
243
244 static int dr_controller_setup(struct fsl_udc *udc)
245 {
246 unsigned int tmp, portctrl, ep_num;
247 unsigned int max_no_of_ep;
248 #ifndef CONFIG_ARCH_MXC
249 unsigned int ctrl;
250 #endif
251 unsigned long timeout;
252 #define FSL_UDC_RESET_TIMEOUT 1000
253
254 /* Config PHY interface */
255 portctrl = fsl_readl(&dr_regs->portsc1);
256 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
257 switch (udc->phy_mode) {
258 case FSL_USB2_PHY_ULPI:
259 portctrl |= PORTSCX_PTS_ULPI;
260 break;
261 case FSL_USB2_PHY_UTMI_WIDE:
262 portctrl |= PORTSCX_PTW_16BIT;
263 /* fall through */
264 case FSL_USB2_PHY_UTMI:
265 portctrl |= PORTSCX_PTS_UTMI;
266 break;
267 case FSL_USB2_PHY_SERIAL:
268 portctrl |= PORTSCX_PTS_FSLS;
269 break;
270 default:
271 return -EINVAL;
272 }
273 fsl_writel(portctrl, &dr_regs->portsc1);
274
275 /* Stop and reset the usb controller */
276 tmp = fsl_readl(&dr_regs->usbcmd);
277 tmp &= ~USB_CMD_RUN_STOP;
278 fsl_writel(tmp, &dr_regs->usbcmd);
279
280 tmp = fsl_readl(&dr_regs->usbcmd);
281 tmp |= USB_CMD_CTRL_RESET;
282 fsl_writel(tmp, &dr_regs->usbcmd);
283
284 /* Wait for reset to complete */
285 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
286 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
287 if (time_after(jiffies, timeout)) {
288 ERR("udc reset timeout!\n");
289 return -ETIMEDOUT;
290 }
291 cpu_relax();
292 }
293
294 /* Set the controller as device mode */
295 tmp = fsl_readl(&dr_regs->usbmode);
296 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
297 tmp |= USB_MODE_CTRL_MODE_DEVICE;
298 /* Disable Setup Lockout */
299 tmp |= USB_MODE_SETUP_LOCK_OFF;
300 if (udc->pdata->es)
301 tmp |= USB_MODE_ES;
302 fsl_writel(tmp, &dr_regs->usbmode);
303
304 /* Clear the setup status */
305 fsl_writel(0, &dr_regs->usbsts);
306
307 tmp = udc->ep_qh_dma;
308 tmp &= USB_EP_LIST_ADDRESS_MASK;
309 fsl_writel(tmp, &dr_regs->endpointlistaddr);
310
311 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
312 udc->ep_qh, (int)tmp,
313 fsl_readl(&dr_regs->endpointlistaddr));
314
315 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
316 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
317 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
318 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
319 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
320 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
321 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
322 }
323 /* Config control enable i/o output, cpu endian register */
324 #ifndef CONFIG_ARCH_MXC
325 if (udc->pdata->have_sysif_regs) {
326 ctrl = __raw_readl(&usb_sys_regs->control);
327 ctrl |= USB_CTRL_IOENB;
328 __raw_writel(ctrl, &usb_sys_regs->control);
329 }
330 #endif
331
332 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
333 /* Turn on cache snooping hardware, since some PowerPC platforms
334 * wholly rely on hardware to deal with cache coherent. */
335
336 if (udc->pdata->have_sysif_regs) {
337 /* Setup Snooping for all the 4GB space */
338 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
339 __raw_writel(tmp, &usb_sys_regs->snoop1);
340 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
341 __raw_writel(tmp, &usb_sys_regs->snoop2);
342 }
343 #endif
344
345 return 0;
346 }
347
348 /* Enable DR irq and set controller to run state */
349 static void dr_controller_run(struct fsl_udc *udc)
350 {
351 u32 temp;
352
353 /* Enable DR irq reg */
354 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
355 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
356 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
357
358 fsl_writel(temp, &dr_regs->usbintr);
359
360 /* Clear stopped bit */
361 udc->stopped = 0;
362
363 /* Set the controller as device mode */
364 temp = fsl_readl(&dr_regs->usbmode);
365 temp |= USB_MODE_CTRL_MODE_DEVICE;
366 fsl_writel(temp, &dr_regs->usbmode);
367
368 /* Set controller to Run */
369 temp = fsl_readl(&dr_regs->usbcmd);
370 temp |= USB_CMD_RUN_STOP;
371 fsl_writel(temp, &dr_regs->usbcmd);
372 }
373
374 static void dr_controller_stop(struct fsl_udc *udc)
375 {
376 unsigned int tmp;
377
378 pr_debug("%s\n", __func__);
379
380 /* if we're in OTG mode, and the Host is currently using the port,
381 * stop now and don't rip the controller out from under the
382 * ehci driver
383 */
384 if (udc->gadget.is_otg) {
385 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
386 pr_debug("udc: Leaving early\n");
387 return;
388 }
389 }
390
391 /* disable all INTR */
392 fsl_writel(0, &dr_regs->usbintr);
393
394 /* Set stopped bit for isr */
395 udc->stopped = 1;
396
397 /* disable IO output */
398 /* usb_sys_regs->control = 0; */
399
400 /* set controller to Stop */
401 tmp = fsl_readl(&dr_regs->usbcmd);
402 tmp &= ~USB_CMD_RUN_STOP;
403 fsl_writel(tmp, &dr_regs->usbcmd);
404 }
405
406 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
407 unsigned char ep_type)
408 {
409 unsigned int tmp_epctrl = 0;
410
411 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
412 if (dir) {
413 if (ep_num)
414 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
415 tmp_epctrl |= EPCTRL_TX_ENABLE;
416 tmp_epctrl &= ~EPCTRL_TX_TYPE;
417 tmp_epctrl |= ((unsigned int)(ep_type)
418 << EPCTRL_TX_EP_TYPE_SHIFT);
419 } else {
420 if (ep_num)
421 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
422 tmp_epctrl |= EPCTRL_RX_ENABLE;
423 tmp_epctrl &= ~EPCTRL_RX_TYPE;
424 tmp_epctrl |= ((unsigned int)(ep_type)
425 << EPCTRL_RX_EP_TYPE_SHIFT);
426 }
427
428 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
429 }
430
431 static void
432 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
433 {
434 u32 tmp_epctrl = 0;
435
436 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
437
438 if (value) {
439 /* set the stall bit */
440 if (dir)
441 tmp_epctrl |= EPCTRL_TX_EP_STALL;
442 else
443 tmp_epctrl |= EPCTRL_RX_EP_STALL;
444 } else {
445 /* clear the stall bit and reset data toggle */
446 if (dir) {
447 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
448 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
449 } else {
450 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
451 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
452 }
453 }
454 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
455 }
456
457 /* Get stall status of a specific ep
458 Return: 0: not stalled; 1:stalled */
459 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
460 {
461 u32 epctrl;
462
463 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
464 if (dir)
465 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
466 else
467 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
468 }
469
470 /********************************************************************
471 Internal Structure Build up functions
472 ********************************************************************/
473
474 /*------------------------------------------------------------------
475 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
476 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
477 * @mult: Mult field
478 ------------------------------------------------------------------*/
479 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
480 unsigned char dir, unsigned char ep_type,
481 unsigned int max_pkt_len,
482 unsigned int zlt, unsigned char mult)
483 {
484 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
485 unsigned int tmp = 0;
486
487 /* set the Endpoint Capabilites in QH */
488 switch (ep_type) {
489 case USB_ENDPOINT_XFER_CONTROL:
490 /* Interrupt On Setup (IOS). for control ep */
491 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
492 | EP_QUEUE_HEAD_IOS;
493 break;
494 case USB_ENDPOINT_XFER_ISOC:
495 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
496 | (mult << EP_QUEUE_HEAD_MULT_POS);
497 break;
498 case USB_ENDPOINT_XFER_BULK:
499 case USB_ENDPOINT_XFER_INT:
500 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
501 break;
502 default:
503 VDBG("error ep type is %d", ep_type);
504 return;
505 }
506 if (zlt)
507 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
508
509 p_QH->max_pkt_length = cpu_to_hc32(tmp);
510 p_QH->next_dtd_ptr = 1;
511 p_QH->size_ioc_int_sts = 0;
512 }
513
514 /* Setup qh structure and ep register for ep0. */
515 static void ep0_setup(struct fsl_udc *udc)
516 {
517 /* the intialization of an ep includes: fields in QH, Regs,
518 * fsl_ep struct */
519 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
520 USB_MAX_CTRL_PAYLOAD, 0, 0);
521 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
522 USB_MAX_CTRL_PAYLOAD, 0, 0);
523 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
524 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
525
526 return;
527
528 }
529
530 /***********************************************************************
531 Endpoint Management Functions
532 ***********************************************************************/
533
534 /*-------------------------------------------------------------------------
535 * when configurations are set, or when interface settings change
536 * for example the do_set_interface() in gadget layer,
537 * the driver will enable or disable the relevant endpoints
538 * ep0 doesn't use this routine. It is always enabled.
539 -------------------------------------------------------------------------*/
540 static int fsl_ep_enable(struct usb_ep *_ep,
541 const struct usb_endpoint_descriptor *desc)
542 {
543 struct fsl_udc *udc = NULL;
544 struct fsl_ep *ep = NULL;
545 unsigned short max = 0;
546 unsigned char mult = 0, zlt;
547 int retval = -EINVAL;
548 unsigned long flags = 0;
549
550 ep = container_of(_ep, struct fsl_ep, ep);
551
552 /* catch various bogus parameters */
553 if (!_ep || !desc || ep->desc
554 || (desc->bDescriptorType != USB_DT_ENDPOINT))
555 return -EINVAL;
556
557 udc = ep->udc;
558
559 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
560 return -ESHUTDOWN;
561
562 max = le16_to_cpu(desc->wMaxPacketSize);
563
564 /* Disable automatic zlp generation. Driver is responsible to indicate
565 * explicitly through req->req.zero. This is needed to enable multi-td
566 * request. */
567 zlt = 1;
568
569 /* Assume the max packet size from gadget is always correct */
570 switch (desc->bmAttributes & 0x03) {
571 case USB_ENDPOINT_XFER_CONTROL:
572 case USB_ENDPOINT_XFER_BULK:
573 case USB_ENDPOINT_XFER_INT:
574 /* mult = 0. Execute N Transactions as demonstrated by
575 * the USB variable length packet protocol where N is
576 * computed using the Maximum Packet Length (dQH) and
577 * the Total Bytes field (dTD) */
578 mult = 0;
579 break;
580 case USB_ENDPOINT_XFER_ISOC:
581 /* Calculate transactions needed for high bandwidth iso */
582 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
583 max = max & 0x7ff; /* bit 0~10 */
584 /* 3 transactions at most */
585 if (mult > 3)
586 goto en_done;
587 break;
588 default:
589 goto en_done;
590 }
591
592 spin_lock_irqsave(&udc->lock, flags);
593 ep->ep.maxpacket = max;
594 ep->desc = desc;
595 ep->stopped = 0;
596
597 /* Controller related setup */
598 /* Init EPx Queue Head (Ep Capabilites field in QH
599 * according to max, zlt, mult) */
600 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
601 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
602 ? USB_SEND : USB_RECV),
603 (unsigned char) (desc->bmAttributes
604 & USB_ENDPOINT_XFERTYPE_MASK),
605 max, zlt, mult);
606
607 /* Init endpoint ctrl register */
608 dr_ep_setup((unsigned char) ep_index(ep),
609 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
610 ? USB_SEND : USB_RECV),
611 (unsigned char) (desc->bmAttributes
612 & USB_ENDPOINT_XFERTYPE_MASK));
613
614 spin_unlock_irqrestore(&udc->lock, flags);
615 retval = 0;
616
617 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
618 ep->desc->bEndpointAddress & 0x0f,
619 (desc->bEndpointAddress & USB_DIR_IN)
620 ? "in" : "out", max);
621 en_done:
622 return retval;
623 }
624
625 /*---------------------------------------------------------------------
626 * @ep : the ep being unconfigured. May not be ep0
627 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
628 *---------------------------------------------------------------------*/
629 static int fsl_ep_disable(struct usb_ep *_ep)
630 {
631 struct fsl_udc *udc = NULL;
632 struct fsl_ep *ep = NULL;
633 unsigned long flags = 0;
634 u32 epctrl;
635 int ep_num;
636
637 ep = container_of(_ep, struct fsl_ep, ep);
638 if (!_ep || !ep->desc) {
639 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
640 return -EINVAL;
641 }
642
643 /* disable ep on controller */
644 ep_num = ep_index(ep);
645 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
646 if (ep_is_in(ep)) {
647 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
648 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
649 } else {
650 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
651 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
652 }
653 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
654
655 udc = (struct fsl_udc *)ep->udc;
656 spin_lock_irqsave(&udc->lock, flags);
657
658 /* nuke all pending requests (does flush) */
659 nuke(ep, -ESHUTDOWN);
660
661 ep->desc = NULL;
662 ep->stopped = 1;
663 spin_unlock_irqrestore(&udc->lock, flags);
664
665 VDBG("disabled %s OK", _ep->name);
666 return 0;
667 }
668
669 /*---------------------------------------------------------------------
670 * allocate a request object used by this endpoint
671 * the main operation is to insert the req->queue to the eq->queue
672 * Returns the request, or null if one could not be allocated
673 *---------------------------------------------------------------------*/
674 static struct usb_request *
675 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
676 {
677 struct fsl_req *req = NULL;
678
679 req = kzalloc(sizeof *req, gfp_flags);
680 if (!req)
681 return NULL;
682
683 req->req.dma = DMA_ADDR_INVALID;
684 INIT_LIST_HEAD(&req->queue);
685
686 return &req->req;
687 }
688
689 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
690 {
691 struct fsl_req *req = NULL;
692
693 req = container_of(_req, struct fsl_req, req);
694
695 if (_req)
696 kfree(req);
697 }
698
699 /*-------------------------------------------------------------------------*/
700 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
701 {
702 int i = ep_index(ep) * 2 + ep_is_in(ep);
703 u32 temp, bitmask, tmp_stat;
704 struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
705
706 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
707 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
708
709 bitmask = ep_is_in(ep)
710 ? (1 << (ep_index(ep) + 16))
711 : (1 << (ep_index(ep)));
712
713 /* check if the pipe is empty */
714 if (!(list_empty(&ep->queue))) {
715 /* Add td to the end */
716 struct fsl_req *lastreq;
717 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
718 lastreq->tail->next_td_ptr =
719 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
720 /* Read prime bit, if 1 goto done */
721 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
722 goto out;
723
724 do {
725 /* Set ATDTW bit in USBCMD */
726 temp = fsl_readl(&dr_regs->usbcmd);
727 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
728
729 /* Read correct status bit */
730 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
731
732 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
733
734 /* Write ATDTW bit to 0 */
735 temp = fsl_readl(&dr_regs->usbcmd);
736 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
737
738 if (tmp_stat)
739 goto out;
740 }
741
742 /* Write dQH next pointer and terminate bit to 0 */
743 temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
744 dQH->next_dtd_ptr = cpu_to_hc32(temp);
745
746 /* Clear active and halt bit */
747 temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
748 | EP_QUEUE_HEAD_STATUS_HALT));
749 dQH->size_ioc_int_sts &= temp;
750
751 /* Ensure that updates to the QH will occur before priming. */
752 wmb();
753
754 /* Prime endpoint by writing 1 to ENDPTPRIME */
755 temp = ep_is_in(ep)
756 ? (1 << (ep_index(ep) + 16))
757 : (1 << (ep_index(ep)));
758 fsl_writel(temp, &dr_regs->endpointprime);
759 out:
760 return;
761 }
762
763 /* Fill in the dTD structure
764 * @req: request that the transfer belongs to
765 * @length: return actually data length of the dTD
766 * @dma: return dma address of the dTD
767 * @is_last: return flag if it is the last dTD of the request
768 * return: pointer to the built dTD */
769 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
770 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
771 {
772 u32 swap_temp;
773 struct ep_td_struct *dtd;
774
775 /* how big will this transfer be? */
776 *length = min(req->req.length - req->req.actual,
777 (unsigned)EP_MAX_LENGTH_TRANSFER);
778
779 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
780 if (dtd == NULL)
781 return dtd;
782
783 dtd->td_dma = *dma;
784 /* Clear reserved field */
785 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
786 swap_temp &= ~DTD_RESERVED_FIELDS;
787 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
788
789 /* Init all of buffer page pointers */
790 swap_temp = (u32) (req->req.dma + req->req.actual);
791 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
792 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
793 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
794 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
795 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
796
797 req->req.actual += *length;
798
799 /* zlp is needed if req->req.zero is set */
800 if (req->req.zero) {
801 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
802 *is_last = 1;
803 else
804 *is_last = 0;
805 } else if (req->req.length == req->req.actual)
806 *is_last = 1;
807 else
808 *is_last = 0;
809
810 if ((*is_last) == 0)
811 VDBG("multi-dtd request!");
812 /* Fill in the transfer size; set active bit */
813 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
814
815 /* Enable interrupt for the last dtd of a request */
816 if (*is_last && !req->req.no_interrupt)
817 swap_temp |= DTD_IOC;
818
819 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
820
821 mb();
822
823 VDBG("length = %d address= 0x%x", *length, (int)*dma);
824
825 return dtd;
826 }
827
828 /* Generate dtd chain for a request */
829 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
830 {
831 unsigned count;
832 int is_last;
833 int is_first =1;
834 struct ep_td_struct *last_dtd = NULL, *dtd;
835 dma_addr_t dma;
836
837 do {
838 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
839 if (dtd == NULL)
840 return -ENOMEM;
841
842 if (is_first) {
843 is_first = 0;
844 req->head = dtd;
845 } else {
846 last_dtd->next_td_ptr = cpu_to_hc32(dma);
847 last_dtd->next_td_virt = dtd;
848 }
849 last_dtd = dtd;
850
851 req->dtd_count++;
852 } while (!is_last);
853
854 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
855
856 req->tail = dtd;
857
858 return 0;
859 }
860
861 /* queues (submits) an I/O request to an endpoint */
862 static int
863 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
864 {
865 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
866 struct fsl_req *req = container_of(_req, struct fsl_req, req);
867 struct fsl_udc *udc;
868 unsigned long flags;
869
870 /* catch various bogus parameters */
871 if (!_req || !req->req.complete || !req->req.buf
872 || !list_empty(&req->queue)) {
873 VDBG("%s, bad params", __func__);
874 return -EINVAL;
875 }
876 if (unlikely(!_ep || !ep->desc)) {
877 VDBG("%s, bad ep", __func__);
878 return -EINVAL;
879 }
880 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
881 if (req->req.length > ep->ep.maxpacket)
882 return -EMSGSIZE;
883 }
884
885 udc = ep->udc;
886 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
887 return -ESHUTDOWN;
888
889 req->ep = ep;
890
891 /* map virtual address to hardware */
892 if (req->req.dma == DMA_ADDR_INVALID) {
893 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
894 req->req.buf,
895 req->req.length, ep_is_in(ep)
896 ? DMA_TO_DEVICE
897 : DMA_FROM_DEVICE);
898 req->mapped = 1;
899 } else {
900 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
901 req->req.dma, req->req.length,
902 ep_is_in(ep)
903 ? DMA_TO_DEVICE
904 : DMA_FROM_DEVICE);
905 req->mapped = 0;
906 }
907
908 req->req.status = -EINPROGRESS;
909 req->req.actual = 0;
910 req->dtd_count = 0;
911
912 /* build dtds and push them to device queue */
913 if (!fsl_req_to_dtd(req, gfp_flags)) {
914 spin_lock_irqsave(&udc->lock, flags);
915 fsl_queue_td(ep, req);
916 } else {
917 return -ENOMEM;
918 }
919
920 /* Update ep0 state */
921 if ((ep_index(ep) == 0))
922 udc->ep0_state = DATA_STATE_XMIT;
923
924 /* irq handler advances the queue */
925 if (req != NULL)
926 list_add_tail(&req->queue, &ep->queue);
927 spin_unlock_irqrestore(&udc->lock, flags);
928
929 return 0;
930 }
931
932 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
933 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
934 {
935 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
936 struct fsl_req *req;
937 unsigned long flags;
938 int ep_num, stopped, ret = 0;
939 u32 epctrl;
940
941 if (!_ep || !_req)
942 return -EINVAL;
943
944 spin_lock_irqsave(&ep->udc->lock, flags);
945 stopped = ep->stopped;
946
947 /* Stop the ep before we deal with the queue */
948 ep->stopped = 1;
949 ep_num = ep_index(ep);
950 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
951 if (ep_is_in(ep))
952 epctrl &= ~EPCTRL_TX_ENABLE;
953 else
954 epctrl &= ~EPCTRL_RX_ENABLE;
955 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
956
957 /* make sure it's actually queued on this endpoint */
958 list_for_each_entry(req, &ep->queue, queue) {
959 if (&req->req == _req)
960 break;
961 }
962 if (&req->req != _req) {
963 ret = -EINVAL;
964 goto out;
965 }
966
967 /* The request is in progress, or completed but not dequeued */
968 if (ep->queue.next == &req->queue) {
969 _req->status = -ECONNRESET;
970 fsl_ep_fifo_flush(_ep); /* flush current transfer */
971
972 /* The request isn't the last request in this ep queue */
973 if (req->queue.next != &ep->queue) {
974 struct ep_queue_head *qh;
975 struct fsl_req *next_req;
976
977 qh = ep->qh;
978 next_req = list_entry(req->queue.next, struct fsl_req,
979 queue);
980
981 /* Point the QH to the first TD of next request */
982 fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
983 }
984
985 /* The request hasn't been processed, patch up the TD chain */
986 } else {
987 struct fsl_req *prev_req;
988
989 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
990 fsl_writel(fsl_readl(&req->tail->next_td_ptr),
991 &prev_req->tail->next_td_ptr);
992
993 }
994
995 done(ep, req, -ECONNRESET);
996
997 /* Enable EP */
998 out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
999 if (ep_is_in(ep))
1000 epctrl |= EPCTRL_TX_ENABLE;
1001 else
1002 epctrl |= EPCTRL_RX_ENABLE;
1003 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1004 ep->stopped = stopped;
1005
1006 spin_unlock_irqrestore(&ep->udc->lock, flags);
1007 return ret;
1008 }
1009
1010 /*-------------------------------------------------------------------------*/
1011
1012 /*-----------------------------------------------------------------
1013 * modify the endpoint halt feature
1014 * @ep: the non-isochronous endpoint being stalled
1015 * @value: 1--set halt 0--clear halt
1016 * Returns zero, or a negative error code.
1017 *----------------------------------------------------------------*/
1018 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1019 {
1020 struct fsl_ep *ep = NULL;
1021 unsigned long flags = 0;
1022 int status = -EOPNOTSUPP; /* operation not supported */
1023 unsigned char ep_dir = 0, ep_num = 0;
1024 struct fsl_udc *udc = NULL;
1025
1026 ep = container_of(_ep, struct fsl_ep, ep);
1027 udc = ep->udc;
1028 if (!_ep || !ep->desc) {
1029 status = -EINVAL;
1030 goto out;
1031 }
1032
1033 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1034 status = -EOPNOTSUPP;
1035 goto out;
1036 }
1037
1038 /* Attempt to halt IN ep will fail if any transfer requests
1039 * are still queue */
1040 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1041 status = -EAGAIN;
1042 goto out;
1043 }
1044
1045 status = 0;
1046 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1047 ep_num = (unsigned char)(ep_index(ep));
1048 spin_lock_irqsave(&ep->udc->lock, flags);
1049 dr_ep_change_stall(ep_num, ep_dir, value);
1050 spin_unlock_irqrestore(&ep->udc->lock, flags);
1051
1052 if (ep_index(ep) == 0) {
1053 udc->ep0_state = WAIT_FOR_SETUP;
1054 udc->ep0_dir = 0;
1055 }
1056 out:
1057 VDBG(" %s %s halt stat %d", ep->ep.name,
1058 value ? "set" : "clear", status);
1059
1060 return status;
1061 }
1062
1063 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1064 {
1065 struct fsl_ep *ep;
1066 struct fsl_udc *udc;
1067 int size = 0;
1068 u32 bitmask;
1069 struct ep_queue_head *d_qh;
1070
1071 ep = container_of(_ep, struct fsl_ep, ep);
1072 if (!_ep || (!ep->desc && ep_index(ep) != 0))
1073 return -ENODEV;
1074
1075 udc = (struct fsl_udc *)ep->udc;
1076
1077 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1078 return -ESHUTDOWN;
1079
1080 d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
1081
1082 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1083 (1 << (ep_index(ep)));
1084
1085 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1086 size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1087 >> DTD_LENGTH_BIT_POS;
1088
1089 pr_debug("%s %u\n", __func__, size);
1090 return size;
1091 }
1092
1093 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1094 {
1095 struct fsl_ep *ep;
1096 int ep_num, ep_dir;
1097 u32 bits;
1098 unsigned long timeout;
1099 #define FSL_UDC_FLUSH_TIMEOUT 1000
1100
1101 if (!_ep) {
1102 return;
1103 } else {
1104 ep = container_of(_ep, struct fsl_ep, ep);
1105 if (!ep->desc)
1106 return;
1107 }
1108 ep_num = ep_index(ep);
1109 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1110
1111 if (ep_num == 0)
1112 bits = (1 << 16) | 1;
1113 else if (ep_dir == USB_SEND)
1114 bits = 1 << (16 + ep_num);
1115 else
1116 bits = 1 << ep_num;
1117
1118 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1119 do {
1120 fsl_writel(bits, &dr_regs->endptflush);
1121
1122 /* Wait until flush complete */
1123 while (fsl_readl(&dr_regs->endptflush)) {
1124 if (time_after(jiffies, timeout)) {
1125 ERR("ep flush timeout\n");
1126 return;
1127 }
1128 cpu_relax();
1129 }
1130 /* See if we need to flush again */
1131 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1132 }
1133
1134 static struct usb_ep_ops fsl_ep_ops = {
1135 .enable = fsl_ep_enable,
1136 .disable = fsl_ep_disable,
1137
1138 .alloc_request = fsl_alloc_request,
1139 .free_request = fsl_free_request,
1140
1141 .queue = fsl_ep_queue,
1142 .dequeue = fsl_ep_dequeue,
1143
1144 .set_halt = fsl_ep_set_halt,
1145 .fifo_status = fsl_ep_fifo_status,
1146 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1147 };
1148
1149 /*-------------------------------------------------------------------------
1150 Gadget Driver Layer Operations
1151 -------------------------------------------------------------------------*/
1152
1153 /*----------------------------------------------------------------------
1154 * Get the current frame number (from DR frame_index Reg )
1155 *----------------------------------------------------------------------*/
1156 static int fsl_get_frame(struct usb_gadget *gadget)
1157 {
1158 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1159 }
1160
1161 /*-----------------------------------------------------------------------
1162 * Tries to wake up the host connected to this gadget
1163 -----------------------------------------------------------------------*/
1164 static int fsl_wakeup(struct usb_gadget *gadget)
1165 {
1166 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1167 u32 portsc;
1168
1169 /* Remote wakeup feature not enabled by host */
1170 if (!udc->remote_wakeup)
1171 return -ENOTSUPP;
1172
1173 portsc = fsl_readl(&dr_regs->portsc1);
1174 /* not suspended? */
1175 if (!(portsc & PORTSCX_PORT_SUSPEND))
1176 return 0;
1177 /* trigger force resume */
1178 portsc |= PORTSCX_PORT_FORCE_RESUME;
1179 fsl_writel(portsc, &dr_regs->portsc1);
1180 return 0;
1181 }
1182
1183 static int can_pullup(struct fsl_udc *udc)
1184 {
1185 return udc->driver && udc->softconnect && udc->vbus_active;
1186 }
1187
1188 /* Notify controller that VBUS is powered, Called by whatever
1189 detects VBUS sessions */
1190 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1191 {
1192 struct fsl_udc *udc;
1193 unsigned long flags;
1194
1195 udc = container_of(gadget, struct fsl_udc, gadget);
1196 spin_lock_irqsave(&udc->lock, flags);
1197 VDBG("VBUS %s", is_active ? "on" : "off");
1198 udc->vbus_active = (is_active != 0);
1199 if (can_pullup(udc))
1200 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1201 &dr_regs->usbcmd);
1202 else
1203 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1204 &dr_regs->usbcmd);
1205 spin_unlock_irqrestore(&udc->lock, flags);
1206 return 0;
1207 }
1208
1209 /* constrain controller's VBUS power usage
1210 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1211 * reporting how much power the device may consume. For example, this
1212 * could affect how quickly batteries are recharged.
1213 *
1214 * Returns zero on success, else negative errno.
1215 */
1216 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1217 {
1218 struct fsl_udc *udc;
1219
1220 udc = container_of(gadget, struct fsl_udc, gadget);
1221 if (udc->transceiver)
1222 return otg_set_power(udc->transceiver, mA);
1223 return -ENOTSUPP;
1224 }
1225
1226 /* Change Data+ pullup status
1227 * this func is used by usb_gadget_connect/disconnet
1228 */
1229 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1230 {
1231 struct fsl_udc *udc;
1232
1233 udc = container_of(gadget, struct fsl_udc, gadget);
1234 udc->softconnect = (is_on != 0);
1235 if (can_pullup(udc))
1236 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1237 &dr_regs->usbcmd);
1238 else
1239 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1240 &dr_regs->usbcmd);
1241
1242 return 0;
1243 }
1244
1245 /* defined in gadget.h */
1246 static struct usb_gadget_ops fsl_gadget_ops = {
1247 .get_frame = fsl_get_frame,
1248 .wakeup = fsl_wakeup,
1249 /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1250 .vbus_session = fsl_vbus_session,
1251 .vbus_draw = fsl_vbus_draw,
1252 .pullup = fsl_pullup,
1253 };
1254
1255 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1256 on new transaction */
1257 static void ep0stall(struct fsl_udc *udc)
1258 {
1259 u32 tmp;
1260
1261 /* must set tx and rx to stall at the same time */
1262 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1263 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1264 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1265 udc->ep0_state = WAIT_FOR_SETUP;
1266 udc->ep0_dir = 0;
1267 }
1268
1269 /* Prime a status phase for ep0 */
1270 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1271 {
1272 struct fsl_req *req = udc->status_req;
1273 struct fsl_ep *ep;
1274
1275 if (direction == EP_DIR_IN)
1276 udc->ep0_dir = USB_DIR_IN;
1277 else
1278 udc->ep0_dir = USB_DIR_OUT;
1279
1280 ep = &udc->eps[0];
1281 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1282
1283 req->ep = ep;
1284 req->req.length = 0;
1285 req->req.status = -EINPROGRESS;
1286 req->req.actual = 0;
1287 req->req.complete = NULL;
1288 req->dtd_count = 0;
1289
1290 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1291 req->req.buf, req->req.length,
1292 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1293 req->mapped = 1;
1294
1295 if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1296 fsl_queue_td(ep, req);
1297 else
1298 return -ENOMEM;
1299
1300 list_add_tail(&req->queue, &ep->queue);
1301
1302 return 0;
1303 }
1304
1305 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1306 {
1307 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1308
1309 if (ep->name)
1310 nuke(ep, -ESHUTDOWN);
1311 }
1312
1313 /*
1314 * ch9 Set address
1315 */
1316 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1317 {
1318 /* Save the new address to device struct */
1319 udc->device_address = (u8) value;
1320 /* Update usb state */
1321 udc->usb_state = USB_STATE_ADDRESS;
1322 /* Status phase */
1323 if (ep0_prime_status(udc, EP_DIR_IN))
1324 ep0stall(udc);
1325 }
1326
1327 /*
1328 * ch9 Get status
1329 */
1330 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1331 u16 index, u16 length)
1332 {
1333 u16 tmp = 0; /* Status, cpu endian */
1334 struct fsl_req *req;
1335 struct fsl_ep *ep;
1336
1337 ep = &udc->eps[0];
1338
1339 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1340 /* Get device status */
1341 tmp = 1 << USB_DEVICE_SELF_POWERED;
1342 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1343 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1344 /* Get interface status */
1345 /* We don't have interface information in udc driver */
1346 tmp = 0;
1347 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1348 /* Get endpoint status */
1349 struct fsl_ep *target_ep;
1350
1351 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1352
1353 /* stall if endpoint doesn't exist */
1354 if (!target_ep->desc)
1355 goto stall;
1356 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1357 << USB_ENDPOINT_HALT;
1358 }
1359
1360 udc->ep0_dir = USB_DIR_IN;
1361 /* Borrow the per device status_req */
1362 req = udc->status_req;
1363 /* Fill in the reqest structure */
1364 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1365
1366 req->ep = ep;
1367 req->req.length = 2;
1368 req->req.status = -EINPROGRESS;
1369 req->req.actual = 0;
1370 req->req.complete = NULL;
1371 req->dtd_count = 0;
1372
1373 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1374 req->req.buf, req->req.length,
1375 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1376 req->mapped = 1;
1377
1378 /* prime the data phase */
1379 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1380 fsl_queue_td(ep, req);
1381 else /* no mem */
1382 goto stall;
1383
1384 list_add_tail(&req->queue, &ep->queue);
1385 udc->ep0_state = DATA_STATE_XMIT;
1386 return;
1387 stall:
1388 ep0stall(udc);
1389 }
1390
1391 static void setup_received_irq(struct fsl_udc *udc,
1392 struct usb_ctrlrequest *setup)
1393 {
1394 u16 wValue = le16_to_cpu(setup->wValue);
1395 u16 wIndex = le16_to_cpu(setup->wIndex);
1396 u16 wLength = le16_to_cpu(setup->wLength);
1397
1398 udc_reset_ep_queue(udc, 0);
1399
1400 /* We process some stardard setup requests here */
1401 switch (setup->bRequest) {
1402 case USB_REQ_GET_STATUS:
1403 /* Data+Status phase from udc */
1404 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1405 != (USB_DIR_IN | USB_TYPE_STANDARD))
1406 break;
1407 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1408 return;
1409
1410 case USB_REQ_SET_ADDRESS:
1411 /* Status phase from udc */
1412 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1413 | USB_RECIP_DEVICE))
1414 break;
1415 ch9setaddress(udc, wValue, wIndex, wLength);
1416 return;
1417
1418 case USB_REQ_CLEAR_FEATURE:
1419 case USB_REQ_SET_FEATURE:
1420 /* Status phase from udc */
1421 {
1422 int rc = -EOPNOTSUPP;
1423 u16 ptc = 0;
1424
1425 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1426 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1427 int pipe = get_pipe_by_windex(wIndex);
1428 struct fsl_ep *ep;
1429
1430 if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
1431 break;
1432 ep = get_ep_by_pipe(udc, pipe);
1433
1434 spin_unlock(&udc->lock);
1435 rc = fsl_ep_set_halt(&ep->ep,
1436 (setup->bRequest == USB_REQ_SET_FEATURE)
1437 ? 1 : 0);
1438 spin_lock(&udc->lock);
1439
1440 } else if ((setup->bRequestType & (USB_RECIP_MASK
1441 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1442 | USB_TYPE_STANDARD)) {
1443 /* Note: The driver has not include OTG support yet.
1444 * This will be set when OTG support is added */
1445 if (wValue == USB_DEVICE_TEST_MODE)
1446 ptc = wIndex >> 8;
1447 else if (gadget_is_otg(&udc->gadget)) {
1448 if (setup->bRequest ==
1449 USB_DEVICE_B_HNP_ENABLE)
1450 udc->gadget.b_hnp_enable = 1;
1451 else if (setup->bRequest ==
1452 USB_DEVICE_A_HNP_SUPPORT)
1453 udc->gadget.a_hnp_support = 1;
1454 else if (setup->bRequest ==
1455 USB_DEVICE_A_ALT_HNP_SUPPORT)
1456 udc->gadget.a_alt_hnp_support = 1;
1457 }
1458 rc = 0;
1459 } else
1460 break;
1461
1462 if (rc == 0) {
1463 if (ep0_prime_status(udc, EP_DIR_IN))
1464 ep0stall(udc);
1465 }
1466 if (ptc) {
1467 u32 tmp;
1468
1469 mdelay(10);
1470 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1471 fsl_writel(tmp, &dr_regs->portsc1);
1472 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1473 }
1474
1475 return;
1476 }
1477
1478 default:
1479 break;
1480 }
1481
1482 /* Requests handled by gadget */
1483 if (wLength) {
1484 /* Data phase from gadget, status phase from udc */
1485 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1486 ? USB_DIR_IN : USB_DIR_OUT;
1487 spin_unlock(&udc->lock);
1488 if (udc->driver->setup(&udc->gadget,
1489 &udc->local_setup_buff) < 0)
1490 ep0stall(udc);
1491 spin_lock(&udc->lock);
1492 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1493 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1494 } else {
1495 /* No data phase, IN status from gadget */
1496 udc->ep0_dir = USB_DIR_IN;
1497 spin_unlock(&udc->lock);
1498 if (udc->driver->setup(&udc->gadget,
1499 &udc->local_setup_buff) < 0)
1500 ep0stall(udc);
1501 spin_lock(&udc->lock);
1502 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1503 }
1504 }
1505
1506 /* Process request for Data or Status phase of ep0
1507 * prime status phase if needed */
1508 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1509 struct fsl_req *req)
1510 {
1511 if (udc->usb_state == USB_STATE_ADDRESS) {
1512 /* Set the new address */
1513 u32 new_address = (u32) udc->device_address;
1514 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1515 &dr_regs->deviceaddr);
1516 }
1517
1518 done(ep0, req, 0);
1519
1520 switch (udc->ep0_state) {
1521 case DATA_STATE_XMIT:
1522 /* receive status phase */
1523 if (ep0_prime_status(udc, EP_DIR_OUT))
1524 ep0stall(udc);
1525 break;
1526 case DATA_STATE_RECV:
1527 /* send status phase */
1528 if (ep0_prime_status(udc, EP_DIR_IN))
1529 ep0stall(udc);
1530 break;
1531 case WAIT_FOR_OUT_STATUS:
1532 udc->ep0_state = WAIT_FOR_SETUP;
1533 break;
1534 case WAIT_FOR_SETUP:
1535 ERR("Unexpect ep0 packets\n");
1536 break;
1537 default:
1538 ep0stall(udc);
1539 break;
1540 }
1541 }
1542
1543 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1544 * being corrupted by another incoming setup packet */
1545 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1546 {
1547 u32 temp;
1548 struct ep_queue_head *qh;
1549 struct fsl_usb2_platform_data *pdata = udc->pdata;
1550
1551 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1552
1553 /* Clear bit in ENDPTSETUPSTAT */
1554 temp = fsl_readl(&dr_regs->endptsetupstat);
1555 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1556
1557 /* while a hazard exists when setup package arrives */
1558 do {
1559 /* Set Setup Tripwire */
1560 temp = fsl_readl(&dr_regs->usbcmd);
1561 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1562
1563 /* Copy the setup packet to local buffer */
1564 if (pdata->le_setup_buf) {
1565 u32 *p = (u32 *)buffer_ptr;
1566 u32 *s = (u32 *)qh->setup_buffer;
1567
1568 /* Convert little endian setup buffer to CPU endian */
1569 *p++ = le32_to_cpu(*s++);
1570 *p = le32_to_cpu(*s);
1571 } else {
1572 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1573 }
1574 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1575
1576 /* Clear Setup Tripwire */
1577 temp = fsl_readl(&dr_regs->usbcmd);
1578 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1579 }
1580
1581 /* process-ep_req(): free the completed Tds for this req */
1582 static int process_ep_req(struct fsl_udc *udc, int pipe,
1583 struct fsl_req *curr_req)
1584 {
1585 struct ep_td_struct *curr_td;
1586 int td_complete, actual, remaining_length, j, tmp;
1587 int status = 0;
1588 int errors = 0;
1589 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1590 int direction = pipe % 2;
1591
1592 curr_td = curr_req->head;
1593 td_complete = 0;
1594 actual = curr_req->req.length;
1595
1596 for (j = 0; j < curr_req->dtd_count; j++) {
1597 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1598 & DTD_PACKET_SIZE)
1599 >> DTD_LENGTH_BIT_POS;
1600 actual -= remaining_length;
1601
1602 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1603 if (errors & DTD_ERROR_MASK) {
1604 if (errors & DTD_STATUS_HALTED) {
1605 ERR("dTD error %08x QH=%d\n", errors, pipe);
1606 /* Clear the errors and Halt condition */
1607 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1608 tmp &= ~errors;
1609 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1610 status = -EPIPE;
1611 /* FIXME: continue with next queued TD? */
1612
1613 break;
1614 }
1615 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1616 VDBG("Transfer overflow");
1617 status = -EPROTO;
1618 break;
1619 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1620 VDBG("ISO error");
1621 status = -EILSEQ;
1622 break;
1623 } else
1624 ERR("Unknown error has occurred (0x%x)!\n",
1625 errors);
1626
1627 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1628 & DTD_STATUS_ACTIVE) {
1629 VDBG("Request not complete");
1630 status = REQ_UNCOMPLETE;
1631 return status;
1632 } else if (remaining_length) {
1633 if (direction) {
1634 VDBG("Transmit dTD remaining length not zero");
1635 status = -EPROTO;
1636 break;
1637 } else {
1638 td_complete++;
1639 break;
1640 }
1641 } else {
1642 td_complete++;
1643 VDBG("dTD transmitted successful");
1644 }
1645
1646 if (j != curr_req->dtd_count - 1)
1647 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1648 }
1649
1650 if (status)
1651 return status;
1652
1653 curr_req->req.actual = actual;
1654
1655 return 0;
1656 }
1657
1658 /* Process a DTD completion interrupt */
1659 static void dtd_complete_irq(struct fsl_udc *udc)
1660 {
1661 u32 bit_pos;
1662 int i, ep_num, direction, bit_mask, status;
1663 struct fsl_ep *curr_ep;
1664 struct fsl_req *curr_req, *temp_req;
1665
1666 /* Clear the bits in the register */
1667 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1668 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1669
1670 if (!bit_pos)
1671 return;
1672
1673 for (i = 0; i < udc->max_ep * 2; i++) {
1674 ep_num = i >> 1;
1675 direction = i % 2;
1676
1677 bit_mask = 1 << (ep_num + 16 * direction);
1678
1679 if (!(bit_pos & bit_mask))
1680 continue;
1681
1682 curr_ep = get_ep_by_pipe(udc, i);
1683
1684 /* If the ep is configured */
1685 if (curr_ep->name == NULL) {
1686 WARNING("Invalid EP?");
1687 continue;
1688 }
1689
1690 /* process the req queue until an uncomplete request */
1691 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1692 queue) {
1693 status = process_ep_req(udc, i, curr_req);
1694
1695 VDBG("status of process_ep_req= %d, ep = %d",
1696 status, ep_num);
1697 if (status == REQ_UNCOMPLETE)
1698 break;
1699 /* write back status to req */
1700 curr_req->req.status = status;
1701
1702 if (ep_num == 0) {
1703 ep0_req_complete(udc, curr_ep, curr_req);
1704 break;
1705 } else
1706 done(curr_ep, curr_req, status);
1707 }
1708 }
1709 }
1710
1711 /* Process a port change interrupt */
1712 static void port_change_irq(struct fsl_udc *udc)
1713 {
1714 u32 speed;
1715
1716 if (udc->bus_reset)
1717 udc->bus_reset = 0;
1718
1719 /* Bus resetting is finished */
1720 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
1721 /* Get the speed */
1722 speed = (fsl_readl(&dr_regs->portsc1)
1723 & PORTSCX_PORT_SPEED_MASK);
1724 switch (speed) {
1725 case PORTSCX_PORT_SPEED_HIGH:
1726 udc->gadget.speed = USB_SPEED_HIGH;
1727 break;
1728 case PORTSCX_PORT_SPEED_FULL:
1729 udc->gadget.speed = USB_SPEED_FULL;
1730 break;
1731 case PORTSCX_PORT_SPEED_LOW:
1732 udc->gadget.speed = USB_SPEED_LOW;
1733 break;
1734 default:
1735 udc->gadget.speed = USB_SPEED_UNKNOWN;
1736 break;
1737 }
1738 }
1739
1740 /* Update USB state */
1741 if (!udc->resume_state)
1742 udc->usb_state = USB_STATE_DEFAULT;
1743 }
1744
1745 /* Process suspend interrupt */
1746 static void suspend_irq(struct fsl_udc *udc)
1747 {
1748 udc->resume_state = udc->usb_state;
1749 udc->usb_state = USB_STATE_SUSPENDED;
1750
1751 /* report suspend to the driver, serial.c does not support this */
1752 if (udc->driver->suspend)
1753 udc->driver->suspend(&udc->gadget);
1754 }
1755
1756 static void bus_resume(struct fsl_udc *udc)
1757 {
1758 udc->usb_state = udc->resume_state;
1759 udc->resume_state = 0;
1760
1761 /* report resume to the driver, serial.c does not support this */
1762 if (udc->driver->resume)
1763 udc->driver->resume(&udc->gadget);
1764 }
1765
1766 /* Clear up all ep queues */
1767 static int reset_queues(struct fsl_udc *udc)
1768 {
1769 u8 pipe;
1770
1771 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1772 udc_reset_ep_queue(udc, pipe);
1773
1774 /* report disconnect; the driver is already quiesced */
1775 spin_unlock(&udc->lock);
1776 udc->driver->disconnect(&udc->gadget);
1777 spin_lock(&udc->lock);
1778
1779 return 0;
1780 }
1781
1782 /* Process reset interrupt */
1783 static void reset_irq(struct fsl_udc *udc)
1784 {
1785 u32 temp;
1786 unsigned long timeout;
1787
1788 /* Clear the device address */
1789 temp = fsl_readl(&dr_regs->deviceaddr);
1790 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1791
1792 udc->device_address = 0;
1793
1794 /* Clear usb state */
1795 udc->resume_state = 0;
1796 udc->ep0_dir = 0;
1797 udc->ep0_state = WAIT_FOR_SETUP;
1798 udc->remote_wakeup = 0; /* default to 0 on reset */
1799 udc->gadget.b_hnp_enable = 0;
1800 udc->gadget.a_hnp_support = 0;
1801 udc->gadget.a_alt_hnp_support = 0;
1802
1803 /* Clear all the setup token semaphores */
1804 temp = fsl_readl(&dr_regs->endptsetupstat);
1805 fsl_writel(temp, &dr_regs->endptsetupstat);
1806
1807 /* Clear all the endpoint complete status bits */
1808 temp = fsl_readl(&dr_regs->endptcomplete);
1809 fsl_writel(temp, &dr_regs->endptcomplete);
1810
1811 timeout = jiffies + 100;
1812 while (fsl_readl(&dr_regs->endpointprime)) {
1813 /* Wait until all endptprime bits cleared */
1814 if (time_after(jiffies, timeout)) {
1815 ERR("Timeout for reset\n");
1816 break;
1817 }
1818 cpu_relax();
1819 }
1820
1821 /* Write 1s to the flush register */
1822 fsl_writel(0xffffffff, &dr_regs->endptflush);
1823
1824 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1825 VDBG("Bus reset");
1826 /* Bus is reseting */
1827 udc->bus_reset = 1;
1828 /* Reset all the queues, include XD, dTD, EP queue
1829 * head and TR Queue */
1830 reset_queues(udc);
1831 udc->usb_state = USB_STATE_DEFAULT;
1832 } else {
1833 VDBG("Controller reset");
1834 /* initialize usb hw reg except for regs for EP, not
1835 * touch usbintr reg */
1836 dr_controller_setup(udc);
1837
1838 /* Reset all internal used Queues */
1839 reset_queues(udc);
1840
1841 ep0_setup(udc);
1842
1843 /* Enable DR IRQ reg, Set Run bit, change udc state */
1844 dr_controller_run(udc);
1845 udc->usb_state = USB_STATE_ATTACHED;
1846 }
1847 }
1848
1849 /*
1850 * USB device controller interrupt handler
1851 */
1852 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1853 {
1854 struct fsl_udc *udc = _udc;
1855 u32 irq_src;
1856 irqreturn_t status = IRQ_NONE;
1857 unsigned long flags;
1858
1859 /* Disable ISR for OTG host mode */
1860 if (udc->stopped)
1861 return IRQ_NONE;
1862 spin_lock_irqsave(&udc->lock, flags);
1863 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1864 /* Clear notification bits */
1865 fsl_writel(irq_src, &dr_regs->usbsts);
1866
1867 /* VDBG("irq_src [0x%8x]", irq_src); */
1868
1869 /* Need to resume? */
1870 if (udc->usb_state == USB_STATE_SUSPENDED)
1871 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1872 bus_resume(udc);
1873
1874 /* USB Interrupt */
1875 if (irq_src & USB_STS_INT) {
1876 VDBG("Packet int");
1877 /* Setup package, we only support ep0 as control ep */
1878 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1879 tripwire_handler(udc, 0,
1880 (u8 *) (&udc->local_setup_buff));
1881 setup_received_irq(udc, &udc->local_setup_buff);
1882 status = IRQ_HANDLED;
1883 }
1884
1885 /* completion of dtd */
1886 if (fsl_readl(&dr_regs->endptcomplete)) {
1887 dtd_complete_irq(udc);
1888 status = IRQ_HANDLED;
1889 }
1890 }
1891
1892 /* SOF (for ISO transfer) */
1893 if (irq_src & USB_STS_SOF) {
1894 status = IRQ_HANDLED;
1895 }
1896
1897 /* Port Change */
1898 if (irq_src & USB_STS_PORT_CHANGE) {
1899 port_change_irq(udc);
1900 status = IRQ_HANDLED;
1901 }
1902
1903 /* Reset Received */
1904 if (irq_src & USB_STS_RESET) {
1905 VDBG("reset int");
1906 reset_irq(udc);
1907 status = IRQ_HANDLED;
1908 }
1909
1910 /* Sleep Enable (Suspend) */
1911 if (irq_src & USB_STS_SUSPEND) {
1912 suspend_irq(udc);
1913 status = IRQ_HANDLED;
1914 }
1915
1916 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1917 VDBG("Error IRQ %x", irq_src);
1918 }
1919
1920 spin_unlock_irqrestore(&udc->lock, flags);
1921 return status;
1922 }
1923
1924 /*----------------------------------------------------------------*
1925 * Hook to gadget drivers
1926 * Called by initialization code of gadget drivers
1927 *----------------------------------------------------------------*/
1928 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
1929 int (*bind)(struct usb_gadget *))
1930 {
1931 int retval = -ENODEV;
1932 unsigned long flags = 0;
1933
1934 if (!udc_controller)
1935 return -ENODEV;
1936
1937 if (!driver || (driver->speed != USB_SPEED_FULL
1938 && driver->speed != USB_SPEED_HIGH)
1939 || !bind || !driver->disconnect || !driver->setup)
1940 return -EINVAL;
1941
1942 if (udc_controller->driver)
1943 return -EBUSY;
1944
1945 /* lock is needed but whether should use this lock or another */
1946 spin_lock_irqsave(&udc_controller->lock, flags);
1947
1948 driver->driver.bus = NULL;
1949 /* hook up the driver */
1950 udc_controller->driver = driver;
1951 udc_controller->gadget.dev.driver = &driver->driver;
1952 spin_unlock_irqrestore(&udc_controller->lock, flags);
1953
1954 /* bind udc driver to gadget driver */
1955 retval = bind(&udc_controller->gadget);
1956 if (retval) {
1957 VDBG("bind to %s --> %d", driver->driver.name, retval);
1958 udc_controller->gadget.dev.driver = NULL;
1959 udc_controller->driver = NULL;
1960 goto out;
1961 }
1962
1963 if (udc_controller->transceiver) {
1964 /* Suspend the controller until OTG enable it */
1965 udc_controller->stopped = 1;
1966 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1967
1968 /* connect to bus through transceiver */
1969 if (udc_controller->transceiver) {
1970 retval = otg_set_peripheral(udc_controller->transceiver,
1971 &udc_controller->gadget);
1972 if (retval < 0) {
1973 ERR("can't bind to transceiver\n");
1974 driver->unbind(&udc_controller->gadget);
1975 udc_controller->gadget.dev.driver = 0;
1976 udc_controller->driver = 0;
1977 return retval;
1978 }
1979 }
1980 } else {
1981 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1982 dr_controller_run(udc_controller);
1983 udc_controller->usb_state = USB_STATE_ATTACHED;
1984 udc_controller->ep0_state = WAIT_FOR_SETUP;
1985 udc_controller->ep0_dir = 0;
1986 }
1987 printk(KERN_INFO "%s: bind to driver %s\n",
1988 udc_controller->gadget.name, driver->driver.name);
1989
1990 out:
1991 if (retval)
1992 printk(KERN_WARNING "gadget driver register failed %d\n",
1993 retval);
1994 return retval;
1995 }
1996 EXPORT_SYMBOL(usb_gadget_probe_driver);
1997
1998 /* Disconnect from gadget driver */
1999 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2000 {
2001 struct fsl_ep *loop_ep;
2002 unsigned long flags;
2003
2004 if (!udc_controller)
2005 return -ENODEV;
2006
2007 if (!driver || driver != udc_controller->driver || !driver->unbind)
2008 return -EINVAL;
2009
2010 if (udc_controller->transceiver)
2011 otg_set_peripheral(udc_controller->transceiver, NULL);
2012
2013 /* stop DR, disable intr */
2014 dr_controller_stop(udc_controller);
2015
2016 /* in fact, no needed */
2017 udc_controller->usb_state = USB_STATE_ATTACHED;
2018 udc_controller->ep0_state = WAIT_FOR_SETUP;
2019 udc_controller->ep0_dir = 0;
2020
2021 /* stand operation */
2022 spin_lock_irqsave(&udc_controller->lock, flags);
2023 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2024 nuke(&udc_controller->eps[0], -ESHUTDOWN);
2025 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2026 ep.ep_list)
2027 nuke(loop_ep, -ESHUTDOWN);
2028 spin_unlock_irqrestore(&udc_controller->lock, flags);
2029
2030 /* report disconnect; the controller is already quiesced */
2031 driver->disconnect(&udc_controller->gadget);
2032
2033 /* unbind gadget and unhook driver. */
2034 driver->unbind(&udc_controller->gadget);
2035 udc_controller->gadget.dev.driver = NULL;
2036 udc_controller->driver = NULL;
2037
2038 printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2039 driver->driver.name);
2040 return 0;
2041 }
2042 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2043
2044 /*-------------------------------------------------------------------------
2045 PROC File System Support
2046 -------------------------------------------------------------------------*/
2047 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2048
2049 #include <linux/seq_file.h>
2050
2051 static const char proc_filename[] = "driver/fsl_usb2_udc";
2052
2053 static int fsl_proc_read(char *page, char **start, off_t off, int count,
2054 int *eof, void *_dev)
2055 {
2056 char *buf = page;
2057 char *next = buf;
2058 unsigned size = count;
2059 unsigned long flags;
2060 int t, i;
2061 u32 tmp_reg;
2062 struct fsl_ep *ep = NULL;
2063 struct fsl_req *req;
2064
2065 struct fsl_udc *udc = udc_controller;
2066 if (off != 0)
2067 return 0;
2068
2069 spin_lock_irqsave(&udc->lock, flags);
2070
2071 /* ------basic driver information ---- */
2072 t = scnprintf(next, size,
2073 DRIVER_DESC "\n"
2074 "%s version: %s\n"
2075 "Gadget driver: %s\n\n",
2076 driver_name, DRIVER_VERSION,
2077 udc->driver ? udc->driver->driver.name : "(none)");
2078 size -= t;
2079 next += t;
2080
2081 /* ------ DR Registers ----- */
2082 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2083 t = scnprintf(next, size,
2084 "USBCMD reg:\n"
2085 "SetupTW: %d\n"
2086 "Run/Stop: %s\n\n",
2087 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2088 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2089 size -= t;
2090 next += t;
2091
2092 tmp_reg = fsl_readl(&dr_regs->usbsts);
2093 t = scnprintf(next, size,
2094 "USB Status Reg:\n"
2095 "Dr Suspend: %d Reset Received: %d System Error: %s "
2096 "USB Error Interrupt: %s\n\n",
2097 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2098 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2099 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2100 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2101 size -= t;
2102 next += t;
2103
2104 tmp_reg = fsl_readl(&dr_regs->usbintr);
2105 t = scnprintf(next, size,
2106 "USB Intrrupt Enable Reg:\n"
2107 "Sleep Enable: %d SOF Received Enable: %d "
2108 "Reset Enable: %d\n"
2109 "System Error Enable: %d "
2110 "Port Change Dectected Enable: %d\n"
2111 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2112 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2113 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2114 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2115 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2116 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2117 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2118 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2119 size -= t;
2120 next += t;
2121
2122 tmp_reg = fsl_readl(&dr_regs->frindex);
2123 t = scnprintf(next, size,
2124 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2125 (tmp_reg & USB_FRINDEX_MASKS));
2126 size -= t;
2127 next += t;
2128
2129 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2130 t = scnprintf(next, size,
2131 "USB Device Address Reg: Device Addr is 0x%x\n\n",
2132 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2133 size -= t;
2134 next += t;
2135
2136 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2137 t = scnprintf(next, size,
2138 "USB Endpoint List Address Reg: "
2139 "Device Addr is 0x%x\n\n",
2140 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2141 size -= t;
2142 next += t;
2143
2144 tmp_reg = fsl_readl(&dr_regs->portsc1);
2145 t = scnprintf(next, size,
2146 "USB Port Status&Control Reg:\n"
2147 "Port Transceiver Type : %s Port Speed: %s\n"
2148 "PHY Low Power Suspend: %s Port Reset: %s "
2149 "Port Suspend Mode: %s\n"
2150 "Over-current Change: %s "
2151 "Port Enable/Disable Change: %s\n"
2152 "Port Enabled/Disabled: %s "
2153 "Current Connect Status: %s\n\n", ( {
2154 char *s;
2155 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2156 case PORTSCX_PTS_UTMI:
2157 s = "UTMI"; break;
2158 case PORTSCX_PTS_ULPI:
2159 s = "ULPI "; break;
2160 case PORTSCX_PTS_FSLS:
2161 s = "FS/LS Serial"; break;
2162 default:
2163 s = "None"; break;
2164 }
2165 s;} ), ( {
2166 char *s;
2167 switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) {
2168 case PORTSCX_PORT_SPEED_FULL:
2169 s = "Full Speed"; break;
2170 case PORTSCX_PORT_SPEED_LOW:
2171 s = "Low Speed"; break;
2172 case PORTSCX_PORT_SPEED_HIGH:
2173 s = "High Speed"; break;
2174 default:
2175 s = "Undefined"; break;
2176 }
2177 s;
2178 } ),
2179 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2180 "Normal PHY mode" : "Low power mode",
2181 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2182 "Not in Reset",
2183 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2184 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2185 "No",
2186 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2187 "Not change",
2188 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2189 "Not correct",
2190 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2191 "Attached" : "Not-Att");
2192 size -= t;
2193 next += t;
2194
2195 tmp_reg = fsl_readl(&dr_regs->usbmode);
2196 t = scnprintf(next, size,
2197 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2198 char *s;
2199 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2200 case USB_MODE_CTRL_MODE_IDLE:
2201 s = "Idle"; break;
2202 case USB_MODE_CTRL_MODE_DEVICE:
2203 s = "Device Controller"; break;
2204 case USB_MODE_CTRL_MODE_HOST:
2205 s = "Host Controller"; break;
2206 default:
2207 s = "None"; break;
2208 }
2209 s;
2210 } ));
2211 size -= t;
2212 next += t;
2213
2214 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2215 t = scnprintf(next, size,
2216 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2217 (tmp_reg & EP_SETUP_STATUS_MASK));
2218 size -= t;
2219 next += t;
2220
2221 for (i = 0; i < udc->max_ep / 2; i++) {
2222 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2223 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2224 i, tmp_reg);
2225 size -= t;
2226 next += t;
2227 }
2228 tmp_reg = fsl_readl(&dr_regs->endpointprime);
2229 t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2230 size -= t;
2231 next += t;
2232
2233 #ifndef CONFIG_ARCH_MXC
2234 if (udc->pdata->have_sysif_regs) {
2235 tmp_reg = usb_sys_regs->snoop1;
2236 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2237 size -= t;
2238 next += t;
2239
2240 tmp_reg = usb_sys_regs->control;
2241 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2242 tmp_reg);
2243 size -= t;
2244 next += t;
2245 }
2246 #endif
2247
2248 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2249 ep = &udc->eps[0];
2250 t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2251 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2252 size -= t;
2253 next += t;
2254
2255 if (list_empty(&ep->queue)) {
2256 t = scnprintf(next, size, "its req queue is empty\n\n");
2257 size -= t;
2258 next += t;
2259 } else {
2260 list_for_each_entry(req, &ep->queue, queue) {
2261 t = scnprintf(next, size,
2262 "req %p actual 0x%x length 0x%x buf %p\n",
2263 &req->req, req->req.actual,
2264 req->req.length, req->req.buf);
2265 size -= t;
2266 next += t;
2267 }
2268 }
2269 /* other gadget->eplist ep */
2270 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2271 if (ep->desc) {
2272 t = scnprintf(next, size,
2273 "\nFor %s Maxpkt is 0x%x "
2274 "index is 0x%x\n",
2275 ep->ep.name, ep_maxpacket(ep),
2276 ep_index(ep));
2277 size -= t;
2278 next += t;
2279
2280 if (list_empty(&ep->queue)) {
2281 t = scnprintf(next, size,
2282 "its req queue is empty\n\n");
2283 size -= t;
2284 next += t;
2285 } else {
2286 list_for_each_entry(req, &ep->queue, queue) {
2287 t = scnprintf(next, size,
2288 "req %p actual 0x%x length "
2289 "0x%x buf %p\n",
2290 &req->req, req->req.actual,
2291 req->req.length, req->req.buf);
2292 size -= t;
2293 next += t;
2294 } /* end for each_entry of ep req */
2295 } /* end for else */
2296 } /* end for if(ep->queue) */
2297 } /* end (ep->desc) */
2298
2299 spin_unlock_irqrestore(&udc->lock, flags);
2300
2301 *eof = 1;
2302 return count - size;
2303 }
2304
2305 #define create_proc_file() create_proc_read_entry(proc_filename, \
2306 0, NULL, fsl_proc_read, NULL)
2307
2308 #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2309
2310 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2311
2312 #define create_proc_file() do {} while (0)
2313 #define remove_proc_file() do {} while (0)
2314
2315 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2316
2317 /*-------------------------------------------------------------------------*/
2318
2319 /* Release udc structures */
2320 static void fsl_udc_release(struct device *dev)
2321 {
2322 complete(udc_controller->done);
2323 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2324 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2325 kfree(udc_controller);
2326 }
2327
2328 /******************************************************************
2329 Internal structure setup functions
2330 *******************************************************************/
2331 /*------------------------------------------------------------------
2332 * init resource for globle controller
2333 * Return the udc handle on success or NULL on failure
2334 ------------------------------------------------------------------*/
2335 static int __init struct_udc_setup(struct fsl_udc *udc,
2336 struct platform_device *pdev)
2337 {
2338 struct fsl_usb2_platform_data *pdata;
2339 size_t size;
2340
2341 pdata = pdev->dev.platform_data;
2342 udc->phy_mode = pdata->phy_mode;
2343
2344 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2345 if (!udc->eps) {
2346 ERR("malloc fsl_ep failed\n");
2347 return -1;
2348 }
2349
2350 /* initialized QHs, take care of alignment */
2351 size = udc->max_ep * sizeof(struct ep_queue_head);
2352 if (size < QH_ALIGNMENT)
2353 size = QH_ALIGNMENT;
2354 else if ((size % QH_ALIGNMENT) != 0) {
2355 size += QH_ALIGNMENT + 1;
2356 size &= ~(QH_ALIGNMENT - 1);
2357 }
2358 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2359 &udc->ep_qh_dma, GFP_KERNEL);
2360 if (!udc->ep_qh) {
2361 ERR("malloc QHs for udc failed\n");
2362 kfree(udc->eps);
2363 return -1;
2364 }
2365
2366 udc->ep_qh_size = size;
2367
2368 /* Initialize ep0 status request structure */
2369 /* FIXME: fsl_alloc_request() ignores ep argument */
2370 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2371 struct fsl_req, req);
2372 /* allocate a small amount of memory to get valid address */
2373 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2374
2375 udc->resume_state = USB_STATE_NOTATTACHED;
2376 udc->usb_state = USB_STATE_POWERED;
2377 udc->ep0_dir = 0;
2378 udc->remote_wakeup = 0; /* default to 0 on reset */
2379
2380 return 0;
2381 }
2382
2383 /*----------------------------------------------------------------
2384 * Setup the fsl_ep struct for eps
2385 * Link fsl_ep->ep to gadget->ep_list
2386 * ep0out is not used so do nothing here
2387 * ep0in should be taken care
2388 *--------------------------------------------------------------*/
2389 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2390 char *name, int link)
2391 {
2392 struct fsl_ep *ep = &udc->eps[index];
2393
2394 ep->udc = udc;
2395 strcpy(ep->name, name);
2396 ep->ep.name = ep->name;
2397
2398 ep->ep.ops = &fsl_ep_ops;
2399 ep->stopped = 0;
2400
2401 /* for ep0: maxP defined in desc
2402 * for other eps, maxP is set by epautoconfig() called by gadget layer
2403 */
2404 ep->ep.maxpacket = (unsigned short) ~0;
2405
2406 /* the queue lists any req for this ep */
2407 INIT_LIST_HEAD(&ep->queue);
2408
2409 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2410 if (link)
2411 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2412 ep->gadget = &udc->gadget;
2413 ep->qh = &udc->ep_qh[index];
2414
2415 return 0;
2416 }
2417
2418 /* Driver probe function
2419 * all intialization operations implemented here except enabling usb_intr reg
2420 * board setup should have been done in the platform code
2421 */
2422 static int __init fsl_udc_probe(struct platform_device *pdev)
2423 {
2424 struct fsl_usb2_platform_data *pdata;
2425 struct resource *res;
2426 int ret = -ENODEV;
2427 unsigned int i;
2428 u32 dccparams;
2429
2430 if (strcmp(pdev->name, driver_name)) {
2431 VDBG("Wrong device");
2432 return -ENODEV;
2433 }
2434
2435 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2436 if (udc_controller == NULL) {
2437 ERR("malloc udc failed\n");
2438 return -ENOMEM;
2439 }
2440
2441 pdata = pdev->dev.platform_data;
2442 udc_controller->pdata = pdata;
2443 spin_lock_init(&udc_controller->lock);
2444 udc_controller->stopped = 1;
2445
2446 #ifdef CONFIG_USB_OTG
2447 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2448 udc_controller->transceiver = otg_get_transceiver();
2449 if (!udc_controller->transceiver) {
2450 ERR("Can't find OTG driver!\n");
2451 ret = -ENODEV;
2452 goto err_kfree;
2453 }
2454 }
2455 #endif
2456
2457 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2458 if (!res) {
2459 ret = -ENXIO;
2460 goto err_kfree;
2461 }
2462
2463 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2464 if (!request_mem_region(res->start, res->end - res->start + 1,
2465 driver_name)) {
2466 ERR("request mem region for %s failed\n", pdev->name);
2467 ret = -EBUSY;
2468 goto err_kfree;
2469 }
2470 }
2471
2472 dr_regs = ioremap(res->start, resource_size(res));
2473 if (!dr_regs) {
2474 ret = -ENOMEM;
2475 goto err_release_mem_region;
2476 }
2477
2478 pdata->regs = (void *)dr_regs;
2479
2480 /*
2481 * do platform specific init: check the clock, grab/config pins, etc.
2482 */
2483 if (pdata->init && pdata->init(pdev)) {
2484 ret = -ENODEV;
2485 goto err_iounmap_noclk;
2486 }
2487
2488 /* Set accessors only after pdata->init() ! */
2489 fsl_set_accessors(pdata);
2490
2491 #ifndef CONFIG_ARCH_MXC
2492 if (pdata->have_sysif_regs)
2493 usb_sys_regs = (struct usb_sys_interface *)
2494 ((u32)dr_regs + USB_DR_SYS_OFFSET);
2495 #endif
2496
2497 /* Initialize USB clocks */
2498 ret = fsl_udc_clk_init(pdev);
2499 if (ret < 0)
2500 goto err_iounmap_noclk;
2501
2502 /* Read Device Controller Capability Parameters register */
2503 dccparams = fsl_readl(&dr_regs->dccparams);
2504 if (!(dccparams & DCCPARAMS_DC)) {
2505 ERR("This SOC doesn't support device role\n");
2506 ret = -ENODEV;
2507 goto err_iounmap;
2508 }
2509 /* Get max device endpoints */
2510 /* DEN is bidirectional ep number, max_ep doubles the number */
2511 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2512
2513 udc_controller->irq = platform_get_irq(pdev, 0);
2514 if (!udc_controller->irq) {
2515 ret = -ENODEV;
2516 goto err_iounmap;
2517 }
2518
2519 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2520 driver_name, udc_controller);
2521 if (ret != 0) {
2522 ERR("cannot request irq %d err %d\n",
2523 udc_controller->irq, ret);
2524 goto err_iounmap;
2525 }
2526
2527 /* Initialize the udc structure including QH member and other member */
2528 if (struct_udc_setup(udc_controller, pdev)) {
2529 ERR("Can't initialize udc data structure\n");
2530 ret = -ENOMEM;
2531 goto err_free_irq;
2532 }
2533
2534 if (!udc_controller->transceiver) {
2535 /* initialize usb hw reg except for regs for EP,
2536 * leave usbintr reg untouched */
2537 dr_controller_setup(udc_controller);
2538 }
2539
2540 fsl_udc_clk_finalize(pdev);
2541
2542 /* Setup gadget structure */
2543 udc_controller->gadget.ops = &fsl_gadget_ops;
2544 udc_controller->gadget.is_dualspeed = 1;
2545 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2546 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2547 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2548 udc_controller->gadget.name = driver_name;
2549
2550 /* Setup gadget.dev and register with kernel */
2551 dev_set_name(&udc_controller->gadget.dev, "gadget");
2552 udc_controller->gadget.dev.release = fsl_udc_release;
2553 udc_controller->gadget.dev.parent = &pdev->dev;
2554 ret = device_register(&udc_controller->gadget.dev);
2555 if (ret < 0)
2556 goto err_free_irq;
2557
2558 if (udc_controller->transceiver)
2559 udc_controller->gadget.is_otg = 1;
2560
2561 /* setup QH and epctrl for ep0 */
2562 ep0_setup(udc_controller);
2563
2564 /* setup udc->eps[] for ep0 */
2565 struct_ep_setup(udc_controller, 0, "ep0", 0);
2566 /* for ep0: the desc defined here;
2567 * for other eps, gadget layer called ep_enable with defined desc
2568 */
2569 udc_controller->eps[0].desc = &fsl_ep0_desc;
2570 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2571
2572 /* setup the udc->eps[] for non-control endpoints and link
2573 * to gadget.ep_list */
2574 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2575 char name[14];
2576
2577 sprintf(name, "ep%dout", i);
2578 struct_ep_setup(udc_controller, i * 2, name, 1);
2579 sprintf(name, "ep%din", i);
2580 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2581 }
2582
2583 /* use dma_pool for TD management */
2584 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2585 sizeof(struct ep_td_struct),
2586 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2587 if (udc_controller->td_pool == NULL) {
2588 ret = -ENOMEM;
2589 goto err_unregister;
2590 }
2591 create_proc_file();
2592 return 0;
2593
2594 err_unregister:
2595 device_unregister(&udc_controller->gadget.dev);
2596 err_free_irq:
2597 free_irq(udc_controller->irq, udc_controller);
2598 err_iounmap:
2599 if (pdata->exit)
2600 pdata->exit(pdev);
2601 fsl_udc_clk_release();
2602 err_iounmap_noclk:
2603 iounmap(dr_regs);
2604 err_release_mem_region:
2605 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2606 release_mem_region(res->start, res->end - res->start + 1);
2607 err_kfree:
2608 kfree(udc_controller);
2609 udc_controller = NULL;
2610 return ret;
2611 }
2612
2613 /* Driver removal function
2614 * Free resources and finish pending transactions
2615 */
2616 static int __exit fsl_udc_remove(struct platform_device *pdev)
2617 {
2618 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2619 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2620
2621 DECLARE_COMPLETION(done);
2622
2623 if (!udc_controller)
2624 return -ENODEV;
2625 udc_controller->done = &done;
2626
2627 fsl_udc_clk_release();
2628
2629 /* DR has been stopped in usb_gadget_unregister_driver() */
2630 remove_proc_file();
2631
2632 /* Free allocated memory */
2633 kfree(udc_controller->status_req->req.buf);
2634 kfree(udc_controller->status_req);
2635 kfree(udc_controller->eps);
2636
2637 dma_pool_destroy(udc_controller->td_pool);
2638 free_irq(udc_controller->irq, udc_controller);
2639 iounmap(dr_regs);
2640 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2641 release_mem_region(res->start, res->end - res->start + 1);
2642
2643 device_unregister(&udc_controller->gadget.dev);
2644 /* free udc --wait for the release() finished */
2645 wait_for_completion(&done);
2646
2647 /*
2648 * do platform specific un-initialization:
2649 * release iomux pins, etc.
2650 */
2651 if (pdata->exit)
2652 pdata->exit(pdev);
2653
2654 return 0;
2655 }
2656
2657 /*-----------------------------------------------------------------
2658 * Modify Power management attributes
2659 * Used by OTG statemachine to disable gadget temporarily
2660 -----------------------------------------------------------------*/
2661 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2662 {
2663 dr_controller_stop(udc_controller);
2664 return 0;
2665 }
2666
2667 /*-----------------------------------------------------------------
2668 * Invoked on USB resume. May be called in_interrupt.
2669 * Here we start the DR controller and enable the irq
2670 *-----------------------------------------------------------------*/
2671 static int fsl_udc_resume(struct platform_device *pdev)
2672 {
2673 /* Enable DR irq reg and set controller Run */
2674 if (udc_controller->stopped) {
2675 dr_controller_setup(udc_controller);
2676 dr_controller_run(udc_controller);
2677 }
2678 udc_controller->usb_state = USB_STATE_ATTACHED;
2679 udc_controller->ep0_state = WAIT_FOR_SETUP;
2680 udc_controller->ep0_dir = 0;
2681 return 0;
2682 }
2683
2684 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2685 {
2686 struct fsl_udc *udc = udc_controller;
2687 u32 mode, usbcmd;
2688
2689 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2690
2691 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2692
2693 /*
2694 * If the controller is already stopped, then this must be a
2695 * PM suspend. Remember this fact, so that we will leave the
2696 * controller stopped at PM resume time.
2697 */
2698 if (udc->stopped) {
2699 pr_debug("gadget already stopped, leaving early\n");
2700 udc->already_stopped = 1;
2701 return 0;
2702 }
2703
2704 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2705 pr_debug("gadget not in device mode, leaving early\n");
2706 return 0;
2707 }
2708
2709 /* stop the controller */
2710 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2711 fsl_writel(usbcmd, &dr_regs->usbcmd);
2712
2713 udc->stopped = 1;
2714
2715 pr_info("USB Gadget suspended\n");
2716
2717 return 0;
2718 }
2719
2720 static int fsl_udc_otg_resume(struct device *dev)
2721 {
2722 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2723 udc_controller->stopped, udc_controller->already_stopped);
2724
2725 /*
2726 * If the controller was stopped at suspend time, then
2727 * don't resume it now.
2728 */
2729 if (udc_controller->already_stopped) {
2730 udc_controller->already_stopped = 0;
2731 pr_debug("gadget was already stopped, leaving early\n");
2732 return 0;
2733 }
2734
2735 pr_info("USB Gadget resume\n");
2736
2737 return fsl_udc_resume(NULL);
2738 }
2739
2740 /*-------------------------------------------------------------------------
2741 Register entry point for the peripheral controller driver
2742 --------------------------------------------------------------------------*/
2743
2744 static struct platform_driver udc_driver = {
2745 .remove = __exit_p(fsl_udc_remove),
2746 /* these suspend and resume are not usb suspend and resume */
2747 .suspend = fsl_udc_suspend,
2748 .resume = fsl_udc_resume,
2749 .driver = {
2750 .name = (char *)driver_name,
2751 .owner = THIS_MODULE,
2752 /* udc suspend/resume called from OTG driver */
2753 .suspend = fsl_udc_otg_suspend,
2754 .resume = fsl_udc_otg_resume,
2755 },
2756 };
2757
2758 static int __init udc_init(void)
2759 {
2760 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2761 return platform_driver_probe(&udc_driver, fsl_udc_probe);
2762 }
2763
2764 module_init(udc_init);
2765
2766 static void __exit udc_exit(void)
2767 {
2768 platform_driver_unregister(&udc_driver);
2769 printk(KERN_WARNING "%s unregistered\n", driver_desc);
2770 }
2771
2772 module_exit(udc_exit);
2773
2774 MODULE_DESCRIPTION(DRIVER_DESC);
2775 MODULE_AUTHOR(DRIVER_AUTHOR);
2776 MODULE_LICENSE("GPL");
2777 MODULE_ALIAS("platform:fsl-usb2-udc");
Linux with added FPC-III support