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s390/ptrace: get rid of long longs in psw_bits
[linux/fpc-iii.git] / drivers / gpu / ipu-v3 / ipu-common.c
blobba47b30d28fad4f3d187393a44a17bd9605f6ad4
1 /*
2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15 #include <linux/module.h>
16 #include <linux/export.h>
17 #include <linux/types.h>
18 #include <linux/reset.h>
19 #include <linux/platform_device.h>
20 #include <linux/err.h>
21 #include <linux/spinlock.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/list.h>
27 #include <linux/irq.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/irqdomain.h>
30 #include <linux/of_device.h>
31
32 #include <drm/drm_fourcc.h>
33
34 #include <video/imx-ipu-v3.h>
35 #include "ipu-prv.h"
36
37 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
38 {
39 return readl(ipu->cm_reg + offset);
40 }
41
42 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
43 {
44 writel(value, ipu->cm_reg + offset);
45 }
46
47 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
48 {
49 u32 val;
50
51 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
52 val |= 0x8;
53 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
54 }
55 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
56
57 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
58 {
59 switch (drm_fourcc) {
60 case DRM_FORMAT_ARGB1555:
61 case DRM_FORMAT_ABGR1555:
62 case DRM_FORMAT_RGBA5551:
63 case DRM_FORMAT_BGRA5551:
64 case DRM_FORMAT_RGB565:
65 case DRM_FORMAT_BGR565:
66 case DRM_FORMAT_RGB888:
67 case DRM_FORMAT_BGR888:
68 case DRM_FORMAT_ARGB4444:
69 case DRM_FORMAT_XRGB8888:
70 case DRM_FORMAT_XBGR8888:
71 case DRM_FORMAT_RGBX8888:
72 case DRM_FORMAT_BGRX8888:
73 case DRM_FORMAT_ARGB8888:
74 case DRM_FORMAT_ABGR8888:
75 case DRM_FORMAT_RGBA8888:
76 case DRM_FORMAT_BGRA8888:
77 return IPUV3_COLORSPACE_RGB;
78 case DRM_FORMAT_YUYV:
79 case DRM_FORMAT_UYVY:
80 case DRM_FORMAT_YUV420:
81 case DRM_FORMAT_YVU420:
82 case DRM_FORMAT_YUV422:
83 case DRM_FORMAT_YVU422:
84 case DRM_FORMAT_NV12:
85 case DRM_FORMAT_NV21:
86 case DRM_FORMAT_NV16:
87 case DRM_FORMAT_NV61:
88 return IPUV3_COLORSPACE_YUV;
89 default:
90 return IPUV3_COLORSPACE_UNKNOWN;
91 }
92 }
93 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
94
95 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
96 {
97 switch (pixelformat) {
98 case V4L2_PIX_FMT_YUV420:
99 case V4L2_PIX_FMT_YVU420:
100 case V4L2_PIX_FMT_YUV422P:
101 case V4L2_PIX_FMT_UYVY:
102 case V4L2_PIX_FMT_YUYV:
103 case V4L2_PIX_FMT_NV12:
104 case V4L2_PIX_FMT_NV21:
105 case V4L2_PIX_FMT_NV16:
106 case V4L2_PIX_FMT_NV61:
107 return IPUV3_COLORSPACE_YUV;
108 case V4L2_PIX_FMT_RGB32:
109 case V4L2_PIX_FMT_BGR32:
110 case V4L2_PIX_FMT_RGB24:
111 case V4L2_PIX_FMT_BGR24:
112 case V4L2_PIX_FMT_RGB565:
113 return IPUV3_COLORSPACE_RGB;
114 default:
115 return IPUV3_COLORSPACE_UNKNOWN;
116 }
117 }
118 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
119
120 bool ipu_pixelformat_is_planar(u32 pixelformat)
121 {
122 switch (pixelformat) {
123 case V4L2_PIX_FMT_YUV420:
124 case V4L2_PIX_FMT_YVU420:
125 case V4L2_PIX_FMT_YUV422P:
126 case V4L2_PIX_FMT_NV12:
127 case V4L2_PIX_FMT_NV21:
128 case V4L2_PIX_FMT_NV16:
129 case V4L2_PIX_FMT_NV61:
130 return true;
131 }
132
133 return false;
134 }
135 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
136
137 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
138 {
139 switch (mbus_code & 0xf000) {
140 case 0x1000:
141 return IPUV3_COLORSPACE_RGB;
142 case 0x2000:
143 return IPUV3_COLORSPACE_YUV;
144 default:
145 return IPUV3_COLORSPACE_UNKNOWN;
146 }
147 }
148 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
149
150 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
151 {
152 switch (pixelformat) {
153 case V4L2_PIX_FMT_YUV420:
154 case V4L2_PIX_FMT_YVU420:
155 case V4L2_PIX_FMT_YUV422P:
156 case V4L2_PIX_FMT_NV12:
157 case V4L2_PIX_FMT_NV21:
158 case V4L2_PIX_FMT_NV16:
159 case V4L2_PIX_FMT_NV61:
160 /*
161 * for the planar YUV formats, the stride passed to
162 * cpmem must be the stride in bytes of the Y plane.
163 * And all the planar YUV formats have an 8-bit
164 * Y component.
165 */
166 return (8 * pixel_stride) >> 3;
167 case V4L2_PIX_FMT_RGB565:
168 case V4L2_PIX_FMT_YUYV:
169 case V4L2_PIX_FMT_UYVY:
170 return (16 * pixel_stride) >> 3;
171 case V4L2_PIX_FMT_BGR24:
172 case V4L2_PIX_FMT_RGB24:
173 return (24 * pixel_stride) >> 3;
174 case V4L2_PIX_FMT_BGR32:
175 case V4L2_PIX_FMT_RGB32:
176 return (32 * pixel_stride) >> 3;
177 default:
178 break;
179 }
180
181 return -EINVAL;
182 }
183 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
184
185 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
186 bool hflip, bool vflip)
187 {
188 u32 r90, vf, hf;
189
190 switch (degrees) {
191 case 0:
192 vf = hf = r90 = 0;
193 break;
194 case 90:
195 vf = hf = 0;
196 r90 = 1;
197 break;
198 case 180:
199 vf = hf = 1;
200 r90 = 0;
201 break;
202 case 270:
203 vf = hf = r90 = 1;
204 break;
205 default:
206 return -EINVAL;
207 }
208
209 hf ^= (u32)hflip;
210 vf ^= (u32)vflip;
211
212 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
213 return 0;
214 }
215 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
216
217 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
218 bool hflip, bool vflip)
219 {
220 u32 r90, vf, hf;
221
222 r90 = ((u32)mode >> 2) & 0x1;
223 hf = ((u32)mode >> 1) & 0x1;
224 vf = ((u32)mode >> 0) & 0x1;
225 hf ^= (u32)hflip;
226 vf ^= (u32)vflip;
227
228 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
229 case IPU_ROTATE_NONE:
230 *degrees = 0;
231 break;
232 case IPU_ROTATE_90_RIGHT:
233 *degrees = 90;
234 break;
235 case IPU_ROTATE_180:
236 *degrees = 180;
237 break;
238 case IPU_ROTATE_90_LEFT:
239 *degrees = 270;
240 break;
241 default:
242 return -EINVAL;
243 }
244
245 return 0;
246 }
247 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
248
249 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
250 {
251 struct ipuv3_channel *channel;
252
253 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
254
255 if (num > 63)
256 return ERR_PTR(-ENODEV);
257
258 mutex_lock(&ipu->channel_lock);
259
260 channel = &ipu->channel[num];
261
262 if (channel->busy) {
263 channel = ERR_PTR(-EBUSY);
264 goto out;
265 }
266
267 channel->busy = true;
268 channel->num = num;
269
270 out:
271 mutex_unlock(&ipu->channel_lock);
272
273 return channel;
274 }
275 EXPORT_SYMBOL_GPL(ipu_idmac_get);
276
277 void ipu_idmac_put(struct ipuv3_channel *channel)
278 {
279 struct ipu_soc *ipu = channel->ipu;
280
281 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
282
283 mutex_lock(&ipu->channel_lock);
284
285 channel->busy = false;
286
287 mutex_unlock(&ipu->channel_lock);
288 }
289 EXPORT_SYMBOL_GPL(ipu_idmac_put);
290
291 #define idma_mask(ch) (1 << ((ch) & 0x1f))
292
293 /*
294 * This is an undocumented feature, a write one to a channel bit in
295 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
296 * internal current buffer pointer so that transfers start from buffer
297 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
298 * only says these are read-only registers). This operation is required
299 * for channel linking to work correctly, for instance video capture
300 * pipelines that carry out image rotations will fail after the first
301 * streaming unless this function is called for each channel before
302 * re-enabling the channels.
303 */
304 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
305 {
306 struct ipu_soc *ipu = channel->ipu;
307 unsigned int chno = channel->num;
308
309 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
310 }
311
312 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
313 bool doublebuffer)
314 {
315 struct ipu_soc *ipu = channel->ipu;
316 unsigned long flags;
317 u32 reg;
318
319 spin_lock_irqsave(&ipu->lock, flags);
320
321 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
322 if (doublebuffer)
323 reg |= idma_mask(channel->num);
324 else
325 reg &= ~idma_mask(channel->num);
326 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
327
328 __ipu_idmac_reset_current_buffer(channel);
329
330 spin_unlock_irqrestore(&ipu->lock, flags);
331 }
332 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
333
334 static const struct {
335 int chnum;
336 u32 reg;
337 int shift;
338 } idmac_lock_en_info[] = {
339 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, },
340 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, },
341 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, },
342 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, },
343 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, },
344 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
345 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
346 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
347 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
348 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
349 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
350 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, },
351 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, },
352 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, },
353 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, },
354 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, },
355 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
356 };
357
358 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
359 {
360 struct ipu_soc *ipu = channel->ipu;
361 unsigned long flags;
362 u32 bursts, regval;
363 int i;
364
365 switch (num_bursts) {
366 case 0:
367 case 1:
368 bursts = 0x00; /* locking disabled */
369 break;
370 case 2:
371 bursts = 0x01;
372 break;
373 case 4:
374 bursts = 0x02;
375 break;
376 case 8:
377 bursts = 0x03;
378 break;
379 default:
380 return -EINVAL;
381 }
382
383 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
384 if (channel->num == idmac_lock_en_info[i].chnum)
385 break;
386 }
387 if (i >= ARRAY_SIZE(idmac_lock_en_info))
388 return -EINVAL;
389
390 spin_lock_irqsave(&ipu->lock, flags);
391
392 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
393 regval &= ~(0x03 << idmac_lock_en_info[i].shift);
394 regval |= (bursts << idmac_lock_en_info[i].shift);
395 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
396
397 spin_unlock_irqrestore(&ipu->lock, flags);
398
399 return 0;
400 }
401 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
402
403 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
404 {
405 unsigned long lock_flags;
406 u32 val;
407
408 spin_lock_irqsave(&ipu->lock, lock_flags);
409
410 val = ipu_cm_read(ipu, IPU_DISP_GEN);
411
412 if (mask & IPU_CONF_DI0_EN)
413 val |= IPU_DI0_COUNTER_RELEASE;
414 if (mask & IPU_CONF_DI1_EN)
415 val |= IPU_DI1_COUNTER_RELEASE;
416
417 ipu_cm_write(ipu, val, IPU_DISP_GEN);
418
419 val = ipu_cm_read(ipu, IPU_CONF);
420 val |= mask;
421 ipu_cm_write(ipu, val, IPU_CONF);
422
423 spin_unlock_irqrestore(&ipu->lock, lock_flags);
424
425 return 0;
426 }
427 EXPORT_SYMBOL_GPL(ipu_module_enable);
428
429 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
430 {
431 unsigned long lock_flags;
432 u32 val;
433
434 spin_lock_irqsave(&ipu->lock, lock_flags);
435
436 val = ipu_cm_read(ipu, IPU_CONF);
437 val &= ~mask;
438 ipu_cm_write(ipu, val, IPU_CONF);
439
440 val = ipu_cm_read(ipu, IPU_DISP_GEN);
441
442 if (mask & IPU_CONF_DI0_EN)
443 val &= ~IPU_DI0_COUNTER_RELEASE;
444 if (mask & IPU_CONF_DI1_EN)
445 val &= ~IPU_DI1_COUNTER_RELEASE;
446
447 ipu_cm_write(ipu, val, IPU_DISP_GEN);
448
449 spin_unlock_irqrestore(&ipu->lock, lock_flags);
450
451 return 0;
452 }
453 EXPORT_SYMBOL_GPL(ipu_module_disable);
454
455 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
456 {
457 struct ipu_soc *ipu = channel->ipu;
458 unsigned int chno = channel->num;
459
460 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
461 }
462 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
463
464 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
465 {
466 struct ipu_soc *ipu = channel->ipu;
467 unsigned long flags;
468 u32 reg = 0;
469
470 spin_lock_irqsave(&ipu->lock, flags);
471 switch (buf_num) {
472 case 0:
473 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
474 break;
475 case 1:
476 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
477 break;
478 case 2:
479 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
480 break;
481 }
482 spin_unlock_irqrestore(&ipu->lock, flags);
483
484 return ((reg & idma_mask(channel->num)) != 0);
485 }
486 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
487
488 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
489 {
490 struct ipu_soc *ipu = channel->ipu;
491 unsigned int chno = channel->num;
492 unsigned long flags;
493
494 spin_lock_irqsave(&ipu->lock, flags);
495
496 /* Mark buffer as ready. */
497 if (buf_num == 0)
498 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
499 else
500 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
501
502 spin_unlock_irqrestore(&ipu->lock, flags);
503 }
504 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
505
506 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
507 {
508 struct ipu_soc *ipu = channel->ipu;
509 unsigned int chno = channel->num;
510 unsigned long flags;
511
512 spin_lock_irqsave(&ipu->lock, flags);
513
514 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
515 switch (buf_num) {
516 case 0:
517 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
518 break;
519 case 1:
520 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
521 break;
522 case 2:
523 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
524 break;
525 default:
526 break;
527 }
528 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
529
530 spin_unlock_irqrestore(&ipu->lock, flags);
531 }
532 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
533
534 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
535 {
536 struct ipu_soc *ipu = channel->ipu;
537 u32 val;
538 unsigned long flags;
539
540 spin_lock_irqsave(&ipu->lock, flags);
541
542 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
543 val |= idma_mask(channel->num);
544 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
545
546 spin_unlock_irqrestore(&ipu->lock, flags);
547
548 return 0;
549 }
550 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
551
552 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
553 {
554 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
555 }
556 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
557
558 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
559 {
560 struct ipu_soc *ipu = channel->ipu;
561 unsigned long timeout;
562
563 timeout = jiffies + msecs_to_jiffies(ms);
564 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
565 idma_mask(channel->num)) {
566 if (time_after(jiffies, timeout))
567 return -ETIMEDOUT;
568 cpu_relax();
569 }
570
571 return 0;
572 }
573 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
574
575 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
576 {
577 unsigned long timeout;
578
579 timeout = jiffies + msecs_to_jiffies(ms);
580 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
581 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
582 if (time_after(jiffies, timeout))
583 return -ETIMEDOUT;
584 cpu_relax();
585 }
586
587 return 0;
588 }
589 EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
590
591 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
592 {
593 struct ipu_soc *ipu = channel->ipu;
594 u32 val;
595 unsigned long flags;
596
597 spin_lock_irqsave(&ipu->lock, flags);
598
599 /* Disable DMA channel(s) */
600 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
601 val &= ~idma_mask(channel->num);
602 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
603
604 __ipu_idmac_reset_current_buffer(channel);
605
606 /* Set channel buffers NOT to be ready */
607 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
608
609 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
610 idma_mask(channel->num)) {
611 ipu_cm_write(ipu, idma_mask(channel->num),
612 IPU_CHA_BUF0_RDY(channel->num));
613 }
614
615 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
616 idma_mask(channel->num)) {
617 ipu_cm_write(ipu, idma_mask(channel->num),
618 IPU_CHA_BUF1_RDY(channel->num));
619 }
620
621 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
622
623 /* Reset the double buffer */
624 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
625 val &= ~idma_mask(channel->num);
626 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
627
628 spin_unlock_irqrestore(&ipu->lock, flags);
629
630 return 0;
631 }
632 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
633
634 /*
635 * The imx6 rev. D TRM says that enabling the WM feature will increase
636 * a channel's priority. Refer to Table 36-8 Calculated priority value.
637 * The sub-module that is the sink or source for the channel must enable
638 * watermark signal for this to take effect (SMFC_WM for instance).
639 */
640 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
641 {
642 struct ipu_soc *ipu = channel->ipu;
643 unsigned long flags;
644 u32 val;
645
646 spin_lock_irqsave(&ipu->lock, flags);
647
648 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
649 if (enable)
650 val |= 1 << (channel->num % 32);
651 else
652 val &= ~(1 << (channel->num % 32));
653 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
654
655 spin_unlock_irqrestore(&ipu->lock, flags);
656 }
657 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
658
659 static int ipu_memory_reset(struct ipu_soc *ipu)
660 {
661 unsigned long timeout;
662
663 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
664
665 timeout = jiffies + msecs_to_jiffies(1000);
666 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
667 if (time_after(jiffies, timeout))
668 return -ETIME;
669 cpu_relax();
670 }
671
672 return 0;
673 }
674
675 /*
676 * Set the source mux for the given CSI. Selects either parallel or
677 * MIPI CSI2 sources.
678 */
679 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
680 {
681 unsigned long flags;
682 u32 val, mask;
683
684 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
685 IPU_CONF_CSI0_DATA_SOURCE;
686
687 spin_lock_irqsave(&ipu->lock, flags);
688
689 val = ipu_cm_read(ipu, IPU_CONF);
690 if (mipi_csi2)
691 val |= mask;
692 else
693 val &= ~mask;
694 ipu_cm_write(ipu, val, IPU_CONF);
695
696 spin_unlock_irqrestore(&ipu->lock, flags);
697 }
698 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
699
700 /*
701 * Set the source mux for the IC. Selects either CSI[01] or the VDI.
702 */
703 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
704 {
705 unsigned long flags;
706 u32 val;
707
708 spin_lock_irqsave(&ipu->lock, flags);
709
710 val = ipu_cm_read(ipu, IPU_CONF);
711 if (vdi) {
712 val |= IPU_CONF_IC_INPUT;
713 } else {
714 val &= ~IPU_CONF_IC_INPUT;
715 if (csi_id == 1)
716 val |= IPU_CONF_CSI_SEL;
717 else
718 val &= ~IPU_CONF_CSI_SEL;
719 }
720 ipu_cm_write(ipu, val, IPU_CONF);
721
722 spin_unlock_irqrestore(&ipu->lock, flags);
723 }
724 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
725
726 struct ipu_devtype {
727 const char *name;
728 unsigned long cm_ofs;
729 unsigned long cpmem_ofs;
730 unsigned long srm_ofs;
731 unsigned long tpm_ofs;
732 unsigned long csi0_ofs;
733 unsigned long csi1_ofs;
734 unsigned long ic_ofs;
735 unsigned long disp0_ofs;
736 unsigned long disp1_ofs;
737 unsigned long dc_tmpl_ofs;
738 unsigned long vdi_ofs;
739 enum ipuv3_type type;
740 };
741
742 static struct ipu_devtype ipu_type_imx51 = {
743 .name = "IPUv3EX",
744 .cm_ofs = 0x1e000000,
745 .cpmem_ofs = 0x1f000000,
746 .srm_ofs = 0x1f040000,
747 .tpm_ofs = 0x1f060000,
748 .csi0_ofs = 0x1f030000,
749 .csi1_ofs = 0x1f038000,
750 .ic_ofs = 0x1e020000,
751 .disp0_ofs = 0x1e040000,
752 .disp1_ofs = 0x1e048000,
753 .dc_tmpl_ofs = 0x1f080000,
754 .vdi_ofs = 0x1e068000,
755 .type = IPUV3EX,
756 };
757
758 static struct ipu_devtype ipu_type_imx53 = {
759 .name = "IPUv3M",
760 .cm_ofs = 0x06000000,
761 .cpmem_ofs = 0x07000000,
762 .srm_ofs = 0x07040000,
763 .tpm_ofs = 0x07060000,
764 .csi0_ofs = 0x07030000,
765 .csi1_ofs = 0x07038000,
766 .ic_ofs = 0x06020000,
767 .disp0_ofs = 0x06040000,
768 .disp1_ofs = 0x06048000,
769 .dc_tmpl_ofs = 0x07080000,
770 .vdi_ofs = 0x06068000,
771 .type = IPUV3M,
772 };
773
774 static struct ipu_devtype ipu_type_imx6q = {
775 .name = "IPUv3H",
776 .cm_ofs = 0x00200000,
777 .cpmem_ofs = 0x00300000,
778 .srm_ofs = 0x00340000,
779 .tpm_ofs = 0x00360000,
780 .csi0_ofs = 0x00230000,
781 .csi1_ofs = 0x00238000,
782 .ic_ofs = 0x00220000,
783 .disp0_ofs = 0x00240000,
784 .disp1_ofs = 0x00248000,
785 .dc_tmpl_ofs = 0x00380000,
786 .vdi_ofs = 0x00268000,
787 .type = IPUV3H,
788 };
789
790 static const struct of_device_id imx_ipu_dt_ids[] = {
791 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
792 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
793 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
794 { /* sentinel */ }
795 };
796 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
797
798 static int ipu_submodules_init(struct ipu_soc *ipu,
799 struct platform_device *pdev, unsigned long ipu_base,
800 struct clk *ipu_clk)
801 {
802 char *unit;
803 int ret;
804 struct device *dev = &pdev->dev;
805 const struct ipu_devtype *devtype = ipu->devtype;
806
807 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
808 if (ret) {
809 unit = "cpmem";
810 goto err_cpmem;
811 }
812
813 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
814 IPU_CONF_CSI0_EN, ipu_clk);
815 if (ret) {
816 unit = "csi0";
817 goto err_csi_0;
818 }
819
820 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
821 IPU_CONF_CSI1_EN, ipu_clk);
822 if (ret) {
823 unit = "csi1";
824 goto err_csi_1;
825 }
826
827 ret = ipu_ic_init(ipu, dev,
828 ipu_base + devtype->ic_ofs,
829 ipu_base + devtype->tpm_ofs);
830 if (ret) {
831 unit = "ic";
832 goto err_ic;
833 }
834
835 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
836 IPU_CONF_DI0_EN, ipu_clk);
837 if (ret) {
838 unit = "di0";
839 goto err_di_0;
840 }
841
842 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
843 IPU_CONF_DI1_EN, ipu_clk);
844 if (ret) {
845 unit = "di1";
846 goto err_di_1;
847 }
848
849 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
850 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
851 if (ret) {
852 unit = "dc_template";
853 goto err_dc;
854 }
855
856 ret = ipu_dmfc_init(ipu, dev, ipu_base +
857 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
858 if (ret) {
859 unit = "dmfc";
860 goto err_dmfc;
861 }
862
863 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
864 if (ret) {
865 unit = "dp";
866 goto err_dp;
867 }
868
869 ret = ipu_smfc_init(ipu, dev, ipu_base +
870 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
871 if (ret) {
872 unit = "smfc";
873 goto err_smfc;
874 }
875
876 return 0;
877
878 err_smfc:
879 ipu_dp_exit(ipu);
880 err_dp:
881 ipu_dmfc_exit(ipu);
882 err_dmfc:
883 ipu_dc_exit(ipu);
884 err_dc:
885 ipu_di_exit(ipu, 1);
886 err_di_1:
887 ipu_di_exit(ipu, 0);
888 err_di_0:
889 ipu_ic_exit(ipu);
890 err_ic:
891 ipu_csi_exit(ipu, 1);
892 err_csi_1:
893 ipu_csi_exit(ipu, 0);
894 err_csi_0:
895 ipu_cpmem_exit(ipu);
896 err_cpmem:
897 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
898 return ret;
899 }
900
901 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
902 {
903 unsigned long status;
904 int i, bit, irq;
905
906 for (i = 0; i < num_regs; i++) {
907
908 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
909 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
910
911 for_each_set_bit(bit, &status, 32) {
912 irq = irq_linear_revmap(ipu->domain,
913 regs[i] * 32 + bit);
914 if (irq)
915 generic_handle_irq(irq);
916 }
917 }
918 }
919
920 static void ipu_irq_handler(struct irq_desc *desc)
921 {
922 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
923 struct irq_chip *chip = irq_desc_get_chip(desc);
924 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
925
926 chained_irq_enter(chip, desc);
927
928 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
929
930 chained_irq_exit(chip, desc);
931 }
932
933 static void ipu_err_irq_handler(struct irq_desc *desc)
934 {
935 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
936 struct irq_chip *chip = irq_desc_get_chip(desc);
937 const int int_reg[] = { 4, 5, 8, 9};
938
939 chained_irq_enter(chip, desc);
940
941 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
942
943 chained_irq_exit(chip, desc);
944 }
945
946 int ipu_map_irq(struct ipu_soc *ipu, int irq)
947 {
948 int virq;
949
950 virq = irq_linear_revmap(ipu->domain, irq);
951 if (!virq)
952 virq = irq_create_mapping(ipu->domain, irq);
953
954 return virq;
955 }
956 EXPORT_SYMBOL_GPL(ipu_map_irq);
957
958 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
959 enum ipu_channel_irq irq_type)
960 {
961 return ipu_map_irq(ipu, irq_type + channel->num);
962 }
963 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
964
965 static void ipu_submodules_exit(struct ipu_soc *ipu)
966 {
967 ipu_smfc_exit(ipu);
968 ipu_dp_exit(ipu);
969 ipu_dmfc_exit(ipu);
970 ipu_dc_exit(ipu);
971 ipu_di_exit(ipu, 1);
972 ipu_di_exit(ipu, 0);
973 ipu_ic_exit(ipu);
974 ipu_csi_exit(ipu, 1);
975 ipu_csi_exit(ipu, 0);
976 ipu_cpmem_exit(ipu);
977 }
978
979 static int platform_remove_devices_fn(struct device *dev, void *unused)
980 {
981 struct platform_device *pdev = to_platform_device(dev);
982
983 platform_device_unregister(pdev);
984
985 return 0;
986 }
987
988 static void platform_device_unregister_children(struct platform_device *pdev)
989 {
990 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
991 }
992
993 struct ipu_platform_reg {
994 struct ipu_client_platformdata pdata;
995 const char *name;
996 int reg_offset;
997 };
998
999 static const struct ipu_platform_reg client_reg[] = {
1000 {
1001 .pdata = {
1002 .di = 0,
1003 .dc = 5,
1004 .dp = IPU_DP_FLOW_SYNC_BG,
1005 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1006 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
1007 },
1008 .name = "imx-ipuv3-crtc",
1009 }, {
1010 .pdata = {
1011 .di = 1,
1012 .dc = 1,
1013 .dp = -EINVAL,
1014 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1015 .dma[1] = -EINVAL,
1016 },
1017 .name = "imx-ipuv3-crtc",
1018 }, {
1019 .pdata = {
1020 .csi = 0,
1021 .dma[0] = IPUV3_CHANNEL_CSI0,
1022 .dma[1] = -EINVAL,
1023 },
1024 .reg_offset = IPU_CM_CSI0_REG_OFS,
1025 .name = "imx-ipuv3-camera",
1026 }, {
1027 .pdata = {
1028 .csi = 1,
1029 .dma[0] = IPUV3_CHANNEL_CSI1,
1030 .dma[1] = -EINVAL,
1031 },
1032 .reg_offset = IPU_CM_CSI1_REG_OFS,
1033 .name = "imx-ipuv3-camera",
1034 },
1035 };
1036
1037 static DEFINE_MUTEX(ipu_client_id_mutex);
1038 static int ipu_client_id;
1039
1040 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1041 {
1042 struct device *dev = ipu->dev;
1043 unsigned i;
1044 int id, ret;
1045
1046 mutex_lock(&ipu_client_id_mutex);
1047 id = ipu_client_id;
1048 ipu_client_id += ARRAY_SIZE(client_reg);
1049 mutex_unlock(&ipu_client_id_mutex);
1050
1051 for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1052 const struct ipu_platform_reg *reg = &client_reg[i];
1053 struct platform_device *pdev;
1054 struct resource res;
1055
1056 if (reg->reg_offset) {
1057 memset(&res, 0, sizeof(res));
1058 res.flags = IORESOURCE_MEM;
1059 res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset;
1060 res.end = res.start + PAGE_SIZE - 1;
1061 pdev = platform_device_register_resndata(dev, reg->name,
1062 id++, &res, 1, &reg->pdata, sizeof(reg->pdata));
1063 } else {
1064 pdev = platform_device_register_data(dev, reg->name,
1065 id++, &reg->pdata, sizeof(reg->pdata));
1066 }
1067
1068 if (IS_ERR(pdev)) {
1069 ret = PTR_ERR(pdev);
1070 goto err_register;
1071 }
1072 }
1073
1074 return 0;
1075
1076 err_register:
1077 platform_device_unregister_children(to_platform_device(dev));
1078
1079 return ret;
1080 }
1081
1082
1083 static int ipu_irq_init(struct ipu_soc *ipu)
1084 {
1085 struct irq_chip_generic *gc;
1086 struct irq_chip_type *ct;
1087 unsigned long unused[IPU_NUM_IRQS / 32] = {
1088 0x400100d0, 0xffe000fd,
1089 0x400100d0, 0xffe000fd,
1090 0x400100d0, 0xffe000fd,
1091 0x4077ffff, 0xffe7e1fd,
1092 0x23fffffe, 0x8880fff0,
1093 0xf98fe7d0, 0xfff81fff,
1094 0x400100d0, 0xffe000fd,
1095 0x00000000,
1096 };
1097 int ret, i;
1098
1099 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1100 &irq_generic_chip_ops, ipu);
1101 if (!ipu->domain) {
1102 dev_err(ipu->dev, "failed to add irq domain\n");
1103 return -ENODEV;
1104 }
1105
1106 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1107 handle_level_irq, 0, 0, 0);
1108 if (ret < 0) {
1109 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1110 irq_domain_remove(ipu->domain);
1111 return ret;
1112 }
1113
1114 for (i = 0; i < IPU_NUM_IRQS; i += 32)
1115 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1116
1117 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1118 gc = irq_get_domain_generic_chip(ipu->domain, i);
1119 gc->reg_base = ipu->cm_reg;
1120 gc->unused = unused[i / 32];
1121 ct = gc->chip_types;
1122 ct->chip.irq_ack = irq_gc_ack_set_bit;
1123 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1124 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1125 ct->regs.ack = IPU_INT_STAT(i / 32);
1126 ct->regs.mask = IPU_INT_CTRL(i / 32);
1127 }
1128
1129 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1130 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1131 ipu);
1132
1133 return 0;
1134 }
1135
1136 static void ipu_irq_exit(struct ipu_soc *ipu)
1137 {
1138 int i, irq;
1139
1140 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1141 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1142
1143 /* TODO: remove irq_domain_generic_chips */
1144
1145 for (i = 0; i < IPU_NUM_IRQS; i++) {
1146 irq = irq_linear_revmap(ipu->domain, i);
1147 if (irq)
1148 irq_dispose_mapping(irq);
1149 }
1150
1151 irq_domain_remove(ipu->domain);
1152 }
1153
1154 void ipu_dump(struct ipu_soc *ipu)
1155 {
1156 int i;
1157
1158 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1159 ipu_cm_read(ipu, IPU_CONF));
1160 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1161 ipu_idmac_read(ipu, IDMAC_CONF));
1162 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1163 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1164 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1165 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1166 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1167 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1168 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1169 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1170 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1171 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1172 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1173 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1174 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1175 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1176 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1177 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1178 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1179 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1180 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1181 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1182 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1183 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1184 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1185 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1186 for (i = 0; i < 15; i++)
1187 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1188 ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1189 }
1190 EXPORT_SYMBOL_GPL(ipu_dump);
1191
1192 static int ipu_probe(struct platform_device *pdev)
1193 {
1194 const struct of_device_id *of_id =
1195 of_match_device(imx_ipu_dt_ids, &pdev->dev);
1196 struct ipu_soc *ipu;
1197 struct resource *res;
1198 unsigned long ipu_base;
1199 int i, ret, irq_sync, irq_err;
1200 const struct ipu_devtype *devtype;
1201
1202 devtype = of_id->data;
1203
1204 irq_sync = platform_get_irq(pdev, 0);
1205 irq_err = platform_get_irq(pdev, 1);
1206 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1207
1208 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1209 irq_sync, irq_err);
1210
1211 if (!res || irq_sync < 0 || irq_err < 0)
1212 return -ENODEV;
1213
1214 ipu_base = res->start;
1215
1216 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1217 if (!ipu)
1218 return -ENODEV;
1219
1220 for (i = 0; i < 64; i++)
1221 ipu->channel[i].ipu = ipu;
1222 ipu->devtype = devtype;
1223 ipu->ipu_type = devtype->type;
1224
1225 spin_lock_init(&ipu->lock);
1226 mutex_init(&ipu->channel_lock);
1227
1228 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
1229 ipu_base + devtype->cm_ofs);
1230 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
1231 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1232 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
1233 ipu_base + devtype->cpmem_ofs);
1234 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
1235 ipu_base + devtype->csi0_ofs);
1236 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
1237 ipu_base + devtype->csi1_ofs);
1238 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1239 ipu_base + devtype->ic_ofs);
1240 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
1241 ipu_base + devtype->disp0_ofs);
1242 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
1243 ipu_base + devtype->disp1_ofs);
1244 dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
1245 ipu_base + devtype->srm_ofs);
1246 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
1247 ipu_base + devtype->tpm_ofs);
1248 dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
1249 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1250 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1251 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1252 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
1253 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1254 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
1255 ipu_base + devtype->vdi_ofs);
1256
1257 ipu->cm_reg = devm_ioremap(&pdev->dev,
1258 ipu_base + devtype->cm_ofs, PAGE_SIZE);
1259 ipu->idmac_reg = devm_ioremap(&pdev->dev,
1260 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1261 PAGE_SIZE);
1262
1263 if (!ipu->cm_reg || !ipu->idmac_reg)
1264 return -ENOMEM;
1265
1266 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1267 if (IS_ERR(ipu->clk)) {
1268 ret = PTR_ERR(ipu->clk);
1269 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1270 return ret;
1271 }
1272
1273 platform_set_drvdata(pdev, ipu);
1274
1275 ret = clk_prepare_enable(ipu->clk);
1276 if (ret) {
1277 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1278 return ret;
1279 }
1280
1281 ipu->dev = &pdev->dev;
1282 ipu->irq_sync = irq_sync;
1283 ipu->irq_err = irq_err;
1284
1285 ret = ipu_irq_init(ipu);
1286 if (ret)
1287 goto out_failed_irq;
1288
1289 ret = device_reset(&pdev->dev);
1290 if (ret) {
1291 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1292 goto out_failed_reset;
1293 }
1294 ret = ipu_memory_reset(ipu);
1295 if (ret)
1296 goto out_failed_reset;
1297
1298 /* Set MCU_T to divide MCU access window into 2 */
1299 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1300 IPU_DISP_GEN);
1301
1302 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1303 if (ret)
1304 goto failed_submodules_init;
1305
1306 ret = ipu_add_client_devices(ipu, ipu_base);
1307 if (ret) {
1308 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1309 ret);
1310 goto failed_add_clients;
1311 }
1312
1313 dev_info(&pdev->dev, "%s probed\n", devtype->name);
1314
1315 return 0;
1316
1317 failed_add_clients:
1318 ipu_submodules_exit(ipu);
1319 failed_submodules_init:
1320 out_failed_reset:
1321 ipu_irq_exit(ipu);
1322 out_failed_irq:
1323 clk_disable_unprepare(ipu->clk);
1324 return ret;
1325 }
1326
1327 static int ipu_remove(struct platform_device *pdev)
1328 {
1329 struct ipu_soc *ipu = platform_get_drvdata(pdev);
1330
1331 platform_device_unregister_children(pdev);
1332 ipu_submodules_exit(ipu);
1333 ipu_irq_exit(ipu);
1334
1335 clk_disable_unprepare(ipu->clk);
1336
1337 return 0;
1338 }
1339
1340 static struct platform_driver imx_ipu_driver = {
1341 .driver = {
1342 .name = "imx-ipuv3",
1343 .of_match_table = imx_ipu_dt_ids,
1344 },
1345 .probe = ipu_probe,
1346 .remove = ipu_remove,
1347 };
1348
1349 module_platform_driver(imx_ipu_driver);
1350
1351 MODULE_ALIAS("platform:imx-ipuv3");
1352 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1353 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1354 MODULE_LICENSE("GPL");
Linux with added FPC-III support