drivers/i2c/busses/i2c-isch.c

   1 /*
   2     i2c-isch.c - Linux kernel driver for Intel SCH chipset SMBus
   3     - Based on i2c-piix4.c
   4     Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
   5     Philip Edelbrock <phil@netroedge.com>
   6     - Intel SCH support
   7     Copyright (c) 2007 - 2008 Jacob Jun Pan <jacob.jun.pan@intel.com>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License version 2 as
  11     published by the Free Software Foundation.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17 */
  18
  19 /*
  20    Supports:
  21         Intel SCH chipsets (AF82US15W, AF82US15L, AF82UL11L)
  22    Note: we assume there can only be one device, with one SMBus interface.
  23 */
  24
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/kernel.h>
  28 #include <linux/delay.h>
  29 #include <linux/stddef.h>
  30 #include <linux/ioport.h>
  31 #include <linux/i2c.h>
  32 #include <linux/io.h>
  33 #include <linux/acpi.h>
  34
  35 /* SCH SMBus address offsets */
  36 #define SMBHSTCNT       (0 + sch_smba)
  37 #define SMBHSTSTS       (1 + sch_smba)
  38 #define SMBHSTCLK       (2 + sch_smba)
  39 #define SMBHSTADD       (4 + sch_smba) /* TSA */
  40 #define SMBHSTCMD       (5 + sch_smba)
  41 #define SMBHSTDAT0      (6 + sch_smba)
  42 #define SMBHSTDAT1      (7 + sch_smba)
  43 #define SMBBLKDAT       (0x20 + sch_smba)
  44
  45 /* Other settings */
  46 #define MAX_RETRIES     5000
  47
  48 /* I2C constants */
  49 #define SCH_QUICK               0x00
  50 #define SCH_BYTE                0x01
  51 #define SCH_BYTE_DATA           0x02
  52 #define SCH_WORD_DATA           0x03
  53 #define SCH_BLOCK_DATA          0x05
  54
  55 static unsigned short sch_smba;
  56 static struct i2c_adapter sch_adapter;
  57 static int backbone_speed = 33000; /* backbone speed in kHz */
  58 module_param(backbone_speed, int, S_IRUSR | S_IWUSR);
  59 MODULE_PARM_DESC(backbone_speed, "Backbone speed in kHz, (default = 33000)");
  60
  61 /*
  62  * Start the i2c transaction -- the i2c_access will prepare the transaction
  63  * and this function will execute it.
  64  * return 0 for success and others for failure.
  65  */
  66 static int sch_transaction(void)
  67 {
  68         int temp;
  69         int result = 0;
  70         int retries = 0;
  71
  72         dev_dbg(&sch_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
  73                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
  74                 inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
  75                 inb(SMBHSTDAT1));
  76
  77         /* Make sure the SMBus host is ready to start transmitting */
  78         temp = inb(SMBHSTSTS) & 0x0f;
  79         if (temp) {
  80                 /* Can not be busy since we checked it in sch_access */
  81                 if (temp & 0x01) {
  82                         dev_dbg(&sch_adapter.dev, "Completion (%02x). "
  83                                 "Clear...\n", temp);
  84                 }
  85                 if (temp & 0x06) {
  86                         dev_dbg(&sch_adapter.dev, "SMBus error (%02x). "
  87                                 "Resetting...\n", temp);
  88                 }
  89                 outb(temp, SMBHSTSTS);
  90                 temp = inb(SMBHSTSTS) & 0x0f;
  91                 if (temp) {
  92                         dev_err(&sch_adapter.dev,
  93                                 "SMBus is not ready: (%02x)\n", temp);
  94                         return -EAGAIN;
  95                 }
  96         }
  97
  98         /* start the transaction by setting bit 4 */
  99         outb(inb(SMBHSTCNT) | 0x10, SMBHSTCNT);
 100
 101         do {
 102                 usleep_range(100, 200);
 103                 temp = inb(SMBHSTSTS) & 0x0f;
 104         } while ((temp & 0x08) && (retries++ < MAX_RETRIES));
 105
 106         /* If the SMBus is still busy, we give up */
 107         if (retries > MAX_RETRIES) {
 108                 dev_err(&sch_adapter.dev, "SMBus Timeout!\n");
 109                 result = -ETIMEDOUT;
 110         }
 111         if (temp & 0x04) {
 112                 result = -EIO;
 113                 dev_dbg(&sch_adapter.dev, "Bus collision! SMBus may be "
 114                         "locked until next hard reset. (sorry!)\n");
 115                 /* Clock stops and slave is stuck in mid-transmission */
 116         } else if (temp & 0x02) {
 117                 result = -EIO;
 118                 dev_err(&sch_adapter.dev, "Error: no response!\n");
 119         } else if (temp & 0x01) {
 120                 dev_dbg(&sch_adapter.dev, "Post complete!\n");
 121                 outb(temp, SMBHSTSTS);
 122                 temp = inb(SMBHSTSTS) & 0x07;
 123                 if (temp & 0x06) {
 124                         /* Completion clear failed */
 125                         dev_dbg(&sch_adapter.dev, "Failed reset at end of "
 126                                 "transaction (%02x), Bus error!\n", temp);
 127                 }
 128         } else {
 129                 result = -ENXIO;
 130                 dev_dbg(&sch_adapter.dev, "No such address.\n");
 131         }
 132         dev_dbg(&sch_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
 133                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
 134                 inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
 135                 inb(SMBHSTDAT1));
 136         return result;
 137 }
 138
 139 /*
 140  * This is the main access entry for i2c-sch access
 141  * adap is i2c_adapter pointer, addr is the i2c device bus address, read_write
 142  * (0 for read and 1 for write), size is i2c transaction type and data is the
 143  * union of transaction for data to be transferred or data read from bus.
 144  * return 0 for success and others for failure.
 145  */
 146 static s32 sch_access(struct i2c_adapter *adap, u16 addr,
 147                  unsigned short flags, char read_write,
 148                  u8 command, int size, union i2c_smbus_data *data)
 149 {
 150         int i, len, temp, rc;
 151
 152         /* Make sure the SMBus host is not busy */
 153         temp = inb(SMBHSTSTS) & 0x0f;
 154         if (temp & 0x08) {
 155                 dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp);
 156                 return -EAGAIN;
 157         }
 158         temp = inw(SMBHSTCLK);
 159         if (!temp) {
 160                 /*
 161                  * We can't determine if we have 33 or 25 MHz clock for
 162                  * SMBus, so expect 33 MHz and calculate a bus clock of
 163                  * 100 kHz. If we actually run at 25 MHz the bus will be
 164                  * run ~75 kHz instead which should do no harm.
 165                  */
 166                 dev_notice(&sch_adapter.dev,
 167                         "Clock divider unitialized. Setting defaults\n");
 168                 outw(backbone_speed / (4 * 100), SMBHSTCLK);
 169         }
 170
 171         dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size,
 172                 (read_write)?"READ":"WRITE");
 173         switch (size) {
 174         case I2C_SMBUS_QUICK:
 175                 outb((addr << 1) | read_write, SMBHSTADD);
 176                 size = SCH_QUICK;
 177                 break;
 178         case I2C_SMBUS_BYTE:
 179                 outb((addr << 1) | read_write, SMBHSTADD);
 180                 if (read_write == I2C_SMBUS_WRITE)
 181                         outb(command, SMBHSTCMD);
 182                 size = SCH_BYTE;
 183                 break;
 184         case I2C_SMBUS_BYTE_DATA:
 185                 outb((addr << 1) | read_write, SMBHSTADD);
 186                 outb(command, SMBHSTCMD);
 187                 if (read_write == I2C_SMBUS_WRITE)
 188                         outb(data->byte, SMBHSTDAT0);
 189                 size = SCH_BYTE_DATA;
 190                 break;
 191         case I2C_SMBUS_WORD_DATA:
 192                 outb((addr << 1) | read_write, SMBHSTADD);
 193                 outb(command, SMBHSTCMD);
 194                 if (read_write == I2C_SMBUS_WRITE) {
 195                         outb(data->word & 0xff, SMBHSTDAT0);
 196                         outb((data->word & 0xff00) >> 8, SMBHSTDAT1);
 197                 }
 198                 size = SCH_WORD_DATA;
 199                 break;
 200         case I2C_SMBUS_BLOCK_DATA:
 201                 outb((addr << 1) | read_write, SMBHSTADD);
 202                 outb(command, SMBHSTCMD);
 203                 if (read_write == I2C_SMBUS_WRITE) {
 204                         len = data->block[0];
 205                         if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
 206                                 return -EINVAL;
 207                         outb(len, SMBHSTDAT0);
 208                         for (i = 1; i <= len; i++)
 209                                 outb(data->block[i], SMBBLKDAT+i-1);
 210                 }
 211                 size = SCH_BLOCK_DATA;
 212                 break;
 213         default:
 214                 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
 215                 return -EOPNOTSUPP;
 216         }
 217         dev_dbg(&sch_adapter.dev, "write size %d to 0x%04x\n", size, SMBHSTCNT);
 218         outb((inb(SMBHSTCNT) & 0xb0) | (size & 0x7), SMBHSTCNT);
 219
 220         rc = sch_transaction();
 221         if (rc) /* Error in transaction */
 222                 return rc;
 223
 224         if ((read_write == I2C_SMBUS_WRITE) || (size == SCH_QUICK))
 225                 return 0;
 226
 227         switch (size) {
 228         case SCH_BYTE:
 229         case SCH_BYTE_DATA:
 230                 data->byte = inb(SMBHSTDAT0);
 231                 break;
 232         case SCH_WORD_DATA:
 233                 data->word = inb(SMBHSTDAT0) + (inb(SMBHSTDAT1) << 8);
 234                 break;
 235         case SCH_BLOCK_DATA:
 236                 data->block[0] = inb(SMBHSTDAT0);
 237                 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 238                         return -EPROTO;
 239                 for (i = 1; i <= data->block[0]; i++)
 240                         data->block[i] = inb(SMBBLKDAT+i-1);
 241                 break;
 242         }
 243         return 0;
 244 }
 245
 246 static u32 sch_func(struct i2c_adapter *adapter)
 247 {
 248         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 249             I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 250             I2C_FUNC_SMBUS_BLOCK_DATA;
 251 }
 252
 253 static const struct i2c_algorithm smbus_algorithm = {
 254         .smbus_xfer     = sch_access,
 255         .functionality  = sch_func,
 256 };
 257
 258 static struct i2c_adapter sch_adapter = {
 259         .owner          = THIS_MODULE,
 260         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 261         .algo           = &smbus_algorithm,
 262 };
 263
 264 static int smbus_sch_probe(struct platform_device *dev)
 265 {
 266         struct resource *res;
 267         int retval;
 268
 269         res = platform_get_resource(dev, IORESOURCE_IO, 0);
 270         if (!res)
 271                 return -EBUSY;
 272
 273         if (!devm_request_region(&dev->dev, res->start, resource_size(res),
 274                                  dev->name)) {
 275                 dev_err(&dev->dev, "SMBus region 0x%x already in use!\n",
 276                         sch_smba);
 277                 return -EBUSY;
 278         }
 279
 280         sch_smba = res->start;
 281
 282         dev_dbg(&dev->dev, "SMBA = 0x%X\n", sch_smba);
 283
 284         /* set up the sysfs linkage to our parent device */
 285         sch_adapter.dev.parent = &dev->dev;
 286
 287         snprintf(sch_adapter.name, sizeof(sch_adapter.name),
 288                 "SMBus SCH adapter at %04x", sch_smba);
 289
 290         retval = i2c_add_adapter(&sch_adapter);
 291         if (retval) {
 292                 dev_err(&dev->dev, "Couldn't register adapter!\n");
 293                 sch_smba = 0;
 294         }
 295
 296         return retval;
 297 }
 298
 299 static int smbus_sch_remove(struct platform_device *pdev)
 300 {
 301         if (sch_smba) {
 302                 i2c_del_adapter(&sch_adapter);
 303                 sch_smba = 0;
 304         }
 305
 306         return 0;
 307 }
 308
 309 static struct platform_driver smbus_sch_driver = {
 310         .driver = {
 311                 .name = "isch_smbus",
 312         },
 313         .probe          = smbus_sch_probe,
 314         .remove         = smbus_sch_remove,
 315 };
 316
 317 module_platform_driver(smbus_sch_driver);
 318
 319 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
 320 MODULE_DESCRIPTION("Intel SCH SMBus driver");
 321 MODULE_LICENSE("GPL");
 322 MODULE_ALIAS("platform:isch_smbus");