2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
5 * Author: Mark A. Greer <mgreer@mvista.com>
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/reset.h>
23 #include <linux/of_device.h>
24 #include <linux/of_irq.h>
25 #include <linux/clk.h>
26 #include <linux/err.h>
27 #include <linux/delay.h>
29 #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
30 #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
31 #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
33 #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2)
34 #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3)
35 #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4)
36 #define MV64XXX_I2C_REG_CONTROL_START BIT(5)
37 #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6)
38 #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7)
40 /* Ctlr status values */
41 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
42 #define MV64XXX_I2C_STATUS_MAST_START 0x08
43 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
44 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
45 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
46 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
47 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
48 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
49 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
50 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
51 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
52 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
53 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
54 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
55 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
56 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
57 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
59 /* Register defines (I2C bridge) */
60 #define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
61 #define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
62 #define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
63 #define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
64 #define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
65 #define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
66 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
67 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
68 #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
70 /* Bridge Control values */
71 #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0)
72 #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1)
73 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
74 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12)
75 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
76 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
77 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19)
78 #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20)
80 /* Bridge Status values */
81 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0)
85 MV64XXX_I2C_STATE_INVALID
,
86 MV64XXX_I2C_STATE_IDLE
,
87 MV64XXX_I2C_STATE_WAITING_FOR_START_COND
,
88 MV64XXX_I2C_STATE_WAITING_FOR_RESTART
,
89 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK
,
90 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK
,
91 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK
,
92 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA
,
97 MV64XXX_I2C_ACTION_INVALID
,
98 MV64XXX_I2C_ACTION_CONTINUE
,
99 MV64XXX_I2C_ACTION_SEND_RESTART
,
100 MV64XXX_I2C_ACTION_SEND_ADDR_1
,
101 MV64XXX_I2C_ACTION_SEND_ADDR_2
,
102 MV64XXX_I2C_ACTION_SEND_DATA
,
103 MV64XXX_I2C_ACTION_RCV_DATA
,
104 MV64XXX_I2C_ACTION_RCV_DATA_STOP
,
105 MV64XXX_I2C_ACTION_SEND_STOP
,
108 struct mv64xxx_i2c_regs
{
118 struct mv64xxx_i2c_data
{
119 struct i2c_msg
*msgs
;
126 void __iomem
*reg_base
;
127 struct mv64xxx_i2c_regs reg_offsets
;
137 #if defined(CONFIG_HAVE_CLK)
140 wait_queue_head_t waitq
;
143 struct i2c_adapter adapter
;
144 bool offload_enabled
;
145 /* 5us delay in order to avoid repeated start timing violation */
147 struct reset_control
*rstc
;
148 bool irq_clear_inverted
;
151 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx
= {
161 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i
= {
172 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data
*drv_data
,
177 drv_data
->cntl_bits
= MV64XXX_I2C_REG_CONTROL_ACK
|
178 MV64XXX_I2C_REG_CONTROL_INTEN
| MV64XXX_I2C_REG_CONTROL_TWSIEN
;
180 if (msg
->flags
& I2C_M_RD
)
183 if (msg
->flags
& I2C_M_TEN
) {
184 drv_data
->addr1
= 0xf0 | (((u32
)msg
->addr
& 0x300) >> 7) | dir
;
185 drv_data
->addr2
= (u32
)msg
->addr
& 0xff;
187 drv_data
->addr1
= MV64XXX_I2C_ADDR_ADDR((u32
)msg
->addr
) | dir
;
193 *****************************************************************************
195 * Finite State Machine & Interrupt Routines
197 *****************************************************************************
200 /* Reset hardware and initialize FSM */
202 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data
*drv_data
)
204 if (drv_data
->offload_enabled
) {
205 writel(0, drv_data
->reg_base
+ MV64XXX_I2C_REG_BRIDGE_CONTROL
);
206 writel(0, drv_data
->reg_base
+ MV64XXX_I2C_REG_BRIDGE_TIMING
);
207 writel(0, drv_data
->reg_base
+
208 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE
);
209 writel(0, drv_data
->reg_base
+
210 MV64XXX_I2C_REG_BRIDGE_INTR_MASK
);
213 writel(0, drv_data
->reg_base
+ drv_data
->reg_offsets
.soft_reset
);
214 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data
->freq_m
) | MV64XXX_I2C_BAUD_DIV_N(drv_data
->freq_n
),
215 drv_data
->reg_base
+ drv_data
->reg_offsets
.clock
);
216 writel(0, drv_data
->reg_base
+ drv_data
->reg_offsets
.addr
);
217 writel(0, drv_data
->reg_base
+ drv_data
->reg_offsets
.ext_addr
);
218 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN
| MV64XXX_I2C_REG_CONTROL_STOP
,
219 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
220 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
224 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data
*drv_data
, u32 status
)
227 * If state is idle, then this is likely the remnants of an old
228 * operation that driver has given up on or the user has killed.
229 * If so, issue the stop condition and go to idle.
231 if (drv_data
->state
== MV64XXX_I2C_STATE_IDLE
) {
232 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_STOP
;
236 /* The status from the ctlr [mostly] tells us what to do next */
238 /* Start condition interrupt */
239 case MV64XXX_I2C_STATUS_MAST_START
: /* 0x08 */
240 case MV64XXX_I2C_STATUS_MAST_REPEAT_START
: /* 0x10 */
241 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_ADDR_1
;
242 drv_data
->state
= MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK
;
245 /* Performing a write */
246 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK
: /* 0x18 */
247 if (drv_data
->msg
->flags
& I2C_M_TEN
) {
248 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_ADDR_2
;
250 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK
;
254 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK
: /* 0xd0 */
255 case MV64XXX_I2C_STATUS_MAST_WR_ACK
: /* 0x28 */
256 if ((drv_data
->bytes_left
== 0)
257 || (drv_data
->aborting
258 && (drv_data
->byte_posn
!= 0))) {
259 if (drv_data
->send_stop
|| drv_data
->aborting
) {
260 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_STOP
;
261 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
264 MV64XXX_I2C_ACTION_SEND_RESTART
;
266 MV64XXX_I2C_STATE_WAITING_FOR_RESTART
;
269 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_DATA
;
271 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK
;
272 drv_data
->bytes_left
--;
276 /* Performing a read */
277 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK
: /* 40 */
278 if (drv_data
->msg
->flags
& I2C_M_TEN
) {
279 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_ADDR_2
;
281 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK
;
285 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK
: /* 0xe0 */
286 if (drv_data
->bytes_left
== 0) {
287 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_STOP
;
288 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
292 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK
: /* 0x50 */
293 if (status
!= MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK
)
294 drv_data
->action
= MV64XXX_I2C_ACTION_CONTINUE
;
296 drv_data
->action
= MV64XXX_I2C_ACTION_RCV_DATA
;
297 drv_data
->bytes_left
--;
299 drv_data
->state
= MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA
;
301 if ((drv_data
->bytes_left
== 1) || drv_data
->aborting
)
302 drv_data
->cntl_bits
&= ~MV64XXX_I2C_REG_CONTROL_ACK
;
305 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK
: /* 0x58 */
306 drv_data
->action
= MV64XXX_I2C_ACTION_RCV_DATA_STOP
;
307 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
310 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK
: /* 0x20 */
311 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK
: /* 30 */
312 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK
: /* 48 */
313 /* Doesn't seem to be a device at other end */
314 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_STOP
;
315 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
316 drv_data
->rc
= -ENXIO
;
320 dev_err(&drv_data
->adapter
.dev
,
321 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
322 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
323 drv_data
->state
, status
, drv_data
->msg
->addr
,
324 drv_data
->msg
->flags
);
325 drv_data
->action
= MV64XXX_I2C_ACTION_SEND_STOP
;
326 mv64xxx_i2c_hw_init(drv_data
);
331 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data
*drv_data
)
333 drv_data
->msg
= drv_data
->msgs
;
334 drv_data
->byte_posn
= 0;
335 drv_data
->bytes_left
= drv_data
->msg
->len
;
336 drv_data
->aborting
= 0;
339 mv64xxx_i2c_prepare_for_io(drv_data
, drv_data
->msgs
);
340 writel(drv_data
->cntl_bits
| MV64XXX_I2C_REG_CONTROL_START
,
341 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
345 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data
*drv_data
)
347 switch(drv_data
->action
) {
348 case MV64XXX_I2C_ACTION_SEND_RESTART
:
349 /* We should only get here if we have further messages */
350 BUG_ON(drv_data
->num_msgs
== 0);
353 drv_data
->num_msgs
--;
354 mv64xxx_i2c_send_start(drv_data
);
356 if (drv_data
->errata_delay
)
360 * We're never at the start of the message here, and by this
361 * time it's already too late to do any protocol mangling.
362 * Thankfully, do not advertise support for that feature.
364 drv_data
->send_stop
= drv_data
->num_msgs
== 1;
367 case MV64XXX_I2C_ACTION_CONTINUE
:
368 writel(drv_data
->cntl_bits
,
369 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
372 case MV64XXX_I2C_ACTION_SEND_ADDR_1
:
373 writel(drv_data
->addr1
,
374 drv_data
->reg_base
+ drv_data
->reg_offsets
.data
);
375 writel(drv_data
->cntl_bits
,
376 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
379 case MV64XXX_I2C_ACTION_SEND_ADDR_2
:
380 writel(drv_data
->addr2
,
381 drv_data
->reg_base
+ drv_data
->reg_offsets
.data
);
382 writel(drv_data
->cntl_bits
,
383 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
386 case MV64XXX_I2C_ACTION_SEND_DATA
:
387 writel(drv_data
->msg
->buf
[drv_data
->byte_posn
++],
388 drv_data
->reg_base
+ drv_data
->reg_offsets
.data
);
389 writel(drv_data
->cntl_bits
,
390 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
393 case MV64XXX_I2C_ACTION_RCV_DATA
:
394 drv_data
->msg
->buf
[drv_data
->byte_posn
++] =
395 readl(drv_data
->reg_base
+ drv_data
->reg_offsets
.data
);
396 writel(drv_data
->cntl_bits
,
397 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
400 case MV64XXX_I2C_ACTION_RCV_DATA_STOP
:
401 drv_data
->msg
->buf
[drv_data
->byte_posn
++] =
402 readl(drv_data
->reg_base
+ drv_data
->reg_offsets
.data
);
403 drv_data
->cntl_bits
&= ~MV64XXX_I2C_REG_CONTROL_INTEN
;
404 writel(drv_data
->cntl_bits
| MV64XXX_I2C_REG_CONTROL_STOP
,
405 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
407 if (drv_data
->errata_delay
)
410 wake_up(&drv_data
->waitq
);
413 case MV64XXX_I2C_ACTION_INVALID
:
415 dev_err(&drv_data
->adapter
.dev
,
416 "mv64xxx_i2c_do_action: Invalid action: %d\n",
421 case MV64XXX_I2C_ACTION_SEND_STOP
:
422 drv_data
->cntl_bits
&= ~MV64XXX_I2C_REG_CONTROL_INTEN
;
423 writel(drv_data
->cntl_bits
| MV64XXX_I2C_REG_CONTROL_STOP
,
424 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
426 wake_up(&drv_data
->waitq
);
432 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data
*drv_data
,
437 buf
[0] = readl(drv_data
->reg_base
+ MV64XXX_I2C_REG_RX_DATA_LO
);
438 buf
[1] = readl(drv_data
->reg_base
+ MV64XXX_I2C_REG_RX_DATA_HI
);
440 memcpy(msg
->buf
, buf
, msg
->len
);
444 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data
*drv_data
)
448 cause
= readl(drv_data
->reg_base
+
449 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE
);
453 status
= readl(drv_data
->reg_base
+
454 MV64XXX_I2C_REG_BRIDGE_STATUS
);
456 if (status
& MV64XXX_I2C_BRIDGE_STATUS_ERROR
) {
464 * Transaction is a one message read transaction, read data
467 if (drv_data
->num_msgs
== 1 && drv_data
->msgs
[0].flags
& I2C_M_RD
) {
468 mv64xxx_i2c_read_offload_rx_data(drv_data
, drv_data
->msgs
);
470 drv_data
->num_msgs
--;
473 * Transaction is a two messages write/read transaction, read
474 * data for the second (read) message.
476 else if (drv_data
->num_msgs
== 2 &&
477 !(drv_data
->msgs
[0].flags
& I2C_M_RD
) &&
478 drv_data
->msgs
[1].flags
& I2C_M_RD
) {
479 mv64xxx_i2c_read_offload_rx_data(drv_data
, drv_data
->msgs
+ 1);
481 drv_data
->num_msgs
-= 2;
485 writel(0, drv_data
->reg_base
+ MV64XXX_I2C_REG_BRIDGE_CONTROL
);
486 writel(0, drv_data
->reg_base
+
487 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE
);
490 wake_up(&drv_data
->waitq
);
496 mv64xxx_i2c_intr(int irq
, void *dev_id
)
498 struct mv64xxx_i2c_data
*drv_data
= dev_id
;
501 irqreturn_t rc
= IRQ_NONE
;
503 spin_lock_irqsave(&drv_data
->lock
, flags
);
505 if (drv_data
->offload_enabled
)
506 rc
= mv64xxx_i2c_intr_offload(drv_data
);
508 while (readl(drv_data
->reg_base
+ drv_data
->reg_offsets
.control
) &
509 MV64XXX_I2C_REG_CONTROL_IFLG
) {
510 status
= readl(drv_data
->reg_base
+ drv_data
->reg_offsets
.status
);
511 mv64xxx_i2c_fsm(drv_data
, status
);
512 mv64xxx_i2c_do_action(drv_data
);
514 if (drv_data
->irq_clear_inverted
)
515 writel(drv_data
->cntl_bits
| MV64XXX_I2C_REG_CONTROL_IFLG
,
516 drv_data
->reg_base
+ drv_data
->reg_offsets
.control
);
520 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
526 *****************************************************************************
528 * I2C Msg Execution Routines
530 *****************************************************************************
533 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data
*drv_data
)
539 time_left
= wait_event_timeout(drv_data
->waitq
,
540 !drv_data
->block
, drv_data
->adapter
.timeout
);
542 spin_lock_irqsave(&drv_data
->lock
, flags
);
543 if (!time_left
) { /* Timed out */
544 drv_data
->rc
= -ETIMEDOUT
;
546 } else if (time_left
< 0) { /* Interrupted/Error */
547 drv_data
->rc
= time_left
; /* errno value */
551 if (abort
&& drv_data
->block
) {
552 drv_data
->aborting
= 1;
553 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
555 time_left
= wait_event_timeout(drv_data
->waitq
,
556 !drv_data
->block
, drv_data
->adapter
.timeout
);
558 if ((time_left
<= 0) && drv_data
->block
) {
559 drv_data
->state
= MV64XXX_I2C_STATE_IDLE
;
560 dev_err(&drv_data
->adapter
.dev
,
561 "mv64xxx: I2C bus locked, block: %d, "
562 "time_left: %d\n", drv_data
->block
,
564 mv64xxx_i2c_hw_init(drv_data
);
567 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
571 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data
*drv_data
, struct i2c_msg
*msg
,
576 spin_lock_irqsave(&drv_data
->lock
, flags
);
578 drv_data
->state
= MV64XXX_I2C_STATE_WAITING_FOR_START_COND
;
580 drv_data
->send_stop
= is_last
;
582 mv64xxx_i2c_send_start(drv_data
);
583 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
585 mv64xxx_i2c_wait_for_completion(drv_data
);
590 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data
*drv_data
)
592 struct i2c_msg
*msg
= drv_data
->msgs
;
595 memcpy(buf
, msg
->buf
, msg
->len
);
597 writel(buf
[0], drv_data
->reg_base
+ MV64XXX_I2C_REG_TX_DATA_LO
);
598 writel(buf
[1], drv_data
->reg_base
+ MV64XXX_I2C_REG_TX_DATA_HI
);
602 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data
*drv_data
)
604 struct i2c_msg
*msgs
= drv_data
->msgs
;
605 int num
= drv_data
->num_msgs
;
606 unsigned long ctrl_reg
;
609 spin_lock_irqsave(&drv_data
->lock
, flags
);
611 /* Build transaction */
612 ctrl_reg
= MV64XXX_I2C_BRIDGE_CONTROL_ENABLE
|
613 (msgs
[0].addr
<< MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT
);
615 if (msgs
[0].flags
& I2C_M_TEN
)
616 ctrl_reg
|= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT
;
618 /* Single write message transaction */
619 if (num
== 1 && !(msgs
[0].flags
& I2C_M_RD
)) {
620 size_t len
= msgs
[0].len
- 1;
622 ctrl_reg
|= MV64XXX_I2C_BRIDGE_CONTROL_WR
|
623 (len
<< MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT
);
624 mv64xxx_i2c_prepare_tx(drv_data
);
626 /* Single read message transaction */
627 else if (num
== 1 && msgs
[0].flags
& I2C_M_RD
) {
628 size_t len
= msgs
[0].len
- 1;
630 ctrl_reg
|= MV64XXX_I2C_BRIDGE_CONTROL_RD
|
631 (len
<< MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT
);
634 * Transaction with one write and one read message. This is
635 * guaranteed by the mv64xx_i2c_can_offload() checks.
638 size_t lentx
= msgs
[0].len
- 1;
639 size_t lenrx
= msgs
[1].len
- 1;
642 MV64XXX_I2C_BRIDGE_CONTROL_RD
|
643 MV64XXX_I2C_BRIDGE_CONTROL_WR
|
644 (lentx
<< MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT
) |
645 (lenrx
<< MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT
) |
646 MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START
;
647 mv64xxx_i2c_prepare_tx(drv_data
);
650 /* Execute transaction */
652 writel(ctrl_reg
, drv_data
->reg_base
+ MV64XXX_I2C_REG_BRIDGE_CONTROL
);
653 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
655 mv64xxx_i2c_wait_for_completion(drv_data
);
661 mv64xxx_i2c_valid_offload_sz(struct i2c_msg
*msg
)
663 return msg
->len
<= 8 && msg
->len
>= 1;
667 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data
*drv_data
)
669 struct i2c_msg
*msgs
= drv_data
->msgs
;
670 int num
= drv_data
->num_msgs
;
672 if (!drv_data
->offload_enabled
)
676 * We can offload a transaction consisting of a single
677 * message, as long as the message has a length between 1 and
680 if (num
== 1 && mv64xxx_i2c_valid_offload_sz(msgs
))
684 * We can offload a transaction consisting of two messages, if
685 * the first is a write and a second is a read, and both have
686 * a length between 1 and 8 bytes.
689 mv64xxx_i2c_valid_offload_sz(msgs
) &&
690 mv64xxx_i2c_valid_offload_sz(msgs
+ 1) &&
691 !(msgs
[0].flags
& I2C_M_RD
) &&
692 msgs
[1].flags
& I2C_M_RD
)
699 *****************************************************************************
701 * I2C Core Support Routines (Interface to higher level I2C code)
703 *****************************************************************************
706 mv64xxx_i2c_functionality(struct i2c_adapter
*adap
)
708 return I2C_FUNC_I2C
| I2C_FUNC_10BIT_ADDR
| I2C_FUNC_SMBUS_EMUL
;
712 mv64xxx_i2c_xfer(struct i2c_adapter
*adap
, struct i2c_msg msgs
[], int num
)
714 struct mv64xxx_i2c_data
*drv_data
= i2c_get_adapdata(adap
);
717 BUG_ON(drv_data
->msgs
!= NULL
);
718 drv_data
->msgs
= msgs
;
719 drv_data
->num_msgs
= num
;
721 if (mv64xxx_i2c_can_offload(drv_data
))
722 rc
= mv64xxx_i2c_offload_xfer(drv_data
);
724 rc
= mv64xxx_i2c_execute_msg(drv_data
, &msgs
[0], num
== 1);
729 drv_data
->num_msgs
= 0;
730 drv_data
->msgs
= NULL
;
735 static const struct i2c_algorithm mv64xxx_i2c_algo
= {
736 .master_xfer
= mv64xxx_i2c_xfer
,
737 .functionality
= mv64xxx_i2c_functionality
,
741 *****************************************************************************
743 * Driver Interface & Early Init Routines
745 *****************************************************************************
747 static const struct of_device_id mv64xxx_i2c_of_match_table
[] = {
748 { .compatible
= "allwinner,sun4i-a10-i2c", .data
= &mv64xxx_i2c_regs_sun4i
},
749 { .compatible
= "allwinner,sun6i-a31-i2c", .data
= &mv64xxx_i2c_regs_sun4i
},
750 { .compatible
= "marvell,mv64xxx-i2c", .data
= &mv64xxx_i2c_regs_mv64xxx
},
751 { .compatible
= "marvell,mv78230-i2c", .data
= &mv64xxx_i2c_regs_mv64xxx
},
752 { .compatible
= "marvell,mv78230-a0-i2c", .data
= &mv64xxx_i2c_regs_mv64xxx
},
755 MODULE_DEVICE_TABLE(of
, mv64xxx_i2c_of_match_table
);
758 #ifdef CONFIG_HAVE_CLK
760 mv64xxx_calc_freq(const int tclk
, const int n
, const int m
)
762 return tclk
/ (10 * (m
+ 1) * (2 << n
));
766 mv64xxx_find_baud_factors(const u32 req_freq
, const u32 tclk
, u32
*best_n
,
769 int freq
, delta
, best_delta
= INT_MAX
;
772 for (n
= 0; n
<= 7; n
++)
773 for (m
= 0; m
<= 15; m
++) {
774 freq
= mv64xxx_calc_freq(tclk
, n
, m
);
775 delta
= req_freq
- freq
;
776 if (delta
>= 0 && delta
< best_delta
) {
784 if (best_delta
== INT_MAX
)
788 #endif /* CONFIG_HAVE_CLK */
791 mv64xxx_of_config(struct mv64xxx_i2c_data
*drv_data
,
794 /* CLK is mandatory when using DT to describe the i2c bus. We
795 * need to know tclk in order to calculate bus clock
798 #if !defined(CONFIG_HAVE_CLK)
799 /* Have OF but no CLK */
802 const struct of_device_id
*device
;
803 struct device_node
*np
= dev
->of_node
;
807 if (IS_ERR(drv_data
->clk
)) {
811 tclk
= clk_get_rate(drv_data
->clk
);
813 if (of_property_read_u32(np
, "clock-frequency", &bus_freq
))
814 bus_freq
= 100000; /* 100kHz by default */
816 if (!mv64xxx_find_baud_factors(bus_freq
, tclk
,
817 &drv_data
->freq_n
, &drv_data
->freq_m
)) {
821 drv_data
->irq
= irq_of_parse_and_map(np
, 0);
823 drv_data
->rstc
= devm_reset_control_get_optional(dev
, NULL
);
824 if (IS_ERR(drv_data
->rstc
)) {
825 if (PTR_ERR(drv_data
->rstc
) == -EPROBE_DEFER
) {
830 reset_control_deassert(drv_data
->rstc
);
833 /* Its not yet defined how timeouts will be specified in device tree.
834 * So hard code the value to 1 second.
836 drv_data
->adapter
.timeout
= HZ
;
838 device
= of_match_device(mv64xxx_i2c_of_match_table
, dev
);
842 memcpy(&drv_data
->reg_offsets
, device
->data
, sizeof(drv_data
->reg_offsets
));
845 * For controllers embedded in new SoCs activate the
846 * Transaction Generator support and the errata fix.
848 if (of_device_is_compatible(np
, "marvell,mv78230-i2c")) {
849 drv_data
->offload_enabled
= true;
850 drv_data
->errata_delay
= true;
853 if (of_device_is_compatible(np
, "marvell,mv78230-a0-i2c")) {
854 drv_data
->offload_enabled
= false;
855 drv_data
->errata_delay
= true;
858 if (of_device_is_compatible(np
, "allwinner,sun6i-a31-i2c"))
859 drv_data
->irq_clear_inverted
= true;
865 #else /* CONFIG_OF */
867 mv64xxx_of_config(struct mv64xxx_i2c_data
*drv_data
,
872 #endif /* CONFIG_OF */
875 mv64xxx_i2c_probe(struct platform_device
*pd
)
877 struct mv64xxx_i2c_data
*drv_data
;
878 struct mv64xxx_i2c_pdata
*pdata
= dev_get_platdata(&pd
->dev
);
882 if ((!pdata
&& !pd
->dev
.of_node
))
885 drv_data
= devm_kzalloc(&pd
->dev
, sizeof(struct mv64xxx_i2c_data
),
890 r
= platform_get_resource(pd
, IORESOURCE_MEM
, 0);
891 drv_data
->reg_base
= devm_ioremap_resource(&pd
->dev
, r
);
892 if (IS_ERR(drv_data
->reg_base
))
893 return PTR_ERR(drv_data
->reg_base
);
895 strlcpy(drv_data
->adapter
.name
, MV64XXX_I2C_CTLR_NAME
" adapter",
896 sizeof(drv_data
->adapter
.name
));
898 init_waitqueue_head(&drv_data
->waitq
);
899 spin_lock_init(&drv_data
->lock
);
901 #if defined(CONFIG_HAVE_CLK)
902 /* Not all platforms have a clk */
903 drv_data
->clk
= devm_clk_get(&pd
->dev
, NULL
);
904 if (!IS_ERR(drv_data
->clk
)) {
905 clk_prepare(drv_data
->clk
);
906 clk_enable(drv_data
->clk
);
910 drv_data
->freq_m
= pdata
->freq_m
;
911 drv_data
->freq_n
= pdata
->freq_n
;
912 drv_data
->irq
= platform_get_irq(pd
, 0);
913 drv_data
->adapter
.timeout
= msecs_to_jiffies(pdata
->timeout
);
914 drv_data
->offload_enabled
= false;
915 memcpy(&drv_data
->reg_offsets
, &mv64xxx_i2c_regs_mv64xxx
, sizeof(drv_data
->reg_offsets
));
916 } else if (pd
->dev
.of_node
) {
917 rc
= mv64xxx_of_config(drv_data
, &pd
->dev
);
921 if (drv_data
->irq
< 0) {
926 drv_data
->adapter
.dev
.parent
= &pd
->dev
;
927 drv_data
->adapter
.algo
= &mv64xxx_i2c_algo
;
928 drv_data
->adapter
.owner
= THIS_MODULE
;
929 drv_data
->adapter
.class = I2C_CLASS_DEPRECATED
;
930 drv_data
->adapter
.nr
= pd
->id
;
931 drv_data
->adapter
.dev
.of_node
= pd
->dev
.of_node
;
932 platform_set_drvdata(pd
, drv_data
);
933 i2c_set_adapdata(&drv_data
->adapter
, drv_data
);
935 mv64xxx_i2c_hw_init(drv_data
);
937 rc
= request_irq(drv_data
->irq
, mv64xxx_i2c_intr
, 0,
938 MV64XXX_I2C_CTLR_NAME
, drv_data
);
940 dev_err(&drv_data
->adapter
.dev
,
941 "mv64xxx: Can't register intr handler irq%d: %d\n",
944 } else if ((rc
= i2c_add_numbered_adapter(&drv_data
->adapter
)) != 0) {
945 dev_err(&drv_data
->adapter
.dev
,
946 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc
);
953 free_irq(drv_data
->irq
, drv_data
);
955 if (!IS_ERR_OR_NULL(drv_data
->rstc
))
956 reset_control_assert(drv_data
->rstc
);
958 #if defined(CONFIG_HAVE_CLK)
959 /* Not all platforms have a clk */
960 if (!IS_ERR(drv_data
->clk
)) {
961 clk_disable(drv_data
->clk
);
962 clk_unprepare(drv_data
->clk
);
969 mv64xxx_i2c_remove(struct platform_device
*dev
)
971 struct mv64xxx_i2c_data
*drv_data
= platform_get_drvdata(dev
);
973 i2c_del_adapter(&drv_data
->adapter
);
974 free_irq(drv_data
->irq
, drv_data
);
975 if (!IS_ERR_OR_NULL(drv_data
->rstc
))
976 reset_control_assert(drv_data
->rstc
);
977 #if defined(CONFIG_HAVE_CLK)
978 /* Not all platforms have a clk */
979 if (!IS_ERR(drv_data
->clk
)) {
980 clk_disable(drv_data
->clk
);
981 clk_unprepare(drv_data
->clk
);
988 static struct platform_driver mv64xxx_i2c_driver
= {
989 .probe
= mv64xxx_i2c_probe
,
990 .remove
= mv64xxx_i2c_remove
,
992 .name
= MV64XXX_I2C_CTLR_NAME
,
993 .of_match_table
= mv64xxx_i2c_of_match_table
,
997 module_platform_driver(mv64xxx_i2c_driver
);
999 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1000 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
1001 MODULE_LICENSE("GPL");