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s390/ptrace: get rid of long longs in psw_bits
[linux/fpc-iii.git] / drivers / media / pci / ngene / ngene-core.c
blob1b92d836a564fd364862acab2e761602e62744bd
1 /*
2 * ngene.c: nGene PCIe bridge driver
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7 * Modifications for new nGene firmware,
8 * support for EEPROM-copying,
9 * support for new dual DVB-S2 card prototype
10 *
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 only, as published by the Free Software Foundation.
15 *
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 * 02110-1301, USA
27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
28 */
29
30 #include <linux/module.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/poll.h>
34 #include <linux/io.h>
35 #include <asm/div64.h>
36 #include <linux/pci.h>
37 #include <linux/timer.h>
38 #include <linux/byteorder/generic.h>
39 #include <linux/firmware.h>
40 #include <linux/vmalloc.h>
41
42 #include "ngene.h"
43
44 static int one_adapter;
45 module_param(one_adapter, int, 0444);
46 MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
47
48 static int shutdown_workaround;
49 module_param(shutdown_workaround, int, 0644);
50 MODULE_PARM_DESC(shutdown_workaround, "Activate workaround for shutdown problem with some chipsets.");
51
52 static int debug;
53 module_param(debug, int, 0444);
54 MODULE_PARM_DESC(debug, "Print debugging information.");
55
56 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
57
58 #define dprintk if (debug) printk
59
60 #define ngwriteb(dat, adr) writeb((dat), dev->iomem + (adr))
61 #define ngwritel(dat, adr) writel((dat), dev->iomem + (adr))
62 #define ngwriteb(dat, adr) writeb((dat), dev->iomem + (adr))
63 #define ngreadl(adr) readl(dev->iomem + (adr))
64 #define ngreadb(adr) readb(dev->iomem + (adr))
65 #define ngcpyto(adr, src, count) memcpy_toio(dev->iomem + (adr), (src), (count))
66 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), dev->iomem + (adr), (count))
67
68 /****************************************************************************/
69 /* nGene interrupt handler **************************************************/
70 /****************************************************************************/
71
72 static void event_tasklet(unsigned long data)
73 {
74 struct ngene *dev = (struct ngene *)data;
75
76 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
77 struct EVENT_BUFFER Event =
78 dev->EventQueue[dev->EventQueueReadIndex];
79 dev->EventQueueReadIndex =
80 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
81
82 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
83 dev->TxEventNotify(dev, Event.TimeStamp);
84 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
85 dev->RxEventNotify(dev, Event.TimeStamp,
86 Event.RXCharacter);
87 }
88 }
89
90 static void demux_tasklet(unsigned long data)
91 {
92 struct ngene_channel *chan = (struct ngene_channel *)data;
93 struct SBufferHeader *Cur = chan->nextBuffer;
94
95 spin_lock_irq(&chan->state_lock);
96
97 while (Cur->ngeneBuffer.SR.Flags & 0x80) {
98 if (chan->mode & NGENE_IO_TSOUT) {
99 u32 Flags = chan->DataFormatFlags;
100 if (Cur->ngeneBuffer.SR.Flags & 0x20)
101 Flags |= BEF_OVERFLOW;
102 if (chan->pBufferExchange) {
103 if (!chan->pBufferExchange(chan,
104 Cur->Buffer1,
105 chan->Capture1Length,
106 Cur->ngeneBuffer.SR.
107 Clock, Flags)) {
108 /*
109 We didn't get data
110 Clear in service flag to make sure we
111 get called on next interrupt again.
112 leave fill/empty (0x80) flag alone
113 to avoid hardware running out of
114 buffers during startup, we hold only
115 in run state ( the source may be late
116 delivering data )
117 */
118
119 if (chan->HWState == HWSTATE_RUN) {
120 Cur->ngeneBuffer.SR.Flags &=
121 ~0x40;
122 break;
123 /* Stop processing stream */
124 }
125 } else {
126 /* We got a valid buffer,
127 so switch to run state */
128 chan->HWState = HWSTATE_RUN;
129 }
130 } else {
131 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
132 if (chan->HWState == HWSTATE_RUN) {
133 Cur->ngeneBuffer.SR.Flags &= ~0x40;
134 break; /* Stop processing stream */
135 }
136 }
137 if (chan->AudioDTOUpdated) {
138 printk(KERN_INFO DEVICE_NAME
139 ": Update AudioDTO = %d\n",
140 chan->AudioDTOValue);
141 Cur->ngeneBuffer.SR.DTOUpdate =
142 chan->AudioDTOValue;
143 chan->AudioDTOUpdated = 0;
144 }
145 } else {
146 if (chan->HWState == HWSTATE_RUN) {
147 u32 Flags = chan->DataFormatFlags;
148 IBufferExchange *exch1 = chan->pBufferExchange;
149 IBufferExchange *exch2 = chan->pBufferExchange2;
150 if (Cur->ngeneBuffer.SR.Flags & 0x01)
151 Flags |= BEF_EVEN_FIELD;
152 if (Cur->ngeneBuffer.SR.Flags & 0x20)
153 Flags |= BEF_OVERFLOW;
154 spin_unlock_irq(&chan->state_lock);
155 if (exch1)
156 exch1(chan, Cur->Buffer1,
157 chan->Capture1Length,
158 Cur->ngeneBuffer.SR.Clock,
159 Flags);
160 if (exch2)
161 exch2(chan, Cur->Buffer2,
162 chan->Capture2Length,
163 Cur->ngeneBuffer.SR.Clock,
164 Flags);
165 spin_lock_irq(&chan->state_lock);
166 } else if (chan->HWState != HWSTATE_STOP)
167 chan->HWState = HWSTATE_RUN;
168 }
169 Cur->ngeneBuffer.SR.Flags = 0x00;
170 Cur = Cur->Next;
171 }
172 chan->nextBuffer = Cur;
173
174 spin_unlock_irq(&chan->state_lock);
175 }
176
177 static irqreturn_t irq_handler(int irq, void *dev_id)
178 {
179 struct ngene *dev = (struct ngene *)dev_id;
180 u32 icounts = 0;
181 irqreturn_t rc = IRQ_NONE;
182 u32 i = MAX_STREAM;
183 u8 *tmpCmdDoneByte;
184
185 if (dev->BootFirmware) {
186 icounts = ngreadl(NGENE_INT_COUNTS);
187 if (icounts != dev->icounts) {
188 ngwritel(0, FORCE_NMI);
189 dev->cmd_done = 1;
190 wake_up(&dev->cmd_wq);
191 dev->icounts = icounts;
192 rc = IRQ_HANDLED;
193 }
194 return rc;
195 }
196
197 ngwritel(0, FORCE_NMI);
198
199 spin_lock(&dev->cmd_lock);
200 tmpCmdDoneByte = dev->CmdDoneByte;
201 if (tmpCmdDoneByte &&
202 (*tmpCmdDoneByte ||
203 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
204 dev->CmdDoneByte = NULL;
205 dev->cmd_done = 1;
206 wake_up(&dev->cmd_wq);
207 rc = IRQ_HANDLED;
208 }
209 spin_unlock(&dev->cmd_lock);
210
211 if (dev->EventBuffer->EventStatus & 0x80) {
212 u8 nextWriteIndex =
213 (dev->EventQueueWriteIndex + 1) &
214 (EVENT_QUEUE_SIZE - 1);
215 if (nextWriteIndex != dev->EventQueueReadIndex) {
216 dev->EventQueue[dev->EventQueueWriteIndex] =
217 *(dev->EventBuffer);
218 dev->EventQueueWriteIndex = nextWriteIndex;
219 } else {
220 printk(KERN_ERR DEVICE_NAME ": event overflow\n");
221 dev->EventQueueOverflowCount += 1;
222 dev->EventQueueOverflowFlag = 1;
223 }
224 dev->EventBuffer->EventStatus &= ~0x80;
225 tasklet_schedule(&dev->event_tasklet);
226 rc = IRQ_HANDLED;
227 }
228
229 while (i > 0) {
230 i--;
231 spin_lock(&dev->channel[i].state_lock);
232 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
233 if (dev->channel[i].nextBuffer) {
234 if ((dev->channel[i].nextBuffer->
235 ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
236 dev->channel[i].nextBuffer->
237 ngeneBuffer.SR.Flags |= 0x40;
238 tasklet_schedule(
239 &dev->channel[i].demux_tasklet);
240 rc = IRQ_HANDLED;
241 }
242 }
243 spin_unlock(&dev->channel[i].state_lock);
244 }
245
246 /* Request might have been processed by a previous call. */
247 return IRQ_HANDLED;
248 }
249
250 /****************************************************************************/
251 /* nGene command interface **************************************************/
252 /****************************************************************************/
253
254 static void dump_command_io(struct ngene *dev)
255 {
256 u8 buf[8], *b;
257
258 ngcpyfrom(buf, HOST_TO_NGENE, 8);
259 printk(KERN_ERR "host_to_ngene (%04x): %*ph\n", HOST_TO_NGENE, 8, buf);
260
261 ngcpyfrom(buf, NGENE_TO_HOST, 8);
262 printk(KERN_ERR "ngene_to_host (%04x): %*ph\n", NGENE_TO_HOST, 8, buf);
263
264 b = dev->hosttongene;
265 printk(KERN_ERR "dev->hosttongene (%p): %*ph\n", b, 8, b);
266
267 b = dev->ngenetohost;
268 printk(KERN_ERR "dev->ngenetohost (%p): %*ph\n", b, 8, b);
269 }
270
271 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
272 {
273 int ret;
274 u8 *tmpCmdDoneByte;
275
276 dev->cmd_done = 0;
277
278 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
279 dev->BootFirmware = 1;
280 dev->icounts = ngreadl(NGENE_INT_COUNTS);
281 ngwritel(0, NGENE_COMMAND);
282 ngwritel(0, NGENE_COMMAND_HI);
283 ngwritel(0, NGENE_STATUS);
284 ngwritel(0, NGENE_STATUS_HI);
285 ngwritel(0, NGENE_EVENT);
286 ngwritel(0, NGENE_EVENT_HI);
287 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
288 u64 fwio = dev->PAFWInterfaceBuffer;
289
290 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
291 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
292 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
293 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
294 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
295 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
296 }
297
298 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
299
300 if (dev->BootFirmware)
301 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
302
303 spin_lock_irq(&dev->cmd_lock);
304 tmpCmdDoneByte = dev->ngenetohost + com->out_len;
305 if (!com->out_len)
306 tmpCmdDoneByte++;
307 *tmpCmdDoneByte = 0;
308 dev->ngenetohost[0] = 0;
309 dev->ngenetohost[1] = 0;
310 dev->CmdDoneByte = tmpCmdDoneByte;
311 spin_unlock_irq(&dev->cmd_lock);
312
313 /* Notify 8051. */
314 ngwritel(1, FORCE_INT);
315
316 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
317 if (!ret) {
318 /*ngwritel(0, FORCE_NMI);*/
319
320 printk(KERN_ERR DEVICE_NAME
321 ": Command timeout cmd=%02x prev=%02x\n",
322 com->cmd.hdr.Opcode, dev->prev_cmd);
323 dump_command_io(dev);
324 return -1;
325 }
326 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
327 dev->BootFirmware = 0;
328
329 dev->prev_cmd = com->cmd.hdr.Opcode;
330
331 if (!com->out_len)
332 return 0;
333
334 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
335
336 return 0;
337 }
338
339 int ngene_command(struct ngene *dev, struct ngene_command *com)
340 {
341 int result;
342
343 down(&dev->cmd_mutex);
344 result = ngene_command_mutex(dev, com);
345 up(&dev->cmd_mutex);
346 return result;
347 }
348
349
350 static int ngene_command_load_firmware(struct ngene *dev,
351 u8 *ngene_fw, u32 size)
352 {
353 #define FIRSTCHUNK (1024)
354 u32 cleft;
355 struct ngene_command com;
356
357 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
358 com.cmd.hdr.Length = 0;
359 com.in_len = 0;
360 com.out_len = 0;
361
362 ngene_command(dev, &com);
363
364 cleft = (size + 3) & ~3;
365 if (cleft > FIRSTCHUNK) {
366 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
367 cleft - FIRSTCHUNK);
368 cleft = FIRSTCHUNK;
369 }
370 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
371
372 memset(&com, 0, sizeof(struct ngene_command));
373 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
374 com.cmd.hdr.Length = 4;
375 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
376 com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
377 com.in_len = 4;
378 com.out_len = 0;
379
380 return ngene_command(dev, &com);
381 }
382
383
384 static int ngene_command_config_buf(struct ngene *dev, u8 config)
385 {
386 struct ngene_command com;
387
388 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
389 com.cmd.hdr.Length = 1;
390 com.cmd.ConfigureBuffers.config = config;
391 com.in_len = 1;
392 com.out_len = 0;
393
394 if (ngene_command(dev, &com) < 0)
395 return -EIO;
396 return 0;
397 }
398
399 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
400 {
401 struct ngene_command com;
402
403 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
404 com.cmd.hdr.Length = 6;
405 memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
406 com.in_len = 6;
407 com.out_len = 0;
408
409 if (ngene_command(dev, &com) < 0)
410 return -EIO;
411
412 return 0;
413 }
414
415 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
416 {
417 struct ngene_command com;
418
419 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
420 com.cmd.hdr.Length = 1;
421 com.cmd.SetGpioPin.select = select | (level << 7);
422 com.in_len = 1;
423 com.out_len = 0;
424
425 return ngene_command(dev, &com);
426 }
427
428
429 /*
430 02000640 is sample on rising edge.
431 02000740 is sample on falling edge.
432 02000040 is ignore "valid" signal
433
434 0: FD_CTL1 Bit 7,6 must be 0,1
435 7 disable(fw controlled)
436 6 0-AUX,1-TS
437 5 0-par,1-ser
438 4 0-lsb/1-msb
439 3,2 reserved
440 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
441 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
442 2: FD_STA is read-only. 0-sync
443 3: FD_INSYNC is number of 47s to trigger "in sync".
444 4: FD_OUTSYNC is number of 47s to trigger "out of sync".
445 5: FD_MAXBYTE1 is low-order of bytes per packet.
446 6: FD_MAXBYTE2 is high-order of bytes per packet.
447 7: Top byte is unused.
448 */
449
450 /****************************************************************************/
451
452 static u8 TSFeatureDecoderSetup[8 * 5] = {
453 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
454 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
455 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
456 0x72, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
457 0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */
458 };
459
460 /* Set NGENE I2S Config to 16 bit packed */
461 static u8 I2SConfiguration[] = {
462 0x00, 0x10, 0x00, 0x00,
463 0x80, 0x10, 0x00, 0x00,
464 };
465
466 static u8 SPDIFConfiguration[10] = {
467 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
468 };
469
470 /* Set NGENE I2S Config to transport stream compatible mode */
471
472 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x18, 0x00, 0x00 };
473
474 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x04, 0x00, 0x00 };
475
476 static u8 ITUDecoderSetup[4][16] = {
477 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */
478 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
479 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
480 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
481 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */
482 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
483 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */
484 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
485 };
486
487 /*
488 * 50 48 60 gleich
489 * 27p50 9f 00 22 80 42 69 18 ...
490 * 27p60 93 00 22 80 82 69 1c ...
491 */
492
493 /* Maxbyte to 1144 (for raw data) */
494 static u8 ITUFeatureDecoderSetup[8] = {
495 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
496 };
497
498 void FillTSBuffer(void *Buffer, int Length, u32 Flags)
499 {
500 u32 *ptr = Buffer;
501
502 memset(Buffer, TS_FILLER, Length);
503 while (Length > 0) {
504 if (Flags & DF_SWAP32)
505 *ptr = 0x471FFF10;
506 else
507 *ptr = 0x10FF1F47;
508 ptr += (188 / 4);
509 Length -= 188;
510 }
511 }
512
513
514 static void flush_buffers(struct ngene_channel *chan)
515 {
516 u8 val;
517
518 do {
519 msleep(1);
520 spin_lock_irq(&chan->state_lock);
521 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
522 spin_unlock_irq(&chan->state_lock);
523 } while (val);
524 }
525
526 static void clear_buffers(struct ngene_channel *chan)
527 {
528 struct SBufferHeader *Cur = chan->nextBuffer;
529
530 do {
531 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
532 if (chan->mode & NGENE_IO_TSOUT)
533 FillTSBuffer(Cur->Buffer1,
534 chan->Capture1Length,
535 chan->DataFormatFlags);
536 Cur = Cur->Next;
537 } while (Cur != chan->nextBuffer);
538
539 if (chan->mode & NGENE_IO_TSOUT) {
540 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
541 chan->AudioDTOValue;
542 chan->AudioDTOUpdated = 0;
543
544 Cur = chan->TSIdleBuffer.Head;
545
546 do {
547 memset(&Cur->ngeneBuffer.SR, 0,
548 sizeof(Cur->ngeneBuffer.SR));
549 FillTSBuffer(Cur->Buffer1,
550 chan->Capture1Length,
551 chan->DataFormatFlags);
552 Cur = Cur->Next;
553 } while (Cur != chan->TSIdleBuffer.Head);
554 }
555 }
556
557 static int ngene_command_stream_control(struct ngene *dev, u8 stream,
558 u8 control, u8 mode, u8 flags)
559 {
560 struct ngene_channel *chan = &dev->channel[stream];
561 struct ngene_command com;
562 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
563 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
564 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
565 u16 BsSDO = 0x9B00;
566
567 down(&dev->stream_mutex);
568 memset(&com, 0, sizeof(com));
569 com.cmd.hdr.Opcode = CMD_CONTROL;
570 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
571 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
572 if (chan->mode & NGENE_IO_TSOUT)
573 com.cmd.StreamControl.Stream |= 0x07;
574 com.cmd.StreamControl.Control = control |
575 (flags & SFLAG_ORDER_LUMA_CHROMA);
576 com.cmd.StreamControl.Mode = mode;
577 com.in_len = sizeof(struct FW_STREAM_CONTROL);
578 com.out_len = 0;
579
580 dprintk(KERN_INFO DEVICE_NAME
581 ": Stream=%02x, Control=%02x, Mode=%02x\n",
582 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
583 com.cmd.StreamControl.Mode);
584
585 chan->Mode = mode;
586
587 if (!(control & 0x80)) {
588 spin_lock_irq(&chan->state_lock);
589 if (chan->State == KSSTATE_RUN) {
590 chan->State = KSSTATE_ACQUIRE;
591 chan->HWState = HWSTATE_STOP;
592 spin_unlock_irq(&chan->state_lock);
593 if (ngene_command(dev, &com) < 0) {
594 up(&dev->stream_mutex);
595 return -1;
596 }
597 /* clear_buffers(chan); */
598 flush_buffers(chan);
599 up(&dev->stream_mutex);
600 return 0;
601 }
602 spin_unlock_irq(&chan->state_lock);
603 up(&dev->stream_mutex);
604 return 0;
605 }
606
607 if (mode & SMODE_AUDIO_CAPTURE) {
608 com.cmd.StreamControl.CaptureBlockCount =
609 chan->Capture1Length / AUDIO_BLOCK_SIZE;
610 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
611 } else if (mode & SMODE_TRANSPORT_STREAM) {
612 com.cmd.StreamControl.CaptureBlockCount =
613 chan->Capture1Length / TS_BLOCK_SIZE;
614 com.cmd.StreamControl.MaxLinesPerField =
615 chan->Capture1Length / TS_BLOCK_SIZE;
616 com.cmd.StreamControl.Buffer_Address =
617 chan->TSRingBuffer.PAHead;
618 if (chan->mode & NGENE_IO_TSOUT) {
619 com.cmd.StreamControl.BytesPerVBILine =
620 chan->Capture1Length / TS_BLOCK_SIZE;
621 com.cmd.StreamControl.Stream |= 0x07;
622 }
623 } else {
624 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
625 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
626 com.cmd.StreamControl.MinLinesPerField = 100;
627 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
628
629 if (mode & SMODE_VBI_CAPTURE) {
630 com.cmd.StreamControl.MaxVBILinesPerField =
631 chan->nVBILines;
632 com.cmd.StreamControl.MinVBILinesPerField = 0;
633 com.cmd.StreamControl.BytesPerVBILine =
634 chan->nBytesPerVBILine;
635 }
636 if (flags & SFLAG_COLORBAR)
637 com.cmd.StreamControl.Stream |= 0x04;
638 }
639
640 spin_lock_irq(&chan->state_lock);
641 if (mode & SMODE_AUDIO_CAPTURE) {
642 chan->nextBuffer = chan->RingBuffer.Head;
643 if (mode & SMODE_AUDIO_SPDIF) {
644 com.cmd.StreamControl.SetupDataLen =
645 sizeof(SPDIFConfiguration);
646 com.cmd.StreamControl.SetupDataAddr = BsSPI;
647 memcpy(com.cmd.StreamControl.SetupData,
648 SPDIFConfiguration, sizeof(SPDIFConfiguration));
649 } else {
650 com.cmd.StreamControl.SetupDataLen = 4;
651 com.cmd.StreamControl.SetupDataAddr = BsSDI;
652 memcpy(com.cmd.StreamControl.SetupData,
653 I2SConfiguration +
654 4 * dev->card_info->i2s[stream], 4);
655 }
656 } else if (mode & SMODE_TRANSPORT_STREAM) {
657 chan->nextBuffer = chan->TSRingBuffer.Head;
658 if (stream >= STREAM_AUDIOIN1) {
659 if (chan->mode & NGENE_IO_TSOUT) {
660 com.cmd.StreamControl.SetupDataLen =
661 sizeof(TS_I2SOutConfiguration);
662 com.cmd.StreamControl.SetupDataAddr = BsSDO;
663 memcpy(com.cmd.StreamControl.SetupData,
664 TS_I2SOutConfiguration,
665 sizeof(TS_I2SOutConfiguration));
666 } else {
667 com.cmd.StreamControl.SetupDataLen =
668 sizeof(TS_I2SConfiguration);
669 com.cmd.StreamControl.SetupDataAddr = BsSDI;
670 memcpy(com.cmd.StreamControl.SetupData,
671 TS_I2SConfiguration,
672 sizeof(TS_I2SConfiguration));
673 }
674 } else {
675 com.cmd.StreamControl.SetupDataLen = 8;
676 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
677 memcpy(com.cmd.StreamControl.SetupData,
678 TSFeatureDecoderSetup +
679 8 * dev->card_info->tsf[stream], 8);
680 }
681 } else {
682 chan->nextBuffer = chan->RingBuffer.Head;
683 com.cmd.StreamControl.SetupDataLen =
684 16 + sizeof(ITUFeatureDecoderSetup);
685 com.cmd.StreamControl.SetupDataAddr = BsUVI;
686 memcpy(com.cmd.StreamControl.SetupData,
687 ITUDecoderSetup[chan->itumode], 16);
688 memcpy(com.cmd.StreamControl.SetupData + 16,
689 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
690 }
691 clear_buffers(chan);
692 chan->State = KSSTATE_RUN;
693 if (mode & SMODE_TRANSPORT_STREAM)
694 chan->HWState = HWSTATE_RUN;
695 else
696 chan->HWState = HWSTATE_STARTUP;
697 spin_unlock_irq(&chan->state_lock);
698
699 if (ngene_command(dev, &com) < 0) {
700 up(&dev->stream_mutex);
701 return -1;
702 }
703 up(&dev->stream_mutex);
704 return 0;
705 }
706
707 void set_transfer(struct ngene_channel *chan, int state)
708 {
709 u8 control = 0, mode = 0, flags = 0;
710 struct ngene *dev = chan->dev;
711 int ret;
712
713 /*
714 printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
715 msleep(100);
716 */
717
718 if (state) {
719 if (chan->running) {
720 printk(KERN_INFO DEVICE_NAME ": already running\n");
721 return;
722 }
723 } else {
724 if (!chan->running) {
725 printk(KERN_INFO DEVICE_NAME ": already stopped\n");
726 return;
727 }
728 }
729
730 if (dev->card_info->switch_ctrl)
731 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
732
733 if (state) {
734 spin_lock_irq(&chan->state_lock);
735
736 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
737 ngreadl(0x9310)); */
738 dvb_ringbuffer_flush(&dev->tsout_rbuf);
739 control = 0x80;
740 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
741 chan->Capture1Length = 512 * 188;
742 mode = SMODE_TRANSPORT_STREAM;
743 }
744 if (chan->mode & NGENE_IO_TSOUT) {
745 chan->pBufferExchange = tsout_exchange;
746 /* 0x66666666 = 50MHz *2^33 /250MHz */
747 chan->AudioDTOValue = 0x80000000;
748 chan->AudioDTOUpdated = 1;
749 }
750 if (chan->mode & NGENE_IO_TSIN)
751 chan->pBufferExchange = tsin_exchange;
752 spin_unlock_irq(&chan->state_lock);
753 }
754 /* else printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
755 ngreadl(0x9310)); */
756
757 ret = ngene_command_stream_control(dev, chan->number,
758 control, mode, flags);
759 if (!ret)
760 chan->running = state;
761 else
762 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
763 state);
764 if (!state) {
765 spin_lock_irq(&chan->state_lock);
766 chan->pBufferExchange = NULL;
767 dvb_ringbuffer_flush(&dev->tsout_rbuf);
768 spin_unlock_irq(&chan->state_lock);
769 }
770 }
771
772
773 /****************************************************************************/
774 /* nGene hardware init and release functions ********************************/
775 /****************************************************************************/
776
777 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
778 {
779 struct SBufferHeader *Cur = rb->Head;
780 u32 j;
781
782 if (!Cur)
783 return;
784
785 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
786 if (Cur->Buffer1)
787 pci_free_consistent(dev->pci_dev,
788 rb->Buffer1Length,
789 Cur->Buffer1,
790 Cur->scList1->Address);
791
792 if (Cur->Buffer2)
793 pci_free_consistent(dev->pci_dev,
794 rb->Buffer2Length,
795 Cur->Buffer2,
796 Cur->scList2->Address);
797 }
798
799 if (rb->SCListMem)
800 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
801 rb->SCListMem, rb->PASCListMem);
802
803 pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
804 }
805
806 static void free_idlebuffer(struct ngene *dev,
807 struct SRingBufferDescriptor *rb,
808 struct SRingBufferDescriptor *tb)
809 {
810 int j;
811 struct SBufferHeader *Cur = tb->Head;
812
813 if (!rb->Head)
814 return;
815 free_ringbuffer(dev, rb);
816 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
817 Cur->Buffer2 = NULL;
818 Cur->scList2 = NULL;
819 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
820 Cur->ngeneBuffer.Number_of_entries_2 = 0;
821 }
822 }
823
824 static void free_common_buffers(struct ngene *dev)
825 {
826 u32 i;
827 struct ngene_channel *chan;
828
829 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
830 chan = &dev->channel[i];
831 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
832 free_ringbuffer(dev, &chan->RingBuffer);
833 free_ringbuffer(dev, &chan->TSRingBuffer);
834 }
835
836 if (dev->OverflowBuffer)
837 pci_free_consistent(dev->pci_dev,
838 OVERFLOW_BUFFER_SIZE,
839 dev->OverflowBuffer, dev->PAOverflowBuffer);
840
841 if (dev->FWInterfaceBuffer)
842 pci_free_consistent(dev->pci_dev,
843 4096,
844 dev->FWInterfaceBuffer,
845 dev->PAFWInterfaceBuffer);
846 }
847
848 /****************************************************************************/
849 /* Ring buffer handling *****************************************************/
850 /****************************************************************************/
851
852 static int create_ring_buffer(struct pci_dev *pci_dev,
853 struct SRingBufferDescriptor *descr, u32 NumBuffers)
854 {
855 dma_addr_t tmp;
856 struct SBufferHeader *Head;
857 u32 i;
858 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
859 u64 PARingBufferHead;
860 u64 PARingBufferCur;
861 u64 PARingBufferNext;
862 struct SBufferHeader *Cur, *Next;
863
864 descr->Head = NULL;
865 descr->MemSize = 0;
866 descr->PAHead = 0;
867 descr->NumBuffers = 0;
868
869 if (MemSize < 4096)
870 MemSize = 4096;
871
872 Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
873 PARingBufferHead = tmp;
874
875 if (!Head)
876 return -ENOMEM;
877
878 memset(Head, 0, MemSize);
879
880 PARingBufferCur = PARingBufferHead;
881 Cur = Head;
882
883 for (i = 0; i < NumBuffers - 1; i++) {
884 Next = (struct SBufferHeader *)
885 (((u8 *) Cur) + SIZEOF_SBufferHeader);
886 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
887 Cur->Next = Next;
888 Cur->ngeneBuffer.Next = PARingBufferNext;
889 Cur = Next;
890 PARingBufferCur = PARingBufferNext;
891 }
892 /* Last Buffer points back to first one */
893 Cur->Next = Head;
894 Cur->ngeneBuffer.Next = PARingBufferHead;
895
896 descr->Head = Head;
897 descr->MemSize = MemSize;
898 descr->PAHead = PARingBufferHead;
899 descr->NumBuffers = NumBuffers;
900
901 return 0;
902 }
903
904 static int AllocateRingBuffers(struct pci_dev *pci_dev,
905 dma_addr_t of,
906 struct SRingBufferDescriptor *pRingBuffer,
907 u32 Buffer1Length, u32 Buffer2Length)
908 {
909 dma_addr_t tmp;
910 u32 i, j;
911 u32 SCListMemSize = pRingBuffer->NumBuffers
912 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
913 NUM_SCATTER_GATHER_ENTRIES)
914 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
915
916 u64 PASCListMem;
917 struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
918 u64 PASCListEntry;
919 struct SBufferHeader *Cur;
920 void *SCListMem;
921
922 if (SCListMemSize < 4096)
923 SCListMemSize = 4096;
924
925 SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
926
927 PASCListMem = tmp;
928 if (SCListMem == NULL)
929 return -ENOMEM;
930
931 memset(SCListMem, 0, SCListMemSize);
932
933 pRingBuffer->SCListMem = SCListMem;
934 pRingBuffer->PASCListMem = PASCListMem;
935 pRingBuffer->SCListMemSize = SCListMemSize;
936 pRingBuffer->Buffer1Length = Buffer1Length;
937 pRingBuffer->Buffer2Length = Buffer2Length;
938
939 SCListEntry = SCListMem;
940 PASCListEntry = PASCListMem;
941 Cur = pRingBuffer->Head;
942
943 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
944 u64 PABuffer;
945
946 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
947 &tmp);
948 PABuffer = tmp;
949
950 if (Buffer == NULL)
951 return -ENOMEM;
952
953 Cur->Buffer1 = Buffer;
954
955 SCListEntry->Address = PABuffer;
956 SCListEntry->Length = Buffer1Length;
957
958 Cur->scList1 = SCListEntry;
959 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
960 Cur->ngeneBuffer.Number_of_entries_1 =
961 NUM_SCATTER_GATHER_ENTRIES;
962
963 SCListEntry += 1;
964 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
965
966 #if NUM_SCATTER_GATHER_ENTRIES > 1
967 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
968 SCListEntry->Address = of;
969 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
970 SCListEntry += 1;
971 PASCListEntry +=
972 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
973 }
974 #endif
975
976 if (!Buffer2Length)
977 continue;
978
979 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
980 PABuffer = tmp;
981
982 if (Buffer == NULL)
983 return -ENOMEM;
984
985 Cur->Buffer2 = Buffer;
986
987 SCListEntry->Address = PABuffer;
988 SCListEntry->Length = Buffer2Length;
989
990 Cur->scList2 = SCListEntry;
991 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
992 Cur->ngeneBuffer.Number_of_entries_2 =
993 NUM_SCATTER_GATHER_ENTRIES;
994
995 SCListEntry += 1;
996 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
997
998 #if NUM_SCATTER_GATHER_ENTRIES > 1
999 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1000 SCListEntry->Address = of;
1001 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1002 SCListEntry += 1;
1003 PASCListEntry +=
1004 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1005 }
1006 #endif
1007
1008 }
1009
1010 return 0;
1011 }
1012
1013 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
1014 struct SRingBufferDescriptor *pRingBuffer)
1015 {
1016 /* Copy pointer to scatter gather list in TSRingbuffer
1017 structure for buffer 2
1018 Load number of buffer
1019 */
1020 u32 n = pRingBuffer->NumBuffers;
1021
1022 /* Point to first buffer entry */
1023 struct SBufferHeader *Cur = pRingBuffer->Head;
1024 int i;
1025 /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
1026 for (i = 0; i < n; i++) {
1027 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1028 Cur->scList2 = pIdleBuffer->Head->scList1;
1029 Cur->ngeneBuffer.Address_of_first_entry_2 =
1030 pIdleBuffer->Head->ngeneBuffer.
1031 Address_of_first_entry_1;
1032 Cur->ngeneBuffer.Number_of_entries_2 =
1033 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1034 Cur = Cur->Next;
1035 }
1036 return 0;
1037 }
1038
1039 static u32 RingBufferSizes[MAX_STREAM] = {
1040 RING_SIZE_VIDEO,
1041 RING_SIZE_VIDEO,
1042 RING_SIZE_AUDIO,
1043 RING_SIZE_AUDIO,
1044 RING_SIZE_AUDIO,
1045 };
1046
1047 static u32 Buffer1Sizes[MAX_STREAM] = {
1048 MAX_VIDEO_BUFFER_SIZE,
1049 MAX_VIDEO_BUFFER_SIZE,
1050 MAX_AUDIO_BUFFER_SIZE,
1051 MAX_AUDIO_BUFFER_SIZE,
1052 MAX_AUDIO_BUFFER_SIZE
1053 };
1054
1055 static u32 Buffer2Sizes[MAX_STREAM] = {
1056 MAX_VBI_BUFFER_SIZE,
1057 MAX_VBI_BUFFER_SIZE,
1058 0,
1059 0,
1060 0
1061 };
1062
1063
1064 static int AllocCommonBuffers(struct ngene *dev)
1065 {
1066 int status = 0, i;
1067
1068 dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
1069 &dev->PAFWInterfaceBuffer);
1070 if (!dev->FWInterfaceBuffer)
1071 return -ENOMEM;
1072 dev->hosttongene = dev->FWInterfaceBuffer;
1073 dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1074 dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1075
1076 dev->OverflowBuffer = pci_zalloc_consistent(dev->pci_dev,
1077 OVERFLOW_BUFFER_SIZE,
1078 &dev->PAOverflowBuffer);
1079 if (!dev->OverflowBuffer)
1080 return -ENOMEM;
1081
1082 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1083 int type = dev->card_info->io_type[i];
1084
1085 dev->channel[i].State = KSSTATE_STOP;
1086
1087 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1088 status = create_ring_buffer(dev->pci_dev,
1089 &dev->channel[i].RingBuffer,
1090 RingBufferSizes[i]);
1091 if (status < 0)
1092 break;
1093
1094 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1095 status = AllocateRingBuffers(dev->pci_dev,
1096 dev->
1097 PAOverflowBuffer,
1098 &dev->channel[i].
1099 RingBuffer,
1100 Buffer1Sizes[i],
1101 Buffer2Sizes[i]);
1102 if (status < 0)
1103 break;
1104 } else if (type & NGENE_IO_HDTV) {
1105 status = AllocateRingBuffers(dev->pci_dev,
1106 dev->
1107 PAOverflowBuffer,
1108 &dev->channel[i].
1109 RingBuffer,
1110 MAX_HDTV_BUFFER_SIZE,
1111 0);
1112 if (status < 0)
1113 break;
1114 }
1115 }
1116
1117 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1118
1119 status = create_ring_buffer(dev->pci_dev,
1120 &dev->channel[i].
1121 TSRingBuffer, RING_SIZE_TS);
1122 if (status < 0)
1123 break;
1124
1125 status = AllocateRingBuffers(dev->pci_dev,
1126 dev->PAOverflowBuffer,
1127 &dev->channel[i].
1128 TSRingBuffer,
1129 MAX_TS_BUFFER_SIZE, 0);
1130 if (status)
1131 break;
1132 }
1133
1134 if (type & NGENE_IO_TSOUT) {
1135 status = create_ring_buffer(dev->pci_dev,
1136 &dev->channel[i].
1137 TSIdleBuffer, 1);
1138 if (status < 0)
1139 break;
1140 status = AllocateRingBuffers(dev->pci_dev,
1141 dev->PAOverflowBuffer,
1142 &dev->channel[i].
1143 TSIdleBuffer,
1144 MAX_TS_BUFFER_SIZE, 0);
1145 if (status)
1146 break;
1147 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1148 &dev->channel[i].TSRingBuffer);
1149 }
1150 }
1151 return status;
1152 }
1153
1154 static void ngene_release_buffers(struct ngene *dev)
1155 {
1156 if (dev->iomem)
1157 iounmap(dev->iomem);
1158 free_common_buffers(dev);
1159 vfree(dev->tsout_buf);
1160 vfree(dev->tsin_buf);
1161 vfree(dev->ain_buf);
1162 vfree(dev->vin_buf);
1163 vfree(dev);
1164 }
1165
1166 static int ngene_get_buffers(struct ngene *dev)
1167 {
1168 if (AllocCommonBuffers(dev))
1169 return -ENOMEM;
1170 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1171 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1172 if (!dev->tsout_buf)
1173 return -ENOMEM;
1174 dvb_ringbuffer_init(&dev->tsout_rbuf,
1175 dev->tsout_buf, TSOUT_BUF_SIZE);
1176 }
1177 if (dev->card_info->io_type[2]&NGENE_IO_TSIN) {
1178 dev->tsin_buf = vmalloc(TSIN_BUF_SIZE);
1179 if (!dev->tsin_buf)
1180 return -ENOMEM;
1181 dvb_ringbuffer_init(&dev->tsin_rbuf,
1182 dev->tsin_buf, TSIN_BUF_SIZE);
1183 }
1184 if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1185 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1186 if (!dev->ain_buf)
1187 return -ENOMEM;
1188 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1189 }
1190 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1191 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1192 if (!dev->vin_buf)
1193 return -ENOMEM;
1194 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1195 }
1196 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1197 pci_resource_len(dev->pci_dev, 0));
1198 if (!dev->iomem)
1199 return -ENOMEM;
1200
1201 return 0;
1202 }
1203
1204 static void ngene_init(struct ngene *dev)
1205 {
1206 int i;
1207
1208 tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
1209
1210 memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1211 memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1212
1213 for (i = 0; i < MAX_STREAM; i++) {
1214 dev->channel[i].dev = dev;
1215 dev->channel[i].number = i;
1216 }
1217
1218 dev->fw_interface_version = 0;
1219
1220 ngwritel(0, NGENE_INT_ENABLE);
1221
1222 dev->icounts = ngreadl(NGENE_INT_COUNTS);
1223
1224 dev->device_version = ngreadl(DEV_VER) & 0x0f;
1225 printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
1226 dev->device_version);
1227 }
1228
1229 static int ngene_load_firm(struct ngene *dev)
1230 {
1231 u32 size;
1232 const struct firmware *fw = NULL;
1233 u8 *ngene_fw;
1234 char *fw_name;
1235 int err, version;
1236
1237 version = dev->card_info->fw_version;
1238
1239 switch (version) {
1240 default:
1241 case 15:
1242 version = 15;
1243 size = 23466;
1244 fw_name = "ngene_15.fw";
1245 dev->cmd_timeout_workaround = true;
1246 break;
1247 case 16:
1248 size = 23498;
1249 fw_name = "ngene_16.fw";
1250 dev->cmd_timeout_workaround = true;
1251 break;
1252 case 17:
1253 size = 24446;
1254 fw_name = "ngene_17.fw";
1255 dev->cmd_timeout_workaround = true;
1256 break;
1257 case 18:
1258 size = 0;
1259 fw_name = "ngene_18.fw";
1260 break;
1261 }
1262
1263 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1264 printk(KERN_ERR DEVICE_NAME
1265 ": Could not load firmware file %s.\n", fw_name);
1266 printk(KERN_INFO DEVICE_NAME
1267 ": Copy %s to your hotplug directory!\n", fw_name);
1268 return -1;
1269 }
1270 if (size == 0)
1271 size = fw->size;
1272 if (size != fw->size) {
1273 printk(KERN_ERR DEVICE_NAME
1274 ": Firmware %s has invalid size!", fw_name);
1275 err = -1;
1276 } else {
1277 printk(KERN_INFO DEVICE_NAME
1278 ": Loading firmware file %s.\n", fw_name);
1279 ngene_fw = (u8 *) fw->data;
1280 err = ngene_command_load_firmware(dev, ngene_fw, size);
1281 }
1282
1283 release_firmware(fw);
1284
1285 return err;
1286 }
1287
1288 static void ngene_stop(struct ngene *dev)
1289 {
1290 down(&dev->cmd_mutex);
1291 i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1292 i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1293 ngwritel(0, NGENE_INT_ENABLE);
1294 ngwritel(0, NGENE_COMMAND);
1295 ngwritel(0, NGENE_COMMAND_HI);
1296 ngwritel(0, NGENE_STATUS);
1297 ngwritel(0, NGENE_STATUS_HI);
1298 ngwritel(0, NGENE_EVENT);
1299 ngwritel(0, NGENE_EVENT_HI);
1300 free_irq(dev->pci_dev->irq, dev);
1301 #ifdef CONFIG_PCI_MSI
1302 if (dev->msi_enabled)
1303 pci_disable_msi(dev->pci_dev);
1304 #endif
1305 }
1306
1307 static int ngene_buffer_config(struct ngene *dev)
1308 {
1309 int stat;
1310
1311 if (dev->card_info->fw_version >= 17) {
1312 u8 tsin12_config[6] = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 };
1313 u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 };
1314 u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 };
1315 u8 *bconf = tsin12_config;
1316
1317 if (dev->card_info->io_type[2]&NGENE_IO_TSIN &&
1318 dev->card_info->io_type[3]&NGENE_IO_TSIN) {
1319 bconf = tsin1234_config;
1320 if (dev->card_info->io_type[4]&NGENE_IO_TSOUT &&
1321 dev->ci.en)
1322 bconf = tsio1235_config;
1323 }
1324 stat = ngene_command_config_free_buf(dev, bconf);
1325 } else {
1326 int bconf = BUFFER_CONFIG_4422;
1327
1328 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1329 bconf = BUFFER_CONFIG_3333;
1330 stat = ngene_command_config_buf(dev, bconf);
1331 }
1332 return stat;
1333 }
1334
1335
1336 static int ngene_start(struct ngene *dev)
1337 {
1338 int stat;
1339 int i;
1340
1341 pci_set_master(dev->pci_dev);
1342 ngene_init(dev);
1343
1344 stat = request_irq(dev->pci_dev->irq, irq_handler,
1345 IRQF_SHARED, "nGene",
1346 (void *)dev);
1347 if (stat < 0)
1348 return stat;
1349
1350 init_waitqueue_head(&dev->cmd_wq);
1351 init_waitqueue_head(&dev->tx_wq);
1352 init_waitqueue_head(&dev->rx_wq);
1353 sema_init(&dev->cmd_mutex, 1);
1354 sema_init(&dev->stream_mutex, 1);
1355 sema_init(&dev->pll_mutex, 1);
1356 sema_init(&dev->i2c_switch_mutex, 1);
1357 spin_lock_init(&dev->cmd_lock);
1358 for (i = 0; i < MAX_STREAM; i++)
1359 spin_lock_init(&dev->channel[i].state_lock);
1360 ngwritel(1, TIMESTAMPS);
1361
1362 ngwritel(1, NGENE_INT_ENABLE);
1363
1364 stat = ngene_load_firm(dev);
1365 if (stat < 0)
1366 goto fail;
1367
1368 #ifdef CONFIG_PCI_MSI
1369 /* enable MSI if kernel and card support it */
1370 if (pci_msi_enabled() && dev->card_info->msi_supported) {
1371 unsigned long flags;
1372
1373 ngwritel(0, NGENE_INT_ENABLE);
1374 free_irq(dev->pci_dev->irq, dev);
1375 stat = pci_enable_msi(dev->pci_dev);
1376 if (stat) {
1377 printk(KERN_INFO DEVICE_NAME
1378 ": MSI not available\n");
1379 flags = IRQF_SHARED;
1380 } else {
1381 flags = 0;
1382 dev->msi_enabled = true;
1383 }
1384 stat = request_irq(dev->pci_dev->irq, irq_handler,
1385 flags, "nGene", dev);
1386 if (stat < 0)
1387 goto fail2;
1388 ngwritel(1, NGENE_INT_ENABLE);
1389 }
1390 #endif
1391
1392 stat = ngene_i2c_init(dev, 0);
1393 if (stat < 0)
1394 goto fail;
1395
1396 stat = ngene_i2c_init(dev, 1);
1397 if (stat < 0)
1398 goto fail;
1399
1400 return 0;
1401
1402 fail:
1403 ngwritel(0, NGENE_INT_ENABLE);
1404 free_irq(dev->pci_dev->irq, dev);
1405 #ifdef CONFIG_PCI_MSI
1406 fail2:
1407 if (dev->msi_enabled)
1408 pci_disable_msi(dev->pci_dev);
1409 #endif
1410 return stat;
1411 }
1412
1413 /****************************************************************************/
1414 /****************************************************************************/
1415 /****************************************************************************/
1416
1417 static void release_channel(struct ngene_channel *chan)
1418 {
1419 struct dvb_demux *dvbdemux = &chan->demux;
1420 struct ngene *dev = chan->dev;
1421
1422 if (chan->running)
1423 set_transfer(chan, 0);
1424
1425 tasklet_kill(&chan->demux_tasklet);
1426
1427 if (chan->ci_dev) {
1428 dvb_unregister_device(chan->ci_dev);
1429 chan->ci_dev = NULL;
1430 }
1431
1432 if (chan->fe2)
1433 dvb_unregister_frontend(chan->fe2);
1434
1435 if (chan->fe) {
1436 dvb_unregister_frontend(chan->fe);
1437 dvb_frontend_detach(chan->fe);
1438 chan->fe = NULL;
1439 }
1440
1441 if (chan->has_demux) {
1442 dvb_net_release(&chan->dvbnet);
1443 dvbdemux->dmx.close(&dvbdemux->dmx);
1444 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1445 &chan->hw_frontend);
1446 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1447 &chan->mem_frontend);
1448 dvb_dmxdev_release(&chan->dmxdev);
1449 dvb_dmx_release(&chan->demux);
1450 chan->has_demux = false;
1451 }
1452
1453 if (chan->has_adapter) {
1454 dvb_unregister_adapter(&dev->adapter[chan->number]);
1455 chan->has_adapter = false;
1456 }
1457 }
1458
1459 static int init_channel(struct ngene_channel *chan)
1460 {
1461 int ret = 0, nr = chan->number;
1462 struct dvb_adapter *adapter = NULL;
1463 struct dvb_demux *dvbdemux = &chan->demux;
1464 struct ngene *dev = chan->dev;
1465 struct ngene_info *ni = dev->card_info;
1466 int io = ni->io_type[nr];
1467
1468 tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
1469 chan->users = 0;
1470 chan->type = io;
1471 chan->mode = chan->type; /* for now only one mode */
1472
1473 if (io & NGENE_IO_TSIN) {
1474 chan->fe = NULL;
1475 if (ni->demod_attach[nr]) {
1476 ret = ni->demod_attach[nr](chan);
1477 if (ret < 0)
1478 goto err;
1479 }
1480 if (chan->fe && ni->tuner_attach[nr]) {
1481 ret = ni->tuner_attach[nr](chan);
1482 if (ret < 0)
1483 goto err;
1484 }
1485 }
1486
1487 if (!dev->ci.en && (io & NGENE_IO_TSOUT))
1488 return 0;
1489
1490 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1491 if (nr >= STREAM_AUDIOIN1)
1492 chan->DataFormatFlags = DF_SWAP32;
1493
1494 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) {
1495 adapter = &dev->adapter[nr];
1496 ret = dvb_register_adapter(adapter, "nGene",
1497 THIS_MODULE,
1498 &chan->dev->pci_dev->dev,
1499 adapter_nr);
1500 if (ret < 0)
1501 goto err;
1502 if (dev->first_adapter == NULL)
1503 dev->first_adapter = adapter;
1504 chan->has_adapter = true;
1505 } else
1506 adapter = dev->first_adapter;
1507 }
1508
1509 if (dev->ci.en && (io & NGENE_IO_TSOUT)) {
1510 dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1);
1511 set_transfer(chan, 1);
1512 chan->dev->channel[2].DataFormatFlags = DF_SWAP32;
1513 set_transfer(&chan->dev->channel[2], 1);
1514 dvb_register_device(adapter, &chan->ci_dev,
1515 &ngene_dvbdev_ci, (void *) chan,
1516 DVB_DEVICE_SEC);
1517 if (!chan->ci_dev)
1518 goto err;
1519 }
1520
1521 if (chan->fe) {
1522 if (dvb_register_frontend(adapter, chan->fe) < 0)
1523 goto err;
1524 chan->has_demux = true;
1525 }
1526 if (chan->fe2) {
1527 if (dvb_register_frontend(adapter, chan->fe2) < 0)
1528 goto err;
1529 if (chan->fe) {
1530 chan->fe2->tuner_priv = chan->fe->tuner_priv;
1531 memcpy(&chan->fe2->ops.tuner_ops,
1532 &chan->fe->ops.tuner_ops,
1533 sizeof(struct dvb_tuner_ops));
1534 }
1535 }
1536
1537 if (chan->has_demux) {
1538 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1539 ngene_start_feed,
1540 ngene_stop_feed, chan);
1541 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1542 &chan->hw_frontend,
1543 &chan->mem_frontend, adapter);
1544 ret = dvb_net_init(adapter, &chan->dvbnet, &chan->demux.dmx);
1545 }
1546
1547 return ret;
1548
1549 err:
1550 if (chan->fe) {
1551 dvb_frontend_detach(chan->fe);
1552 chan->fe = NULL;
1553 }
1554 release_channel(chan);
1555 return 0;
1556 }
1557
1558 static int init_channels(struct ngene *dev)
1559 {
1560 int i, j;
1561
1562 for (i = 0; i < MAX_STREAM; i++) {
1563 dev->channel[i].number = i;
1564 if (init_channel(&dev->channel[i]) < 0) {
1565 for (j = i - 1; j >= 0; j--)
1566 release_channel(&dev->channel[j]);
1567 return -1;
1568 }
1569 }
1570 return 0;
1571 }
1572
1573 static struct cxd2099_cfg cxd_cfg = {
1574 .bitrate = 62000,
1575 .adr = 0x40,
1576 .polarity = 0,
1577 .clock_mode = 0,
1578 };
1579
1580 static void cxd_attach(struct ngene *dev)
1581 {
1582 struct ngene_ci *ci = &dev->ci;
1583
1584 ci->en = cxd2099_attach(&cxd_cfg, dev, &dev->channel[0].i2c_adapter);
1585 ci->dev = dev;
1586 return;
1587 }
1588
1589 static void cxd_detach(struct ngene *dev)
1590 {
1591 struct ngene_ci *ci = &dev->ci;
1592
1593 dvb_ca_en50221_release(ci->en);
1594 kfree(ci->en);
1595 ci->en = NULL;
1596 }
1597
1598 /***********************************/
1599 /* workaround for shutdown failure */
1600 /***********************************/
1601
1602 static void ngene_unlink(struct ngene *dev)
1603 {
1604 struct ngene_command com;
1605
1606 com.cmd.hdr.Opcode = CMD_MEM_WRITE;
1607 com.cmd.hdr.Length = 3;
1608 com.cmd.MemoryWrite.address = 0x910c;
1609 com.cmd.MemoryWrite.data = 0xff;
1610 com.in_len = 3;
1611 com.out_len = 1;
1612
1613 down(&dev->cmd_mutex);
1614 ngwritel(0, NGENE_INT_ENABLE);
1615 ngene_command_mutex(dev, &com);
1616 up(&dev->cmd_mutex);
1617 }
1618
1619 void ngene_shutdown(struct pci_dev *pdev)
1620 {
1621 struct ngene *dev = pci_get_drvdata(pdev);
1622
1623 if (!dev || !shutdown_workaround)
1624 return;
1625
1626 printk(KERN_INFO DEVICE_NAME ": shutdown workaround...\n");
1627 ngene_unlink(dev);
1628 pci_disable_device(pdev);
1629 }
1630
1631 /****************************************************************************/
1632 /* device probe/remove calls ************************************************/
1633 /****************************************************************************/
1634
1635 void ngene_remove(struct pci_dev *pdev)
1636 {
1637 struct ngene *dev = pci_get_drvdata(pdev);
1638 int i;
1639
1640 tasklet_kill(&dev->event_tasklet);
1641 for (i = MAX_STREAM - 1; i >= 0; i--)
1642 release_channel(&dev->channel[i]);
1643 if (dev->ci.en)
1644 cxd_detach(dev);
1645 ngene_stop(dev);
1646 ngene_release_buffers(dev);
1647 pci_disable_device(pdev);
1648 }
1649
1650 int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
1651 {
1652 struct ngene *dev;
1653 int stat = 0;
1654
1655 if (pci_enable_device(pci_dev) < 0)
1656 return -ENODEV;
1657
1658 dev = vzalloc(sizeof(struct ngene));
1659 if (dev == NULL) {
1660 stat = -ENOMEM;
1661 goto fail0;
1662 }
1663
1664 dev->pci_dev = pci_dev;
1665 dev->card_info = (struct ngene_info *)id->driver_data;
1666 printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
1667
1668 pci_set_drvdata(pci_dev, dev);
1669
1670 /* Alloc buffers and start nGene */
1671 stat = ngene_get_buffers(dev);
1672 if (stat < 0)
1673 goto fail1;
1674 stat = ngene_start(dev);
1675 if (stat < 0)
1676 goto fail1;
1677
1678 cxd_attach(dev);
1679
1680 stat = ngene_buffer_config(dev);
1681 if (stat < 0)
1682 goto fail1;
1683
1684
1685 dev->i2c_current_bus = -1;
1686
1687 /* Register DVB adapters and devices for both channels */
1688 stat = init_channels(dev);
1689 if (stat < 0)
1690 goto fail2;
1691
1692 return 0;
1693
1694 fail2:
1695 ngene_stop(dev);
1696 fail1:
1697 ngene_release_buffers(dev);
1698 fail0:
1699 pci_disable_device(pci_dev);
1700 return stat;
1701 }
Linux with added FPC-III support