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s390/ptrace: get rid of long longs in psw_bits
[linux/fpc-iii.git] / drivers / media / pci / smipcie / smipcie-main.c
blobb039a229b7d2baffde01fc9be0127a9cef254ec3
1 /*
2 * SMI PCIe driver for DVBSky cards.
3 *
4 * Copyright (C) 2014 Max nibble <nibble.max@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include "smipcie.h"
18 #include "m88ds3103.h"
19 #include "ts2020.h"
20 #include "m88rs6000t.h"
21 #include "si2168.h"
22 #include "si2157.h"
23
24 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
25
26 static int smi_hw_init(struct smi_dev *dev)
27 {
28 u32 port_mux, port_ctrl, int_stat;
29
30 /* set port mux.*/
31 port_mux = smi_read(MUX_MODE_CTRL);
32 port_mux &= ~(rbPaMSMask);
33 port_mux |= rbPaMSDtvNoGpio;
34 port_mux &= ~(rbPbMSMask);
35 port_mux |= rbPbMSDtvNoGpio;
36 port_mux &= ~(0x0f0000);
37 port_mux |= 0x50000;
38 smi_write(MUX_MODE_CTRL, port_mux);
39
40 /* set DTV register.*/
41 /* Port A */
42 port_ctrl = smi_read(VIDEO_CTRL_STATUS_A);
43 port_ctrl &= ~0x01;
44 smi_write(VIDEO_CTRL_STATUS_A, port_ctrl);
45 port_ctrl = smi_read(MPEG2_CTRL_A);
46 port_ctrl &= ~0x40;
47 port_ctrl |= 0x80;
48 smi_write(MPEG2_CTRL_A, port_ctrl);
49 /* Port B */
50 port_ctrl = smi_read(VIDEO_CTRL_STATUS_B);
51 port_ctrl &= ~0x01;
52 smi_write(VIDEO_CTRL_STATUS_B, port_ctrl);
53 port_ctrl = smi_read(MPEG2_CTRL_B);
54 port_ctrl &= ~0x40;
55 port_ctrl |= 0x80;
56 smi_write(MPEG2_CTRL_B, port_ctrl);
57
58 /* disable and clear interrupt.*/
59 smi_write(MSI_INT_ENA_CLR, ALL_INT);
60 int_stat = smi_read(MSI_INT_STATUS);
61 smi_write(MSI_INT_STATUS_CLR, int_stat);
62
63 /* reset demod.*/
64 smi_clear(PERIPHERAL_CTRL, 0x0303);
65 msleep(50);
66 smi_set(PERIPHERAL_CTRL, 0x0101);
67 return 0;
68 }
69
70 /* i2c bit bus.*/
71 static void smi_i2c_cfg(struct smi_dev *dev, u32 sw_ctl)
72 {
73 u32 dwCtrl;
74
75 dwCtrl = smi_read(sw_ctl);
76 dwCtrl &= ~0x18; /* disable output.*/
77 dwCtrl |= 0x21; /* reset and software mode.*/
78 dwCtrl &= ~0xff00;
79 dwCtrl |= 0x6400;
80 smi_write(sw_ctl, dwCtrl);
81 msleep(20);
82 dwCtrl = smi_read(sw_ctl);
83 dwCtrl &= ~0x20;
84 smi_write(sw_ctl, dwCtrl);
85 }
86
87 static void smi_i2c_setsda(struct smi_dev *dev, int state, u32 sw_ctl)
88 {
89 if (state) {
90 /* set as input.*/
91 smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
92 } else {
93 smi_clear(sw_ctl, SW_I2C_MSK_DAT_OUT);
94 /* set as output.*/
95 smi_set(sw_ctl, SW_I2C_MSK_DAT_EN);
96 }
97 }
98
99 static void smi_i2c_setscl(void *data, int state, u32 sw_ctl)
100 {
101 struct smi_dev *dev = data;
102
103 if (state) {
104 /* set as input.*/
105 smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
106 } else {
107 smi_clear(sw_ctl, SW_I2C_MSK_CLK_OUT);
108 /* set as output.*/
109 smi_set(sw_ctl, SW_I2C_MSK_CLK_EN);
110 }
111 }
112
113 static int smi_i2c_getsda(void *data, u32 sw_ctl)
114 {
115 struct smi_dev *dev = data;
116 /* set as input.*/
117 smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
118 udelay(1);
119 return (smi_read(sw_ctl) & SW_I2C_MSK_DAT_IN) ? 1 : 0;
120 }
121
122 static int smi_i2c_getscl(void *data, u32 sw_ctl)
123 {
124 struct smi_dev *dev = data;
125 /* set as input.*/
126 smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
127 udelay(1);
128 return (smi_read(sw_ctl) & SW_I2C_MSK_CLK_IN) ? 1 : 0;
129 }
130 /* i2c 0.*/
131 static void smi_i2c0_setsda(void *data, int state)
132 {
133 struct smi_dev *dev = data;
134
135 smi_i2c_setsda(dev, state, I2C_A_SW_CTL);
136 }
137
138 static void smi_i2c0_setscl(void *data, int state)
139 {
140 struct smi_dev *dev = data;
141
142 smi_i2c_setscl(dev, state, I2C_A_SW_CTL);
143 }
144
145 static int smi_i2c0_getsda(void *data)
146 {
147 struct smi_dev *dev = data;
148
149 return smi_i2c_getsda(dev, I2C_A_SW_CTL);
150 }
151
152 static int smi_i2c0_getscl(void *data)
153 {
154 struct smi_dev *dev = data;
155
156 return smi_i2c_getscl(dev, I2C_A_SW_CTL);
157 }
158 /* i2c 1.*/
159 static void smi_i2c1_setsda(void *data, int state)
160 {
161 struct smi_dev *dev = data;
162
163 smi_i2c_setsda(dev, state, I2C_B_SW_CTL);
164 }
165
166 static void smi_i2c1_setscl(void *data, int state)
167 {
168 struct smi_dev *dev = data;
169
170 smi_i2c_setscl(dev, state, I2C_B_SW_CTL);
171 }
172
173 static int smi_i2c1_getsda(void *data)
174 {
175 struct smi_dev *dev = data;
176
177 return smi_i2c_getsda(dev, I2C_B_SW_CTL);
178 }
179
180 static int smi_i2c1_getscl(void *data)
181 {
182 struct smi_dev *dev = data;
183
184 return smi_i2c_getscl(dev, I2C_B_SW_CTL);
185 }
186
187 static int smi_i2c_init(struct smi_dev *dev)
188 {
189 int ret;
190
191 /* i2c bus 0 */
192 smi_i2c_cfg(dev, I2C_A_SW_CTL);
193 i2c_set_adapdata(&dev->i2c_bus[0], dev);
194 strcpy(dev->i2c_bus[0].name, "SMI-I2C0");
195 dev->i2c_bus[0].owner = THIS_MODULE;
196 dev->i2c_bus[0].dev.parent = &dev->pci_dev->dev;
197 dev->i2c_bus[0].algo_data = &dev->i2c_bit[0];
198 dev->i2c_bit[0].data = dev;
199 dev->i2c_bit[0].setsda = smi_i2c0_setsda;
200 dev->i2c_bit[0].setscl = smi_i2c0_setscl;
201 dev->i2c_bit[0].getsda = smi_i2c0_getsda;
202 dev->i2c_bit[0].getscl = smi_i2c0_getscl;
203 dev->i2c_bit[0].udelay = 12;
204 dev->i2c_bit[0].timeout = 10;
205 /* Raise SCL and SDA */
206 smi_i2c0_setsda(dev, 1);
207 smi_i2c0_setscl(dev, 1);
208
209 ret = i2c_bit_add_bus(&dev->i2c_bus[0]);
210 if (ret < 0)
211 return ret;
212
213 /* i2c bus 1 */
214 smi_i2c_cfg(dev, I2C_B_SW_CTL);
215 i2c_set_adapdata(&dev->i2c_bus[1], dev);
216 strcpy(dev->i2c_bus[1].name, "SMI-I2C1");
217 dev->i2c_bus[1].owner = THIS_MODULE;
218 dev->i2c_bus[1].dev.parent = &dev->pci_dev->dev;
219 dev->i2c_bus[1].algo_data = &dev->i2c_bit[1];
220 dev->i2c_bit[1].data = dev;
221 dev->i2c_bit[1].setsda = smi_i2c1_setsda;
222 dev->i2c_bit[1].setscl = smi_i2c1_setscl;
223 dev->i2c_bit[1].getsda = smi_i2c1_getsda;
224 dev->i2c_bit[1].getscl = smi_i2c1_getscl;
225 dev->i2c_bit[1].udelay = 12;
226 dev->i2c_bit[1].timeout = 10;
227 /* Raise SCL and SDA */
228 smi_i2c1_setsda(dev, 1);
229 smi_i2c1_setscl(dev, 1);
230
231 ret = i2c_bit_add_bus(&dev->i2c_bus[1]);
232 if (ret < 0)
233 i2c_del_adapter(&dev->i2c_bus[0]);
234
235 return ret;
236 }
237
238 static void smi_i2c_exit(struct smi_dev *dev)
239 {
240 i2c_del_adapter(&dev->i2c_bus[0]);
241 i2c_del_adapter(&dev->i2c_bus[1]);
242 }
243
244 static int smi_read_eeprom(struct i2c_adapter *i2c, u16 reg, u8 *data, u16 size)
245 {
246 int ret;
247 u8 b0[2] = { (reg >> 8) & 0xff, reg & 0xff };
248
249 struct i2c_msg msg[] = {
250 { .addr = 0x50, .flags = 0,
251 .buf = b0, .len = 2 },
252 { .addr = 0x50, .flags = I2C_M_RD,
253 .buf = data, .len = size }
254 };
255
256 ret = i2c_transfer(i2c, msg, 2);
257
258 if (ret != 2) {
259 dev_err(&i2c->dev, "%s: reg=0x%x (error=%d)\n",
260 __func__, reg, ret);
261 return ret;
262 }
263 return ret;
264 }
265
266 /* ts port interrupt operations */
267 static void smi_port_disableInterrupt(struct smi_port *port)
268 {
269 struct smi_dev *dev = port->dev;
270
271 smi_write(MSI_INT_ENA_CLR,
272 (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
273 }
274
275 static void smi_port_enableInterrupt(struct smi_port *port)
276 {
277 struct smi_dev *dev = port->dev;
278
279 smi_write(MSI_INT_ENA_SET,
280 (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
281 }
282
283 static void smi_port_clearInterrupt(struct smi_port *port)
284 {
285 struct smi_dev *dev = port->dev;
286
287 smi_write(MSI_INT_STATUS_CLR,
288 (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
289 }
290
291 /* tasklet handler: DMA data to dmx.*/
292 static void smi_dma_xfer(unsigned long data)
293 {
294 struct smi_port *port = (struct smi_port *) data;
295 struct smi_dev *dev = port->dev;
296 u32 intr_status, finishedData, dmaManagement;
297 u8 dmaChan0State, dmaChan1State;
298
299 intr_status = port->_int_status;
300 dmaManagement = smi_read(port->DMA_MANAGEMENT);
301 dmaChan0State = (u8)((dmaManagement & 0x00000030) >> 4);
302 dmaChan1State = (u8)((dmaManagement & 0x00300000) >> 20);
303
304 /* CH-0 DMA interrupt.*/
305 if ((intr_status & port->_dmaInterruptCH0) && (dmaChan0State == 0x01)) {
306 dev_dbg(&dev->pci_dev->dev,
307 "Port[%d]-DMA CH0 engine complete successful !\n",
308 port->idx);
309 finishedData = smi_read(port->DMA_CHAN0_TRANS_STATE);
310 finishedData &= 0x003FFFFF;
311 /* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
312 * indicate dma total transfer length and
313 * zero of [21:0] indicate dma total transfer length
314 * equal to 0x400000 (4MB)*/
315 if (finishedData == 0)
316 finishedData = 0x00400000;
317 if (finishedData != SMI_TS_DMA_BUF_SIZE) {
318 dev_dbg(&dev->pci_dev->dev,
319 "DMA CH0 engine complete length mismatched, finish data=%d !\n",
320 finishedData);
321 }
322 dvb_dmx_swfilter_packets(&port->demux,
323 port->cpu_addr[0], (finishedData / 188));
324 /*dvb_dmx_swfilter(&port->demux,
325 port->cpu_addr[0], finishedData);*/
326 }
327 /* CH-1 DMA interrupt.*/
328 if ((intr_status & port->_dmaInterruptCH1) && (dmaChan1State == 0x01)) {
329 dev_dbg(&dev->pci_dev->dev,
330 "Port[%d]-DMA CH1 engine complete successful !\n",
331 port->idx);
332 finishedData = smi_read(port->DMA_CHAN1_TRANS_STATE);
333 finishedData &= 0x003FFFFF;
334 /* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
335 * indicate dma total transfer length and
336 * zero of [21:0] indicate dma total transfer length
337 * equal to 0x400000 (4MB)*/
338 if (finishedData == 0)
339 finishedData = 0x00400000;
340 if (finishedData != SMI_TS_DMA_BUF_SIZE) {
341 dev_dbg(&dev->pci_dev->dev,
342 "DMA CH1 engine complete length mismatched, finish data=%d !\n",
343 finishedData);
344 }
345 dvb_dmx_swfilter_packets(&port->demux,
346 port->cpu_addr[1], (finishedData / 188));
347 /*dvb_dmx_swfilter(&port->demux,
348 port->cpu_addr[1], finishedData);*/
349 }
350 /* restart DMA.*/
351 if (intr_status & port->_dmaInterruptCH0)
352 dmaManagement |= 0x00000002;
353 if (intr_status & port->_dmaInterruptCH1)
354 dmaManagement |= 0x00020000;
355 smi_write(port->DMA_MANAGEMENT, dmaManagement);
356 /* Re-enable interrupts */
357 smi_port_enableInterrupt(port);
358 }
359
360 static void smi_port_dma_free(struct smi_port *port)
361 {
362 if (port->cpu_addr[0]) {
363 pci_free_consistent(port->dev->pci_dev, SMI_TS_DMA_BUF_SIZE,
364 port->cpu_addr[0], port->dma_addr[0]);
365 port->cpu_addr[0] = NULL;
366 }
367 if (port->cpu_addr[1]) {
368 pci_free_consistent(port->dev->pci_dev, SMI_TS_DMA_BUF_SIZE,
369 port->cpu_addr[1], port->dma_addr[1]);
370 port->cpu_addr[1] = NULL;
371 }
372 }
373
374 static int smi_port_init(struct smi_port *port, int dmaChanUsed)
375 {
376 dev_dbg(&port->dev->pci_dev->dev,
377 "%s, port %d, dmaused %d\n", __func__, port->idx, dmaChanUsed);
378 port->enable = 0;
379 if (port->idx == 0) {
380 /* Port A */
381 port->_dmaInterruptCH0 = dmaChanUsed & 0x01;
382 port->_dmaInterruptCH1 = dmaChanUsed & 0x02;
383
384 port->DMA_CHAN0_ADDR_LOW = DMA_PORTA_CHAN0_ADDR_LOW;
385 port->DMA_CHAN0_ADDR_HI = DMA_PORTA_CHAN0_ADDR_HI;
386 port->DMA_CHAN0_TRANS_STATE = DMA_PORTA_CHAN0_TRANS_STATE;
387 port->DMA_CHAN0_CONTROL = DMA_PORTA_CHAN0_CONTROL;
388 port->DMA_CHAN1_ADDR_LOW = DMA_PORTA_CHAN1_ADDR_LOW;
389 port->DMA_CHAN1_ADDR_HI = DMA_PORTA_CHAN1_ADDR_HI;
390 port->DMA_CHAN1_TRANS_STATE = DMA_PORTA_CHAN1_TRANS_STATE;
391 port->DMA_CHAN1_CONTROL = DMA_PORTA_CHAN1_CONTROL;
392 port->DMA_MANAGEMENT = DMA_PORTA_MANAGEMENT;
393 } else {
394 /* Port B */
395 port->_dmaInterruptCH0 = (dmaChanUsed << 2) & 0x04;
396 port->_dmaInterruptCH1 = (dmaChanUsed << 2) & 0x08;
397
398 port->DMA_CHAN0_ADDR_LOW = DMA_PORTB_CHAN0_ADDR_LOW;
399 port->DMA_CHAN0_ADDR_HI = DMA_PORTB_CHAN0_ADDR_HI;
400 port->DMA_CHAN0_TRANS_STATE = DMA_PORTB_CHAN0_TRANS_STATE;
401 port->DMA_CHAN0_CONTROL = DMA_PORTB_CHAN0_CONTROL;
402 port->DMA_CHAN1_ADDR_LOW = DMA_PORTB_CHAN1_ADDR_LOW;
403 port->DMA_CHAN1_ADDR_HI = DMA_PORTB_CHAN1_ADDR_HI;
404 port->DMA_CHAN1_TRANS_STATE = DMA_PORTB_CHAN1_TRANS_STATE;
405 port->DMA_CHAN1_CONTROL = DMA_PORTB_CHAN1_CONTROL;
406 port->DMA_MANAGEMENT = DMA_PORTB_MANAGEMENT;
407 }
408
409 if (port->_dmaInterruptCH0) {
410 port->cpu_addr[0] = pci_alloc_consistent(port->dev->pci_dev,
411 SMI_TS_DMA_BUF_SIZE,
412 &port->dma_addr[0]);
413 if (!port->cpu_addr[0]) {
414 dev_err(&port->dev->pci_dev->dev,
415 "Port[%d] DMA CH0 memory allocation failed!\n",
416 port->idx);
417 goto err;
418 }
419 }
420
421 if (port->_dmaInterruptCH1) {
422 port->cpu_addr[1] = pci_alloc_consistent(port->dev->pci_dev,
423 SMI_TS_DMA_BUF_SIZE,
424 &port->dma_addr[1]);
425 if (!port->cpu_addr[1]) {
426 dev_err(&port->dev->pci_dev->dev,
427 "Port[%d] DMA CH1 memory allocation failed!\n",
428 port->idx);
429 goto err;
430 }
431 }
432
433 smi_port_disableInterrupt(port);
434 tasklet_init(&port->tasklet, smi_dma_xfer, (unsigned long)port);
435 tasklet_disable(&port->tasklet);
436 port->enable = 1;
437 return 0;
438 err:
439 smi_port_dma_free(port);
440 return -ENOMEM;
441 }
442
443 static void smi_port_exit(struct smi_port *port)
444 {
445 smi_port_disableInterrupt(port);
446 tasklet_kill(&port->tasklet);
447 smi_port_dma_free(port);
448 port->enable = 0;
449 }
450
451 static int smi_port_irq(struct smi_port *port, u32 int_status)
452 {
453 u32 port_req_irq = port->_dmaInterruptCH0 | port->_dmaInterruptCH1;
454 int handled = 0;
455
456 if (int_status & port_req_irq) {
457 smi_port_disableInterrupt(port);
458 port->_int_status = int_status;
459 smi_port_clearInterrupt(port);
460 tasklet_schedule(&port->tasklet);
461 handled = 1;
462 }
463 return handled;
464 }
465
466 static irqreturn_t smi_irq_handler(int irq, void *dev_id)
467 {
468 struct smi_dev *dev = dev_id;
469 struct smi_port *port0 = &dev->ts_port[0];
470 struct smi_port *port1 = &dev->ts_port[1];
471 struct smi_rc *ir = &dev->ir;
472 int handled = 0;
473
474 u32 intr_status = smi_read(MSI_INT_STATUS);
475
476 /* ts0 interrupt.*/
477 if (dev->info->ts_0)
478 handled += smi_port_irq(port0, intr_status);
479
480 /* ts1 interrupt.*/
481 if (dev->info->ts_1)
482 handled += smi_port_irq(port1, intr_status);
483
484 /* ir interrupt.*/
485 handled += smi_ir_irq(ir, intr_status);
486
487 return IRQ_RETVAL(handled);
488 }
489
490 static struct i2c_client *smi_add_i2c_client(struct i2c_adapter *adapter,
491 struct i2c_board_info *info)
492 {
493 struct i2c_client *client;
494
495 request_module(info->type);
496 client = i2c_new_device(adapter, info);
497 if (client == NULL || client->dev.driver == NULL)
498 goto err_add_i2c_client;
499
500 if (!try_module_get(client->dev.driver->owner)) {
501 i2c_unregister_device(client);
502 goto err_add_i2c_client;
503 }
504 return client;
505
506 err_add_i2c_client:
507 client = NULL;
508 return client;
509 }
510
511 static void smi_del_i2c_client(struct i2c_client *client)
512 {
513 module_put(client->dev.driver->owner);
514 i2c_unregister_device(client);
515 }
516
517 static const struct m88ds3103_config smi_dvbsky_m88ds3103_cfg = {
518 .i2c_addr = 0x68,
519 .clock = 27000000,
520 .i2c_wr_max = 33,
521 .clock_out = 0,
522 .ts_mode = M88DS3103_TS_PARALLEL,
523 .ts_clk = 16000,
524 .ts_clk_pol = 1,
525 .agc = 0x99,
526 .lnb_hv_pol = 0,
527 .lnb_en_pol = 1,
528 };
529
530 static int smi_dvbsky_m88ds3103_fe_attach(struct smi_port *port)
531 {
532 int ret = 0;
533 struct smi_dev *dev = port->dev;
534 struct i2c_adapter *i2c;
535 /* tuner I2C module */
536 struct i2c_adapter *tuner_i2c_adapter;
537 struct i2c_client *tuner_client;
538 struct i2c_board_info tuner_info;
539 struct ts2020_config ts2020_config = {};
540 memset(&tuner_info, 0, sizeof(struct i2c_board_info));
541 i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
542
543 /* attach demod */
544 port->fe = dvb_attach(m88ds3103_attach,
545 &smi_dvbsky_m88ds3103_cfg, i2c, &tuner_i2c_adapter);
546 if (!port->fe) {
547 ret = -ENODEV;
548 return ret;
549 }
550 /* attach tuner */
551 ts2020_config.fe = port->fe;
552 strlcpy(tuner_info.type, "ts2020", I2C_NAME_SIZE);
553 tuner_info.addr = 0x60;
554 tuner_info.platform_data = &ts2020_config;
555 tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
556 if (!tuner_client) {
557 ret = -ENODEV;
558 goto err_tuner_i2c_device;
559 }
560
561 /* delegate signal strength measurement to tuner */
562 port->fe->ops.read_signal_strength =
563 port->fe->ops.tuner_ops.get_rf_strength;
564
565 port->i2c_client_tuner = tuner_client;
566 return ret;
567
568 err_tuner_i2c_device:
569 dvb_frontend_detach(port->fe);
570 return ret;
571 }
572
573 static const struct m88ds3103_config smi_dvbsky_m88rs6000_cfg = {
574 .i2c_addr = 0x69,
575 .clock = 27000000,
576 .i2c_wr_max = 33,
577 .ts_mode = M88DS3103_TS_PARALLEL,
578 .ts_clk = 16000,
579 .ts_clk_pol = 1,
580 .agc = 0x99,
581 .lnb_hv_pol = 0,
582 .lnb_en_pol = 1,
583 };
584
585 static int smi_dvbsky_m88rs6000_fe_attach(struct smi_port *port)
586 {
587 int ret = 0;
588 struct smi_dev *dev = port->dev;
589 struct i2c_adapter *i2c;
590 /* tuner I2C module */
591 struct i2c_adapter *tuner_i2c_adapter;
592 struct i2c_client *tuner_client;
593 struct i2c_board_info tuner_info;
594 struct m88rs6000t_config m88rs6000t_config;
595
596 memset(&tuner_info, 0, sizeof(struct i2c_board_info));
597 i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
598
599 /* attach demod */
600 port->fe = dvb_attach(m88ds3103_attach,
601 &smi_dvbsky_m88rs6000_cfg, i2c, &tuner_i2c_adapter);
602 if (!port->fe) {
603 ret = -ENODEV;
604 return ret;
605 }
606 /* attach tuner */
607 m88rs6000t_config.fe = port->fe;
608 strlcpy(tuner_info.type, "m88rs6000t", I2C_NAME_SIZE);
609 tuner_info.addr = 0x21;
610 tuner_info.platform_data = &m88rs6000t_config;
611 tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
612 if (!tuner_client) {
613 ret = -ENODEV;
614 goto err_tuner_i2c_device;
615 }
616
617 /* delegate signal strength measurement to tuner */
618 port->fe->ops.read_signal_strength =
619 port->fe->ops.tuner_ops.get_rf_strength;
620
621 port->i2c_client_tuner = tuner_client;
622 return ret;
623
624 err_tuner_i2c_device:
625 dvb_frontend_detach(port->fe);
626 return ret;
627 }
628
629 static int smi_dvbsky_sit2_fe_attach(struct smi_port *port)
630 {
631 int ret = 0;
632 struct smi_dev *dev = port->dev;
633 struct i2c_adapter *i2c;
634 struct i2c_adapter *tuner_i2c_adapter;
635 struct i2c_client *client_tuner, *client_demod;
636 struct i2c_board_info client_info;
637 struct si2168_config si2168_config;
638 struct si2157_config si2157_config;
639
640 /* select i2c bus */
641 i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
642
643 /* attach demod */
644 memset(&si2168_config, 0, sizeof(si2168_config));
645 si2168_config.i2c_adapter = &tuner_i2c_adapter;
646 si2168_config.fe = &port->fe;
647 si2168_config.ts_mode = SI2168_TS_PARALLEL;
648
649 memset(&client_info, 0, sizeof(struct i2c_board_info));
650 strlcpy(client_info.type, "si2168", I2C_NAME_SIZE);
651 client_info.addr = 0x64;
652 client_info.platform_data = &si2168_config;
653
654 client_demod = smi_add_i2c_client(i2c, &client_info);
655 if (!client_demod) {
656 ret = -ENODEV;
657 return ret;
658 }
659 port->i2c_client_demod = client_demod;
660
661 /* attach tuner */
662 memset(&si2157_config, 0, sizeof(si2157_config));
663 si2157_config.fe = port->fe;
664 si2157_config.if_port = 1;
665
666 memset(&client_info, 0, sizeof(struct i2c_board_info));
667 strlcpy(client_info.type, "si2157", I2C_NAME_SIZE);
668 client_info.addr = 0x60;
669 client_info.platform_data = &si2157_config;
670
671 client_tuner = smi_add_i2c_client(tuner_i2c_adapter, &client_info);
672 if (!client_tuner) {
673 smi_del_i2c_client(port->i2c_client_demod);
674 port->i2c_client_demod = NULL;
675 ret = -ENODEV;
676 return ret;
677 }
678 port->i2c_client_tuner = client_tuner;
679 return ret;
680 }
681
682 static int smi_fe_init(struct smi_port *port)
683 {
684 int ret = 0;
685 struct smi_dev *dev = port->dev;
686 struct dvb_adapter *adap = &port->dvb_adapter;
687 u8 mac_ee[16];
688
689 dev_dbg(&port->dev->pci_dev->dev,
690 "%s: port %d, fe_type = %d\n",
691 __func__, port->idx, port->fe_type);
692 switch (port->fe_type) {
693 case DVBSKY_FE_M88DS3103:
694 ret = smi_dvbsky_m88ds3103_fe_attach(port);
695 break;
696 case DVBSKY_FE_M88RS6000:
697 ret = smi_dvbsky_m88rs6000_fe_attach(port);
698 break;
699 case DVBSKY_FE_SIT2:
700 ret = smi_dvbsky_sit2_fe_attach(port);
701 break;
702 }
703 if (ret < 0)
704 return ret;
705
706 /* register dvb frontend */
707 ret = dvb_register_frontend(adap, port->fe);
708 if (ret < 0) {
709 if (port->i2c_client_tuner)
710 smi_del_i2c_client(port->i2c_client_tuner);
711 if (port->i2c_client_demod)
712 smi_del_i2c_client(port->i2c_client_demod);
713 dvb_frontend_detach(port->fe);
714 return ret;
715 }
716 /* init MAC.*/
717 ret = smi_read_eeprom(&dev->i2c_bus[0], 0xc0, mac_ee, 16);
718 dev_info(&port->dev->pci_dev->dev,
719 "DVBSky SMI PCIe MAC= %pM\n", mac_ee + (port->idx)*8);
720 memcpy(adap->proposed_mac, mac_ee + (port->idx)*8, 6);
721 return ret;
722 }
723
724 static void smi_fe_exit(struct smi_port *port)
725 {
726 dvb_unregister_frontend(port->fe);
727 /* remove I2C demod and tuner */
728 if (port->i2c_client_tuner)
729 smi_del_i2c_client(port->i2c_client_tuner);
730 if (port->i2c_client_demod)
731 smi_del_i2c_client(port->i2c_client_demod);
732 dvb_frontend_detach(port->fe);
733 }
734
735 static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
736 int (*start_feed)(struct dvb_demux_feed *),
737 int (*stop_feed)(struct dvb_demux_feed *),
738 void *priv)
739 {
740 dvbdemux->priv = priv;
741
742 dvbdemux->filternum = 256;
743 dvbdemux->feednum = 256;
744 dvbdemux->start_feed = start_feed;
745 dvbdemux->stop_feed = stop_feed;
746 dvbdemux->write_to_decoder = NULL;
747 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
748 DMX_SECTION_FILTERING |
749 DMX_MEMORY_BASED_FILTERING);
750 return dvb_dmx_init(dvbdemux);
751 }
752
753 static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
754 struct dvb_demux *dvbdemux,
755 struct dmx_frontend *hw_frontend,
756 struct dmx_frontend *mem_frontend,
757 struct dvb_adapter *dvb_adapter)
758 {
759 int ret;
760
761 dmxdev->filternum = 256;
762 dmxdev->demux = &dvbdemux->dmx;
763 dmxdev->capabilities = 0;
764 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
765 if (ret < 0)
766 return ret;
767
768 hw_frontend->source = DMX_FRONTEND_0;
769 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
770 mem_frontend->source = DMX_MEMORY_FE;
771 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
772 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
773 }
774
775 static u32 smi_config_DMA(struct smi_port *port)
776 {
777 struct smi_dev *dev = port->dev;
778 u32 totalLength = 0, dmaMemPtrLow, dmaMemPtrHi, dmaCtlReg;
779 u8 chanLatencyTimer = 0, dmaChanEnable = 1, dmaTransStart = 1;
780 u32 dmaManagement = 0, tlpTransUnit = DMA_TRANS_UNIT_188;
781 u8 tlpTc = 0, tlpTd = 1, tlpEp = 0, tlpAttr = 0;
782 u64 mem;
783
784 dmaManagement = smi_read(port->DMA_MANAGEMENT);
785 /* Setup Channel-0 */
786 if (port->_dmaInterruptCH0) {
787 totalLength = SMI_TS_DMA_BUF_SIZE;
788 mem = port->dma_addr[0];
789 dmaMemPtrLow = mem & 0xffffffff;
790 dmaMemPtrHi = mem >> 32;
791 dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
792 | (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
793 dmaManagement |= dmaChanEnable | (dmaTransStart << 1)
794 | (chanLatencyTimer << 8);
795 /* write DMA register, start DMA engine */
796 smi_write(port->DMA_CHAN0_ADDR_LOW, dmaMemPtrLow);
797 smi_write(port->DMA_CHAN0_ADDR_HI, dmaMemPtrHi);
798 smi_write(port->DMA_CHAN0_CONTROL, dmaCtlReg);
799 }
800 /* Setup Channel-1 */
801 if (port->_dmaInterruptCH1) {
802 totalLength = SMI_TS_DMA_BUF_SIZE;
803 mem = port->dma_addr[1];
804 dmaMemPtrLow = mem & 0xffffffff;
805 dmaMemPtrHi = mem >> 32;
806 dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
807 | (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
808 dmaManagement |= (dmaChanEnable << 16) | (dmaTransStart << 17)
809 | (chanLatencyTimer << 24);
810 /* write DMA register, start DMA engine */
811 smi_write(port->DMA_CHAN1_ADDR_LOW, dmaMemPtrLow);
812 smi_write(port->DMA_CHAN1_ADDR_HI, dmaMemPtrHi);
813 smi_write(port->DMA_CHAN1_CONTROL, dmaCtlReg);
814 }
815 return dmaManagement;
816 }
817
818 static int smi_start_feed(struct dvb_demux_feed *dvbdmxfeed)
819 {
820 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
821 struct smi_port *port = dvbdmx->priv;
822 struct smi_dev *dev = port->dev;
823 u32 dmaManagement;
824
825 if (port->users++ == 0) {
826 dmaManagement = smi_config_DMA(port);
827 smi_port_clearInterrupt(port);
828 smi_port_enableInterrupt(port);
829 smi_write(port->DMA_MANAGEMENT, dmaManagement);
830 tasklet_enable(&port->tasklet);
831 }
832 return port->users;
833 }
834
835 static int smi_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
836 {
837 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
838 struct smi_port *port = dvbdmx->priv;
839 struct smi_dev *dev = port->dev;
840
841 if (--port->users)
842 return port->users;
843
844 tasklet_disable(&port->tasklet);
845 smi_port_disableInterrupt(port);
846 smi_clear(port->DMA_MANAGEMENT, 0x30003);
847 return 0;
848 }
849
850 static int smi_dvb_init(struct smi_port *port)
851 {
852 int ret;
853 struct dvb_adapter *adap = &port->dvb_adapter;
854 struct dvb_demux *dvbdemux = &port->demux;
855
856 dev_dbg(&port->dev->pci_dev->dev,
857 "%s, port %d\n", __func__, port->idx);
858
859 ret = dvb_register_adapter(adap, "SMI_DVB", THIS_MODULE,
860 &port->dev->pci_dev->dev,
861 adapter_nr);
862 if (ret < 0) {
863 dev_err(&port->dev->pci_dev->dev, "Fail to register DVB adapter.\n");
864 return ret;
865 }
866 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
867 smi_start_feed,
868 smi_stop_feed, port);
869 if (ret < 0)
870 goto err_del_dvb_register_adapter;
871
872 ret = my_dvb_dmxdev_ts_card_init(&port->dmxdev, &port->demux,
873 &port->hw_frontend,
874 &port->mem_frontend, adap);
875 if (ret < 0)
876 goto err_del_dvb_dmx;
877
878 ret = dvb_net_init(adap, &port->dvbnet, port->dmxdev.demux);
879 if (ret < 0)
880 goto err_del_dvb_dmxdev;
881 return 0;
882 err_del_dvb_dmxdev:
883 dvbdemux->dmx.close(&dvbdemux->dmx);
884 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
885 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
886 dvb_dmxdev_release(&port->dmxdev);
887 err_del_dvb_dmx:
888 dvb_dmx_release(&port->demux);
889 err_del_dvb_register_adapter:
890 dvb_unregister_adapter(&port->dvb_adapter);
891 return ret;
892 }
893
894 static void smi_dvb_exit(struct smi_port *port)
895 {
896 struct dvb_demux *dvbdemux = &port->demux;
897
898 dvb_net_release(&port->dvbnet);
899
900 dvbdemux->dmx.close(&dvbdemux->dmx);
901 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
902 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
903 dvb_dmxdev_release(&port->dmxdev);
904 dvb_dmx_release(&port->demux);
905
906 dvb_unregister_adapter(&port->dvb_adapter);
907 }
908
909 static int smi_port_attach(struct smi_dev *dev,
910 struct smi_port *port, int index)
911 {
912 int ret, dmachs;
913
914 port->dev = dev;
915 port->idx = index;
916 port->fe_type = (index == 0) ? dev->info->fe_0 : dev->info->fe_1;
917 dmachs = (index == 0) ? dev->info->ts_0 : dev->info->ts_1;
918 /* port init.*/
919 ret = smi_port_init(port, dmachs);
920 if (ret < 0)
921 return ret;
922 /* dvb init.*/
923 ret = smi_dvb_init(port);
924 if (ret < 0)
925 goto err_del_port_init;
926 /* fe init.*/
927 ret = smi_fe_init(port);
928 if (ret < 0)
929 goto err_del_dvb_init;
930 return 0;
931 err_del_dvb_init:
932 smi_dvb_exit(port);
933 err_del_port_init:
934 smi_port_exit(port);
935 return ret;
936 }
937
938 static void smi_port_detach(struct smi_port *port)
939 {
940 smi_fe_exit(port);
941 smi_dvb_exit(port);
942 smi_port_exit(port);
943 }
944
945 static int smi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
946 {
947 struct smi_dev *dev;
948 int ret = -ENOMEM;
949
950 if (pci_enable_device(pdev) < 0)
951 return -ENODEV;
952
953 dev = kzalloc(sizeof(struct smi_dev), GFP_KERNEL);
954 if (!dev) {
955 ret = -ENOMEM;
956 goto err_pci_disable_device;
957 }
958
959 dev->pci_dev = pdev;
960 pci_set_drvdata(pdev, dev);
961 dev->info = (struct smi_cfg_info *) id->driver_data;
962 dev_info(&dev->pci_dev->dev,
963 "card detected: %s\n", dev->info->name);
964
965 dev->nr = dev->info->type;
966 dev->lmmio = ioremap(pci_resource_start(dev->pci_dev, 0),
967 pci_resource_len(dev->pci_dev, 0));
968 if (!dev->lmmio) {
969 ret = -ENOMEM;
970 goto err_kfree;
971 }
972
973 /* should we set to 32bit DMA? */
974 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
975 if (ret < 0)
976 goto err_pci_iounmap;
977
978 pci_set_master(pdev);
979
980 ret = smi_hw_init(dev);
981 if (ret < 0)
982 goto err_pci_iounmap;
983
984 ret = smi_i2c_init(dev);
985 if (ret < 0)
986 goto err_pci_iounmap;
987
988 if (dev->info->ts_0) {
989 ret = smi_port_attach(dev, &dev->ts_port[0], 0);
990 if (ret < 0)
991 goto err_del_i2c_adaptor;
992 }
993
994 if (dev->info->ts_1) {
995 ret = smi_port_attach(dev, &dev->ts_port[1], 1);
996 if (ret < 0)
997 goto err_del_port0_attach;
998 }
999
1000 ret = smi_ir_init(dev);
1001 if (ret < 0)
1002 goto err_del_port1_attach;
1003
1004 #ifdef CONFIG_PCI_MSI /* to do msi interrupt.???*/
1005 if (pci_msi_enabled())
1006 ret = pci_enable_msi(dev->pci_dev);
1007 if (ret)
1008 dev_info(&dev->pci_dev->dev, "MSI not available.\n");
1009 #endif
1010
1011 ret = request_irq(dev->pci_dev->irq, smi_irq_handler,
1012 IRQF_SHARED, "SMI_PCIE", dev);
1013 if (ret < 0)
1014 goto err_del_ir;
1015
1016 smi_ir_start(&dev->ir);
1017 return 0;
1018
1019 err_del_ir:
1020 smi_ir_exit(dev);
1021 err_del_port1_attach:
1022 if (dev->info->ts_1)
1023 smi_port_detach(&dev->ts_port[1]);
1024 err_del_port0_attach:
1025 if (dev->info->ts_0)
1026 smi_port_detach(&dev->ts_port[0]);
1027 err_del_i2c_adaptor:
1028 smi_i2c_exit(dev);
1029 err_pci_iounmap:
1030 iounmap(dev->lmmio);
1031 err_kfree:
1032 pci_set_drvdata(pdev, NULL);
1033 kfree(dev);
1034 err_pci_disable_device:
1035 pci_disable_device(pdev);
1036 return ret;
1037 }
1038
1039 static void smi_remove(struct pci_dev *pdev)
1040 {
1041 struct smi_dev *dev = pci_get_drvdata(pdev);
1042
1043 smi_write(MSI_INT_ENA_CLR, ALL_INT);
1044 free_irq(dev->pci_dev->irq, dev);
1045 #ifdef CONFIG_PCI_MSI
1046 pci_disable_msi(dev->pci_dev);
1047 #endif
1048 if (dev->info->ts_1)
1049 smi_port_detach(&dev->ts_port[1]);
1050 if (dev->info->ts_0)
1051 smi_port_detach(&dev->ts_port[0]);
1052
1053 smi_ir_exit(dev);
1054 smi_i2c_exit(dev);
1055 iounmap(dev->lmmio);
1056 pci_set_drvdata(pdev, NULL);
1057 pci_disable_device(pdev);
1058 kfree(dev);
1059 }
1060
1061 /* DVBSky cards */
1062 static struct smi_cfg_info dvbsky_s950_cfg = {
1063 .type = SMI_DVBSKY_S950,
1064 .name = "DVBSky S950 V3",
1065 .ts_0 = SMI_TS_NULL,
1066 .ts_1 = SMI_TS_DMA_BOTH,
1067 .fe_0 = DVBSKY_FE_NULL,
1068 .fe_1 = DVBSKY_FE_M88DS3103,
1069 };
1070
1071 static struct smi_cfg_info dvbsky_s952_cfg = {
1072 .type = SMI_DVBSKY_S952,
1073 .name = "DVBSky S952 V3",
1074 .ts_0 = SMI_TS_DMA_BOTH,
1075 .ts_1 = SMI_TS_DMA_BOTH,
1076 .fe_0 = DVBSKY_FE_M88RS6000,
1077 .fe_1 = DVBSKY_FE_M88RS6000,
1078 };
1079
1080 static struct smi_cfg_info dvbsky_t9580_cfg = {
1081 .type = SMI_DVBSKY_T9580,
1082 .name = "DVBSky T9580 V3",
1083 .ts_0 = SMI_TS_DMA_BOTH,
1084 .ts_1 = SMI_TS_DMA_BOTH,
1085 .fe_0 = DVBSKY_FE_SIT2,
1086 .fe_1 = DVBSKY_FE_M88DS3103,
1087 };
1088
1089 /* PCI IDs */
1090 #define SMI_ID(_subvend, _subdev, _driverdata) { \
1091 .vendor = SMI_VID, .device = SMI_PID, \
1092 .subvendor = _subvend, .subdevice = _subdev, \
1093 .driver_data = (unsigned long)&_driverdata }
1094
1095 static const struct pci_device_id smi_id_table[] = {
1096 SMI_ID(0x4254, 0x0550, dvbsky_s950_cfg),
1097 SMI_ID(0x4254, 0x0552, dvbsky_s952_cfg),
1098 SMI_ID(0x4254, 0x5580, dvbsky_t9580_cfg),
1099 {0}
1100 };
1101 MODULE_DEVICE_TABLE(pci, smi_id_table);
1102
1103 static struct pci_driver smipcie_driver = {
1104 .name = "SMI PCIe driver",
1105 .id_table = smi_id_table,
1106 .probe = smi_probe,
1107 .remove = smi_remove,
1108 };
1109
1110 module_pci_driver(smipcie_driver);
1111
1112 MODULE_AUTHOR("Max nibble <nibble.max@gmail.com>");
1113 MODULE_DESCRIPTION("SMI PCIe driver");
1114 MODULE_LICENSE("GPL");
Linux with added FPC-III support