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s390/ptrace: get rid of long longs in psw_bits
[linux/fpc-iii.git] / drivers / pci / probe.c
blobedb1984201e9702162321c50f33f76ba362bac5a
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <asm-generic/pci-bridge.h>
19 #include "pci.h"
20
21 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
22 #define CARDBUS_RESERVE_BUSNR 3
23
24 static struct resource busn_resource = {
25 .name = "PCI busn",
26 .start = 0,
27 .end = 255,
28 .flags = IORESOURCE_BUS,
29 };
30
31 /* Ugh. Need to stop exporting this to modules. */
32 LIST_HEAD(pci_root_buses);
33 EXPORT_SYMBOL(pci_root_buses);
34
35 static LIST_HEAD(pci_domain_busn_res_list);
36
37 struct pci_domain_busn_res {
38 struct list_head list;
39 struct resource res;
40 int domain_nr;
41 };
42
43 static struct resource *get_pci_domain_busn_res(int domain_nr)
44 {
45 struct pci_domain_busn_res *r;
46
47 list_for_each_entry(r, &pci_domain_busn_res_list, list)
48 if (r->domain_nr == domain_nr)
49 return &r->res;
50
51 r = kzalloc(sizeof(*r), GFP_KERNEL);
52 if (!r)
53 return NULL;
54
55 r->domain_nr = domain_nr;
56 r->res.start = 0;
57 r->res.end = 0xff;
58 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
59
60 list_add_tail(&r->list, &pci_domain_busn_res_list);
61
62 return &r->res;
63 }
64
65 static int find_anything(struct device *dev, void *data)
66 {
67 return 1;
68 }
69
70 /*
71 * Some device drivers need know if pci is initiated.
72 * Basically, we think pci is not initiated when there
73 * is no device to be found on the pci_bus_type.
74 */
75 int no_pci_devices(void)
76 {
77 struct device *dev;
78 int no_devices;
79
80 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
81 no_devices = (dev == NULL);
82 put_device(dev);
83 return no_devices;
84 }
85 EXPORT_SYMBOL(no_pci_devices);
86
87 /*
88 * PCI Bus Class
89 */
90 static void release_pcibus_dev(struct device *dev)
91 {
92 struct pci_bus *pci_bus = to_pci_bus(dev);
93
94 put_device(pci_bus->bridge);
95 pci_bus_remove_resources(pci_bus);
96 pci_release_bus_of_node(pci_bus);
97 kfree(pci_bus);
98 }
99
100 static struct class pcibus_class = {
101 .name = "pci_bus",
102 .dev_release = &release_pcibus_dev,
103 .dev_groups = pcibus_groups,
104 };
105
106 static int __init pcibus_class_init(void)
107 {
108 return class_register(&pcibus_class);
109 }
110 postcore_initcall(pcibus_class_init);
111
112 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
113 {
114 u64 size = mask & maxbase; /* Find the significant bits */
115 if (!size)
116 return 0;
117
118 /* Get the lowest of them to find the decode size, and
119 from that the extent. */
120 size = (size & ~(size-1)) - 1;
121
122 /* base == maxbase can be valid only if the BAR has
123 already been programmed with all 1s. */
124 if (base == maxbase && ((base | size) & mask) != mask)
125 return 0;
126
127 return size;
128 }
129
130 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
131 {
132 u32 mem_type;
133 unsigned long flags;
134
135 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
136 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
137 flags |= IORESOURCE_IO;
138 return flags;
139 }
140
141 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
142 flags |= IORESOURCE_MEM;
143 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
144 flags |= IORESOURCE_PREFETCH;
145
146 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
147 switch (mem_type) {
148 case PCI_BASE_ADDRESS_MEM_TYPE_32:
149 break;
150 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
151 /* 1M mem BAR treated as 32-bit BAR */
152 break;
153 case PCI_BASE_ADDRESS_MEM_TYPE_64:
154 flags |= IORESOURCE_MEM_64;
155 break;
156 default:
157 /* mem unknown type treated as 32-bit BAR */
158 break;
159 }
160 return flags;
161 }
162
163 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
164
165 /**
166 * pci_read_base - read a PCI BAR
167 * @dev: the PCI device
168 * @type: type of the BAR
169 * @res: resource buffer to be filled in
170 * @pos: BAR position in the config space
171 *
172 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
173 */
174 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
175 struct resource *res, unsigned int pos)
176 {
177 u32 l, sz, mask;
178 u64 l64, sz64, mask64;
179 u16 orig_cmd;
180 struct pci_bus_region region, inverted_region;
181
182 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
183
184 /* No printks while decoding is disabled! */
185 if (!dev->mmio_always_on) {
186 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
187 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
188 pci_write_config_word(dev, PCI_COMMAND,
189 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
190 }
191 }
192
193 res->name = pci_name(dev);
194
195 pci_read_config_dword(dev, pos, &l);
196 pci_write_config_dword(dev, pos, l | mask);
197 pci_read_config_dword(dev, pos, &sz);
198 pci_write_config_dword(dev, pos, l);
199
200 /*
201 * All bits set in sz means the device isn't working properly.
202 * If the BAR isn't implemented, all bits must be 0. If it's a
203 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
204 * 1 must be clear.
205 */
206 if (sz == 0xffffffff)
207 sz = 0;
208
209 /*
210 * I don't know how l can have all bits set. Copied from old code.
211 * Maybe it fixes a bug on some ancient platform.
212 */
213 if (l == 0xffffffff)
214 l = 0;
215
216 if (type == pci_bar_unknown) {
217 res->flags = decode_bar(dev, l);
218 res->flags |= IORESOURCE_SIZEALIGN;
219 if (res->flags & IORESOURCE_IO) {
220 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
221 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
222 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
223 } else {
224 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
225 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
226 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
227 }
228 } else {
229 res->flags |= (l & IORESOURCE_ROM_ENABLE);
230 l64 = l & PCI_ROM_ADDRESS_MASK;
231 sz64 = sz & PCI_ROM_ADDRESS_MASK;
232 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
233 }
234
235 if (res->flags & IORESOURCE_MEM_64) {
236 pci_read_config_dword(dev, pos + 4, &l);
237 pci_write_config_dword(dev, pos + 4, ~0);
238 pci_read_config_dword(dev, pos + 4, &sz);
239 pci_write_config_dword(dev, pos + 4, l);
240
241 l64 |= ((u64)l << 32);
242 sz64 |= ((u64)sz << 32);
243 mask64 |= ((u64)~0 << 32);
244 }
245
246 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
247 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
248
249 if (!sz64)
250 goto fail;
251
252 sz64 = pci_size(l64, sz64, mask64);
253 if (!sz64) {
254 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
255 pos);
256 goto fail;
257 }
258
259 if (res->flags & IORESOURCE_MEM_64) {
260 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
261 && sz64 > 0x100000000ULL) {
262 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
263 res->start = 0;
264 res->end = 0;
265 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
266 pos, (unsigned long long)sz64);
267 goto out;
268 }
269
270 if ((sizeof(pci_bus_addr_t) < 8) && l) {
271 /* Above 32-bit boundary; try to reallocate */
272 res->flags |= IORESOURCE_UNSET;
273 res->start = 0;
274 res->end = sz64;
275 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
276 pos, (unsigned long long)l64);
277 goto out;
278 }
279 }
280
281 region.start = l64;
282 region.end = l64 + sz64;
283
284 pcibios_bus_to_resource(dev->bus, res, &region);
285 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
286
287 /*
288 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
289 * the corresponding resource address (the physical address used by
290 * the CPU. Converting that resource address back to a bus address
291 * should yield the original BAR value:
292 *
293 * resource_to_bus(bus_to_resource(A)) == A
294 *
295 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
296 * be claimed by the device.
297 */
298 if (inverted_region.start != region.start) {
299 res->flags |= IORESOURCE_UNSET;
300 res->start = 0;
301 res->end = region.end - region.start;
302 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
303 pos, (unsigned long long)region.start);
304 }
305
306 goto out;
307
308
309 fail:
310 res->flags = 0;
311 out:
312 if (res->flags)
313 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
314
315 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
316 }
317
318 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
319 {
320 unsigned int pos, reg;
321
322 for (pos = 0; pos < howmany; pos++) {
323 struct resource *res = &dev->resource[pos];
324 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
325 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
326 }
327
328 if (rom) {
329 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
330 dev->rom_base_reg = rom;
331 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
332 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
333 __pci_read_base(dev, pci_bar_mem32, res, rom);
334 }
335 }
336
337 static void pci_read_bridge_io(struct pci_bus *child)
338 {
339 struct pci_dev *dev = child->self;
340 u8 io_base_lo, io_limit_lo;
341 unsigned long io_mask, io_granularity, base, limit;
342 struct pci_bus_region region;
343 struct resource *res;
344
345 io_mask = PCI_IO_RANGE_MASK;
346 io_granularity = 0x1000;
347 if (dev->io_window_1k) {
348 /* Support 1K I/O space granularity */
349 io_mask = PCI_IO_1K_RANGE_MASK;
350 io_granularity = 0x400;
351 }
352
353 res = child->resource[0];
354 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
355 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
356 base = (io_base_lo & io_mask) << 8;
357 limit = (io_limit_lo & io_mask) << 8;
358
359 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
360 u16 io_base_hi, io_limit_hi;
361
362 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
363 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
364 base |= ((unsigned long) io_base_hi << 16);
365 limit |= ((unsigned long) io_limit_hi << 16);
366 }
367
368 if (base <= limit) {
369 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
370 region.start = base;
371 region.end = limit + io_granularity - 1;
372 pcibios_bus_to_resource(dev->bus, res, &region);
373 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
374 }
375 }
376
377 static void pci_read_bridge_mmio(struct pci_bus *child)
378 {
379 struct pci_dev *dev = child->self;
380 u16 mem_base_lo, mem_limit_lo;
381 unsigned long base, limit;
382 struct pci_bus_region region;
383 struct resource *res;
384
385 res = child->resource[1];
386 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
387 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
388 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
389 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
390 if (base <= limit) {
391 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
392 region.start = base;
393 region.end = limit + 0xfffff;
394 pcibios_bus_to_resource(dev->bus, res, &region);
395 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
396 }
397 }
398
399 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
400 {
401 struct pci_dev *dev = child->self;
402 u16 mem_base_lo, mem_limit_lo;
403 u64 base64, limit64;
404 pci_bus_addr_t base, limit;
405 struct pci_bus_region region;
406 struct resource *res;
407
408 res = child->resource[2];
409 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
410 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
411 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
412 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
413
414 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
415 u32 mem_base_hi, mem_limit_hi;
416
417 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
418 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
419
420 /*
421 * Some bridges set the base > limit by default, and some
422 * (broken) BIOSes do not initialize them. If we find
423 * this, just assume they are not being used.
424 */
425 if (mem_base_hi <= mem_limit_hi) {
426 base64 |= (u64) mem_base_hi << 32;
427 limit64 |= (u64) mem_limit_hi << 32;
428 }
429 }
430
431 base = (pci_bus_addr_t) base64;
432 limit = (pci_bus_addr_t) limit64;
433
434 if (base != base64) {
435 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
436 (unsigned long long) base64);
437 return;
438 }
439
440 if (base <= limit) {
441 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
442 IORESOURCE_MEM | IORESOURCE_PREFETCH;
443 if (res->flags & PCI_PREF_RANGE_TYPE_64)
444 res->flags |= IORESOURCE_MEM_64;
445 region.start = base;
446 region.end = limit + 0xfffff;
447 pcibios_bus_to_resource(dev->bus, res, &region);
448 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
449 }
450 }
451
452 void pci_read_bridge_bases(struct pci_bus *child)
453 {
454 struct pci_dev *dev = child->self;
455 struct resource *res;
456 int i;
457
458 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
459 return;
460
461 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
462 &child->busn_res,
463 dev->transparent ? " (subtractive decode)" : "");
464
465 pci_bus_remove_resources(child);
466 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
467 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
468
469 pci_read_bridge_io(child);
470 pci_read_bridge_mmio(child);
471 pci_read_bridge_mmio_pref(child);
472
473 if (dev->transparent) {
474 pci_bus_for_each_resource(child->parent, res, i) {
475 if (res && res->flags) {
476 pci_bus_add_resource(child, res,
477 PCI_SUBTRACTIVE_DECODE);
478 dev_printk(KERN_DEBUG, &dev->dev,
479 " bridge window %pR (subtractive decode)\n",
480 res);
481 }
482 }
483 }
484 }
485
486 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
487 {
488 struct pci_bus *b;
489
490 b = kzalloc(sizeof(*b), GFP_KERNEL);
491 if (!b)
492 return NULL;
493
494 INIT_LIST_HEAD(&b->node);
495 INIT_LIST_HEAD(&b->children);
496 INIT_LIST_HEAD(&b->devices);
497 INIT_LIST_HEAD(&b->slots);
498 INIT_LIST_HEAD(&b->resources);
499 b->max_bus_speed = PCI_SPEED_UNKNOWN;
500 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
501 #ifdef CONFIG_PCI_DOMAINS_GENERIC
502 if (parent)
503 b->domain_nr = parent->domain_nr;
504 #endif
505 return b;
506 }
507
508 static void pci_release_host_bridge_dev(struct device *dev)
509 {
510 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
511
512 if (bridge->release_fn)
513 bridge->release_fn(bridge);
514
515 pci_free_resource_list(&bridge->windows);
516
517 kfree(bridge);
518 }
519
520 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
521 {
522 struct pci_host_bridge *bridge;
523
524 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
525 if (!bridge)
526 return NULL;
527
528 INIT_LIST_HEAD(&bridge->windows);
529 bridge->bus = b;
530 return bridge;
531 }
532
533 static const unsigned char pcix_bus_speed[] = {
534 PCI_SPEED_UNKNOWN, /* 0 */
535 PCI_SPEED_66MHz_PCIX, /* 1 */
536 PCI_SPEED_100MHz_PCIX, /* 2 */
537 PCI_SPEED_133MHz_PCIX, /* 3 */
538 PCI_SPEED_UNKNOWN, /* 4 */
539 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
540 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
541 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
542 PCI_SPEED_UNKNOWN, /* 8 */
543 PCI_SPEED_66MHz_PCIX_266, /* 9 */
544 PCI_SPEED_100MHz_PCIX_266, /* A */
545 PCI_SPEED_133MHz_PCIX_266, /* B */
546 PCI_SPEED_UNKNOWN, /* C */
547 PCI_SPEED_66MHz_PCIX_533, /* D */
548 PCI_SPEED_100MHz_PCIX_533, /* E */
549 PCI_SPEED_133MHz_PCIX_533 /* F */
550 };
551
552 const unsigned char pcie_link_speed[] = {
553 PCI_SPEED_UNKNOWN, /* 0 */
554 PCIE_SPEED_2_5GT, /* 1 */
555 PCIE_SPEED_5_0GT, /* 2 */
556 PCIE_SPEED_8_0GT, /* 3 */
557 PCI_SPEED_UNKNOWN, /* 4 */
558 PCI_SPEED_UNKNOWN, /* 5 */
559 PCI_SPEED_UNKNOWN, /* 6 */
560 PCI_SPEED_UNKNOWN, /* 7 */
561 PCI_SPEED_UNKNOWN, /* 8 */
562 PCI_SPEED_UNKNOWN, /* 9 */
563 PCI_SPEED_UNKNOWN, /* A */
564 PCI_SPEED_UNKNOWN, /* B */
565 PCI_SPEED_UNKNOWN, /* C */
566 PCI_SPEED_UNKNOWN, /* D */
567 PCI_SPEED_UNKNOWN, /* E */
568 PCI_SPEED_UNKNOWN /* F */
569 };
570
571 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
572 {
573 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
574 }
575 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
576
577 static unsigned char agp_speeds[] = {
578 AGP_UNKNOWN,
579 AGP_1X,
580 AGP_2X,
581 AGP_4X,
582 AGP_8X
583 };
584
585 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
586 {
587 int index = 0;
588
589 if (agpstat & 4)
590 index = 3;
591 else if (agpstat & 2)
592 index = 2;
593 else if (agpstat & 1)
594 index = 1;
595 else
596 goto out;
597
598 if (agp3) {
599 index += 2;
600 if (index == 5)
601 index = 0;
602 }
603
604 out:
605 return agp_speeds[index];
606 }
607
608 static void pci_set_bus_speed(struct pci_bus *bus)
609 {
610 struct pci_dev *bridge = bus->self;
611 int pos;
612
613 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
614 if (!pos)
615 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
616 if (pos) {
617 u32 agpstat, agpcmd;
618
619 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
620 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
621
622 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
623 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
624 }
625
626 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
627 if (pos) {
628 u16 status;
629 enum pci_bus_speed max;
630
631 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
632 &status);
633
634 if (status & PCI_X_SSTATUS_533MHZ) {
635 max = PCI_SPEED_133MHz_PCIX_533;
636 } else if (status & PCI_X_SSTATUS_266MHZ) {
637 max = PCI_SPEED_133MHz_PCIX_266;
638 } else if (status & PCI_X_SSTATUS_133MHZ) {
639 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
640 max = PCI_SPEED_133MHz_PCIX_ECC;
641 else
642 max = PCI_SPEED_133MHz_PCIX;
643 } else {
644 max = PCI_SPEED_66MHz_PCIX;
645 }
646
647 bus->max_bus_speed = max;
648 bus->cur_bus_speed = pcix_bus_speed[
649 (status & PCI_X_SSTATUS_FREQ) >> 6];
650
651 return;
652 }
653
654 if (pci_is_pcie(bridge)) {
655 u32 linkcap;
656 u16 linksta;
657
658 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
659 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
660
661 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
662 pcie_update_link_speed(bus, linksta);
663 }
664 }
665
666 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
667 {
668 struct irq_domain *d;
669
670 /*
671 * Any firmware interface that can resolve the msi_domain
672 * should be called from here.
673 */
674 d = pci_host_bridge_of_msi_domain(bus);
675
676 return d;
677 }
678
679 static void pci_set_bus_msi_domain(struct pci_bus *bus)
680 {
681 struct irq_domain *d;
682 struct pci_bus *b;
683
684 /*
685 * The bus can be a root bus, a subordinate bus, or a virtual bus
686 * created by an SR-IOV device. Walk up to the first bridge device
687 * found or derive the domain from the host bridge.
688 */
689 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
690 if (b->self)
691 d = dev_get_msi_domain(&b->self->dev);
692 }
693
694 if (!d)
695 d = pci_host_bridge_msi_domain(b);
696
697 dev_set_msi_domain(&bus->dev, d);
698 }
699
700 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
701 struct pci_dev *bridge, int busnr)
702 {
703 struct pci_bus *child;
704 int i;
705 int ret;
706
707 /*
708 * Allocate a new bus, and inherit stuff from the parent..
709 */
710 child = pci_alloc_bus(parent);
711 if (!child)
712 return NULL;
713
714 child->parent = parent;
715 child->ops = parent->ops;
716 child->msi = parent->msi;
717 child->sysdata = parent->sysdata;
718 child->bus_flags = parent->bus_flags;
719
720 /* initialize some portions of the bus device, but don't register it
721 * now as the parent is not properly set up yet.
722 */
723 child->dev.class = &pcibus_class;
724 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
725
726 /*
727 * Set up the primary, secondary and subordinate
728 * bus numbers.
729 */
730 child->number = child->busn_res.start = busnr;
731 child->primary = parent->busn_res.start;
732 child->busn_res.end = 0xff;
733
734 if (!bridge) {
735 child->dev.parent = parent->bridge;
736 goto add_dev;
737 }
738
739 child->self = bridge;
740 child->bridge = get_device(&bridge->dev);
741 child->dev.parent = child->bridge;
742 pci_set_bus_of_node(child);
743 pci_set_bus_speed(child);
744
745 /* Set up default resource pointers and names.. */
746 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
747 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
748 child->resource[i]->name = child->name;
749 }
750 bridge->subordinate = child;
751
752 add_dev:
753 pci_set_bus_msi_domain(child);
754 ret = device_register(&child->dev);
755 WARN_ON(ret < 0);
756
757 pcibios_add_bus(child);
758
759 /* Create legacy_io and legacy_mem files for this bus */
760 pci_create_legacy_files(child);
761
762 return child;
763 }
764
765 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
766 int busnr)
767 {
768 struct pci_bus *child;
769
770 child = pci_alloc_child_bus(parent, dev, busnr);
771 if (child) {
772 down_write(&pci_bus_sem);
773 list_add_tail(&child->node, &parent->children);
774 up_write(&pci_bus_sem);
775 }
776 return child;
777 }
778 EXPORT_SYMBOL(pci_add_new_bus);
779
780 static void pci_enable_crs(struct pci_dev *pdev)
781 {
782 u16 root_cap = 0;
783
784 /* Enable CRS Software Visibility if supported */
785 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
786 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
787 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
788 PCI_EXP_RTCTL_CRSSVE);
789 }
790
791 /*
792 * If it's a bridge, configure it and scan the bus behind it.
793 * For CardBus bridges, we don't scan behind as the devices will
794 * be handled by the bridge driver itself.
795 *
796 * We need to process bridges in two passes -- first we scan those
797 * already configured by the BIOS and after we are done with all of
798 * them, we proceed to assigning numbers to the remaining buses in
799 * order to avoid overlaps between old and new bus numbers.
800 */
801 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
802 {
803 struct pci_bus *child;
804 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
805 u32 buses, i, j = 0;
806 u16 bctl;
807 u8 primary, secondary, subordinate;
808 int broken = 0;
809
810 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
811 primary = buses & 0xFF;
812 secondary = (buses >> 8) & 0xFF;
813 subordinate = (buses >> 16) & 0xFF;
814
815 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
816 secondary, subordinate, pass);
817
818 if (!primary && (primary != bus->number) && secondary && subordinate) {
819 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
820 primary = bus->number;
821 }
822
823 /* Check if setup is sensible at all */
824 if (!pass &&
825 (primary != bus->number || secondary <= bus->number ||
826 secondary > subordinate)) {
827 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
828 secondary, subordinate);
829 broken = 1;
830 }
831
832 /* Disable MasterAbortMode during probing to avoid reporting
833 of bus errors (in some architectures) */
834 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
835 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
836 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
837
838 pci_enable_crs(dev);
839
840 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
841 !is_cardbus && !broken) {
842 unsigned int cmax;
843 /*
844 * Bus already configured by firmware, process it in the first
845 * pass and just note the configuration.
846 */
847 if (pass)
848 goto out;
849
850 /*
851 * The bus might already exist for two reasons: Either we are
852 * rescanning the bus or the bus is reachable through more than
853 * one bridge. The second case can happen with the i450NX
854 * chipset.
855 */
856 child = pci_find_bus(pci_domain_nr(bus), secondary);
857 if (!child) {
858 child = pci_add_new_bus(bus, dev, secondary);
859 if (!child)
860 goto out;
861 child->primary = primary;
862 pci_bus_insert_busn_res(child, secondary, subordinate);
863 child->bridge_ctl = bctl;
864 }
865
866 cmax = pci_scan_child_bus(child);
867 if (cmax > subordinate)
868 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
869 subordinate, cmax);
870 /* subordinate should equal child->busn_res.end */
871 if (subordinate > max)
872 max = subordinate;
873 } else {
874 /*
875 * We need to assign a number to this bus which we always
876 * do in the second pass.
877 */
878 if (!pass) {
879 if (pcibios_assign_all_busses() || broken || is_cardbus)
880 /* Temporarily disable forwarding of the
881 configuration cycles on all bridges in
882 this bus segment to avoid possible
883 conflicts in the second pass between two
884 bridges programmed with overlapping
885 bus ranges. */
886 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
887 buses & ~0xffffff);
888 goto out;
889 }
890
891 /* Clear errors */
892 pci_write_config_word(dev, PCI_STATUS, 0xffff);
893
894 /* Prevent assigning a bus number that already exists.
895 * This can happen when a bridge is hot-plugged, so in
896 * this case we only re-scan this bus. */
897 child = pci_find_bus(pci_domain_nr(bus), max+1);
898 if (!child) {
899 child = pci_add_new_bus(bus, dev, max+1);
900 if (!child)
901 goto out;
902 pci_bus_insert_busn_res(child, max+1, 0xff);
903 }
904 max++;
905 buses = (buses & 0xff000000)
906 | ((unsigned int)(child->primary) << 0)
907 | ((unsigned int)(child->busn_res.start) << 8)
908 | ((unsigned int)(child->busn_res.end) << 16);
909
910 /*
911 * yenta.c forces a secondary latency timer of 176.
912 * Copy that behaviour here.
913 */
914 if (is_cardbus) {
915 buses &= ~0xff000000;
916 buses |= CARDBUS_LATENCY_TIMER << 24;
917 }
918
919 /*
920 * We need to blast all three values with a single write.
921 */
922 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
923
924 if (!is_cardbus) {
925 child->bridge_ctl = bctl;
926 max = pci_scan_child_bus(child);
927 } else {
928 /*
929 * For CardBus bridges, we leave 4 bus numbers
930 * as cards with a PCI-to-PCI bridge can be
931 * inserted later.
932 */
933 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
934 struct pci_bus *parent = bus;
935 if (pci_find_bus(pci_domain_nr(bus),
936 max+i+1))
937 break;
938 while (parent->parent) {
939 if ((!pcibios_assign_all_busses()) &&
940 (parent->busn_res.end > max) &&
941 (parent->busn_res.end <= max+i)) {
942 j = 1;
943 }
944 parent = parent->parent;
945 }
946 if (j) {
947 /*
948 * Often, there are two cardbus bridges
949 * -- try to leave one valid bus number
950 * for each one.
951 */
952 i /= 2;
953 break;
954 }
955 }
956 max += i;
957 }
958 /*
959 * Set the subordinate bus number to its real value.
960 */
961 pci_bus_update_busn_res_end(child, max);
962 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
963 }
964
965 sprintf(child->name,
966 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
967 pci_domain_nr(bus), child->number);
968
969 /* Has only triggered on CardBus, fixup is in yenta_socket */
970 while (bus->parent) {
971 if ((child->busn_res.end > bus->busn_res.end) ||
972 (child->number > bus->busn_res.end) ||
973 (child->number < bus->number) ||
974 (child->busn_res.end < bus->number)) {
975 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
976 &child->busn_res,
977 (bus->number > child->busn_res.end &&
978 bus->busn_res.end < child->number) ?
979 "wholly" : "partially",
980 bus->self->transparent ? " transparent" : "",
981 dev_name(&bus->dev),
982 &bus->busn_res);
983 }
984 bus = bus->parent;
985 }
986
987 out:
988 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
989
990 return max;
991 }
992 EXPORT_SYMBOL(pci_scan_bridge);
993
994 /*
995 * Read interrupt line and base address registers.
996 * The architecture-dependent code can tweak these, of course.
997 */
998 static void pci_read_irq(struct pci_dev *dev)
999 {
1000 unsigned char irq;
1001
1002 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1003 dev->pin = irq;
1004 if (irq)
1005 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1006 dev->irq = irq;
1007 }
1008
1009 void set_pcie_port_type(struct pci_dev *pdev)
1010 {
1011 int pos;
1012 u16 reg16;
1013 int type;
1014 struct pci_dev *parent;
1015
1016 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1017 if (!pos)
1018 return;
1019 pdev->pcie_cap = pos;
1020 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
1021 pdev->pcie_flags_reg = reg16;
1022 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
1023 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1024
1025 /*
1026 * A Root Port is always the upstream end of a Link. No PCIe
1027 * component has two Links. Two Links are connected by a Switch
1028 * that has a Port on each Link and internal logic to connect the
1029 * two Ports.
1030 */
1031 type = pci_pcie_type(pdev);
1032 if (type == PCI_EXP_TYPE_ROOT_PORT)
1033 pdev->has_secondary_link = 1;
1034 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1035 type == PCI_EXP_TYPE_DOWNSTREAM) {
1036 parent = pci_upstream_bridge(pdev);
1037
1038 /*
1039 * Usually there's an upstream device (Root Port or Switch
1040 * Downstream Port), but we can't assume one exists.
1041 */
1042 if (parent && !parent->has_secondary_link)
1043 pdev->has_secondary_link = 1;
1044 }
1045 }
1046
1047 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1048 {
1049 u32 reg32;
1050
1051 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
1052 if (reg32 & PCI_EXP_SLTCAP_HPC)
1053 pdev->is_hotplug_bridge = 1;
1054 }
1055
1056 /**
1057 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1058 * @dev: PCI device
1059 *
1060 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1061 * when forwarding a type1 configuration request the bridge must check that
1062 * the extended register address field is zero. The bridge is not permitted
1063 * to forward the transactions and must handle it as an Unsupported Request.
1064 * Some bridges do not follow this rule and simply drop the extended register
1065 * bits, resulting in the standard config space being aliased, every 256
1066 * bytes across the entire configuration space. Test for this condition by
1067 * comparing the first dword of each potential alias to the vendor/device ID.
1068 * Known offenders:
1069 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1070 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1071 */
1072 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1073 {
1074 #ifdef CONFIG_PCI_QUIRKS
1075 int pos;
1076 u32 header, tmp;
1077
1078 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1079
1080 for (pos = PCI_CFG_SPACE_SIZE;
1081 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1082 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1083 || header != tmp)
1084 return false;
1085 }
1086
1087 return true;
1088 #else
1089 return false;
1090 #endif
1091 }
1092
1093 /**
1094 * pci_cfg_space_size - get the configuration space size of the PCI device.
1095 * @dev: PCI device
1096 *
1097 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1098 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1099 * access it. Maybe we don't have a way to generate extended config space
1100 * accesses, or the device is behind a reverse Express bridge. So we try
1101 * reading the dword at 0x100 which must either be 0 or a valid extended
1102 * capability header.
1103 */
1104 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1105 {
1106 u32 status;
1107 int pos = PCI_CFG_SPACE_SIZE;
1108
1109 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1110 goto fail;
1111 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1112 goto fail;
1113
1114 return PCI_CFG_SPACE_EXP_SIZE;
1115
1116 fail:
1117 return PCI_CFG_SPACE_SIZE;
1118 }
1119
1120 int pci_cfg_space_size(struct pci_dev *dev)
1121 {
1122 int pos;
1123 u32 status;
1124 u16 class;
1125
1126 class = dev->class >> 8;
1127 if (class == PCI_CLASS_BRIDGE_HOST)
1128 return pci_cfg_space_size_ext(dev);
1129
1130 if (!pci_is_pcie(dev)) {
1131 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1132 if (!pos)
1133 goto fail;
1134
1135 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1136 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1137 goto fail;
1138 }
1139
1140 return pci_cfg_space_size_ext(dev);
1141
1142 fail:
1143 return PCI_CFG_SPACE_SIZE;
1144 }
1145
1146 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1147
1148 void pci_msi_setup_pci_dev(struct pci_dev *dev)
1149 {
1150 /*
1151 * Disable the MSI hardware to avoid screaming interrupts
1152 * during boot. This is the power on reset default so
1153 * usually this should be a noop.
1154 */
1155 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1156 if (dev->msi_cap)
1157 pci_msi_set_enable(dev, 0);
1158
1159 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1160 if (dev->msix_cap)
1161 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1162 }
1163
1164 /**
1165 * pci_setup_device - fill in class and map information of a device
1166 * @dev: the device structure to fill
1167 *
1168 * Initialize the device structure with information about the device's
1169 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1170 * Called at initialisation of the PCI subsystem and by CardBus services.
1171 * Returns 0 on success and negative if unknown type of device (not normal,
1172 * bridge or CardBus).
1173 */
1174 int pci_setup_device(struct pci_dev *dev)
1175 {
1176 u32 class;
1177 u8 hdr_type;
1178 int pos = 0;
1179 struct pci_bus_region region;
1180 struct resource *res;
1181
1182 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1183 return -EIO;
1184
1185 dev->sysdata = dev->bus->sysdata;
1186 dev->dev.parent = dev->bus->bridge;
1187 dev->dev.bus = &pci_bus_type;
1188 dev->hdr_type = hdr_type & 0x7f;
1189 dev->multifunction = !!(hdr_type & 0x80);
1190 dev->error_state = pci_channel_io_normal;
1191 set_pcie_port_type(dev);
1192
1193 pci_dev_assign_slot(dev);
1194 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1195 set this higher, assuming the system even supports it. */
1196 dev->dma_mask = 0xffffffff;
1197
1198 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1199 dev->bus->number, PCI_SLOT(dev->devfn),
1200 PCI_FUNC(dev->devfn));
1201
1202 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1203 dev->revision = class & 0xff;
1204 dev->class = class >> 8; /* upper 3 bytes */
1205
1206 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1207 dev->vendor, dev->device, dev->hdr_type, dev->class);
1208
1209 /* need to have dev->class ready */
1210 dev->cfg_size = pci_cfg_space_size(dev);
1211
1212 /* "Unknown power state" */
1213 dev->current_state = PCI_UNKNOWN;
1214
1215 pci_msi_setup_pci_dev(dev);
1216
1217 /* Early fixups, before probing the BARs */
1218 pci_fixup_device(pci_fixup_early, dev);
1219 /* device class may be changed after fixup */
1220 class = dev->class >> 8;
1221
1222 switch (dev->hdr_type) { /* header type */
1223 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1224 if (class == PCI_CLASS_BRIDGE_PCI)
1225 goto bad;
1226 pci_read_irq(dev);
1227 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1228 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1229 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1230
1231 /*
1232 * Do the ugly legacy mode stuff here rather than broken chip
1233 * quirk code. Legacy mode ATA controllers have fixed
1234 * addresses. These are not always echoed in BAR0-3, and
1235 * BAR0-3 in a few cases contain junk!
1236 */
1237 if (class == PCI_CLASS_STORAGE_IDE) {
1238 u8 progif;
1239 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1240 if ((progif & 1) == 0) {
1241 region.start = 0x1F0;
1242 region.end = 0x1F7;
1243 res = &dev->resource[0];
1244 res->flags = LEGACY_IO_RESOURCE;
1245 pcibios_bus_to_resource(dev->bus, res, &region);
1246 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1247 res);
1248 region.start = 0x3F6;
1249 region.end = 0x3F6;
1250 res = &dev->resource[1];
1251 res->flags = LEGACY_IO_RESOURCE;
1252 pcibios_bus_to_resource(dev->bus, res, &region);
1253 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1254 res);
1255 }
1256 if ((progif & 4) == 0) {
1257 region.start = 0x170;
1258 region.end = 0x177;
1259 res = &dev->resource[2];
1260 res->flags = LEGACY_IO_RESOURCE;
1261 pcibios_bus_to_resource(dev->bus, res, &region);
1262 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1263 res);
1264 region.start = 0x376;
1265 region.end = 0x376;
1266 res = &dev->resource[3];
1267 res->flags = LEGACY_IO_RESOURCE;
1268 pcibios_bus_to_resource(dev->bus, res, &region);
1269 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1270 res);
1271 }
1272 }
1273 break;
1274
1275 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1276 if (class != PCI_CLASS_BRIDGE_PCI)
1277 goto bad;
1278 /* The PCI-to-PCI bridge spec requires that subtractive
1279 decoding (i.e. transparent) bridge must have programming
1280 interface code of 0x01. */
1281 pci_read_irq(dev);
1282 dev->transparent = ((dev->class & 0xff) == 1);
1283 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1284 set_pcie_hotplug_bridge(dev);
1285 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1286 if (pos) {
1287 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1288 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1289 }
1290 break;
1291
1292 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1293 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1294 goto bad;
1295 pci_read_irq(dev);
1296 pci_read_bases(dev, 1, 0);
1297 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1298 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1299 break;
1300
1301 default: /* unknown header */
1302 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1303 dev->hdr_type);
1304 return -EIO;
1305
1306 bad:
1307 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1308 dev->class, dev->hdr_type);
1309 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1310 }
1311
1312 /* We found a fine healthy device, go go go... */
1313 return 0;
1314 }
1315
1316 static void pci_configure_mps(struct pci_dev *dev)
1317 {
1318 struct pci_dev *bridge = pci_upstream_bridge(dev);
1319 int mps, p_mps, rc;
1320
1321 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1322 return;
1323
1324 mps = pcie_get_mps(dev);
1325 p_mps = pcie_get_mps(bridge);
1326
1327 if (mps == p_mps)
1328 return;
1329
1330 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1331 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1332 mps, pci_name(bridge), p_mps);
1333 return;
1334 }
1335
1336 /*
1337 * Fancier MPS configuration is done later by
1338 * pcie_bus_configure_settings()
1339 */
1340 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1341 return;
1342
1343 rc = pcie_set_mps(dev, p_mps);
1344 if (rc) {
1345 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1346 p_mps);
1347 return;
1348 }
1349
1350 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1351 p_mps, mps, 128 << dev->pcie_mpss);
1352 }
1353
1354 static struct hpp_type0 pci_default_type0 = {
1355 .revision = 1,
1356 .cache_line_size = 8,
1357 .latency_timer = 0x40,
1358 .enable_serr = 0,
1359 .enable_perr = 0,
1360 };
1361
1362 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1363 {
1364 u16 pci_cmd, pci_bctl;
1365
1366 if (!hpp)
1367 hpp = &pci_default_type0;
1368
1369 if (hpp->revision > 1) {
1370 dev_warn(&dev->dev,
1371 "PCI settings rev %d not supported; using defaults\n",
1372 hpp->revision);
1373 hpp = &pci_default_type0;
1374 }
1375
1376 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1377 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1378 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1379 if (hpp->enable_serr)
1380 pci_cmd |= PCI_COMMAND_SERR;
1381 if (hpp->enable_perr)
1382 pci_cmd |= PCI_COMMAND_PARITY;
1383 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1384
1385 /* Program bridge control value */
1386 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1387 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1388 hpp->latency_timer);
1389 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1390 if (hpp->enable_serr)
1391 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1392 if (hpp->enable_perr)
1393 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1394 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1395 }
1396 }
1397
1398 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1399 {
1400 if (hpp)
1401 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1402 }
1403
1404 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1405 {
1406 int pos;
1407 u32 reg32;
1408
1409 if (!hpp)
1410 return;
1411
1412 if (hpp->revision > 1) {
1413 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1414 hpp->revision);
1415 return;
1416 }
1417
1418 /*
1419 * Don't allow _HPX to change MPS or MRRS settings. We manage
1420 * those to make sure they're consistent with the rest of the
1421 * platform.
1422 */
1423 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1424 PCI_EXP_DEVCTL_READRQ;
1425 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1426 PCI_EXP_DEVCTL_READRQ);
1427
1428 /* Initialize Device Control Register */
1429 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1430 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1431
1432 /* Initialize Link Control Register */
1433 if (pcie_cap_has_lnkctl(dev))
1434 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1435 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1436
1437 /* Find Advanced Error Reporting Enhanced Capability */
1438 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1439 if (!pos)
1440 return;
1441
1442 /* Initialize Uncorrectable Error Mask Register */
1443 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1444 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1445 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1446
1447 /* Initialize Uncorrectable Error Severity Register */
1448 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1449 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1450 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1451
1452 /* Initialize Correctable Error Mask Register */
1453 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1454 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1455 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1456
1457 /* Initialize Advanced Error Capabilities and Control Register */
1458 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1459 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1460 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1461
1462 /*
1463 * FIXME: The following two registers are not supported yet.
1464 *
1465 * o Secondary Uncorrectable Error Severity Register
1466 * o Secondary Uncorrectable Error Mask Register
1467 */
1468 }
1469
1470 static void pci_configure_device(struct pci_dev *dev)
1471 {
1472 struct hotplug_params hpp;
1473 int ret;
1474
1475 pci_configure_mps(dev);
1476
1477 memset(&hpp, 0, sizeof(hpp));
1478 ret = pci_get_hp_params(dev, &hpp);
1479 if (ret)
1480 return;
1481
1482 program_hpp_type2(dev, hpp.t2);
1483 program_hpp_type1(dev, hpp.t1);
1484 program_hpp_type0(dev, hpp.t0);
1485 }
1486
1487 static void pci_release_capabilities(struct pci_dev *dev)
1488 {
1489 pci_vpd_release(dev);
1490 pci_iov_release(dev);
1491 pci_free_cap_save_buffers(dev);
1492 }
1493
1494 /**
1495 * pci_release_dev - free a pci device structure when all users of it are finished.
1496 * @dev: device that's been disconnected
1497 *
1498 * Will be called only by the device core when all users of this pci device are
1499 * done.
1500 */
1501 static void pci_release_dev(struct device *dev)
1502 {
1503 struct pci_dev *pci_dev;
1504
1505 pci_dev = to_pci_dev(dev);
1506 pci_release_capabilities(pci_dev);
1507 pci_release_of_node(pci_dev);
1508 pcibios_release_device(pci_dev);
1509 pci_bus_put(pci_dev->bus);
1510 kfree(pci_dev->driver_override);
1511 kfree(pci_dev);
1512 }
1513
1514 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1515 {
1516 struct pci_dev *dev;
1517
1518 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1519 if (!dev)
1520 return NULL;
1521
1522 INIT_LIST_HEAD(&dev->bus_list);
1523 dev->dev.type = &pci_dev_type;
1524 dev->bus = pci_bus_get(bus);
1525
1526 return dev;
1527 }
1528 EXPORT_SYMBOL(pci_alloc_dev);
1529
1530 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1531 int crs_timeout)
1532 {
1533 int delay = 1;
1534
1535 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1536 return false;
1537
1538 /* some broken boards return 0 or ~0 if a slot is empty: */
1539 if (*l == 0xffffffff || *l == 0x00000000 ||
1540 *l == 0x0000ffff || *l == 0xffff0000)
1541 return false;
1542
1543 /*
1544 * Configuration Request Retry Status. Some root ports return the
1545 * actual device ID instead of the synthetic ID (0xFFFF) required
1546 * by the PCIe spec. Ignore the device ID and only check for
1547 * (vendor id == 1).
1548 */
1549 while ((*l & 0xffff) == 0x0001) {
1550 if (!crs_timeout)
1551 return false;
1552
1553 msleep(delay);
1554 delay *= 2;
1555 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1556 return false;
1557 /* Card hasn't responded in 60 seconds? Must be stuck. */
1558 if (delay > crs_timeout) {
1559 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1560 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1561 PCI_FUNC(devfn));
1562 return false;
1563 }
1564 }
1565
1566 return true;
1567 }
1568 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1569
1570 /*
1571 * Read the config data for a PCI device, sanity-check it
1572 * and fill in the dev structure...
1573 */
1574 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1575 {
1576 struct pci_dev *dev;
1577 u32 l;
1578
1579 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1580 return NULL;
1581
1582 dev = pci_alloc_dev(bus);
1583 if (!dev)
1584 return NULL;
1585
1586 dev->devfn = devfn;
1587 dev->vendor = l & 0xffff;
1588 dev->device = (l >> 16) & 0xffff;
1589
1590 pci_set_of_node(dev);
1591
1592 if (pci_setup_device(dev)) {
1593 pci_bus_put(dev->bus);
1594 kfree(dev);
1595 return NULL;
1596 }
1597
1598 return dev;
1599 }
1600
1601 static void pci_init_capabilities(struct pci_dev *dev)
1602 {
1603 /* Enhanced Allocation */
1604 pci_ea_init(dev);
1605
1606 /* MSI/MSI-X list */
1607 pci_msi_init_pci_dev(dev);
1608
1609 /* Buffers for saving PCIe and PCI-X capabilities */
1610 pci_allocate_cap_save_buffers(dev);
1611
1612 /* Power Management */
1613 pci_pm_init(dev);
1614
1615 /* Vital Product Data */
1616 pci_vpd_pci22_init(dev);
1617
1618 /* Alternative Routing-ID Forwarding */
1619 pci_configure_ari(dev);
1620
1621 /* Single Root I/O Virtualization */
1622 pci_iov_init(dev);
1623
1624 /* Address Translation Services */
1625 pci_ats_init(dev);
1626
1627 /* Enable ACS P2P upstream forwarding */
1628 pci_enable_acs(dev);
1629
1630 pci_cleanup_aer_error_status_regs(dev);
1631 }
1632
1633 /*
1634 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1635 * devices. Firmware interfaces that can select the MSI domain on a
1636 * per-device basis should be called from here.
1637 */
1638 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1639 {
1640 struct irq_domain *d;
1641
1642 /*
1643 * If a domain has been set through the pcibios_add_device
1644 * callback, then this is the one (platform code knows best).
1645 */
1646 d = dev_get_msi_domain(&dev->dev);
1647 if (d)
1648 return d;
1649
1650 /*
1651 * Let's see if we have a firmware interface able to provide
1652 * the domain.
1653 */
1654 d = pci_msi_get_device_domain(dev);
1655 if (d)
1656 return d;
1657
1658 return NULL;
1659 }
1660
1661 static void pci_set_msi_domain(struct pci_dev *dev)
1662 {
1663 struct irq_domain *d;
1664
1665 /*
1666 * If the platform or firmware interfaces cannot supply a
1667 * device-specific MSI domain, then inherit the default domain
1668 * from the host bridge itself.
1669 */
1670 d = pci_dev_msi_domain(dev);
1671 if (!d)
1672 d = dev_get_msi_domain(&dev->bus->dev);
1673
1674 dev_set_msi_domain(&dev->dev, d);
1675 }
1676
1677 /**
1678 * pci_dma_configure - Setup DMA configuration
1679 * @dev: ptr to pci_dev struct of the PCI device
1680 *
1681 * Function to update PCI devices's DMA configuration using the same
1682 * info from the OF node or ACPI node of host bridge's parent (if any).
1683 */
1684 static void pci_dma_configure(struct pci_dev *dev)
1685 {
1686 struct device *bridge = pci_get_host_bridge_device(dev);
1687
1688 if (IS_ENABLED(CONFIG_OF) &&
1689 bridge->parent && bridge->parent->of_node) {
1690 of_dma_configure(&dev->dev, bridge->parent->of_node);
1691 } else if (has_acpi_companion(bridge)) {
1692 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1693 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1694
1695 if (attr == DEV_DMA_NOT_SUPPORTED)
1696 dev_warn(&dev->dev, "DMA not supported.\n");
1697 else
1698 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1699 attr == DEV_DMA_COHERENT);
1700 }
1701
1702 pci_put_host_bridge_device(bridge);
1703 }
1704
1705 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1706 {
1707 int ret;
1708
1709 pci_configure_device(dev);
1710
1711 device_initialize(&dev->dev);
1712 dev->dev.release = pci_release_dev;
1713
1714 set_dev_node(&dev->dev, pcibus_to_node(bus));
1715 dev->dev.dma_mask = &dev->dma_mask;
1716 dev->dev.dma_parms = &dev->dma_parms;
1717 dev->dev.coherent_dma_mask = 0xffffffffull;
1718 pci_dma_configure(dev);
1719
1720 pci_set_dma_max_seg_size(dev, 65536);
1721 pci_set_dma_seg_boundary(dev, 0xffffffff);
1722
1723 /* Fix up broken headers */
1724 pci_fixup_device(pci_fixup_header, dev);
1725
1726 /* moved out from quirk header fixup code */
1727 pci_reassigndev_resource_alignment(dev);
1728
1729 /* Clear the state_saved flag. */
1730 dev->state_saved = false;
1731
1732 /* Initialize various capabilities */
1733 pci_init_capabilities(dev);
1734
1735 /*
1736 * Add the device to our list of discovered devices
1737 * and the bus list for fixup functions, etc.
1738 */
1739 down_write(&pci_bus_sem);
1740 list_add_tail(&dev->bus_list, &bus->devices);
1741 up_write(&pci_bus_sem);
1742
1743 ret = pcibios_add_device(dev);
1744 WARN_ON(ret < 0);
1745
1746 /* Setup MSI irq domain */
1747 pci_set_msi_domain(dev);
1748
1749 /* Notifier could use PCI capabilities */
1750 dev->match_driver = false;
1751 ret = device_add(&dev->dev);
1752 WARN_ON(ret < 0);
1753 }
1754
1755 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1756 {
1757 struct pci_dev *dev;
1758
1759 dev = pci_get_slot(bus, devfn);
1760 if (dev) {
1761 pci_dev_put(dev);
1762 return dev;
1763 }
1764
1765 dev = pci_scan_device(bus, devfn);
1766 if (!dev)
1767 return NULL;
1768
1769 pci_device_add(dev, bus);
1770
1771 return dev;
1772 }
1773 EXPORT_SYMBOL(pci_scan_single_device);
1774
1775 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1776 {
1777 int pos;
1778 u16 cap = 0;
1779 unsigned next_fn;
1780
1781 if (pci_ari_enabled(bus)) {
1782 if (!dev)
1783 return 0;
1784 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1785 if (!pos)
1786 return 0;
1787
1788 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1789 next_fn = PCI_ARI_CAP_NFN(cap);
1790 if (next_fn <= fn)
1791 return 0; /* protect against malformed list */
1792
1793 return next_fn;
1794 }
1795
1796 /* dev may be NULL for non-contiguous multifunction devices */
1797 if (!dev || dev->multifunction)
1798 return (fn + 1) % 8;
1799
1800 return 0;
1801 }
1802
1803 static int only_one_child(struct pci_bus *bus)
1804 {
1805 struct pci_dev *parent = bus->self;
1806
1807 if (!parent || !pci_is_pcie(parent))
1808 return 0;
1809 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1810 return 1;
1811 if (parent->has_secondary_link &&
1812 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1813 return 1;
1814 return 0;
1815 }
1816
1817 /**
1818 * pci_scan_slot - scan a PCI slot on a bus for devices.
1819 * @bus: PCI bus to scan
1820 * @devfn: slot number to scan (must have zero function.)
1821 *
1822 * Scan a PCI slot on the specified PCI bus for devices, adding
1823 * discovered devices to the @bus->devices list. New devices
1824 * will not have is_added set.
1825 *
1826 * Returns the number of new devices found.
1827 */
1828 int pci_scan_slot(struct pci_bus *bus, int devfn)
1829 {
1830 unsigned fn, nr = 0;
1831 struct pci_dev *dev;
1832
1833 if (only_one_child(bus) && (devfn > 0))
1834 return 0; /* Already scanned the entire slot */
1835
1836 dev = pci_scan_single_device(bus, devfn);
1837 if (!dev)
1838 return 0;
1839 if (!dev->is_added)
1840 nr++;
1841
1842 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1843 dev = pci_scan_single_device(bus, devfn + fn);
1844 if (dev) {
1845 if (!dev->is_added)
1846 nr++;
1847 dev->multifunction = 1;
1848 }
1849 }
1850
1851 /* only one slot has pcie device */
1852 if (bus->self && nr)
1853 pcie_aspm_init_link_state(bus->self);
1854
1855 return nr;
1856 }
1857 EXPORT_SYMBOL(pci_scan_slot);
1858
1859 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1860 {
1861 u8 *smpss = data;
1862
1863 if (!pci_is_pcie(dev))
1864 return 0;
1865
1866 /*
1867 * We don't have a way to change MPS settings on devices that have
1868 * drivers attached. A hot-added device might support only the minimum
1869 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1870 * where devices may be hot-added, we limit the fabric MPS to 128 so
1871 * hot-added devices will work correctly.
1872 *
1873 * However, if we hot-add a device to a slot directly below a Root
1874 * Port, it's impossible for there to be other existing devices below
1875 * the port. We don't limit the MPS in this case because we can
1876 * reconfigure MPS on both the Root Port and the hot-added device,
1877 * and there are no other devices involved.
1878 *
1879 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1880 */
1881 if (dev->is_hotplug_bridge &&
1882 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1883 *smpss = 0;
1884
1885 if (*smpss > dev->pcie_mpss)
1886 *smpss = dev->pcie_mpss;
1887
1888 return 0;
1889 }
1890
1891 static void pcie_write_mps(struct pci_dev *dev, int mps)
1892 {
1893 int rc;
1894
1895 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1896 mps = 128 << dev->pcie_mpss;
1897
1898 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1899 dev->bus->self)
1900 /* For "Performance", the assumption is made that
1901 * downstream communication will never be larger than
1902 * the MRRS. So, the MPS only needs to be configured
1903 * for the upstream communication. This being the case,
1904 * walk from the top down and set the MPS of the child
1905 * to that of the parent bus.
1906 *
1907 * Configure the device MPS with the smaller of the
1908 * device MPSS or the bridge MPS (which is assumed to be
1909 * properly configured at this point to the largest
1910 * allowable MPS based on its parent bus).
1911 */
1912 mps = min(mps, pcie_get_mps(dev->bus->self));
1913 }
1914
1915 rc = pcie_set_mps(dev, mps);
1916 if (rc)
1917 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1918 }
1919
1920 static void pcie_write_mrrs(struct pci_dev *dev)
1921 {
1922 int rc, mrrs;
1923
1924 /* In the "safe" case, do not configure the MRRS. There appear to be
1925 * issues with setting MRRS to 0 on a number of devices.
1926 */
1927 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1928 return;
1929
1930 /* For Max performance, the MRRS must be set to the largest supported
1931 * value. However, it cannot be configured larger than the MPS the
1932 * device or the bus can support. This should already be properly
1933 * configured by a prior call to pcie_write_mps.
1934 */
1935 mrrs = pcie_get_mps(dev);
1936
1937 /* MRRS is a R/W register. Invalid values can be written, but a
1938 * subsequent read will verify if the value is acceptable or not.
1939 * If the MRRS value provided is not acceptable (e.g., too large),
1940 * shrink the value until it is acceptable to the HW.
1941 */
1942 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1943 rc = pcie_set_readrq(dev, mrrs);
1944 if (!rc)
1945 break;
1946
1947 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1948 mrrs /= 2;
1949 }
1950
1951 if (mrrs < 128)
1952 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1953 }
1954
1955 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1956 {
1957 int mps, orig_mps;
1958
1959 if (!pci_is_pcie(dev))
1960 return 0;
1961
1962 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
1963 pcie_bus_config == PCIE_BUS_DEFAULT)
1964 return 0;
1965
1966 mps = 128 << *(u8 *)data;
1967 orig_mps = pcie_get_mps(dev);
1968
1969 pcie_write_mps(dev, mps);
1970 pcie_write_mrrs(dev);
1971
1972 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1973 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1974 orig_mps, pcie_get_readrq(dev));
1975
1976 return 0;
1977 }
1978
1979 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1980 * parents then children fashion. If this changes, then this code will not
1981 * work as designed.
1982 */
1983 void pcie_bus_configure_settings(struct pci_bus *bus)
1984 {
1985 u8 smpss = 0;
1986
1987 if (!bus->self)
1988 return;
1989
1990 if (!pci_is_pcie(bus->self))
1991 return;
1992
1993 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1994 * to be aware of the MPS of the destination. To work around this,
1995 * simply force the MPS of the entire system to the smallest possible.
1996 */
1997 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1998 smpss = 0;
1999
2000 if (pcie_bus_config == PCIE_BUS_SAFE) {
2001 smpss = bus->self->pcie_mpss;
2002
2003 pcie_find_smpss(bus->self, &smpss);
2004 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2005 }
2006
2007 pcie_bus_configure_set(bus->self, &smpss);
2008 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2009 }
2010 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2011
2012 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2013 {
2014 unsigned int devfn, pass, max = bus->busn_res.start;
2015 struct pci_dev *dev;
2016
2017 dev_dbg(&bus->dev, "scanning bus\n");
2018
2019 /* Go find them, Rover! */
2020 for (devfn = 0; devfn < 0x100; devfn += 8)
2021 pci_scan_slot(bus, devfn);
2022
2023 /* Reserve buses for SR-IOV capability. */
2024 max += pci_iov_bus_range(bus);
2025
2026 /*
2027 * After performing arch-dependent fixup of the bus, look behind
2028 * all PCI-to-PCI bridges on this bus.
2029 */
2030 if (!bus->is_added) {
2031 dev_dbg(&bus->dev, "fixups for bus\n");
2032 pcibios_fixup_bus(bus);
2033 bus->is_added = 1;
2034 }
2035
2036 for (pass = 0; pass < 2; pass++)
2037 list_for_each_entry(dev, &bus->devices, bus_list) {
2038 if (pci_is_bridge(dev))
2039 max = pci_scan_bridge(bus, dev, max, pass);
2040 }
2041
2042 /*
2043 * We've scanned the bus and so we know all about what's on
2044 * the other side of any bridges that may be on this bus plus
2045 * any devices.
2046 *
2047 * Return how far we've got finding sub-buses.
2048 */
2049 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2050 return max;
2051 }
2052 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2053
2054 /**
2055 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2056 * @bridge: Host bridge to set up.
2057 *
2058 * Default empty implementation. Replace with an architecture-specific setup
2059 * routine, if necessary.
2060 */
2061 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2062 {
2063 return 0;
2064 }
2065
2066 void __weak pcibios_add_bus(struct pci_bus *bus)
2067 {
2068 }
2069
2070 void __weak pcibios_remove_bus(struct pci_bus *bus)
2071 {
2072 }
2073
2074 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2075 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2076 {
2077 int error;
2078 struct pci_host_bridge *bridge;
2079 struct pci_bus *b, *b2;
2080 struct resource_entry *window, *n;
2081 struct resource *res;
2082 resource_size_t offset;
2083 char bus_addr[64];
2084 char *fmt;
2085
2086 b = pci_alloc_bus(NULL);
2087 if (!b)
2088 return NULL;
2089
2090 b->sysdata = sysdata;
2091 b->ops = ops;
2092 b->number = b->busn_res.start = bus;
2093 pci_bus_assign_domain_nr(b, parent);
2094 b2 = pci_find_bus(pci_domain_nr(b), bus);
2095 if (b2) {
2096 /* If we already got to this bus through a different bridge, ignore it */
2097 dev_dbg(&b2->dev, "bus already known\n");
2098 goto err_out;
2099 }
2100
2101 bridge = pci_alloc_host_bridge(b);
2102 if (!bridge)
2103 goto err_out;
2104
2105 bridge->dev.parent = parent;
2106 bridge->dev.release = pci_release_host_bridge_dev;
2107 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2108 error = pcibios_root_bridge_prepare(bridge);
2109 if (error) {
2110 kfree(bridge);
2111 goto err_out;
2112 }
2113
2114 error = device_register(&bridge->dev);
2115 if (error) {
2116 put_device(&bridge->dev);
2117 goto err_out;
2118 }
2119 b->bridge = get_device(&bridge->dev);
2120 device_enable_async_suspend(b->bridge);
2121 pci_set_bus_of_node(b);
2122 pci_set_bus_msi_domain(b);
2123
2124 if (!parent)
2125 set_dev_node(b->bridge, pcibus_to_node(b));
2126
2127 b->dev.class = &pcibus_class;
2128 b->dev.parent = b->bridge;
2129 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2130 error = device_register(&b->dev);
2131 if (error)
2132 goto class_dev_reg_err;
2133
2134 pcibios_add_bus(b);
2135
2136 /* Create legacy_io and legacy_mem files for this bus */
2137 pci_create_legacy_files(b);
2138
2139 if (parent)
2140 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2141 else
2142 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2143
2144 /* Add initial resources to the bus */
2145 resource_list_for_each_entry_safe(window, n, resources) {
2146 list_move_tail(&window->node, &bridge->windows);
2147 res = window->res;
2148 offset = window->offset;
2149 if (res->flags & IORESOURCE_BUS)
2150 pci_bus_insert_busn_res(b, bus, res->end);
2151 else
2152 pci_bus_add_resource(b, res, 0);
2153 if (offset) {
2154 if (resource_type(res) == IORESOURCE_IO)
2155 fmt = " (bus address [%#06llx-%#06llx])";
2156 else
2157 fmt = " (bus address [%#010llx-%#010llx])";
2158 snprintf(bus_addr, sizeof(bus_addr), fmt,
2159 (unsigned long long) (res->start - offset),
2160 (unsigned long long) (res->end - offset));
2161 } else
2162 bus_addr[0] = '\0';
2163 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2164 }
2165
2166 down_write(&pci_bus_sem);
2167 list_add_tail(&b->node, &pci_root_buses);
2168 up_write(&pci_bus_sem);
2169
2170 return b;
2171
2172 class_dev_reg_err:
2173 put_device(&bridge->dev);
2174 device_unregister(&bridge->dev);
2175 err_out:
2176 kfree(b);
2177 return NULL;
2178 }
2179 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2180
2181 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2182 {
2183 struct resource *res = &b->busn_res;
2184 struct resource *parent_res, *conflict;
2185
2186 res->start = bus;
2187 res->end = bus_max;
2188 res->flags = IORESOURCE_BUS;
2189
2190 if (!pci_is_root_bus(b))
2191 parent_res = &b->parent->busn_res;
2192 else {
2193 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2194 res->flags |= IORESOURCE_PCI_FIXED;
2195 }
2196
2197 conflict = request_resource_conflict(parent_res, res);
2198
2199 if (conflict)
2200 dev_printk(KERN_DEBUG, &b->dev,
2201 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2202 res, pci_is_root_bus(b) ? "domain " : "",
2203 parent_res, conflict->name, conflict);
2204
2205 return conflict == NULL;
2206 }
2207
2208 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2209 {
2210 struct resource *res = &b->busn_res;
2211 struct resource old_res = *res;
2212 resource_size_t size;
2213 int ret;
2214
2215 if (res->start > bus_max)
2216 return -EINVAL;
2217
2218 size = bus_max - res->start + 1;
2219 ret = adjust_resource(res, res->start, size);
2220 dev_printk(KERN_DEBUG, &b->dev,
2221 "busn_res: %pR end %s updated to %02x\n",
2222 &old_res, ret ? "can not be" : "is", bus_max);
2223
2224 if (!ret && !res->parent)
2225 pci_bus_insert_busn_res(b, res->start, res->end);
2226
2227 return ret;
2228 }
2229
2230 void pci_bus_release_busn_res(struct pci_bus *b)
2231 {
2232 struct resource *res = &b->busn_res;
2233 int ret;
2234
2235 if (!res->flags || !res->parent)
2236 return;
2237
2238 ret = release_resource(res);
2239 dev_printk(KERN_DEBUG, &b->dev,
2240 "busn_res: %pR %s released\n",
2241 res, ret ? "can not be" : "is");
2242 }
2243
2244 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2245 struct pci_ops *ops, void *sysdata,
2246 struct list_head *resources, struct msi_controller *msi)
2247 {
2248 struct resource_entry *window;
2249 bool found = false;
2250 struct pci_bus *b;
2251 int max;
2252
2253 resource_list_for_each_entry(window, resources)
2254 if (window->res->flags & IORESOURCE_BUS) {
2255 found = true;
2256 break;
2257 }
2258
2259 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2260 if (!b)
2261 return NULL;
2262
2263 b->msi = msi;
2264
2265 if (!found) {
2266 dev_info(&b->dev,
2267 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2268 bus);
2269 pci_bus_insert_busn_res(b, bus, 255);
2270 }
2271
2272 max = pci_scan_child_bus(b);
2273
2274 if (!found)
2275 pci_bus_update_busn_res_end(b, max);
2276
2277 return b;
2278 }
2279
2280 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2281 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2282 {
2283 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2284 NULL);
2285 }
2286 EXPORT_SYMBOL(pci_scan_root_bus);
2287
2288 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2289 void *sysdata)
2290 {
2291 LIST_HEAD(resources);
2292 struct pci_bus *b;
2293
2294 pci_add_resource(&resources, &ioport_resource);
2295 pci_add_resource(&resources, &iomem_resource);
2296 pci_add_resource(&resources, &busn_resource);
2297 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2298 if (b) {
2299 pci_scan_child_bus(b);
2300 } else {
2301 pci_free_resource_list(&resources);
2302 }
2303 return b;
2304 }
2305 EXPORT_SYMBOL(pci_scan_bus);
2306
2307 /**
2308 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2309 * @bridge: PCI bridge for the bus to scan
2310 *
2311 * Scan a PCI bus and child buses for new devices, add them,
2312 * and enable them, resizing bridge mmio/io resource if necessary
2313 * and possible. The caller must ensure the child devices are already
2314 * removed for resizing to occur.
2315 *
2316 * Returns the max number of subordinate bus discovered.
2317 */
2318 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2319 {
2320 unsigned int max;
2321 struct pci_bus *bus = bridge->subordinate;
2322
2323 max = pci_scan_child_bus(bus);
2324
2325 pci_assign_unassigned_bridge_resources(bridge);
2326
2327 pci_bus_add_devices(bus);
2328
2329 return max;
2330 }
2331
2332 /**
2333 * pci_rescan_bus - scan a PCI bus for devices.
2334 * @bus: PCI bus to scan
2335 *
2336 * Scan a PCI bus and child buses for new devices, adds them,
2337 * and enables them.
2338 *
2339 * Returns the max number of subordinate bus discovered.
2340 */
2341 unsigned int pci_rescan_bus(struct pci_bus *bus)
2342 {
2343 unsigned int max;
2344
2345 max = pci_scan_child_bus(bus);
2346 pci_assign_unassigned_bus_resources(bus);
2347 pci_bus_add_devices(bus);
2348
2349 return max;
2350 }
2351 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2352
2353 /*
2354 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2355 * routines should always be executed under this mutex.
2356 */
2357 static DEFINE_MUTEX(pci_rescan_remove_lock);
2358
2359 void pci_lock_rescan_remove(void)
2360 {
2361 mutex_lock(&pci_rescan_remove_lock);
2362 }
2363 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2364
2365 void pci_unlock_rescan_remove(void)
2366 {
2367 mutex_unlock(&pci_rescan_remove_lock);
2368 }
2369 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2370
2371 static int __init pci_sort_bf_cmp(const struct device *d_a,
2372 const struct device *d_b)
2373 {
2374 const struct pci_dev *a = to_pci_dev(d_a);
2375 const struct pci_dev *b = to_pci_dev(d_b);
2376
2377 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2378 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2379
2380 if (a->bus->number < b->bus->number) return -1;
2381 else if (a->bus->number > b->bus->number) return 1;
2382
2383 if (a->devfn < b->devfn) return -1;
2384 else if (a->devfn > b->devfn) return 1;
2385
2386 return 0;
2387 }
2388
2389 void __init pci_sort_breadthfirst(void)
2390 {
2391 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2392 }
Linux with added FPC-III support