?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
s390/ptrace: get rid of long longs in psw_bits
[linux/fpc-iii.git] / drivers / scsi / lpfc / lpfc_hw.h
blob2cce88e967ce168500e4f5bc738451532fb49144
1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2015 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21 #define FDMI_DID 0xfffffaU
22 #define NameServer_DID 0xfffffcU
23 #define SCR_DID 0xfffffdU
24 #define Fabric_DID 0xfffffeU
25 #define Bcast_DID 0xffffffU
26 #define Mask_DID 0xffffffU
27 #define CT_DID_MASK 0xffff00U
28 #define Fabric_DID_MASK 0xfff000U
29 #define WELL_KNOWN_DID_MASK 0xfffff0U
30
31 #define PT2PT_LocalID 1
32 #define PT2PT_RemoteID 2
33
34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42 #define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47 #define LPFC_FCP_NEXT_RING 3
48 #define LPFC_FCP_OAS_RING 3
49
50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
58 #define SLI2_IOCB_CMD_R3_ENTRIES 0
59 #define SLI2_IOCB_RSP_R3_ENTRIES 0
60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
63 #define SLI2_IOCB_CMD_SIZE 32
64 #define SLI2_IOCB_RSP_SIZE 32
65 #define SLI3_IOCB_CMD_SIZE 128
66 #define SLI3_IOCB_RSP_SIZE 64
67
68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
70
71 /* vendor ID used in SCSI netlink calls */
72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
74 #define FW_REV_STR_SIZE 32
75 /* Common Transport structures and definitions */
76
77 union CtRevisionId {
78 /* Structure is in Big Endian format */
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84 };
85
86 union CtCommandResponse {
87 /* Structure is in Big Endian format */
88 struct {
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
91 } bits;
92 uint32_t word;
93 };
94
95 #define FC4_FEATURE_INIT 0x2
96 #define FC4_FEATURE_TARGET 0x1
97
98 struct lpfc_sli_ct_request {
99 /* Structure is in Big Endian format */
100 union CtRevisionId RevisionId;
101 uint8_t FsType;
102 uint8_t FsSubType;
103 uint8_t Options;
104 uint8_t Rsrvd1;
105 union CtCommandResponse CommandResponse;
106 uint8_t Rsrvd2;
107 uint8_t ReasonCode;
108 uint8_t Explanation;
109 uint8_t VendorUnique;
110 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
111
112 union {
113 uint32_t PortID;
114 struct gid {
115 uint8_t PortType; /* for GID_PT requests */
116 uint8_t DomainScope;
117 uint8_t AreaScope;
118 uint8_t Fc4Type; /* for GID_FT requests */
119 } gid;
120 struct rft {
121 uint32_t PortId; /* For RFT_ID requests */
122
123 #ifdef __BIG_ENDIAN_BITFIELD
124 uint32_t rsvd0:16;
125 uint32_t rsvd1:7;
126 uint32_t fcpReg:1; /* Type 8 */
127 uint32_t rsvd2:2;
128 uint32_t ipReg:1; /* Type 5 */
129 uint32_t rsvd3:5;
130 #else /* __LITTLE_ENDIAN_BITFIELD */
131 uint32_t rsvd0:16;
132 uint32_t fcpReg:1; /* Type 8 */
133 uint32_t rsvd1:7;
134 uint32_t rsvd3:5;
135 uint32_t ipReg:1; /* Type 5 */
136 uint32_t rsvd2:2;
137 #endif
138
139 uint32_t rsvd[7];
140 } rft;
141 struct rnn {
142 uint32_t PortId; /* For RNN_ID requests */
143 uint8_t wwnn[8];
144 } rnn;
145 struct rsnn { /* For RSNN_ID requests */
146 uint8_t wwnn[8];
147 uint8_t len;
148 uint8_t symbname[255];
149 } rsnn;
150 struct da_id { /* For DA_ID requests */
151 uint32_t port_id;
152 } da_id;
153 struct rspn { /* For RSPN_ID requests */
154 uint32_t PortId;
155 uint8_t len;
156 uint8_t symbname[255];
157 } rspn;
158 struct gff {
159 uint32_t PortId;
160 } gff;
161 struct gff_acc {
162 uint8_t fbits[128];
163 } gff_acc;
164 #define FCP_TYPE_FEATURE_OFFSET 7
165 struct rff {
166 uint32_t PortId;
167 uint8_t reserved[2];
168 uint8_t fbits;
169 uint8_t type_code; /* type=8 for FCP */
170 } rff;
171 } un;
172 };
173
174 #define LPFC_MAX_CT_SIZE (60 * 4096)
175
176 #define SLI_CT_REVISION 1
177 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
178 sizeof(struct gid))
179 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
180 sizeof(struct gff))
181 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
182 sizeof(struct rft))
183 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
184 sizeof(struct rff))
185 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
186 sizeof(struct rnn))
187 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
188 sizeof(struct rsnn))
189 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
190 sizeof(struct da_id))
191 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
192 sizeof(struct rspn))
193
194 /*
195 * FsType Definitions
196 */
197
198 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
199 #define SLI_CT_TIME_SERVICE 0xFB
200 #define SLI_CT_DIRECTORY_SERVICE 0xFC
201 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
202
203 /*
204 * Directory Service Subtypes
205 */
206
207 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
208
209 /*
210 * Response Codes
211 */
212
213 #define SLI_CT_RESPONSE_FS_RJT 0x8001
214 #define SLI_CT_RESPONSE_FS_ACC 0x8002
215
216 /*
217 * Reason Codes
218 */
219
220 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
221 #define SLI_CT_INVALID_COMMAND 0x01
222 #define SLI_CT_INVALID_VERSION 0x02
223 #define SLI_CT_LOGICAL_ERROR 0x03
224 #define SLI_CT_INVALID_IU_SIZE 0x04
225 #define SLI_CT_LOGICAL_BUSY 0x05
226 #define SLI_CT_PROTOCOL_ERROR 0x07
227 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
228 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
229 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
230 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
231 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
232 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
233 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
234 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
235 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
236 #define SLI_CT_VENDOR_UNIQUE 0xff
237
238 /*
239 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
240 */
241
242 #define SLI_CT_NO_PORT_ID 0x01
243 #define SLI_CT_NO_PORT_NAME 0x02
244 #define SLI_CT_NO_NODE_NAME 0x03
245 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
246 #define SLI_CT_NO_IP_ADDRESS 0x05
247 #define SLI_CT_NO_IPA 0x06
248 #define SLI_CT_NO_FC4_TYPES 0x07
249 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
250 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
251 #define SLI_CT_NO_PORT_TYPE 0x0A
252 #define SLI_CT_ACCESS_DENIED 0x10
253 #define SLI_CT_INVALID_PORT_ID 0x11
254 #define SLI_CT_DATABASE_EMPTY 0x12
255
256 /*
257 * Name Server Command Codes
258 */
259
260 #define SLI_CTNS_GA_NXT 0x0100
261 #define SLI_CTNS_GPN_ID 0x0112
262 #define SLI_CTNS_GNN_ID 0x0113
263 #define SLI_CTNS_GCS_ID 0x0114
264 #define SLI_CTNS_GFT_ID 0x0117
265 #define SLI_CTNS_GSPN_ID 0x0118
266 #define SLI_CTNS_GPT_ID 0x011A
267 #define SLI_CTNS_GFF_ID 0x011F
268 #define SLI_CTNS_GID_PN 0x0121
269 #define SLI_CTNS_GID_NN 0x0131
270 #define SLI_CTNS_GIP_NN 0x0135
271 #define SLI_CTNS_GIPA_NN 0x0136
272 #define SLI_CTNS_GSNN_NN 0x0139
273 #define SLI_CTNS_GNN_IP 0x0153
274 #define SLI_CTNS_GIPA_IP 0x0156
275 #define SLI_CTNS_GID_FT 0x0171
276 #define SLI_CTNS_GID_PT 0x01A1
277 #define SLI_CTNS_RPN_ID 0x0212
278 #define SLI_CTNS_RNN_ID 0x0213
279 #define SLI_CTNS_RCS_ID 0x0214
280 #define SLI_CTNS_RFT_ID 0x0217
281 #define SLI_CTNS_RSPN_ID 0x0218
282 #define SLI_CTNS_RPT_ID 0x021A
283 #define SLI_CTNS_RFF_ID 0x021F
284 #define SLI_CTNS_RIP_NN 0x0235
285 #define SLI_CTNS_RIPA_NN 0x0236
286 #define SLI_CTNS_RSNN_NN 0x0239
287 #define SLI_CTNS_DA_ID 0x0300
288
289 /*
290 * Port Types
291 */
292
293 #define SLI_CTPT_N_PORT 0x01
294 #define SLI_CTPT_NL_PORT 0x02
295 #define SLI_CTPT_FNL_PORT 0x03
296 #define SLI_CTPT_IP 0x04
297 #define SLI_CTPT_FCP 0x08
298 #define SLI_CTPT_NX_PORT 0x7F
299 #define SLI_CTPT_F_PORT 0x81
300 #define SLI_CTPT_FL_PORT 0x82
301 #define SLI_CTPT_E_PORT 0x84
302
303 #define SLI_CT_LAST_ENTRY 0x80000000
304
305 /* Fibre Channel Service Parameter definitions */
306
307 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
308 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
309 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
310 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
311
312 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
313 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
314 #define FC_PH3 0x20 /* FC-PH-3 version */
315
316 #define FF_FRAME_SIZE 2048
317
318 struct lpfc_name {
319 union {
320 struct {
321 #ifdef __BIG_ENDIAN_BITFIELD
322 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
323 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
324 8:11 of IEEE ext */
325 #else /* __LITTLE_ENDIAN_BITFIELD */
326 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
327 8:11 of IEEE ext */
328 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
329 #endif
330
331 #define NAME_IEEE 0x1 /* IEEE name - nameType */
332 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
333 #define NAME_FC_TYPE 0x3 /* FC native name type */
334 #define NAME_IP_TYPE 0x4 /* IP address */
335 #define NAME_CCITT_TYPE 0xC
336 #define NAME_CCITT_GR_TYPE 0xE
337 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
338 extended Lsb */
339 uint8_t IEEE[6]; /* FC IEEE address */
340 } s;
341 uint8_t wwn[8];
342 } u;
343 };
344
345 struct csp {
346 uint8_t fcphHigh; /* FC Word 0, byte 0 */
347 uint8_t fcphLow;
348 uint8_t bbCreditMsb;
349 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
350
351 /*
352 * Word 1 Bit 31 in common service parameter is overloaded.
353 * Word 1 Bit 31 in FLOGI request is multiple NPort request
354 * Word 1 Bit 31 in FLOGI response is clean address bit
355 */
356 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
357 /*
358 * Word 1 Bit 30 in common service parameter is overloaded.
359 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
360 * Word 1 Bit 30 in PLOGI request is random offset
361 */
362 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
363 #ifdef __BIG_ENDIAN_BITFIELD
364 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
365 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
366 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
367 uint16_t fPort:1; /* FC Word 1, bit 28 */
368 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
369 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
370 uint16_t multicast:1; /* FC Word 1, bit 25 */
371 uint16_t broadcast:1; /* FC Word 1, bit 24 */
372
373 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
374 uint16_t simplex:1; /* FC Word 1, bit 22 */
375 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
376 uint16_t dhd:1; /* FC Word 1, bit 18 */
377 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
378 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
379 #else /* __LITTLE_ENDIAN_BITFIELD */
380 uint16_t broadcast:1; /* FC Word 1, bit 24 */
381 uint16_t multicast:1; /* FC Word 1, bit 25 */
382 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
383 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
384 uint16_t fPort:1; /* FC Word 1, bit 28 */
385 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
386 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
387 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
388
389 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
390 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
391 uint16_t dhd:1; /* FC Word 1, bit 18 */
392 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
393 uint16_t simplex:1; /* FC Word 1, bit 22 */
394 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
395 #endif
396
397 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
398 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
399 union {
400 struct {
401 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
402
403 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
404 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
405
406 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
407 } nPort;
408 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
409 } w2;
410
411 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
412 };
413
414 struct class_parms {
415 #ifdef __BIG_ENDIAN_BITFIELD
416 uint8_t classValid:1; /* FC Word 0, bit 31 */
417 uint8_t intermix:1; /* FC Word 0, bit 30 */
418 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
419 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
420 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
421 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
422 #else /* __LITTLE_ENDIAN_BITFIELD */
423 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
424 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
425 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
426 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
427 uint8_t intermix:1; /* FC Word 0, bit 30 */
428 uint8_t classValid:1; /* FC Word 0, bit 31 */
429
430 #endif
431
432 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
433
434 #ifdef __BIG_ENDIAN_BITFIELD
435 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
436 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
437 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
438 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
439 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
440 #else /* __LITTLE_ENDIAN_BITFIELD */
441 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
442 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
443 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
444 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
445 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
446 #endif
447
448 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
449
450 #ifdef __BIG_ENDIAN_BITFIELD
451 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
452 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
453 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
454 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
455 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
456 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
457 #else /* __LITTLE_ENDIAN_BITFIELD */
458 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
459 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
460 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
461 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
462 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
463 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
464 #endif
465
466 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
467 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
468 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
469
470 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
471 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
472 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
473 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
474
475 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
476 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
477 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
478 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
479 };
480
481 struct serv_parm { /* Structure is in Big Endian format */
482 struct csp cmn;
483 struct lpfc_name portName;
484 struct lpfc_name nodeName;
485 struct class_parms cls1;
486 struct class_parms cls2;
487 struct class_parms cls3;
488 struct class_parms cls4;
489 uint8_t vendorVersion[16];
490 };
491
492 /*
493 * Virtual Fabric Tagging Header
494 */
495 struct fc_vft_header {
496 uint32_t word0;
497 #define fc_vft_hdr_r_ctl_SHIFT 24
498 #define fc_vft_hdr_r_ctl_MASK 0xFF
499 #define fc_vft_hdr_r_ctl_WORD word0
500 #define fc_vft_hdr_ver_SHIFT 22
501 #define fc_vft_hdr_ver_MASK 0x3
502 #define fc_vft_hdr_ver_WORD word0
503 #define fc_vft_hdr_type_SHIFT 18
504 #define fc_vft_hdr_type_MASK 0xF
505 #define fc_vft_hdr_type_WORD word0
506 #define fc_vft_hdr_e_SHIFT 16
507 #define fc_vft_hdr_e_MASK 0x1
508 #define fc_vft_hdr_e_WORD word0
509 #define fc_vft_hdr_priority_SHIFT 13
510 #define fc_vft_hdr_priority_MASK 0x7
511 #define fc_vft_hdr_priority_WORD word0
512 #define fc_vft_hdr_vf_id_SHIFT 1
513 #define fc_vft_hdr_vf_id_MASK 0xFFF
514 #define fc_vft_hdr_vf_id_WORD word0
515 uint32_t word1;
516 #define fc_vft_hdr_hopct_SHIFT 24
517 #define fc_vft_hdr_hopct_MASK 0xFF
518 #define fc_vft_hdr_hopct_WORD word1
519 };
520
521 /*
522 * Extended Link Service LS_COMMAND codes (Payload Word 0)
523 */
524 #ifdef __BIG_ENDIAN_BITFIELD
525 #define ELS_CMD_MASK 0xffff0000
526 #define ELS_RSP_MASK 0xff000000
527 #define ELS_CMD_LS_RJT 0x01000000
528 #define ELS_CMD_ACC 0x02000000
529 #define ELS_CMD_PLOGI 0x03000000
530 #define ELS_CMD_FLOGI 0x04000000
531 #define ELS_CMD_LOGO 0x05000000
532 #define ELS_CMD_ABTX 0x06000000
533 #define ELS_CMD_RCS 0x07000000
534 #define ELS_CMD_RES 0x08000000
535 #define ELS_CMD_RSS 0x09000000
536 #define ELS_CMD_RSI 0x0A000000
537 #define ELS_CMD_ESTS 0x0B000000
538 #define ELS_CMD_ESTC 0x0C000000
539 #define ELS_CMD_ADVC 0x0D000000
540 #define ELS_CMD_RTV 0x0E000000
541 #define ELS_CMD_RLS 0x0F000000
542 #define ELS_CMD_ECHO 0x10000000
543 #define ELS_CMD_TEST 0x11000000
544 #define ELS_CMD_RRQ 0x12000000
545 #define ELS_CMD_REC 0x13000000
546 #define ELS_CMD_RDP 0x18000000
547 #define ELS_CMD_PRLI 0x20100014
548 #define ELS_CMD_PRLO 0x21100014
549 #define ELS_CMD_PRLO_ACC 0x02100014
550 #define ELS_CMD_PDISC 0x50000000
551 #define ELS_CMD_FDISC 0x51000000
552 #define ELS_CMD_ADISC 0x52000000
553 #define ELS_CMD_FARP 0x54000000
554 #define ELS_CMD_FARPR 0x55000000
555 #define ELS_CMD_RPS 0x56000000
556 #define ELS_CMD_RPL 0x57000000
557 #define ELS_CMD_FAN 0x60000000
558 #define ELS_CMD_RSCN 0x61040000
559 #define ELS_CMD_SCR 0x62000000
560 #define ELS_CMD_RNID 0x78000000
561 #define ELS_CMD_LIRR 0x7A000000
562 #define ELS_CMD_LCB 0x81000000
563 #else /* __LITTLE_ENDIAN_BITFIELD */
564 #define ELS_CMD_MASK 0xffff
565 #define ELS_RSP_MASK 0xff
566 #define ELS_CMD_LS_RJT 0x01
567 #define ELS_CMD_ACC 0x02
568 #define ELS_CMD_PLOGI 0x03
569 #define ELS_CMD_FLOGI 0x04
570 #define ELS_CMD_LOGO 0x05
571 #define ELS_CMD_ABTX 0x06
572 #define ELS_CMD_RCS 0x07
573 #define ELS_CMD_RES 0x08
574 #define ELS_CMD_RSS 0x09
575 #define ELS_CMD_RSI 0x0A
576 #define ELS_CMD_ESTS 0x0B
577 #define ELS_CMD_ESTC 0x0C
578 #define ELS_CMD_ADVC 0x0D
579 #define ELS_CMD_RTV 0x0E
580 #define ELS_CMD_RLS 0x0F
581 #define ELS_CMD_ECHO 0x10
582 #define ELS_CMD_TEST 0x11
583 #define ELS_CMD_RRQ 0x12
584 #define ELS_CMD_REC 0x13
585 #define ELS_CMD_RDP 0x18
586 #define ELS_CMD_PRLI 0x14001020
587 #define ELS_CMD_PRLO 0x14001021
588 #define ELS_CMD_PRLO_ACC 0x14001002
589 #define ELS_CMD_PDISC 0x50
590 #define ELS_CMD_FDISC 0x51
591 #define ELS_CMD_ADISC 0x52
592 #define ELS_CMD_FARP 0x54
593 #define ELS_CMD_FARPR 0x55
594 #define ELS_CMD_RPS 0x56
595 #define ELS_CMD_RPL 0x57
596 #define ELS_CMD_FAN 0x60
597 #define ELS_CMD_RSCN 0x0461
598 #define ELS_CMD_SCR 0x62
599 #define ELS_CMD_RNID 0x78
600 #define ELS_CMD_LIRR 0x7A
601 #define ELS_CMD_LCB 0x81
602 #endif
603
604 /*
605 * LS_RJT Payload Definition
606 */
607
608 struct ls_rjt { /* Structure is in Big Endian format */
609 union {
610 uint32_t lsRjtError;
611 struct {
612 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
613
614 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
615 /* LS_RJT reason codes */
616 #define LSRJT_INVALID_CMD 0x01
617 #define LSRJT_LOGICAL_ERR 0x03
618 #define LSRJT_LOGICAL_BSY 0x05
619 #define LSRJT_PROTOCOL_ERR 0x07
620 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
621 #define LSRJT_CMD_UNSUPPORTED 0x0B
622 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
623
624 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
625 /* LS_RJT reason explanation */
626 #define LSEXP_NOTHING_MORE 0x00
627 #define LSEXP_SPARM_OPTIONS 0x01
628 #define LSEXP_SPARM_ICTL 0x03
629 #define LSEXP_SPARM_RCTL 0x05
630 #define LSEXP_SPARM_RCV_SIZE 0x07
631 #define LSEXP_SPARM_CONCUR_SEQ 0x09
632 #define LSEXP_SPARM_CREDIT 0x0B
633 #define LSEXP_INVALID_PNAME 0x0D
634 #define LSEXP_INVALID_NNAME 0x0E
635 #define LSEXP_INVALID_CSP 0x0F
636 #define LSEXP_INVALID_ASSOC_HDR 0x11
637 #define LSEXP_ASSOC_HDR_REQ 0x13
638 #define LSEXP_INVALID_O_SID 0x15
639 #define LSEXP_INVALID_OX_RX 0x17
640 #define LSEXP_CMD_IN_PROGRESS 0x19
641 #define LSEXP_PORT_LOGIN_REQ 0x1E
642 #define LSEXP_INVALID_NPORT_ID 0x1F
643 #define LSEXP_INVALID_SEQ_ID 0x21
644 #define LSEXP_INVALID_XCHG 0x23
645 #define LSEXP_INACTIVE_XCHG 0x25
646 #define LSEXP_RQ_REQUIRED 0x27
647 #define LSEXP_OUT_OF_RESOURCE 0x29
648 #define LSEXP_CANT_GIVE_DATA 0x2A
649 #define LSEXP_REQ_UNSUPPORTED 0x2C
650 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
651 } b;
652 } un;
653 };
654
655 /*
656 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
657 */
658
659 typedef struct _LOGO { /* Structure is in Big Endian format */
660 union {
661 uint32_t nPortId32; /* Access nPortId as a word */
662 struct {
663 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
664 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
665 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
666 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
667 } b;
668 } un;
669 struct lpfc_name portName; /* N_port name field */
670 } LOGO;
671
672 /*
673 * FCP Login (PRLI Request / ACC) Payload Definition
674 */
675
676 #define PRLX_PAGE_LEN 0x10
677 #define TPRLO_PAGE_LEN 0x14
678
679 typedef struct _PRLI { /* Structure is in Big Endian format */
680 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
681
682 #define PRLI_FCP_TYPE 0x08
683 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
684
685 #ifdef __BIG_ENDIAN_BITFIELD
686 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
687 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
688 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
689
690 /* ACC = imagePairEstablished */
691 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
692 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
693 #else /* __LITTLE_ENDIAN_BITFIELD */
694 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
695 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
696 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
697 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
698 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
699 /* ACC = imagePairEstablished */
700 #endif
701
702 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
703 #define PRLI_NO_RESOURCES 0x2
704 #define PRLI_INIT_INCOMPLETE 0x3
705 #define PRLI_NO_SUCH_PA 0x4
706 #define PRLI_PREDEF_CONFIG 0x5
707 #define PRLI_PARTIAL_SUCCESS 0x6
708 #define PRLI_INVALID_PAGE_CNT 0x7
709 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
710
711 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
712
713 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
714
715 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
716 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
717
718 #ifdef __BIG_ENDIAN_BITFIELD
719 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
720 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
721 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
722 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
723 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
724 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
725 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
726 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
727 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
728 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
729 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
730 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
731 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
732 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
733 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
734 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
735 #else /* __LITTLE_ENDIAN_BITFIELD */
736 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
737 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
738 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
739 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
740 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
741 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
742 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
743 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
744 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
745 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
746 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
747 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
748 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
749 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
750 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
751 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
752 #endif
753 } PRLI;
754
755 /*
756 * FCP Logout (PRLO Request / ACC) Payload Definition
757 */
758
759 typedef struct _PRLO { /* Structure is in Big Endian format */
760 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
761
762 #define PRLO_FCP_TYPE 0x08
763 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
764
765 #ifdef __BIG_ENDIAN_BITFIELD
766 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
767 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
768 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
769 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
770 #else /* __LITTLE_ENDIAN_BITFIELD */
771 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
772 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
773 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
774 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
775 #endif
776
777 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
778 #define PRLO_NO_SUCH_IMAGE 0x4
779 #define PRLO_INVALID_PAGE_CNT 0x7
780
781 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
782
783 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
784
785 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
786
787 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
788 } PRLO;
789
790 typedef struct _ADISC { /* Structure is in Big Endian format */
791 uint32_t hardAL_PA;
792 struct lpfc_name portName;
793 struct lpfc_name nodeName;
794 uint32_t DID;
795 } ADISC;
796
797 typedef struct _FARP { /* Structure is in Big Endian format */
798 uint32_t Mflags:8;
799 uint32_t Odid:24;
800 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
801 action */
802 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
803 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
804 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
805 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
806 supported */
807 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
808 supported */
809 uint32_t Rflags:8;
810 uint32_t Rdid:24;
811 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
812 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
813 struct lpfc_name OportName;
814 struct lpfc_name OnodeName;
815 struct lpfc_name RportName;
816 struct lpfc_name RnodeName;
817 uint8_t Oipaddr[16];
818 uint8_t Ripaddr[16];
819 } FARP;
820
821 typedef struct _FAN { /* Structure is in Big Endian format */
822 uint32_t Fdid;
823 struct lpfc_name FportName;
824 struct lpfc_name FnodeName;
825 } FAN;
826
827 typedef struct _SCR { /* Structure is in Big Endian format */
828 uint8_t resvd1;
829 uint8_t resvd2;
830 uint8_t resvd3;
831 uint8_t Function;
832 #define SCR_FUNC_FABRIC 0x01
833 #define SCR_FUNC_NPORT 0x02
834 #define SCR_FUNC_FULL 0x03
835 #define SCR_CLEAR 0xff
836 } SCR;
837
838 typedef struct _RNID_TOP_DISC {
839 struct lpfc_name portName;
840 uint8_t resvd[8];
841 uint32_t unitType;
842 #define RNID_HBA 0x7
843 #define RNID_HOST 0xa
844 #define RNID_DRIVER 0xd
845 uint32_t physPort;
846 uint32_t attachedNodes;
847 uint16_t ipVersion;
848 #define RNID_IPV4 0x1
849 #define RNID_IPV6 0x2
850 uint16_t UDPport;
851 uint8_t ipAddr[16];
852 uint16_t resvd1;
853 uint16_t flags;
854 #define RNID_TD_SUPPORT 0x1
855 #define RNID_LP_VALID 0x2
856 } RNID_TOP_DISC;
857
858 typedef struct _RNID { /* Structure is in Big Endian format */
859 uint8_t Format;
860 #define RNID_TOPOLOGY_DISC 0xdf
861 uint8_t CommonLen;
862 uint8_t resvd1;
863 uint8_t SpecificLen;
864 struct lpfc_name portName;
865 struct lpfc_name nodeName;
866 union {
867 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
868 } un;
869 } RNID;
870
871 typedef struct _RPS { /* Structure is in Big Endian format */
872 union {
873 uint32_t portNum;
874 struct lpfc_name portName;
875 } un;
876 } RPS;
877
878 typedef struct _RPS_RSP { /* Structure is in Big Endian format */
879 uint16_t rsvd1;
880 uint16_t portStatus;
881 uint32_t linkFailureCnt;
882 uint32_t lossSyncCnt;
883 uint32_t lossSignalCnt;
884 uint32_t primSeqErrCnt;
885 uint32_t invalidXmitWord;
886 uint32_t crcCnt;
887 } RPS_RSP;
888
889 struct RLS { /* Structure is in Big Endian format */
890 uint32_t rls;
891 #define rls_rsvd_SHIFT 24
892 #define rls_rsvd_MASK 0x000000ff
893 #define rls_rsvd_WORD rls
894 #define rls_did_SHIFT 0
895 #define rls_did_MASK 0x00ffffff
896 #define rls_did_WORD rls
897 };
898
899 struct RLS_RSP { /* Structure is in Big Endian format */
900 uint32_t linkFailureCnt;
901 uint32_t lossSyncCnt;
902 uint32_t lossSignalCnt;
903 uint32_t primSeqErrCnt;
904 uint32_t invalidXmitWord;
905 uint32_t crcCnt;
906 };
907
908 struct RRQ { /* Structure is in Big Endian format */
909 uint32_t rrq;
910 #define rrq_rsvd_SHIFT 24
911 #define rrq_rsvd_MASK 0x000000ff
912 #define rrq_rsvd_WORD rrq
913 #define rrq_did_SHIFT 0
914 #define rrq_did_MASK 0x00ffffff
915 #define rrq_did_WORD rrq
916 uint32_t rrq_exchg;
917 #define rrq_oxid_SHIFT 16
918 #define rrq_oxid_MASK 0xffff
919 #define rrq_oxid_WORD rrq_exchg
920 #define rrq_rxid_SHIFT 0
921 #define rrq_rxid_MASK 0xffff
922 #define rrq_rxid_WORD rrq_exchg
923 };
924
925 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
926 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
927
928 struct RTV_RSP { /* Structure is in Big Endian format */
929 uint32_t ratov;
930 uint32_t edtov;
931 uint32_t qtov;
932 #define qtov_rsvd0_SHIFT 28
933 #define qtov_rsvd0_MASK 0x0000000f
934 #define qtov_rsvd0_WORD qtov /* reserved */
935 #define qtov_edtovres_SHIFT 27
936 #define qtov_edtovres_MASK 0x00000001
937 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
938 #define qtov__rsvd1_SHIFT 19
939 #define qtov_rsvd1_MASK 0x0000003f
940 #define qtov_rsvd1_WORD qtov /* reserved */
941 #define qtov_rttov_SHIFT 18
942 #define qtov_rttov_MASK 0x00000001
943 #define qtov_rttov_WORD qtov /* R_T_TOV value */
944 #define qtov_rsvd2_SHIFT 0
945 #define qtov_rsvd2_MASK 0x0003ffff
946 #define qtov_rsvd2_WORD qtov /* reserved */
947 };
948
949
950 typedef struct _RPL { /* Structure is in Big Endian format */
951 uint32_t maxsize;
952 uint32_t index;
953 } RPL;
954
955 typedef struct _PORT_NUM_BLK {
956 uint32_t portNum;
957 uint32_t portID;
958 struct lpfc_name portName;
959 } PORT_NUM_BLK;
960
961 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
962 uint32_t listLen;
963 uint32_t index;
964 PORT_NUM_BLK port_num_blk;
965 } RPL_RSP;
966
967 /* This is used for RSCN command */
968 typedef struct _D_ID { /* Structure is in Big Endian format */
969 union {
970 uint32_t word;
971 struct {
972 #ifdef __BIG_ENDIAN_BITFIELD
973 uint8_t resv;
974 uint8_t domain;
975 uint8_t area;
976 uint8_t id;
977 #else /* __LITTLE_ENDIAN_BITFIELD */
978 uint8_t id;
979 uint8_t area;
980 uint8_t domain;
981 uint8_t resv;
982 #endif
983 } b;
984 } un;
985 } D_ID;
986
987 #define RSCN_ADDRESS_FORMAT_PORT 0x0
988 #define RSCN_ADDRESS_FORMAT_AREA 0x1
989 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
990 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
991 #define RSCN_ADDRESS_FORMAT_MASK 0x3
992
993 /*
994 * Structure to define all ELS Payload types
995 */
996
997 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
998 uint8_t elsCode; /* FC Word 0, bit 24:31 */
999 uint8_t elsByte1;
1000 uint8_t elsByte2;
1001 uint8_t elsByte3;
1002 union {
1003 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
1004 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
1005 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
1006 PRLI prli; /* Payload for PRLI/ACC */
1007 PRLO prlo; /* Payload for PRLO/ACC */
1008 ADISC adisc; /* Payload for ADISC/ACC */
1009 FARP farp; /* Payload for FARP/ACC */
1010 FAN fan; /* Payload for FAN */
1011 SCR scr; /* Payload for SCR/ACC */
1012 RNID rnid; /* Payload for RNID */
1013 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1014 } un;
1015 } ELS_PKT;
1016
1017 /*
1018 * Link Cable Beacon (LCB) ELS Frame
1019 */
1020
1021 struct fc_lcb_request_frame {
1022 uint32_t lcb_command; /* ELS command opcode (0x81) */
1023 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1024 #define LPFC_LCB_ON 0x1
1025 #define LPFC_LCB_OFF 0x2
1026 uint8_t reserved[3];
1027
1028 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1029 #define LPFC_LCB_GREEN 0x1
1030 #define LPFC_LCB_AMBER 0x2
1031 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1032 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1033 };
1034
1035 /*
1036 * Link Cable Beacon (LCB) ELS Response Frame
1037 */
1038 struct fc_lcb_res_frame {
1039 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
1040 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1041 uint8_t reserved[3];
1042 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1043 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1044 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1045 };
1046
1047 /*
1048 * Read Diagnostic Parameters (RDP) ELS frame.
1049 */
1050 #define SFF_PG0_IDENT_SFP 0x3
1051
1052 #define SFP_FLAG_PT_OPTICAL 0x0
1053 #define SFP_FLAG_PT_SWLASER 0x01
1054 #define SFP_FLAG_PT_LWLASER_LC1310 0x02
1055 #define SFP_FLAG_PT_LWLASER_LL1550 0x03
1056 #define SFP_FLAG_PT_MASK 0x0F
1057 #define SFP_FLAG_PT_SHIFT 0
1058
1059 #define SFP_FLAG_IS_OPTICAL_PORT 0x01
1060 #define SFP_FLAG_IS_OPTICAL_MASK 0x010
1061 #define SFP_FLAG_IS_OPTICAL_SHIFT 4
1062
1063 #define SFP_FLAG_IS_DESC_VALID 0x01
1064 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1065 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1066
1067 #define SFP_FLAG_CT_UNKNOWN 0x0
1068 #define SFP_FLAG_CT_SFP_PLUS 0x01
1069 #define SFP_FLAG_CT_MASK 0x3C
1070 #define SFP_FLAG_CT_SHIFT 6
1071
1072 struct fc_rdp_port_name_info {
1073 uint8_t wwnn[8];
1074 uint8_t wwpn[8];
1075 };
1076
1077
1078 /*
1079 * Link Error Status Block Structure (FC-FS-3) for RDP
1080 * This similar to RPS ELS
1081 */
1082 struct fc_link_status {
1083 uint32_t link_failure_cnt;
1084 uint32_t loss_of_synch_cnt;
1085 uint32_t loss_of_signal_cnt;
1086 uint32_t primitive_seq_proto_err;
1087 uint32_t invalid_trans_word;
1088 uint32_t invalid_crc_cnt;
1089
1090 };
1091
1092 #define RDP_PORT_NAMES_DESC_TAG 0x00010003
1093 struct fc_rdp_port_name_desc {
1094 uint32_t tag; /* 0001 0003h */
1095 uint32_t length; /* set to size of payload struct */
1096 struct fc_rdp_port_name_info port_names;
1097 };
1098
1099
1100 struct fc_rdp_link_error_status_payload_info {
1101 struct fc_link_status link_status; /* 24 bytes */
1102 uint32_t port_type; /* bits 31-30 only */
1103 };
1104
1105 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1106 struct fc_rdp_link_error_status_desc {
1107 uint32_t tag; /* 0001 0002h */
1108 uint32_t length; /* set to size of payload struct */
1109 struct fc_rdp_link_error_status_payload_info info;
1110 };
1111
1112 #define VN_PT_PHY_UNKNOWN 0x00
1113 #define VN_PT_PHY_PF_PORT 0x01
1114 #define VN_PT_PHY_ETH_MAC 0x10
1115 #define VN_PT_PHY_SHIFT 30
1116
1117 #define RDP_PS_1GB 0x8000
1118 #define RDP_PS_2GB 0x4000
1119 #define RDP_PS_4GB 0x2000
1120 #define RDP_PS_10GB 0x1000
1121 #define RDP_PS_8GB 0x0800
1122 #define RDP_PS_16GB 0x0400
1123 #define RDP_PS_32GB 0x0200
1124
1125 #define RDP_CAP_UNKNOWN 0x0001
1126 #define RDP_PS_UNKNOWN 0x0002
1127 #define RDP_PS_NOT_ESTABLISHED 0x0001
1128
1129 struct fc_rdp_port_speed {
1130 uint16_t capabilities;
1131 uint16_t speed;
1132 };
1133
1134 struct fc_rdp_port_speed_info {
1135 struct fc_rdp_port_speed port_speed;
1136 };
1137
1138 #define RDP_PORT_SPEED_DESC_TAG 0x00010001
1139 struct fc_rdp_port_speed_desc {
1140 uint32_t tag; /* 00010001h */
1141 uint32_t length; /* set to size of payload struct */
1142 struct fc_rdp_port_speed_info info;
1143 };
1144
1145 #define RDP_NPORT_ID_SIZE 4
1146 #define RDP_N_PORT_DESC_TAG 0x00000003
1147 struct fc_rdp_nport_desc {
1148 uint32_t tag; /* 0000 0003h, big endian */
1149 uint32_t length; /* size of RDP_N_PORT_ID struct */
1150 uint32_t nport_id : 12;
1151 uint32_t reserved : 8;
1152 };
1153
1154
1155 struct fc_rdp_link_service_info {
1156 uint32_t els_req; /* Request payload word 0 value.*/
1157 };
1158
1159 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1160 struct fc_rdp_link_service_desc {
1161 uint32_t tag; /* Descriptor tag 1 */
1162 uint32_t length; /* set to size of payload struct. */
1163 struct fc_rdp_link_service_info payload;
1164 /* must be ELS req Word 0(0x18) */
1165 };
1166
1167 struct fc_rdp_sfp_info {
1168 uint16_t temperature;
1169 uint16_t vcc;
1170 uint16_t tx_bias;
1171 uint16_t tx_power;
1172 uint16_t rx_power;
1173 uint16_t flags;
1174 };
1175
1176 #define RDP_SFP_DESC_TAG 0x00010000
1177 struct fc_rdp_sfp_desc {
1178 uint32_t tag;
1179 uint32_t length; /* set to size of sfp_info struct */
1180 struct fc_rdp_sfp_info sfp_info;
1181 };
1182
1183 struct fc_rdp_req_frame {
1184 uint32_t rdp_command; /* ELS command opcode (0x18)*/
1185 uint32_t rdp_des_length; /* RDP Payload Word 1 */
1186 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1187 };
1188
1189
1190 struct fc_rdp_res_frame {
1191 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
1192 uint32_t length; /* FC Word 1 */
1193 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
1194 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
1195 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10-12 */
1196 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13-21 */
1197 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22-27 */
1198 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28-33 */
1199 };
1200
1201
1202 #define RDP_DESC_PAYLOAD_SIZE (sizeof(struct fc_rdp_link_service_desc) \
1203 + sizeof(struct fc_rdp_sfp_desc) \
1204 + sizeof(struct fc_rdp_port_speed_desc) \
1205 + sizeof(struct fc_rdp_link_error_status_desc) \
1206 + (sizeof(struct fc_rdp_port_name_desc) * 2))
1207
1208
1209 /******** FDMI ********/
1210
1211 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1212 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
1213
1214 /*
1215 * Registered Port List Format
1216 */
1217 struct lpfc_fdmi_reg_port_list {
1218 uint32_t EntryCnt;
1219 uint32_t pe; /* Variable-length array */
1220 };
1221
1222
1223 /* Definitions for HBA / Port attribute entries */
1224
1225 struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1226 /* Structure is in Big Endian format */
1227 uint32_t AttrType:16;
1228 uint32_t AttrLen:16;
1229 uint32_t AttrValue; /* Marks start of Value (ATTRIBUTE_ENTRY) */
1230 };
1231
1232
1233 /* Attribute Entry */
1234 struct lpfc_fdmi_attr_entry {
1235 union {
1236 uint32_t VendorSpecific;
1237 uint32_t SupportClass;
1238 uint32_t SupportSpeed;
1239 uint32_t PortSpeed;
1240 uint32_t MaxFrameSize;
1241 uint32_t MaxCTPayloadLen;
1242 uint32_t PortState;
1243 uint32_t PortId;
1244 struct lpfc_name NodeName;
1245 struct lpfc_name PortName;
1246 struct lpfc_name FabricName;
1247 uint8_t FC4Types[32];
1248 uint8_t Manufacturer[64];
1249 uint8_t SerialNumber[64];
1250 uint8_t Model[256];
1251 uint8_t ModelDescription[256];
1252 uint8_t HardwareVersion[256];
1253 uint8_t DriverVersion[256];
1254 uint8_t OptionROMVersion[256];
1255 uint8_t FirmwareVersion[256];
1256 uint8_t OsHostName[256];
1257 uint8_t NodeSymName[256];
1258 uint8_t OsDeviceName[256];
1259 uint8_t OsNameVersion[256];
1260 uint8_t HostName[256];
1261 } un;
1262 };
1263
1264 #define LPFC_FDMI_MAX_AE_SIZE sizeof(struct lpfc_fdmi_attr_entry)
1265
1266 /*
1267 * HBA Attribute Block
1268 */
1269 struct lpfc_fdmi_attr_block {
1270 uint32_t EntryCnt; /* Number of HBA attribute entries */
1271 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */
1272 };
1273
1274 /*
1275 * Port Entry
1276 */
1277 struct lpfc_fdmi_port_entry {
1278 struct lpfc_name PortName;
1279 };
1280
1281 /*
1282 * HBA Identifier
1283 */
1284 struct lpfc_fdmi_hba_ident {
1285 struct lpfc_name PortName;
1286 };
1287
1288 /*
1289 * Register HBA(RHBA)
1290 */
1291 struct lpfc_fdmi_reg_hba {
1292 struct lpfc_fdmi_hba_ident hi;
1293 struct lpfc_fdmi_reg_port_list rpl; /* variable-length array */
1294 /* struct lpfc_fdmi_attr_block ab; */
1295 };
1296
1297 /*
1298 * Register HBA Attributes (RHAT)
1299 */
1300 struct lpfc_fdmi_reg_hbaattr {
1301 struct lpfc_name HBA_PortName;
1302 struct lpfc_fdmi_attr_block ab;
1303 };
1304
1305 /*
1306 * Register Port Attributes (RPA)
1307 */
1308 struct lpfc_fdmi_reg_portattr {
1309 struct lpfc_name PortName;
1310 struct lpfc_fdmi_attr_block ab;
1311 };
1312
1313 /*
1314 * HBA MAnagement Operations Command Codes
1315 */
1316 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1317 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1318 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1319 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1320 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
1321 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
1322 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1323 #define SLI_MGMT_RPRT 0x210 /* Register Port */
1324 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1325 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1326 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
1327 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
1328 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
1329
1330 /*
1331 * HBA Attribute Types
1332 */
1333 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */
1334 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
1335 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
1336 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
1337 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
1338 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
1339 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
1340 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1341 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
1342 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
1343 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1344 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
1345
1346 /*
1347 * Port Attrubute Types
1348 */
1349 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
1350 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
1351 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
1352 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
1353 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
1354 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
1355 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */
1356 #define RPRT_PORTNAME 0x8 /* 8 byte WWNN */
1357 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
1358 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
1359 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
1360 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWNN */
1361 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
1362 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
1363 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
1364 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
1365
1366 /*
1367 * Begin HBA configuration parameters.
1368 * The PCI configuration register BAR assignments are:
1369 * BAR0, offset 0x10 - SLIM base memory address
1370 * BAR1, offset 0x14 - SLIM base memory high address
1371 * BAR2, offset 0x18 - REGISTER base memory address
1372 * BAR3, offset 0x1c - REGISTER base memory high address
1373 * BAR4, offset 0x20 - BIU I/O registers
1374 * BAR5, offset 0x24 - REGISTER base io high address
1375 */
1376
1377 /* Number of rings currently used and available. */
1378 #define MAX_SLI3_CONFIGURED_RINGS 3
1379 #define MAX_SLI3_RINGS 4
1380
1381 /* IOCB / Mailbox is owned by FireFly */
1382 #define OWN_CHIP 1
1383
1384 /* IOCB / Mailbox is owned by Host */
1385 #define OWN_HOST 0
1386
1387 /* Number of 4-byte words in an IOCB. */
1388 #define IOCB_WORD_SZ 8
1389
1390 /* network headers for Dfctl field */
1391 #define FC_NET_HDR 0x20
1392
1393 /* Start FireFly Register definitions */
1394 #define PCI_VENDOR_ID_EMULEX 0x10df
1395 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1396 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1397 #define PCI_DEVICE_ID_BALIUS 0xe131
1398 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1399 #define PCI_DEVICE_ID_LANCER_FC 0xe200
1400 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1401 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1402 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1403 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1404 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1405 #define PCI_DEVICE_ID_SAT_MID 0xf015
1406 #define PCI_DEVICE_ID_RFLY 0xf095
1407 #define PCI_DEVICE_ID_PFLY 0xf098
1408 #define PCI_DEVICE_ID_LP101 0xf0a1
1409 #define PCI_DEVICE_ID_TFLY 0xf0a5
1410 #define PCI_DEVICE_ID_BSMB 0xf0d1
1411 #define PCI_DEVICE_ID_BMID 0xf0d5
1412 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1413 #define PCI_DEVICE_ID_ZMID 0xf0e5
1414 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1415 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1416 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1417 #define PCI_DEVICE_ID_SAT 0xf100
1418 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1419 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1420 #define PCI_DEVICE_ID_FALCON 0xf180
1421 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1422 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1423 #define PCI_DEVICE_ID_CENTAUR 0xf900
1424 #define PCI_DEVICE_ID_PEGASUS 0xf980
1425 #define PCI_DEVICE_ID_THOR 0xfa00
1426 #define PCI_DEVICE_ID_VIPER 0xfb00
1427 #define PCI_DEVICE_ID_LP10000S 0xfc00
1428 #define PCI_DEVICE_ID_LP11000S 0xfc10
1429 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1430 #define PCI_DEVICE_ID_SAT_S 0xfc40
1431 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1432 #define PCI_DEVICE_ID_HELIOS 0xfd00
1433 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1434 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1435 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1436 #define PCI_DEVICE_ID_HORNET 0xfe05
1437 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1438 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1439 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1440 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1441 #define PCI_DEVICE_ID_TOMCAT 0x0714
1442 #define PCI_DEVICE_ID_SKYHAWK 0x0724
1443 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1444
1445 #define JEDEC_ID_ADDRESS 0x0080001c
1446 #define FIREFLY_JEDEC_ID 0x1ACC
1447 #define SUPERFLY_JEDEC_ID 0x0020
1448 #define DRAGONFLY_JEDEC_ID 0x0021
1449 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1450 #define CENTAUR_2G_JEDEC_ID 0x0026
1451 #define CENTAUR_1G_JEDEC_ID 0x0028
1452 #define PEGASUS_ORION_JEDEC_ID 0x0036
1453 #define PEGASUS_JEDEC_ID 0x0038
1454 #define THOR_JEDEC_ID 0x0012
1455 #define HELIOS_JEDEC_ID 0x0364
1456 #define ZEPHYR_JEDEC_ID 0x0577
1457 #define VIPER_JEDEC_ID 0x4838
1458 #define SATURN_JEDEC_ID 0x1004
1459 #define HORNET_JDEC_ID 0x2057706D
1460
1461 #define JEDEC_ID_MASK 0x0FFFF000
1462 #define JEDEC_ID_SHIFT 12
1463 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1464
1465 typedef struct { /* FireFly BIU registers */
1466 uint32_t hostAtt; /* See definitions for Host Attention
1467 register */
1468 uint32_t chipAtt; /* See definitions for Chip Attention
1469 register */
1470 uint32_t hostStatus; /* See definitions for Host Status register */
1471 uint32_t hostControl; /* See definitions for Host Control register */
1472 uint32_t buiConfig; /* See definitions for BIU configuration
1473 register */
1474 } FF_REGS;
1475
1476 /* IO Register size in bytes */
1477 #define FF_REG_AREA_SIZE 256
1478
1479 /* Host Attention Register */
1480
1481 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1482
1483 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1484 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1485 #define HA_R0ATT 0x00000008 /* Bit 3 */
1486 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1487 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1488 #define HA_R1ATT 0x00000080 /* Bit 7 */
1489 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1490 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1491 #define HA_R2ATT 0x00000800 /* Bit 11 */
1492 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1493 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1494 #define HA_R3ATT 0x00008000 /* Bit 15 */
1495 #define HA_LATT 0x20000000 /* Bit 29 */
1496 #define HA_MBATT 0x40000000 /* Bit 30 */
1497 #define HA_ERATT 0x80000000 /* Bit 31 */
1498
1499 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1500 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1501 #define HA_RXATT 0x00000008 /* Bit 3 */
1502 #define HA_RXMASK 0x0000000f
1503
1504 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1505 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1506 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1507 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1508
1509 #define HA_R0_POS 3
1510 #define HA_R1_POS 7
1511 #define HA_R2_POS 11
1512 #define HA_R3_POS 15
1513 #define HA_LE_POS 29
1514 #define HA_MB_POS 30
1515 #define HA_ER_POS 31
1516 /* Chip Attention Register */
1517
1518 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1519
1520 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1521 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1522 #define CA_R0ATT 0x00000008 /* Bit 3 */
1523 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1524 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1525 #define CA_R1ATT 0x00000080 /* Bit 7 */
1526 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1527 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1528 #define CA_R2ATT 0x00000800 /* Bit 11 */
1529 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1530 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1531 #define CA_R3ATT 0x00008000 /* Bit 15 */
1532 #define CA_MBATT 0x40000000 /* Bit 30 */
1533
1534 /* Host Status Register */
1535
1536 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1537
1538 #define HS_MBRDY 0x00400000 /* Bit 22 */
1539 #define HS_FFRDY 0x00800000 /* Bit 23 */
1540 #define HS_FFER8 0x01000000 /* Bit 24 */
1541 #define HS_FFER7 0x02000000 /* Bit 25 */
1542 #define HS_FFER6 0x04000000 /* Bit 26 */
1543 #define HS_FFER5 0x08000000 /* Bit 27 */
1544 #define HS_FFER4 0x10000000 /* Bit 28 */
1545 #define HS_FFER3 0x20000000 /* Bit 29 */
1546 #define HS_FFER2 0x40000000 /* Bit 30 */
1547 #define HS_FFER1 0x80000000 /* Bit 31 */
1548 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1549 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1550 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1551 /* Host Control Register */
1552
1553 #define HC_REG_OFFSET 12 /* Byte offset from register base address */
1554
1555 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1556 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1557 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1558 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1559 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1560 #define HC_INITHBI 0x02000000 /* Bit 25 */
1561 #define HC_INITMB 0x04000000 /* Bit 26 */
1562 #define HC_INITFF 0x08000000 /* Bit 27 */
1563 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1564 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1565
1566 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1567 #define MSIX_DFLT_ID 0
1568 #define MSIX_RNG0_ID 0
1569 #define MSIX_RNG1_ID 1
1570 #define MSIX_RNG2_ID 2
1571 #define MSIX_RNG3_ID 3
1572
1573 #define MSIX_LINK_ID 4
1574 #define MSIX_MBOX_ID 5
1575
1576 #define MSIX_SPARE0_ID 6
1577 #define MSIX_SPARE1_ID 7
1578
1579 /* Mailbox Commands */
1580 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1581 #define MBX_LOAD_SM 0x01
1582 #define MBX_READ_NV 0x02
1583 #define MBX_WRITE_NV 0x03
1584 #define MBX_RUN_BIU_DIAG 0x04
1585 #define MBX_INIT_LINK 0x05
1586 #define MBX_DOWN_LINK 0x06
1587 #define MBX_CONFIG_LINK 0x07
1588 #define MBX_CONFIG_RING 0x09
1589 #define MBX_RESET_RING 0x0A
1590 #define MBX_READ_CONFIG 0x0B
1591 #define MBX_READ_RCONFIG 0x0C
1592 #define MBX_READ_SPARM 0x0D
1593 #define MBX_READ_STATUS 0x0E
1594 #define MBX_READ_RPI 0x0F
1595 #define MBX_READ_XRI 0x10
1596 #define MBX_READ_REV 0x11
1597 #define MBX_READ_LNK_STAT 0x12
1598 #define MBX_REG_LOGIN 0x13
1599 #define MBX_UNREG_LOGIN 0x14
1600 #define MBX_CLEAR_LA 0x16
1601 #define MBX_DUMP_MEMORY 0x17
1602 #define MBX_DUMP_CONTEXT 0x18
1603 #define MBX_RUN_DIAGS 0x19
1604 #define MBX_RESTART 0x1A
1605 #define MBX_UPDATE_CFG 0x1B
1606 #define MBX_DOWN_LOAD 0x1C
1607 #define MBX_DEL_LD_ENTRY 0x1D
1608 #define MBX_RUN_PROGRAM 0x1E
1609 #define MBX_SET_MASK 0x20
1610 #define MBX_SET_VARIABLE 0x21
1611 #define MBX_UNREG_D_ID 0x23
1612 #define MBX_KILL_BOARD 0x24
1613 #define MBX_CONFIG_FARP 0x25
1614 #define MBX_BEACON 0x2A
1615 #define MBX_CONFIG_MSI 0x30
1616 #define MBX_HEARTBEAT 0x31
1617 #define MBX_WRITE_VPARMS 0x32
1618 #define MBX_ASYNCEVT_ENABLE 0x33
1619 #define MBX_READ_EVENT_LOG_STATUS 0x37
1620 #define MBX_READ_EVENT_LOG 0x38
1621 #define MBX_WRITE_EVENT_LOG 0x39
1622
1623 #define MBX_PORT_CAPABILITIES 0x3B
1624 #define MBX_PORT_IOV_CONTROL 0x3C
1625
1626 #define MBX_CONFIG_HBQ 0x7C
1627 #define MBX_LOAD_AREA 0x81
1628 #define MBX_RUN_BIU_DIAG64 0x84
1629 #define MBX_CONFIG_PORT 0x88
1630 #define MBX_READ_SPARM64 0x8D
1631 #define MBX_READ_RPI64 0x8F
1632 #define MBX_REG_LOGIN64 0x93
1633 #define MBX_READ_TOPOLOGY 0x95
1634 #define MBX_REG_VPI 0x96
1635 #define MBX_UNREG_VPI 0x97
1636
1637 #define MBX_WRITE_WWN 0x98
1638 #define MBX_SET_DEBUG 0x99
1639 #define MBX_LOAD_EXP_ROM 0x9C
1640 #define MBX_SLI4_CONFIG 0x9B
1641 #define MBX_SLI4_REQ_FTRS 0x9D
1642 #define MBX_MAX_CMDS 0x9E
1643 #define MBX_RESUME_RPI 0x9E
1644 #define MBX_SLI2_CMD_MASK 0x80
1645 #define MBX_REG_VFI 0x9F
1646 #define MBX_REG_FCFI 0xA0
1647 #define MBX_UNREG_VFI 0xA1
1648 #define MBX_UNREG_FCFI 0xA2
1649 #define MBX_INIT_VFI 0xA3
1650 #define MBX_INIT_VPI 0xA4
1651 #define MBX_ACCESS_VDATA 0xA5
1652
1653 #define MBX_AUTH_PORT 0xF8
1654 #define MBX_SECURITY_MGMT 0xF9
1655
1656 /* IOCB Commands */
1657
1658 #define CMD_RCV_SEQUENCE_CX 0x01
1659 #define CMD_XMIT_SEQUENCE_CR 0x02
1660 #define CMD_XMIT_SEQUENCE_CX 0x03
1661 #define CMD_XMIT_BCAST_CN 0x04
1662 #define CMD_XMIT_BCAST_CX 0x05
1663 #define CMD_QUE_RING_BUF_CN 0x06
1664 #define CMD_QUE_XRI_BUF_CX 0x07
1665 #define CMD_IOCB_CONTINUE_CN 0x08
1666 #define CMD_RET_XRI_BUF_CX 0x09
1667 #define CMD_ELS_REQUEST_CR 0x0A
1668 #define CMD_ELS_REQUEST_CX 0x0B
1669 #define CMD_RCV_ELS_REQ_CX 0x0D
1670 #define CMD_ABORT_XRI_CN 0x0E
1671 #define CMD_ABORT_XRI_CX 0x0F
1672 #define CMD_CLOSE_XRI_CN 0x10
1673 #define CMD_CLOSE_XRI_CX 0x11
1674 #define CMD_CREATE_XRI_CR 0x12
1675 #define CMD_CREATE_XRI_CX 0x13
1676 #define CMD_GET_RPI_CN 0x14
1677 #define CMD_XMIT_ELS_RSP_CX 0x15
1678 #define CMD_GET_RPI_CR 0x16
1679 #define CMD_XRI_ABORTED_CX 0x17
1680 #define CMD_FCP_IWRITE_CR 0x18
1681 #define CMD_FCP_IWRITE_CX 0x19
1682 #define CMD_FCP_IREAD_CR 0x1A
1683 #define CMD_FCP_IREAD_CX 0x1B
1684 #define CMD_FCP_ICMND_CR 0x1C
1685 #define CMD_FCP_ICMND_CX 0x1D
1686 #define CMD_FCP_TSEND_CX 0x1F
1687 #define CMD_FCP_TRECEIVE_CX 0x21
1688 #define CMD_FCP_TRSP_CX 0x23
1689 #define CMD_FCP_AUTO_TRSP_CX 0x29
1690
1691 #define CMD_ADAPTER_MSG 0x20
1692 #define CMD_ADAPTER_DUMP 0x22
1693
1694 /* SLI_2 IOCB Command Set */
1695
1696 #define CMD_ASYNC_STATUS 0x7C
1697 #define CMD_RCV_SEQUENCE64_CX 0x81
1698 #define CMD_XMIT_SEQUENCE64_CR 0x82
1699 #define CMD_XMIT_SEQUENCE64_CX 0x83
1700 #define CMD_XMIT_BCAST64_CN 0x84
1701 #define CMD_XMIT_BCAST64_CX 0x85
1702 #define CMD_QUE_RING_BUF64_CN 0x86
1703 #define CMD_QUE_XRI_BUF64_CX 0x87
1704 #define CMD_IOCB_CONTINUE64_CN 0x88
1705 #define CMD_RET_XRI_BUF64_CX 0x89
1706 #define CMD_ELS_REQUEST64_CR 0x8A
1707 #define CMD_ELS_REQUEST64_CX 0x8B
1708 #define CMD_ABORT_MXRI64_CN 0x8C
1709 #define CMD_RCV_ELS_REQ64_CX 0x8D
1710 #define CMD_XMIT_ELS_RSP64_CX 0x95
1711 #define CMD_XMIT_BLS_RSP64_CX 0x97
1712 #define CMD_FCP_IWRITE64_CR 0x98
1713 #define CMD_FCP_IWRITE64_CX 0x99
1714 #define CMD_FCP_IREAD64_CR 0x9A
1715 #define CMD_FCP_IREAD64_CX 0x9B
1716 #define CMD_FCP_ICMND64_CR 0x9C
1717 #define CMD_FCP_ICMND64_CX 0x9D
1718 #define CMD_FCP_TSEND64_CX 0x9F
1719 #define CMD_FCP_TRECEIVE64_CX 0xA1
1720 #define CMD_FCP_TRSP64_CX 0xA3
1721
1722 #define CMD_QUE_XRI64_CX 0xB3
1723 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1724 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1725 #define CMD_IOCB_RET_XRI64_CX 0xB9
1726 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1727
1728 #define CMD_GEN_REQUEST64_CR 0xC2
1729 #define CMD_GEN_REQUEST64_CX 0xC3
1730
1731 /* Unhandled SLI-3 Commands */
1732 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1733 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1734 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1735 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1736 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1737 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1738 #define CMD_IOCB_RET_HBQE64_CN 0xCA
1739 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1740 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1741 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1742 #define CMD_IOCB_LOGENTRY_CN 0x94
1743 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1744
1745 /* Data Security SLI Commands */
1746 #define DSSCMD_IWRITE64_CR 0xF8
1747 #define DSSCMD_IWRITE64_CX 0xF9
1748 #define DSSCMD_IREAD64_CR 0xFA
1749 #define DSSCMD_IREAD64_CX 0xFB
1750
1751 #define CMD_MAX_IOCB_CMD 0xFB
1752 #define CMD_IOCB_MASK 0xff
1753
1754 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1755 iocb */
1756 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1757 /*
1758 * Define Status
1759 */
1760 #define MBX_SUCCESS 0
1761 #define MBXERR_NUM_RINGS 1
1762 #define MBXERR_NUM_IOCBS 2
1763 #define MBXERR_IOCBS_EXCEEDED 3
1764 #define MBXERR_BAD_RING_NUMBER 4
1765 #define MBXERR_MASK_ENTRIES_RANGE 5
1766 #define MBXERR_MASKS_EXCEEDED 6
1767 #define MBXERR_BAD_PROFILE 7
1768 #define MBXERR_BAD_DEF_CLASS 8
1769 #define MBXERR_BAD_MAX_RESPONDER 9
1770 #define MBXERR_BAD_MAX_ORIGINATOR 10
1771 #define MBXERR_RPI_REGISTERED 11
1772 #define MBXERR_RPI_FULL 12
1773 #define MBXERR_NO_RESOURCES 13
1774 #define MBXERR_BAD_RCV_LENGTH 14
1775 #define MBXERR_DMA_ERROR 15
1776 #define MBXERR_ERROR 16
1777 #define MBXERR_LINK_DOWN 0x33
1778 #define MBXERR_SEC_NO_PERMISSION 0xF02
1779 #define MBX_NOT_FINISHED 255
1780
1781 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1782 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1783
1784 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1785
1786 /*
1787 * return code Fail
1788 */
1789 #define FAILURE 1
1790
1791 /*
1792 * Begin Structure Definitions for Mailbox Commands
1793 */
1794
1795 typedef struct {
1796 #ifdef __BIG_ENDIAN_BITFIELD
1797 uint8_t tval;
1798 uint8_t tmask;
1799 uint8_t rval;
1800 uint8_t rmask;
1801 #else /* __LITTLE_ENDIAN_BITFIELD */
1802 uint8_t rmask;
1803 uint8_t rval;
1804 uint8_t tmask;
1805 uint8_t tval;
1806 #endif
1807 } RR_REG;
1808
1809 struct ulp_bde {
1810 uint32_t bdeAddress;
1811 #ifdef __BIG_ENDIAN_BITFIELD
1812 uint32_t bdeReserved:4;
1813 uint32_t bdeAddrHigh:4;
1814 uint32_t bdeSize:24;
1815 #else /* __LITTLE_ENDIAN_BITFIELD */
1816 uint32_t bdeSize:24;
1817 uint32_t bdeAddrHigh:4;
1818 uint32_t bdeReserved:4;
1819 #endif
1820 };
1821
1822 typedef struct ULP_BDL { /* SLI-2 */
1823 #ifdef __BIG_ENDIAN_BITFIELD
1824 uint32_t bdeFlags:8; /* BDL Flags */
1825 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1826 #else /* __LITTLE_ENDIAN_BITFIELD */
1827 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1828 uint32_t bdeFlags:8; /* BDL Flags */
1829 #endif
1830
1831 uint32_t addrLow; /* Address 0:31 */
1832 uint32_t addrHigh; /* Address 32:63 */
1833 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1834 } ULP_BDL;
1835
1836 /*
1837 * BlockGuard Definitions
1838 */
1839
1840 enum lpfc_protgrp_type {
1841 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
1842 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
1843 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
1844 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
1845 };
1846
1847 /* PDE Descriptors */
1848 #define LPFC_PDE5_DESCRIPTOR 0x85
1849 #define LPFC_PDE6_DESCRIPTOR 0x86
1850 #define LPFC_PDE7_DESCRIPTOR 0x87
1851
1852 /* BlockGuard Opcodes */
1853 #define BG_OP_IN_NODIF_OUT_CRC 0x0
1854 #define BG_OP_IN_CRC_OUT_NODIF 0x1
1855 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
1856 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
1857 #define BG_OP_IN_CRC_OUT_CRC 0x4
1858 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
1859 #define BG_OP_IN_CRC_OUT_CSUM 0x6
1860 #define BG_OP_IN_CSUM_OUT_CRC 0x7
1861 #define BG_OP_RAW_MODE 0x8
1862
1863 struct lpfc_pde5 {
1864 uint32_t word0;
1865 #define pde5_type_SHIFT 24
1866 #define pde5_type_MASK 0x000000ff
1867 #define pde5_type_WORD word0
1868 #define pde5_rsvd0_SHIFT 0
1869 #define pde5_rsvd0_MASK 0x00ffffff
1870 #define pde5_rsvd0_WORD word0
1871 uint32_t reftag; /* Reference Tag Value */
1872 uint32_t reftagtr; /* Reference Tag Translation Value */
1873 };
1874
1875 struct lpfc_pde6 {
1876 uint32_t word0;
1877 #define pde6_type_SHIFT 24
1878 #define pde6_type_MASK 0x000000ff
1879 #define pde6_type_WORD word0
1880 #define pde6_rsvd0_SHIFT 0
1881 #define pde6_rsvd0_MASK 0x00ffffff
1882 #define pde6_rsvd0_WORD word0
1883 uint32_t word1;
1884 #define pde6_rsvd1_SHIFT 26
1885 #define pde6_rsvd1_MASK 0x0000003f
1886 #define pde6_rsvd1_WORD word1
1887 #define pde6_na_SHIFT 25
1888 #define pde6_na_MASK 0x00000001
1889 #define pde6_na_WORD word1
1890 #define pde6_rsvd2_SHIFT 16
1891 #define pde6_rsvd2_MASK 0x000001FF
1892 #define pde6_rsvd2_WORD word1
1893 #define pde6_apptagtr_SHIFT 0
1894 #define pde6_apptagtr_MASK 0x0000ffff
1895 #define pde6_apptagtr_WORD word1
1896 uint32_t word2;
1897 #define pde6_optx_SHIFT 28
1898 #define pde6_optx_MASK 0x0000000f
1899 #define pde6_optx_WORD word2
1900 #define pde6_oprx_SHIFT 24
1901 #define pde6_oprx_MASK 0x0000000f
1902 #define pde6_oprx_WORD word2
1903 #define pde6_nr_SHIFT 23
1904 #define pde6_nr_MASK 0x00000001
1905 #define pde6_nr_WORD word2
1906 #define pde6_ce_SHIFT 22
1907 #define pde6_ce_MASK 0x00000001
1908 #define pde6_ce_WORD word2
1909 #define pde6_re_SHIFT 21
1910 #define pde6_re_MASK 0x00000001
1911 #define pde6_re_WORD word2
1912 #define pde6_ae_SHIFT 20
1913 #define pde6_ae_MASK 0x00000001
1914 #define pde6_ae_WORD word2
1915 #define pde6_ai_SHIFT 19
1916 #define pde6_ai_MASK 0x00000001
1917 #define pde6_ai_WORD word2
1918 #define pde6_bs_SHIFT 16
1919 #define pde6_bs_MASK 0x00000007
1920 #define pde6_bs_WORD word2
1921 #define pde6_apptagval_SHIFT 0
1922 #define pde6_apptagval_MASK 0x0000ffff
1923 #define pde6_apptagval_WORD word2
1924 };
1925
1926 struct lpfc_pde7 {
1927 uint32_t word0;
1928 #define pde7_type_SHIFT 24
1929 #define pde7_type_MASK 0x000000ff
1930 #define pde7_type_WORD word0
1931 #define pde7_rsvd0_SHIFT 0
1932 #define pde7_rsvd0_MASK 0x00ffffff
1933 #define pde7_rsvd0_WORD word0
1934 uint32_t addrHigh;
1935 uint32_t addrLow;
1936 };
1937
1938 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1939
1940 typedef struct {
1941 #ifdef __BIG_ENDIAN_BITFIELD
1942 uint32_t rsvd2:25;
1943 uint32_t acknowledgment:1;
1944 uint32_t version:1;
1945 uint32_t erase_or_prog:1;
1946 uint32_t update_flash:1;
1947 uint32_t update_ram:1;
1948 uint32_t method:1;
1949 uint32_t load_cmplt:1;
1950 #else /* __LITTLE_ENDIAN_BITFIELD */
1951 uint32_t load_cmplt:1;
1952 uint32_t method:1;
1953 uint32_t update_ram:1;
1954 uint32_t update_flash:1;
1955 uint32_t erase_or_prog:1;
1956 uint32_t version:1;
1957 uint32_t acknowledgment:1;
1958 uint32_t rsvd2:25;
1959 #endif
1960
1961 uint32_t dl_to_adr_low;
1962 uint32_t dl_to_adr_high;
1963 uint32_t dl_len;
1964 union {
1965 uint32_t dl_from_mbx_offset;
1966 struct ulp_bde dl_from_bde;
1967 struct ulp_bde64 dl_from_bde64;
1968 } un;
1969
1970 } LOAD_SM_VAR;
1971
1972 /* Structure for MB Command READ_NVPARM (02) */
1973
1974 typedef struct {
1975 uint32_t rsvd1[3]; /* Read as all one's */
1976 uint32_t rsvd2; /* Read as all zero's */
1977 uint32_t portname[2]; /* N_PORT name */
1978 uint32_t nodename[2]; /* NODE name */
1979
1980 #ifdef __BIG_ENDIAN_BITFIELD
1981 uint32_t pref_DID:24;
1982 uint32_t hardAL_PA:8;
1983 #else /* __LITTLE_ENDIAN_BITFIELD */
1984 uint32_t hardAL_PA:8;
1985 uint32_t pref_DID:24;
1986 #endif
1987
1988 uint32_t rsvd3[21]; /* Read as all one's */
1989 } READ_NV_VAR;
1990
1991 /* Structure for MB Command WRITE_NVPARMS (03) */
1992
1993 typedef struct {
1994 uint32_t rsvd1[3]; /* Must be all one's */
1995 uint32_t rsvd2; /* Must be all zero's */
1996 uint32_t portname[2]; /* N_PORT name */
1997 uint32_t nodename[2]; /* NODE name */
1998
1999 #ifdef __BIG_ENDIAN_BITFIELD
2000 uint32_t pref_DID:24;
2001 uint32_t hardAL_PA:8;
2002 #else /* __LITTLE_ENDIAN_BITFIELD */
2003 uint32_t hardAL_PA:8;
2004 uint32_t pref_DID:24;
2005 #endif
2006
2007 uint32_t rsvd3[21]; /* Must be all one's */
2008 } WRITE_NV_VAR;
2009
2010 /* Structure for MB Command RUN_BIU_DIAG (04) */
2011 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2012
2013 typedef struct {
2014 uint32_t rsvd1;
2015 union {
2016 struct {
2017 struct ulp_bde xmit_bde;
2018 struct ulp_bde rcv_bde;
2019 } s1;
2020 struct {
2021 struct ulp_bde64 xmit_bde64;
2022 struct ulp_bde64 rcv_bde64;
2023 } s2;
2024 } un;
2025 } BIU_DIAG_VAR;
2026
2027 /* Structure for MB command READ_EVENT_LOG (0x38) */
2028 struct READ_EVENT_LOG_VAR {
2029 uint32_t word1;
2030 #define lpfc_event_log_SHIFT 29
2031 #define lpfc_event_log_MASK 0x00000001
2032 #define lpfc_event_log_WORD word1
2033 #define USE_MAILBOX_RESPONSE 1
2034 uint32_t offset;
2035 struct ulp_bde64 rcv_bde64;
2036 };
2037
2038 /* Structure for MB Command INIT_LINK (05) */
2039
2040 typedef struct {
2041 #ifdef __BIG_ENDIAN_BITFIELD
2042 uint32_t rsvd1:24;
2043 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2044 #else /* __LITTLE_ENDIAN_BITFIELD */
2045 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2046 uint32_t rsvd1:24;
2047 #endif
2048
2049 #ifdef __BIG_ENDIAN_BITFIELD
2050 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2051 uint8_t rsvd2;
2052 uint16_t link_flags;
2053 #else /* __LITTLE_ENDIAN_BITFIELD */
2054 uint16_t link_flags;
2055 uint8_t rsvd2;
2056 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2057 #endif
2058
2059 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
2060 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
2061 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
2062 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
2063 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
2064 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
2065 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
2066
2067 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
2068 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
2069 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
2070
2071 uint32_t link_speed;
2072 #define LINK_SPEED_AUTO 0x0 /* Auto selection */
2073 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
2074 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
2075 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
2076 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
2077 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
2078 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
2079 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
2080
2081 } INIT_LINK_VAR;
2082
2083 /* Structure for MB Command DOWN_LINK (06) */
2084
2085 typedef struct {
2086 uint32_t rsvd1;
2087 } DOWN_LINK_VAR;
2088
2089 /* Structure for MB Command CONFIG_LINK (07) */
2090
2091 typedef struct {
2092 #ifdef __BIG_ENDIAN_BITFIELD
2093 uint32_t cr:1;
2094 uint32_t ci:1;
2095 uint32_t cr_delay:6;
2096 uint32_t cr_count:8;
2097 uint32_t rsvd1:8;
2098 uint32_t MaxBBC:8;
2099 #else /* __LITTLE_ENDIAN_BITFIELD */
2100 uint32_t MaxBBC:8;
2101 uint32_t rsvd1:8;
2102 uint32_t cr_count:8;
2103 uint32_t cr_delay:6;
2104 uint32_t ci:1;
2105 uint32_t cr:1;
2106 #endif
2107
2108 uint32_t myId;
2109 uint32_t rsvd2;
2110 uint32_t edtov;
2111 uint32_t arbtov;
2112 uint32_t ratov;
2113 uint32_t rttov;
2114 uint32_t altov;
2115 uint32_t crtov;
2116 uint32_t citov;
2117 #ifdef __BIG_ENDIAN_BITFIELD
2118 uint32_t rrq_enable:1;
2119 uint32_t rrq_immed:1;
2120 uint32_t rsvd4:29;
2121 uint32_t ack0_enable:1;
2122 #else /* __LITTLE_ENDIAN_BITFIELD */
2123 uint32_t ack0_enable:1;
2124 uint32_t rsvd4:29;
2125 uint32_t rrq_immed:1;
2126 uint32_t rrq_enable:1;
2127 #endif
2128 } CONFIG_LINK;
2129
2130 /* Structure for MB Command PART_SLIM (08)
2131 * will be removed since SLI1 is no longer supported!
2132 */
2133 typedef struct {
2134 #ifdef __BIG_ENDIAN_BITFIELD
2135 uint16_t offCiocb;
2136 uint16_t numCiocb;
2137 uint16_t offRiocb;
2138 uint16_t numRiocb;
2139 #else /* __LITTLE_ENDIAN_BITFIELD */
2140 uint16_t numCiocb;
2141 uint16_t offCiocb;
2142 uint16_t numRiocb;
2143 uint16_t offRiocb;
2144 #endif
2145 } RING_DEF;
2146
2147 typedef struct {
2148 #ifdef __BIG_ENDIAN_BITFIELD
2149 uint32_t unused1:24;
2150 uint32_t numRing:8;
2151 #else /* __LITTLE_ENDIAN_BITFIELD */
2152 uint32_t numRing:8;
2153 uint32_t unused1:24;
2154 #endif
2155
2156 RING_DEF ringdef[4];
2157 uint32_t hbainit;
2158 } PART_SLIM_VAR;
2159
2160 /* Structure for MB Command CONFIG_RING (09) */
2161
2162 typedef struct {
2163 #ifdef __BIG_ENDIAN_BITFIELD
2164 uint32_t unused2:6;
2165 uint32_t recvSeq:1;
2166 uint32_t recvNotify:1;
2167 uint32_t numMask:8;
2168 uint32_t profile:8;
2169 uint32_t unused1:4;
2170 uint32_t ring:4;
2171 #else /* __LITTLE_ENDIAN_BITFIELD */
2172 uint32_t ring:4;
2173 uint32_t unused1:4;
2174 uint32_t profile:8;
2175 uint32_t numMask:8;
2176 uint32_t recvNotify:1;
2177 uint32_t recvSeq:1;
2178 uint32_t unused2:6;
2179 #endif
2180
2181 #ifdef __BIG_ENDIAN_BITFIELD
2182 uint16_t maxRespXchg;
2183 uint16_t maxOrigXchg;
2184 #else /* __LITTLE_ENDIAN_BITFIELD */
2185 uint16_t maxOrigXchg;
2186 uint16_t maxRespXchg;
2187 #endif
2188
2189 RR_REG rrRegs[6];
2190 } CONFIG_RING_VAR;
2191
2192 /* Structure for MB Command RESET_RING (10) */
2193
2194 typedef struct {
2195 uint32_t ring_no;
2196 } RESET_RING_VAR;
2197
2198 /* Structure for MB Command READ_CONFIG (11) */
2199
2200 typedef struct {
2201 #ifdef __BIG_ENDIAN_BITFIELD
2202 uint32_t cr:1;
2203 uint32_t ci:1;
2204 uint32_t cr_delay:6;
2205 uint32_t cr_count:8;
2206 uint32_t InitBBC:8;
2207 uint32_t MaxBBC:8;
2208 #else /* __LITTLE_ENDIAN_BITFIELD */
2209 uint32_t MaxBBC:8;
2210 uint32_t InitBBC:8;
2211 uint32_t cr_count:8;
2212 uint32_t cr_delay:6;
2213 uint32_t ci:1;
2214 uint32_t cr:1;
2215 #endif
2216
2217 #ifdef __BIG_ENDIAN_BITFIELD
2218 uint32_t topology:8;
2219 uint32_t myDid:24;
2220 #else /* __LITTLE_ENDIAN_BITFIELD */
2221 uint32_t myDid:24;
2222 uint32_t topology:8;
2223 #endif
2224
2225 /* Defines for topology (defined previously) */
2226 #ifdef __BIG_ENDIAN_BITFIELD
2227 uint32_t AR:1;
2228 uint32_t IR:1;
2229 uint32_t rsvd1:29;
2230 uint32_t ack0:1;
2231 #else /* __LITTLE_ENDIAN_BITFIELD */
2232 uint32_t ack0:1;
2233 uint32_t rsvd1:29;
2234 uint32_t IR:1;
2235 uint32_t AR:1;
2236 #endif
2237
2238 uint32_t edtov;
2239 uint32_t arbtov;
2240 uint32_t ratov;
2241 uint32_t rttov;
2242 uint32_t altov;
2243 uint32_t lmt;
2244 #define LMT_RESERVED 0x000 /* Not used */
2245 #define LMT_1Gb 0x004
2246 #define LMT_2Gb 0x008
2247 #define LMT_4Gb 0x040
2248 #define LMT_8Gb 0x080
2249 #define LMT_10Gb 0x100
2250 #define LMT_16Gb 0x200
2251 #define LMT_32Gb 0x400
2252 uint32_t rsvd2;
2253 uint32_t rsvd3;
2254 uint32_t max_xri;
2255 uint32_t max_iocb;
2256 uint32_t max_rpi;
2257 uint32_t avail_xri;
2258 uint32_t avail_iocb;
2259 uint32_t avail_rpi;
2260 uint32_t max_vpi;
2261 uint32_t rsvd4;
2262 uint32_t rsvd5;
2263 uint32_t avail_vpi;
2264 } READ_CONFIG_VAR;
2265
2266 /* Structure for MB Command READ_RCONFIG (12) */
2267
2268 typedef struct {
2269 #ifdef __BIG_ENDIAN_BITFIELD
2270 uint32_t rsvd2:7;
2271 uint32_t recvNotify:1;
2272 uint32_t numMask:8;
2273 uint32_t profile:8;
2274 uint32_t rsvd1:4;
2275 uint32_t ring:4;
2276 #else /* __LITTLE_ENDIAN_BITFIELD */
2277 uint32_t ring:4;
2278 uint32_t rsvd1:4;
2279 uint32_t profile:8;
2280 uint32_t numMask:8;
2281 uint32_t recvNotify:1;
2282 uint32_t rsvd2:7;
2283 #endif
2284
2285 #ifdef __BIG_ENDIAN_BITFIELD
2286 uint16_t maxResp;
2287 uint16_t maxOrig;
2288 #else /* __LITTLE_ENDIAN_BITFIELD */
2289 uint16_t maxOrig;
2290 uint16_t maxResp;
2291 #endif
2292
2293 RR_REG rrRegs[6];
2294
2295 #ifdef __BIG_ENDIAN_BITFIELD
2296 uint16_t cmdRingOffset;
2297 uint16_t cmdEntryCnt;
2298 uint16_t rspRingOffset;
2299 uint16_t rspEntryCnt;
2300 uint16_t nextCmdOffset;
2301 uint16_t rsvd3;
2302 uint16_t nextRspOffset;
2303 uint16_t rsvd4;
2304 #else /* __LITTLE_ENDIAN_BITFIELD */
2305 uint16_t cmdEntryCnt;
2306 uint16_t cmdRingOffset;
2307 uint16_t rspEntryCnt;
2308 uint16_t rspRingOffset;
2309 uint16_t rsvd3;
2310 uint16_t nextCmdOffset;
2311 uint16_t rsvd4;
2312 uint16_t nextRspOffset;
2313 #endif
2314 } READ_RCONF_VAR;
2315
2316 /* Structure for MB Command READ_SPARM (13) */
2317 /* Structure for MB Command READ_SPARM64 (0x8D) */
2318
2319 typedef struct {
2320 uint32_t rsvd1;
2321 uint32_t rsvd2;
2322 union {
2323 struct ulp_bde sp; /* This BDE points to struct serv_parm
2324 structure */
2325 struct ulp_bde64 sp64;
2326 } un;
2327 #ifdef __BIG_ENDIAN_BITFIELD
2328 uint16_t rsvd3;
2329 uint16_t vpi;
2330 #else /* __LITTLE_ENDIAN_BITFIELD */
2331 uint16_t vpi;
2332 uint16_t rsvd3;
2333 #endif
2334 } READ_SPARM_VAR;
2335
2336 /* Structure for MB Command READ_STATUS (14) */
2337
2338 typedef struct {
2339 #ifdef __BIG_ENDIAN_BITFIELD
2340 uint32_t rsvd1:31;
2341 uint32_t clrCounters:1;
2342 uint16_t activeXriCnt;
2343 uint16_t activeRpiCnt;
2344 #else /* __LITTLE_ENDIAN_BITFIELD */
2345 uint32_t clrCounters:1;
2346 uint32_t rsvd1:31;
2347 uint16_t activeRpiCnt;
2348 uint16_t activeXriCnt;
2349 #endif
2350
2351 uint32_t xmitByteCnt;
2352 uint32_t rcvByteCnt;
2353 uint32_t xmitFrameCnt;
2354 uint32_t rcvFrameCnt;
2355 uint32_t xmitSeqCnt;
2356 uint32_t rcvSeqCnt;
2357 uint32_t totalOrigExchanges;
2358 uint32_t totalRespExchanges;
2359 uint32_t rcvPbsyCnt;
2360 uint32_t rcvFbsyCnt;
2361 } READ_STATUS_VAR;
2362
2363 /* Structure for MB Command READ_RPI (15) */
2364 /* Structure for MB Command READ_RPI64 (0x8F) */
2365
2366 typedef struct {
2367 #ifdef __BIG_ENDIAN_BITFIELD
2368 uint16_t nextRpi;
2369 uint16_t reqRpi;
2370 uint32_t rsvd2:8;
2371 uint32_t DID:24;
2372 #else /* __LITTLE_ENDIAN_BITFIELD */
2373 uint16_t reqRpi;
2374 uint16_t nextRpi;
2375 uint32_t DID:24;
2376 uint32_t rsvd2:8;
2377 #endif
2378
2379 union {
2380 struct ulp_bde sp;
2381 struct ulp_bde64 sp64;
2382 } un;
2383
2384 } READ_RPI_VAR;
2385
2386 /* Structure for MB Command READ_XRI (16) */
2387
2388 typedef struct {
2389 #ifdef __BIG_ENDIAN_BITFIELD
2390 uint16_t nextXri;
2391 uint16_t reqXri;
2392 uint16_t rsvd1;
2393 uint16_t rpi;
2394 uint32_t rsvd2:8;
2395 uint32_t DID:24;
2396 uint32_t rsvd3:8;
2397 uint32_t SID:24;
2398 uint32_t rsvd4;
2399 uint8_t seqId;
2400 uint8_t rsvd5;
2401 uint16_t seqCount;
2402 uint16_t oxId;
2403 uint16_t rxId;
2404 uint32_t rsvd6:30;
2405 uint32_t si:1;
2406 uint32_t exchOrig:1;
2407 #else /* __LITTLE_ENDIAN_BITFIELD */
2408 uint16_t reqXri;
2409 uint16_t nextXri;
2410 uint16_t rpi;
2411 uint16_t rsvd1;
2412 uint32_t DID:24;
2413 uint32_t rsvd2:8;
2414 uint32_t SID:24;
2415 uint32_t rsvd3:8;
2416 uint32_t rsvd4;
2417 uint16_t seqCount;
2418 uint8_t rsvd5;
2419 uint8_t seqId;
2420 uint16_t rxId;
2421 uint16_t oxId;
2422 uint32_t exchOrig:1;
2423 uint32_t si:1;
2424 uint32_t rsvd6:30;
2425 #endif
2426 } READ_XRI_VAR;
2427
2428 /* Structure for MB Command READ_REV (17) */
2429
2430 typedef struct {
2431 #ifdef __BIG_ENDIAN_BITFIELD
2432 uint32_t cv:1;
2433 uint32_t rr:1;
2434 uint32_t rsvd2:2;
2435 uint32_t v3req:1;
2436 uint32_t v3rsp:1;
2437 uint32_t rsvd1:25;
2438 uint32_t rv:1;
2439 #else /* __LITTLE_ENDIAN_BITFIELD */
2440 uint32_t rv:1;
2441 uint32_t rsvd1:25;
2442 uint32_t v3rsp:1;
2443 uint32_t v3req:1;
2444 uint32_t rsvd2:2;
2445 uint32_t rr:1;
2446 uint32_t cv:1;
2447 #endif
2448
2449 uint32_t biuRev;
2450 uint32_t smRev;
2451 union {
2452 uint32_t smFwRev;
2453 struct {
2454 #ifdef __BIG_ENDIAN_BITFIELD
2455 uint8_t ProgType;
2456 uint8_t ProgId;
2457 uint16_t ProgVer:4;
2458 uint16_t ProgRev:4;
2459 uint16_t ProgFixLvl:2;
2460 uint16_t ProgDistType:2;
2461 uint16_t DistCnt:4;
2462 #else /* __LITTLE_ENDIAN_BITFIELD */
2463 uint16_t DistCnt:4;
2464 uint16_t ProgDistType:2;
2465 uint16_t ProgFixLvl:2;
2466 uint16_t ProgRev:4;
2467 uint16_t ProgVer:4;
2468 uint8_t ProgId;
2469 uint8_t ProgType;
2470 #endif
2471
2472 } b;
2473 } un;
2474 uint32_t endecRev;
2475 #ifdef __BIG_ENDIAN_BITFIELD
2476 uint8_t feaLevelHigh;
2477 uint8_t feaLevelLow;
2478 uint8_t fcphHigh;
2479 uint8_t fcphLow;
2480 #else /* __LITTLE_ENDIAN_BITFIELD */
2481 uint8_t fcphLow;
2482 uint8_t fcphHigh;
2483 uint8_t feaLevelLow;
2484 uint8_t feaLevelHigh;
2485 #endif
2486
2487 uint32_t postKernRev;
2488 uint32_t opFwRev;
2489 uint8_t opFwName[16];
2490 uint32_t sli1FwRev;
2491 uint8_t sli1FwName[16];
2492 uint32_t sli2FwRev;
2493 uint8_t sli2FwName[16];
2494 uint32_t sli3Feat;
2495 uint32_t RandomData[6];
2496 } READ_REV_VAR;
2497
2498 /* Structure for MB Command READ_LINK_STAT (18) */
2499
2500 typedef struct {
2501 uint32_t rsvd1;
2502 uint32_t linkFailureCnt;
2503 uint32_t lossSyncCnt;
2504
2505 uint32_t lossSignalCnt;
2506 uint32_t primSeqErrCnt;
2507 uint32_t invalidXmitWord;
2508 uint32_t crcCnt;
2509 uint32_t primSeqTimeout;
2510 uint32_t elasticOverrun;
2511 uint32_t arbTimeout;
2512 } READ_LNK_VAR;
2513
2514 /* Structure for MB Command REG_LOGIN (19) */
2515 /* Structure for MB Command REG_LOGIN64 (0x93) */
2516
2517 typedef struct {
2518 #ifdef __BIG_ENDIAN_BITFIELD
2519 uint16_t rsvd1;
2520 uint16_t rpi;
2521 uint32_t rsvd2:8;
2522 uint32_t did:24;
2523 #else /* __LITTLE_ENDIAN_BITFIELD */
2524 uint16_t rpi;
2525 uint16_t rsvd1;
2526 uint32_t did:24;
2527 uint32_t rsvd2:8;
2528 #endif
2529
2530 union {
2531 struct ulp_bde sp;
2532 struct ulp_bde64 sp64;
2533 } un;
2534
2535 #ifdef __BIG_ENDIAN_BITFIELD
2536 uint16_t rsvd6;
2537 uint16_t vpi;
2538 #else /* __LITTLE_ENDIAN_BITFIELD */
2539 uint16_t vpi;
2540 uint16_t rsvd6;
2541 #endif
2542
2543 } REG_LOGIN_VAR;
2544
2545 /* Word 30 contents for REG_LOGIN */
2546 typedef union {
2547 struct {
2548 #ifdef __BIG_ENDIAN_BITFIELD
2549 uint16_t rsvd1:12;
2550 uint16_t wd30_class:4;
2551 uint16_t xri;
2552 #else /* __LITTLE_ENDIAN_BITFIELD */
2553 uint16_t xri;
2554 uint16_t wd30_class:4;
2555 uint16_t rsvd1:12;
2556 #endif
2557 } f;
2558 uint32_t word;
2559 } REG_WD30;
2560
2561 /* Structure for MB Command UNREG_LOGIN (20) */
2562
2563 typedef struct {
2564 #ifdef __BIG_ENDIAN_BITFIELD
2565 uint16_t rsvd1;
2566 uint16_t rpi;
2567 uint32_t rsvd2;
2568 uint32_t rsvd3;
2569 uint32_t rsvd4;
2570 uint32_t rsvd5;
2571 uint16_t rsvd6;
2572 uint16_t vpi;
2573 #else /* __LITTLE_ENDIAN_BITFIELD */
2574 uint16_t rpi;
2575 uint16_t rsvd1;
2576 uint32_t rsvd2;
2577 uint32_t rsvd3;
2578 uint32_t rsvd4;
2579 uint32_t rsvd5;
2580 uint16_t vpi;
2581 uint16_t rsvd6;
2582 #endif
2583 } UNREG_LOGIN_VAR;
2584
2585 /* Structure for MB Command REG_VPI (0x96) */
2586 typedef struct {
2587 #ifdef __BIG_ENDIAN_BITFIELD
2588 uint32_t rsvd1;
2589 uint32_t rsvd2:7;
2590 uint32_t upd:1;
2591 uint32_t sid:24;
2592 uint32_t wwn[2];
2593 uint32_t rsvd5;
2594 uint16_t vfi;
2595 uint16_t vpi;
2596 #else /* __LITTLE_ENDIAN */
2597 uint32_t rsvd1;
2598 uint32_t sid:24;
2599 uint32_t upd:1;
2600 uint32_t rsvd2:7;
2601 uint32_t wwn[2];
2602 uint32_t rsvd5;
2603 uint16_t vpi;
2604 uint16_t vfi;
2605 #endif
2606 } REG_VPI_VAR;
2607
2608 /* Structure for MB Command UNREG_VPI (0x97) */
2609 typedef struct {
2610 uint32_t rsvd1;
2611 #ifdef __BIG_ENDIAN_BITFIELD
2612 uint16_t rsvd2;
2613 uint16_t sli4_vpi;
2614 #else /* __LITTLE_ENDIAN */
2615 uint16_t sli4_vpi;
2616 uint16_t rsvd2;
2617 #endif
2618 uint32_t rsvd3;
2619 uint32_t rsvd4;
2620 uint32_t rsvd5;
2621 #ifdef __BIG_ENDIAN_BITFIELD
2622 uint16_t rsvd6;
2623 uint16_t vpi;
2624 #else /* __LITTLE_ENDIAN */
2625 uint16_t vpi;
2626 uint16_t rsvd6;
2627 #endif
2628 } UNREG_VPI_VAR;
2629
2630 /* Structure for MB Command UNREG_D_ID (0x23) */
2631
2632 typedef struct {
2633 uint32_t did;
2634 uint32_t rsvd2;
2635 uint32_t rsvd3;
2636 uint32_t rsvd4;
2637 uint32_t rsvd5;
2638 #ifdef __BIG_ENDIAN_BITFIELD
2639 uint16_t rsvd6;
2640 uint16_t vpi;
2641 #else
2642 uint16_t vpi;
2643 uint16_t rsvd6;
2644 #endif
2645 } UNREG_D_ID_VAR;
2646
2647 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2648 struct lpfc_mbx_read_top {
2649 uint32_t eventTag; /* Event tag */
2650 uint32_t word2;
2651 #define lpfc_mbx_read_top_fa_SHIFT 12
2652 #define lpfc_mbx_read_top_fa_MASK 0x00000001
2653 #define lpfc_mbx_read_top_fa_WORD word2
2654 #define lpfc_mbx_read_top_mm_SHIFT 11
2655 #define lpfc_mbx_read_top_mm_MASK 0x00000001
2656 #define lpfc_mbx_read_top_mm_WORD word2
2657 #define lpfc_mbx_read_top_pb_SHIFT 9
2658 #define lpfc_mbx_read_top_pb_MASK 0X00000001
2659 #define lpfc_mbx_read_top_pb_WORD word2
2660 #define lpfc_mbx_read_top_il_SHIFT 8
2661 #define lpfc_mbx_read_top_il_MASK 0x00000001
2662 #define lpfc_mbx_read_top_il_WORD word2
2663 #define lpfc_mbx_read_top_att_type_SHIFT 0
2664 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2665 #define lpfc_mbx_read_top_att_type_WORD word2
2666 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2667 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2668 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2669 uint32_t word3;
2670 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2671 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2672 #define lpfc_mbx_read_top_alpa_granted_WORD word3
2673 #define lpfc_mbx_read_top_lip_alps_SHIFT 16
2674 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2675 #define lpfc_mbx_read_top_lip_alps_WORD word3
2676 #define lpfc_mbx_read_top_lip_type_SHIFT 8
2677 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2678 #define lpfc_mbx_read_top_lip_type_WORD word3
2679 #define lpfc_mbx_read_top_topology_SHIFT 0
2680 #define lpfc_mbx_read_top_topology_MASK 0x000000FF
2681 #define lpfc_mbx_read_top_topology_WORD word3
2682 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2683 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2684 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2685 /* store the LILP AL_PA position map into */
2686 struct ulp_bde64 lilpBde64;
2687 #define LPFC_ALPA_MAP_SIZE 128
2688 uint32_t word7;
2689 #define lpfc_mbx_read_top_ld_lu_SHIFT 31
2690 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2691 #define lpfc_mbx_read_top_ld_lu_WORD word7
2692 #define lpfc_mbx_read_top_ld_tf_SHIFT 30
2693 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2694 #define lpfc_mbx_read_top_ld_tf_WORD word7
2695 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2696 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2697 #define lpfc_mbx_read_top_ld_link_spd_WORD word7
2698 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2699 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2700 #define lpfc_mbx_read_top_ld_nl_port_WORD word7
2701 #define lpfc_mbx_read_top_ld_tx_SHIFT 2
2702 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2703 #define lpfc_mbx_read_top_ld_tx_WORD word7
2704 #define lpfc_mbx_read_top_ld_rx_SHIFT 0
2705 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2706 #define lpfc_mbx_read_top_ld_rx_WORD word7
2707 uint32_t word8;
2708 #define lpfc_mbx_read_top_lu_SHIFT 31
2709 #define lpfc_mbx_read_top_lu_MASK 0x00000001
2710 #define lpfc_mbx_read_top_lu_WORD word8
2711 #define lpfc_mbx_read_top_tf_SHIFT 30
2712 #define lpfc_mbx_read_top_tf_MASK 0x00000001
2713 #define lpfc_mbx_read_top_tf_WORD word8
2714 #define lpfc_mbx_read_top_link_spd_SHIFT 8
2715 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2716 #define lpfc_mbx_read_top_link_spd_WORD word8
2717 #define lpfc_mbx_read_top_nl_port_SHIFT 4
2718 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2719 #define lpfc_mbx_read_top_nl_port_WORD word8
2720 #define lpfc_mbx_read_top_tx_SHIFT 2
2721 #define lpfc_mbx_read_top_tx_MASK 0x00000003
2722 #define lpfc_mbx_read_top_tx_WORD word8
2723 #define lpfc_mbx_read_top_rx_SHIFT 0
2724 #define lpfc_mbx_read_top_rx_MASK 0x00000003
2725 #define lpfc_mbx_read_top_rx_WORD word8
2726 #define LPFC_LINK_SPEED_UNKNOWN 0x0
2727 #define LPFC_LINK_SPEED_1GHZ 0x04
2728 #define LPFC_LINK_SPEED_2GHZ 0x08
2729 #define LPFC_LINK_SPEED_4GHZ 0x10
2730 #define LPFC_LINK_SPEED_8GHZ 0x20
2731 #define LPFC_LINK_SPEED_10GHZ 0x40
2732 #define LPFC_LINK_SPEED_16GHZ 0x80
2733 #define LPFC_LINK_SPEED_32GHZ 0x90
2734 };
2735
2736 /* Structure for MB Command CLEAR_LA (22) */
2737
2738 typedef struct {
2739 uint32_t eventTag; /* Event tag */
2740 uint32_t rsvd1;
2741 } CLEAR_LA_VAR;
2742
2743 /* Structure for MB Command DUMP */
2744
2745 typedef struct {
2746 #ifdef __BIG_ENDIAN_BITFIELD
2747 uint32_t rsvd:25;
2748 uint32_t ra:1;
2749 uint32_t co:1;
2750 uint32_t cv:1;
2751 uint32_t type:4;
2752 uint32_t entry_index:16;
2753 uint32_t region_id:16;
2754 #else /* __LITTLE_ENDIAN_BITFIELD */
2755 uint32_t type:4;
2756 uint32_t cv:1;
2757 uint32_t co:1;
2758 uint32_t ra:1;
2759 uint32_t rsvd:25;
2760 uint32_t region_id:16;
2761 uint32_t entry_index:16;
2762 #endif
2763
2764 uint32_t sli4_length;
2765 uint32_t word_cnt;
2766 uint32_t resp_offset;
2767 } DUMP_VAR;
2768
2769 #define DMP_MEM_REG 0x1
2770 #define DMP_NV_PARAMS 0x2
2771 #define DMP_LMSD 0x3 /* Link Module Serial Data */
2772 #define DMP_WELL_KNOWN 0x4
2773
2774 #define DMP_REGION_VPD 0xe
2775 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2776 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2777 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2778
2779 #define DMP_REGION_VPORT 0x16 /* VPort info region */
2780 #define DMP_VPORT_REGION_SIZE 0x200
2781 #define DMP_MBOX_OFFSET_WORD 0x5
2782
2783 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
2784 #define DMP_RGN23_SIZE 0x400
2785
2786 #define WAKE_UP_PARMS_REGION_ID 4
2787 #define WAKE_UP_PARMS_WORD_SIZE 15
2788
2789 struct vport_rec {
2790 uint8_t wwpn[8];
2791 uint8_t wwnn[8];
2792 };
2793
2794 #define VPORT_INFO_SIG 0x32324752
2795 #define VPORT_INFO_REV_MASK 0xff
2796 #define VPORT_INFO_REV 0x1
2797 #define MAX_STATIC_VPORT_COUNT 16
2798 struct static_vport_info {
2799 uint32_t signature;
2800 uint32_t rev;
2801 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
2802 uint32_t resvd[66];
2803 };
2804
2805 /* Option rom version structure */
2806 struct prog_id {
2807 #ifdef __BIG_ENDIAN_BITFIELD
2808 uint8_t type;
2809 uint8_t id;
2810 uint32_t ver:4; /* Major Version */
2811 uint32_t rev:4; /* Revision */
2812 uint32_t lev:2; /* Level */
2813 uint32_t dist:2; /* Dist Type */
2814 uint32_t num:4; /* number after dist type */
2815 #else /* __LITTLE_ENDIAN_BITFIELD */
2816 uint32_t num:4; /* number after dist type */
2817 uint32_t dist:2; /* Dist Type */
2818 uint32_t lev:2; /* Level */
2819 uint32_t rev:4; /* Revision */
2820 uint32_t ver:4; /* Major Version */
2821 uint8_t id;
2822 uint8_t type;
2823 #endif
2824 };
2825
2826 /* Structure for MB Command UPDATE_CFG (0x1B) */
2827
2828 struct update_cfg_var {
2829 #ifdef __BIG_ENDIAN_BITFIELD
2830 uint32_t rsvd2:16;
2831 uint32_t type:8;
2832 uint32_t rsvd:1;
2833 uint32_t ra:1;
2834 uint32_t co:1;
2835 uint32_t cv:1;
2836 uint32_t req:4;
2837 uint32_t entry_length:16;
2838 uint32_t region_id:16;
2839 #else /* __LITTLE_ENDIAN_BITFIELD */
2840 uint32_t req:4;
2841 uint32_t cv:1;
2842 uint32_t co:1;
2843 uint32_t ra:1;
2844 uint32_t rsvd:1;
2845 uint32_t type:8;
2846 uint32_t rsvd2:16;
2847 uint32_t region_id:16;
2848 uint32_t entry_length:16;
2849 #endif
2850
2851 uint32_t resp_info;
2852 uint32_t byte_cnt;
2853 uint32_t data_offset;
2854 };
2855
2856 struct hbq_mask {
2857 #ifdef __BIG_ENDIAN_BITFIELD
2858 uint8_t tmatch;
2859 uint8_t tmask;
2860 uint8_t rctlmatch;
2861 uint8_t rctlmask;
2862 #else /* __LITTLE_ENDIAN */
2863 uint8_t rctlmask;
2864 uint8_t rctlmatch;
2865 uint8_t tmask;
2866 uint8_t tmatch;
2867 #endif
2868 };
2869
2870
2871 /* Structure for MB Command CONFIG_HBQ (7c) */
2872
2873 struct config_hbq_var {
2874 #ifdef __BIG_ENDIAN_BITFIELD
2875 uint32_t rsvd1 :7;
2876 uint32_t recvNotify :1; /* Receive Notification */
2877 uint32_t numMask :8; /* # Mask Entries */
2878 uint32_t profile :8; /* Selection Profile */
2879 uint32_t rsvd2 :8;
2880 #else /* __LITTLE_ENDIAN */
2881 uint32_t rsvd2 :8;
2882 uint32_t profile :8; /* Selection Profile */
2883 uint32_t numMask :8; /* # Mask Entries */
2884 uint32_t recvNotify :1; /* Receive Notification */
2885 uint32_t rsvd1 :7;
2886 #endif
2887
2888 #ifdef __BIG_ENDIAN_BITFIELD
2889 uint32_t hbqId :16;
2890 uint32_t rsvd3 :12;
2891 uint32_t ringMask :4;
2892 #else /* __LITTLE_ENDIAN */
2893 uint32_t ringMask :4;
2894 uint32_t rsvd3 :12;
2895 uint32_t hbqId :16;
2896 #endif
2897
2898 #ifdef __BIG_ENDIAN_BITFIELD
2899 uint32_t entry_count :16;
2900 uint32_t rsvd4 :8;
2901 uint32_t headerLen :8;
2902 #else /* __LITTLE_ENDIAN */
2903 uint32_t headerLen :8;
2904 uint32_t rsvd4 :8;
2905 uint32_t entry_count :16;
2906 #endif
2907
2908 uint32_t hbqaddrLow;
2909 uint32_t hbqaddrHigh;
2910
2911 #ifdef __BIG_ENDIAN_BITFIELD
2912 uint32_t rsvd5 :31;
2913 uint32_t logEntry :1;
2914 #else /* __LITTLE_ENDIAN */
2915 uint32_t logEntry :1;
2916 uint32_t rsvd5 :31;
2917 #endif
2918
2919 uint32_t rsvd6; /* w7 */
2920 uint32_t rsvd7; /* w8 */
2921 uint32_t rsvd8; /* w9 */
2922
2923 struct hbq_mask hbqMasks[6];
2924
2925
2926 union {
2927 uint32_t allprofiles[12];
2928
2929 struct {
2930 #ifdef __BIG_ENDIAN_BITFIELD
2931 uint32_t seqlenoff :16;
2932 uint32_t maxlen :16;
2933 #else /* __LITTLE_ENDIAN */
2934 uint32_t maxlen :16;
2935 uint32_t seqlenoff :16;
2936 #endif
2937 #ifdef __BIG_ENDIAN_BITFIELD
2938 uint32_t rsvd1 :28;
2939 uint32_t seqlenbcnt :4;
2940 #else /* __LITTLE_ENDIAN */
2941 uint32_t seqlenbcnt :4;
2942 uint32_t rsvd1 :28;
2943 #endif
2944 uint32_t rsvd[10];
2945 } profile2;
2946
2947 struct {
2948 #ifdef __BIG_ENDIAN_BITFIELD
2949 uint32_t seqlenoff :16;
2950 uint32_t maxlen :16;
2951 #else /* __LITTLE_ENDIAN */
2952 uint32_t maxlen :16;
2953 uint32_t seqlenoff :16;
2954 #endif
2955 #ifdef __BIG_ENDIAN_BITFIELD
2956 uint32_t cmdcodeoff :28;
2957 uint32_t rsvd1 :12;
2958 uint32_t seqlenbcnt :4;
2959 #else /* __LITTLE_ENDIAN */
2960 uint32_t seqlenbcnt :4;
2961 uint32_t rsvd1 :12;
2962 uint32_t cmdcodeoff :28;
2963 #endif
2964 uint32_t cmdmatch[8];
2965
2966 uint32_t rsvd[2];
2967 } profile3;
2968
2969 struct {
2970 #ifdef __BIG_ENDIAN_BITFIELD
2971 uint32_t seqlenoff :16;
2972 uint32_t maxlen :16;
2973 #else /* __LITTLE_ENDIAN */
2974 uint32_t maxlen :16;
2975 uint32_t seqlenoff :16;
2976 #endif
2977 #ifdef __BIG_ENDIAN_BITFIELD
2978 uint32_t cmdcodeoff :28;
2979 uint32_t rsvd1 :12;
2980 uint32_t seqlenbcnt :4;
2981 #else /* __LITTLE_ENDIAN */
2982 uint32_t seqlenbcnt :4;
2983 uint32_t rsvd1 :12;
2984 uint32_t cmdcodeoff :28;
2985 #endif
2986 uint32_t cmdmatch[8];
2987
2988 uint32_t rsvd[2];
2989 } profile5;
2990
2991 } profiles;
2992
2993 };
2994
2995
2996
2997 /* Structure for MB Command CONFIG_PORT (0x88) */
2998 typedef struct {
2999 #ifdef __BIG_ENDIAN_BITFIELD
3000 uint32_t cBE : 1;
3001 uint32_t cET : 1;
3002 uint32_t cHpcb : 1;
3003 uint32_t cMA : 1;
3004 uint32_t sli_mode : 4;
3005 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3006 * config block */
3007 #else /* __LITTLE_ENDIAN */
3008 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3009 * config block */
3010 uint32_t sli_mode : 4;
3011 uint32_t cMA : 1;
3012 uint32_t cHpcb : 1;
3013 uint32_t cET : 1;
3014 uint32_t cBE : 1;
3015 #endif
3016
3017 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
3018 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
3019 uint32_t hbainit[5];
3020 #ifdef __BIG_ENDIAN_BITFIELD
3021 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3022 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3023 #else /* __LITTLE_ENDIAN */
3024 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3025 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3026 #endif
3027
3028 #ifdef __BIG_ENDIAN_BITFIELD
3029 uint32_t rsvd1 : 19; /* Reserved */
3030 uint32_t cdss : 1; /* Configure Data Security SLI */
3031 uint32_t casabt : 1; /* Configure async abts status notice */
3032 uint32_t rsvd2 : 2; /* Reserved */
3033 uint32_t cbg : 1; /* Configure BlockGuard */
3034 uint32_t cmv : 1; /* Configure Max VPIs */
3035 uint32_t ccrp : 1; /* Config Command Ring Polling */
3036 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3037 uint32_t chbs : 1; /* Cofigure Host Backing store */
3038 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3039 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3040 uint32_t cmx : 1; /* Configure Max XRIs */
3041 uint32_t cmr : 1; /* Configure Max RPIs */
3042 #else /* __LITTLE_ENDIAN */
3043 uint32_t cmr : 1; /* Configure Max RPIs */
3044 uint32_t cmx : 1; /* Configure Max XRIs */
3045 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3046 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3047 uint32_t chbs : 1; /* Cofigure Host Backing store */
3048 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3049 uint32_t ccrp : 1; /* Config Command Ring Polling */
3050 uint32_t cmv : 1; /* Configure Max VPIs */
3051 uint32_t cbg : 1; /* Configure BlockGuard */
3052 uint32_t rsvd2 : 2; /* Reserved */
3053 uint32_t casabt : 1; /* Configure async abts status notice */
3054 uint32_t cdss : 1; /* Configure Data Security SLI */
3055 uint32_t rsvd1 : 19; /* Reserved */
3056 #endif
3057 #ifdef __BIG_ENDIAN_BITFIELD
3058 uint32_t rsvd3 : 19; /* Reserved */
3059 uint32_t gdss : 1; /* Configure Data Security SLI */
3060 uint32_t gasabt : 1; /* Grant async abts status notice */
3061 uint32_t rsvd4 : 2; /* Reserved */
3062 uint32_t gbg : 1; /* Grant BlockGuard */
3063 uint32_t gmv : 1; /* Grant Max VPIs */
3064 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3065 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3066 uint32_t ghbs : 1; /* Grant Host Backing Store */
3067 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3068 uint32_t gerbm : 1; /* Grant ERBM Request */
3069 uint32_t gmx : 1; /* Grant Max XRIs */
3070 uint32_t gmr : 1; /* Grant Max RPIs */
3071 #else /* __LITTLE_ENDIAN */
3072 uint32_t gmr : 1; /* Grant Max RPIs */
3073 uint32_t gmx : 1; /* Grant Max XRIs */
3074 uint32_t gerbm : 1; /* Grant ERBM Request */
3075 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3076 uint32_t ghbs : 1; /* Grant Host Backing Store */
3077 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3078 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3079 uint32_t gmv : 1; /* Grant Max VPIs */
3080 uint32_t gbg : 1; /* Grant BlockGuard */
3081 uint32_t rsvd4 : 2; /* Reserved */
3082 uint32_t gasabt : 1; /* Grant async abts status notice */
3083 uint32_t gdss : 1; /* Configure Data Security SLI */
3084 uint32_t rsvd3 : 19; /* Reserved */
3085 #endif
3086
3087 #ifdef __BIG_ENDIAN_BITFIELD
3088 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3089 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3090 #else /* __LITTLE_ENDIAN */
3091 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3092 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3093 #endif
3094
3095 #ifdef __BIG_ENDIAN_BITFIELD
3096 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3097 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3098 #else /* __LITTLE_ENDIAN */
3099 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3100 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3101 #endif
3102
3103 uint32_t rsvd6; /* Reserved */
3104
3105 #ifdef __BIG_ENDIAN_BITFIELD
3106 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3107 uint32_t fips_level : 4; /* FIPS Level */
3108 uint32_t sec_err : 9; /* security crypto error */
3109 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3110 #else /* __LITTLE_ENDIAN */
3111 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3112 uint32_t sec_err : 9; /* security crypto error */
3113 uint32_t fips_level : 4; /* FIPS Level */
3114 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3115 #endif
3116
3117 } CONFIG_PORT_VAR;
3118
3119 /* Structure for MB Command CONFIG_MSI (0x30) */
3120 struct config_msi_var {
3121 #ifdef __BIG_ENDIAN_BITFIELD
3122 uint32_t dfltMsgNum:8; /* Default message number */
3123 uint32_t rsvd1:11; /* Reserved */
3124 uint32_t NID:5; /* Number of secondary attention IDs */
3125 uint32_t rsvd2:5; /* Reserved */
3126 uint32_t dfltPresent:1; /* Default message number present */
3127 uint32_t addFlag:1; /* Add association flag */
3128 uint32_t reportFlag:1; /* Report association flag */
3129 #else /* __LITTLE_ENDIAN_BITFIELD */
3130 uint32_t reportFlag:1; /* Report association flag */
3131 uint32_t addFlag:1; /* Add association flag */
3132 uint32_t dfltPresent:1; /* Default message number present */
3133 uint32_t rsvd2:5; /* Reserved */
3134 uint32_t NID:5; /* Number of secondary attention IDs */
3135 uint32_t rsvd1:11; /* Reserved */
3136 uint32_t dfltMsgNum:8; /* Default message number */
3137 #endif
3138 uint32_t attentionConditions[2];
3139 uint8_t attentionId[16];
3140 uint8_t messageNumberByHA[64];
3141 uint8_t messageNumberByID[16];
3142 uint32_t autoClearHA[2];
3143 #ifdef __BIG_ENDIAN_BITFIELD
3144 uint32_t rsvd3:16;
3145 uint32_t autoClearID:16;
3146 #else /* __LITTLE_ENDIAN_BITFIELD */
3147 uint32_t autoClearID:16;
3148 uint32_t rsvd3:16;
3149 #endif
3150 uint32_t rsvd4;
3151 };
3152
3153 /* SLI-2 Port Control Block */
3154
3155 /* SLIM POINTER */
3156 #define SLIMOFF 0x30 /* WORD */
3157
3158 typedef struct _SLI2_RDSC {
3159 uint32_t cmdEntries;
3160 uint32_t cmdAddrLow;
3161 uint32_t cmdAddrHigh;
3162
3163 uint32_t rspEntries;
3164 uint32_t rspAddrLow;
3165 uint32_t rspAddrHigh;
3166 } SLI2_RDSC;
3167
3168 typedef struct _PCB {
3169 #ifdef __BIG_ENDIAN_BITFIELD
3170 uint32_t type:8;
3171 #define TYPE_NATIVE_SLI2 0x01
3172 uint32_t feature:8;
3173 #define FEATURE_INITIAL_SLI2 0x01
3174 uint32_t rsvd:12;
3175 uint32_t maxRing:4;
3176 #else /* __LITTLE_ENDIAN_BITFIELD */
3177 uint32_t maxRing:4;
3178 uint32_t rsvd:12;
3179 uint32_t feature:8;
3180 #define FEATURE_INITIAL_SLI2 0x01
3181 uint32_t type:8;
3182 #define TYPE_NATIVE_SLI2 0x01
3183 #endif
3184
3185 uint32_t mailBoxSize;
3186 uint32_t mbAddrLow;
3187 uint32_t mbAddrHigh;
3188
3189 uint32_t hgpAddrLow;
3190 uint32_t hgpAddrHigh;
3191
3192 uint32_t pgpAddrLow;
3193 uint32_t pgpAddrHigh;
3194 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3195 } PCB_t;
3196
3197 /* NEW_FEATURE */
3198 typedef struct {
3199 #ifdef __BIG_ENDIAN_BITFIELD
3200 uint32_t rsvd0:27;
3201 uint32_t discardFarp:1;
3202 uint32_t IPEnable:1;
3203 uint32_t nodeName:1;
3204 uint32_t portName:1;
3205 uint32_t filterEnable:1;
3206 #else /* __LITTLE_ENDIAN_BITFIELD */
3207 uint32_t filterEnable:1;
3208 uint32_t portName:1;
3209 uint32_t nodeName:1;
3210 uint32_t IPEnable:1;
3211 uint32_t discardFarp:1;
3212 uint32_t rsvd:27;
3213 #endif
3214
3215 uint8_t portname[8]; /* Used to be struct lpfc_name */
3216 uint8_t nodename[8];
3217 uint32_t rsvd1;
3218 uint32_t rsvd2;
3219 uint32_t rsvd3;
3220 uint32_t IPAddress;
3221 } CONFIG_FARP_VAR;
3222
3223 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3224
3225 typedef struct {
3226 #ifdef __BIG_ENDIAN_BITFIELD
3227 uint32_t rsvd:30;
3228 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3229 #else /* __LITTLE_ENDIAN */
3230 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3231 uint32_t rsvd:30;
3232 #endif
3233 } ASYNCEVT_ENABLE_VAR;
3234
3235 /* Union of all Mailbox Command types */
3236 #define MAILBOX_CMD_WSIZE 32
3237 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3238 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3239 #define MAILBOX_EXT_WSIZE 512
3240 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3241 #define MAILBOX_HBA_EXT_OFFSET 0x100
3242 /* max mbox xmit size is a page size for sysfs IO operations */
3243 #define MAILBOX_SYSFS_MAX 4096
3244
3245 typedef union {
3246 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3247 * feature/max ring number
3248 */
3249 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3250 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3251 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3252 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3253 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3254 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3255 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3256 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3257 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3258 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3259 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3260 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3261 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3262 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3263 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3264 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3265 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3266 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3267 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3268 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3269 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3270 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3271 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3272 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3273 * NEW_FEATURE
3274 */
3275 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3276 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3277 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3278 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3279 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3280 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3281 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3282 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3283 * (READ_EVENT_LOG)
3284 */
3285 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3286 } MAILVARIANTS;
3287
3288 /*
3289 * SLI-2 specific structures
3290 */
3291
3292 struct lpfc_hgp {
3293 __le32 cmdPutInx;
3294 __le32 rspGetInx;
3295 };
3296
3297 struct lpfc_pgp {
3298 __le32 cmdGetInx;
3299 __le32 rspPutInx;
3300 };
3301
3302 struct sli2_desc {
3303 uint32_t unused1[16];
3304 struct lpfc_hgp host[MAX_SLI3_RINGS];
3305 struct lpfc_pgp port[MAX_SLI3_RINGS];
3306 };
3307
3308 struct sli3_desc {
3309 struct lpfc_hgp host[MAX_SLI3_RINGS];
3310 uint32_t reserved[8];
3311 uint32_t hbq_put[16];
3312 };
3313
3314 struct sli3_pgp {
3315 struct lpfc_pgp port[MAX_SLI3_RINGS];
3316 uint32_t hbq_get[16];
3317 };
3318
3319 union sli_var {
3320 struct sli2_desc s2;
3321 struct sli3_desc s3;
3322 struct sli3_pgp s3_pgp;
3323 };
3324
3325 typedef struct {
3326 #ifdef __BIG_ENDIAN_BITFIELD
3327 uint16_t mbxStatus;
3328 uint8_t mbxCommand;
3329 uint8_t mbxReserved:6;
3330 uint8_t mbxHc:1;
3331 uint8_t mbxOwner:1; /* Low order bit first word */
3332 #else /* __LITTLE_ENDIAN_BITFIELD */
3333 uint8_t mbxOwner:1; /* Low order bit first word */
3334 uint8_t mbxHc:1;
3335 uint8_t mbxReserved:6;
3336 uint8_t mbxCommand;
3337 uint16_t mbxStatus;
3338 #endif
3339
3340 MAILVARIANTS un;
3341 union sli_var us;
3342 } MAILBOX_t;
3343
3344 /*
3345 * Begin Structure Definitions for IOCB Commands
3346 */
3347
3348 typedef struct {
3349 #ifdef __BIG_ENDIAN_BITFIELD
3350 uint8_t statAction;
3351 uint8_t statRsn;
3352 uint8_t statBaExp;
3353 uint8_t statLocalError;
3354 #else /* __LITTLE_ENDIAN_BITFIELD */
3355 uint8_t statLocalError;
3356 uint8_t statBaExp;
3357 uint8_t statRsn;
3358 uint8_t statAction;
3359 #endif
3360 /* statRsn P/F_RJT reason codes */
3361 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3362 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3363 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3364 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3365 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3366 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3367 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3368 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3369 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3370 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3371 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3372 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3373 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3374 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3375 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3376 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3377 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3378 #define RJT_PROT_ERR 0x12 /* Protocol error */
3379 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3380 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3381 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3382 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3383 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3384 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3385 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3386 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3387
3388 #define IOERR_SUCCESS 0x00 /* statLocalError */
3389 #define IOERR_MISSING_CONTINUE 0x01
3390 #define IOERR_SEQUENCE_TIMEOUT 0x02
3391 #define IOERR_INTERNAL_ERROR 0x03
3392 #define IOERR_INVALID_RPI 0x04
3393 #define IOERR_NO_XRI 0x05
3394 #define IOERR_ILLEGAL_COMMAND 0x06
3395 #define IOERR_XCHG_DROPPED 0x07
3396 #define IOERR_ILLEGAL_FIELD 0x08
3397 #define IOERR_BAD_CONTINUE 0x09
3398 #define IOERR_TOO_MANY_BUFFERS 0x0A
3399 #define IOERR_RCV_BUFFER_WAITING 0x0B
3400 #define IOERR_NO_CONNECTION 0x0C
3401 #define IOERR_TX_DMA_FAILED 0x0D
3402 #define IOERR_RX_DMA_FAILED 0x0E
3403 #define IOERR_ILLEGAL_FRAME 0x0F
3404 #define IOERR_EXTRA_DATA 0x10
3405 #define IOERR_NO_RESOURCES 0x11
3406 #define IOERR_RESERVED 0x12
3407 #define IOERR_ILLEGAL_LENGTH 0x13
3408 #define IOERR_UNSUPPORTED_FEATURE 0x14
3409 #define IOERR_ABORT_IN_PROGRESS 0x15
3410 #define IOERR_ABORT_REQUESTED 0x16
3411 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3412 #define IOERR_LOOP_OPEN_FAILURE 0x18
3413 #define IOERR_RING_RESET 0x19
3414 #define IOERR_LINK_DOWN 0x1A
3415 #define IOERR_CORRUPTED_DATA 0x1B
3416 #define IOERR_CORRUPTED_RPI 0x1C
3417 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3418 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3419 #define IOERR_DUP_FRAME 0x1F
3420 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3421 #define IOERR_BAD_HOST_ADDRESS 0x21
3422 #define IOERR_RCV_HDRBUF_WAITING 0x22
3423 #define IOERR_MISSING_HDR_BUFFER 0x23
3424 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3425 #define IOERR_ABORTMULT_REQUESTED 0x25
3426 #define IOERR_BUFFER_SHORTAGE 0x28
3427 #define IOERR_DEFAULT 0x29
3428 #define IOERR_CNT 0x2A
3429 #define IOERR_SLER_FAILURE 0x46
3430 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3431 #define IOERR_SLER_REC_RJT_ERR 0x48
3432 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3433 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3434 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3435 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3436 #define IOERR_SLER_ABTS_ERR 0x4E
3437 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3438 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3439 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3440 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3441 #define IOERR_DRVR_MASK 0x100
3442 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3443 #define IOERR_SLI_BRESET 0x102
3444 #define IOERR_SLI_ABORTED 0x103
3445 #define IOERR_PARAM_MASK 0x1ff
3446 } PARM_ERR;
3447
3448 typedef union {
3449 struct {
3450 #ifdef __BIG_ENDIAN_BITFIELD
3451 uint8_t Rctl; /* R_CTL field */
3452 uint8_t Type; /* TYPE field */
3453 uint8_t Dfctl; /* DF_CTL field */
3454 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3455 #else /* __LITTLE_ENDIAN_BITFIELD */
3456 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3457 uint8_t Dfctl; /* DF_CTL field */
3458 uint8_t Type; /* TYPE field */
3459 uint8_t Rctl; /* R_CTL field */
3460 #endif
3461
3462 #define BC 0x02 /* Broadcast Received - Fctl */
3463 #define SI 0x04 /* Sequence Initiative */
3464 #define LA 0x08 /* Ignore Link Attention state */
3465 #define LS 0x80 /* Last Sequence */
3466 } hcsw;
3467 uint32_t reserved;
3468 } WORD5;
3469
3470 /* IOCB Command template for a generic response */
3471 typedef struct {
3472 uint32_t reserved[4];
3473 PARM_ERR perr;
3474 } GENERIC_RSP;
3475
3476 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3477 typedef struct {
3478 struct ulp_bde xrsqbde[2];
3479 uint32_t xrsqRo; /* Starting Relative Offset */
3480 WORD5 w5; /* Header control/status word */
3481 } XR_SEQ_FIELDS;
3482
3483 /* IOCB Command template for ELS_REQUEST */
3484 typedef struct {
3485 struct ulp_bde elsReq;
3486 struct ulp_bde elsRsp;
3487
3488 #ifdef __BIG_ENDIAN_BITFIELD
3489 uint32_t word4Rsvd:7;
3490 uint32_t fl:1;
3491 uint32_t myID:24;
3492 uint32_t word5Rsvd:8;
3493 uint32_t remoteID:24;
3494 #else /* __LITTLE_ENDIAN_BITFIELD */
3495 uint32_t myID:24;
3496 uint32_t fl:1;
3497 uint32_t word4Rsvd:7;
3498 uint32_t remoteID:24;
3499 uint32_t word5Rsvd:8;
3500 #endif
3501 } ELS_REQUEST;
3502
3503 /* IOCB Command template for RCV_ELS_REQ */
3504 typedef struct {
3505 struct ulp_bde elsReq[2];
3506 uint32_t parmRo;
3507
3508 #ifdef __BIG_ENDIAN_BITFIELD
3509 uint32_t word5Rsvd:8;
3510 uint32_t remoteID:24;
3511 #else /* __LITTLE_ENDIAN_BITFIELD */
3512 uint32_t remoteID:24;
3513 uint32_t word5Rsvd:8;
3514 #endif
3515 } RCV_ELS_REQ;
3516
3517 /* IOCB Command template for ABORT / CLOSE_XRI */
3518 typedef struct {
3519 uint32_t rsvd[3];
3520 uint32_t abortType;
3521 #define ABORT_TYPE_ABTX 0x00000000
3522 #define ABORT_TYPE_ABTS 0x00000001
3523 uint32_t parm;
3524 #ifdef __BIG_ENDIAN_BITFIELD
3525 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3526 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3527 #else /* __LITTLE_ENDIAN_BITFIELD */
3528 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3529 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3530 #endif
3531 } AC_XRI;
3532
3533 /* IOCB Command template for ABORT_MXRI64 */
3534 typedef struct {
3535 uint32_t rsvd[3];
3536 uint32_t abortType;
3537 uint32_t parm;
3538 uint32_t iotag32;
3539 } A_MXRI64;
3540
3541 /* IOCB Command template for GET_RPI */
3542 typedef struct {
3543 uint32_t rsvd[4];
3544 uint32_t parmRo;
3545 #ifdef __BIG_ENDIAN_BITFIELD
3546 uint32_t word5Rsvd:8;
3547 uint32_t remoteID:24;
3548 #else /* __LITTLE_ENDIAN_BITFIELD */
3549 uint32_t remoteID:24;
3550 uint32_t word5Rsvd:8;
3551 #endif
3552 } GET_RPI;
3553
3554 /* IOCB Command template for all FCP Initiator commands */
3555 typedef struct {
3556 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3557 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3558 uint32_t fcpi_parm;
3559 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3560 } FCPI_FIELDS;
3561
3562 /* IOCB Command template for all FCP Target commands */
3563 typedef struct {
3564 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3565 uint32_t fcpt_Offset;
3566 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3567 } FCPT_FIELDS;
3568
3569 /* SLI-2 IOCB structure definitions */
3570
3571 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3572 typedef struct {
3573 ULP_BDL bdl;
3574 uint32_t xrsqRo; /* Starting Relative Offset */
3575 WORD5 w5; /* Header control/status word */
3576 } XMT_SEQ_FIELDS64;
3577
3578 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3579 #define xmit_els_remoteID xrsqRo
3580
3581 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3582 typedef struct {
3583 struct ulp_bde64 rcvBde;
3584 uint32_t rsvd1;
3585 uint32_t xrsqRo; /* Starting Relative Offset */
3586 WORD5 w5; /* Header control/status word */
3587 } RCV_SEQ_FIELDS64;
3588
3589 /* IOCB Command template for ELS_REQUEST64 */
3590 typedef struct {
3591 ULP_BDL bdl;
3592 #ifdef __BIG_ENDIAN_BITFIELD
3593 uint32_t word4Rsvd:7;
3594 uint32_t fl:1;
3595 uint32_t myID:24;
3596 uint32_t word5Rsvd:8;
3597 uint32_t remoteID:24;
3598 #else /* __LITTLE_ENDIAN_BITFIELD */
3599 uint32_t myID:24;
3600 uint32_t fl:1;
3601 uint32_t word4Rsvd:7;
3602 uint32_t remoteID:24;
3603 uint32_t word5Rsvd:8;
3604 #endif
3605 } ELS_REQUEST64;
3606
3607 /* IOCB Command template for GEN_REQUEST64 */
3608 typedef struct {
3609 ULP_BDL bdl;
3610 uint32_t xrsqRo; /* Starting Relative Offset */
3611 WORD5 w5; /* Header control/status word */
3612 } GEN_REQUEST64;
3613
3614 /* IOCB Command template for RCV_ELS_REQ64 */
3615 typedef struct {
3616 struct ulp_bde64 elsReq;
3617 uint32_t rcvd1;
3618 uint32_t parmRo;
3619
3620 #ifdef __BIG_ENDIAN_BITFIELD
3621 uint32_t word5Rsvd:8;
3622 uint32_t remoteID:24;
3623 #else /* __LITTLE_ENDIAN_BITFIELD */
3624 uint32_t remoteID:24;
3625 uint32_t word5Rsvd:8;
3626 #endif
3627 } RCV_ELS_REQ64;
3628
3629 /* IOCB Command template for RCV_SEQ64 */
3630 struct rcv_seq64 {
3631 struct ulp_bde64 elsReq;
3632 uint32_t hbq_1;
3633 uint32_t parmRo;
3634 #ifdef __BIG_ENDIAN_BITFIELD
3635 uint32_t rctl:8;
3636 uint32_t type:8;
3637 uint32_t dfctl:8;
3638 uint32_t ls:1;
3639 uint32_t fs:1;
3640 uint32_t rsvd2:3;
3641 uint32_t si:1;
3642 uint32_t bc:1;
3643 uint32_t rsvd3:1;
3644 #else /* __LITTLE_ENDIAN_BITFIELD */
3645 uint32_t rsvd3:1;
3646 uint32_t bc:1;
3647 uint32_t si:1;
3648 uint32_t rsvd2:3;
3649 uint32_t fs:1;
3650 uint32_t ls:1;
3651 uint32_t dfctl:8;
3652 uint32_t type:8;
3653 uint32_t rctl:8;
3654 #endif
3655 };
3656
3657 /* IOCB Command template for all 64 bit FCP Initiator commands */
3658 typedef struct {
3659 ULP_BDL bdl;
3660 uint32_t fcpi_parm;
3661 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3662 } FCPI_FIELDS64;
3663
3664 /* IOCB Command template for all 64 bit FCP Target commands */
3665 typedef struct {
3666 ULP_BDL bdl;
3667 uint32_t fcpt_Offset;
3668 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3669 } FCPT_FIELDS64;
3670
3671 /* IOCB Command template for Async Status iocb commands */
3672 typedef struct {
3673 uint32_t rsvd[4];
3674 uint32_t param;
3675 #ifdef __BIG_ENDIAN_BITFIELD
3676 uint16_t evt_code; /* High order bits word 5 */
3677 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3678 #else /* __LITTLE_ENDIAN_BITFIELD */
3679 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3680 uint16_t evt_code; /* Low order bits word 5 */
3681 #endif
3682 } ASYNCSTAT_FIELDS;
3683 #define ASYNC_TEMP_WARN 0x100
3684 #define ASYNC_TEMP_SAFE 0x101
3685 #define ASYNC_STATUS_CN 0x102
3686
3687 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3688 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3689
3690 struct rcv_sli3 {
3691 #ifdef __BIG_ENDIAN_BITFIELD
3692 uint16_t ox_id;
3693 uint16_t seq_cnt;
3694
3695 uint16_t vpi;
3696 uint16_t word9Rsvd;
3697 #else /* __LITTLE_ENDIAN */
3698 uint16_t seq_cnt;
3699 uint16_t ox_id;
3700
3701 uint16_t word9Rsvd;
3702 uint16_t vpi;
3703 #endif
3704 uint32_t word10Rsvd;
3705 uint32_t acc_len; /* accumulated length */
3706 struct ulp_bde64 bde2;
3707 };
3708
3709 /* Structure used for a single HBQ entry */
3710 struct lpfc_hbq_entry {
3711 struct ulp_bde64 bde;
3712 uint32_t buffer_tag;
3713 };
3714
3715 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3716 typedef struct {
3717 struct lpfc_hbq_entry buff;
3718 uint32_t rsvd;
3719 uint32_t rsvd1;
3720 } QUE_XRI64_CX_FIELDS;
3721
3722 struct que_xri64cx_ext_fields {
3723 uint32_t iotag64_low;
3724 uint32_t iotag64_high;
3725 uint32_t ebde_count;
3726 uint32_t rsvd;
3727 struct lpfc_hbq_entry buff[5];
3728 };
3729
3730 struct sli3_bg_fields {
3731 uint32_t filler[6]; /* word 8-13 in IOCB */
3732 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3733 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3734 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
3735 #define BGS_BIDIR_BG_PROF_SHIFT 24
3736 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3737 #define BGS_BIDIR_ERR_COND_SHIFT 16
3738 #define BGS_BG_PROFILE_MASK 0x0000ff00
3739 #define BGS_BG_PROFILE_SHIFT 8
3740 #define BGS_INVALID_PROF_MASK 0x00000020
3741 #define BGS_INVALID_PROF_SHIFT 5
3742 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3743 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3744 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3745 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3746 #define BGS_REFTAG_ERR_MASK 0x00000004
3747 #define BGS_REFTAG_ERR_SHIFT 2
3748 #define BGS_APPTAG_ERR_MASK 0x00000002
3749 #define BGS_APPTAG_ERR_SHIFT 1
3750 #define BGS_GUARD_ERR_MASK 0x00000001
3751 #define BGS_GUARD_ERR_SHIFT 0
3752 uint32_t bgstat; /* word 15 - BlockGuard Status */
3753 };
3754
3755 static inline uint32_t
3756 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3757 {
3758 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3759 BGS_BIDIR_BG_PROF_SHIFT;
3760 }
3761
3762 static inline uint32_t
3763 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3764 {
3765 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3766 BGS_BIDIR_ERR_COND_SHIFT;
3767 }
3768
3769 static inline uint32_t
3770 lpfc_bgs_get_bg_prof(uint32_t bgstat)
3771 {
3772 return (bgstat & BGS_BG_PROFILE_MASK) >>
3773 BGS_BG_PROFILE_SHIFT;
3774 }
3775
3776 static inline uint32_t
3777 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3778 {
3779 return (bgstat & BGS_INVALID_PROF_MASK) >>
3780 BGS_INVALID_PROF_SHIFT;
3781 }
3782
3783 static inline uint32_t
3784 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3785 {
3786 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
3787 BGS_UNINIT_DIF_BLOCK_SHIFT;
3788 }
3789
3790 static inline uint32_t
3791 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3792 {
3793 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
3794 BGS_HI_WATER_MARK_PRESENT_SHIFT;
3795 }
3796
3797 static inline uint32_t
3798 lpfc_bgs_get_reftag_err(uint32_t bgstat)
3799 {
3800 return (bgstat & BGS_REFTAG_ERR_MASK) >>
3801 BGS_REFTAG_ERR_SHIFT;
3802 }
3803
3804 static inline uint32_t
3805 lpfc_bgs_get_apptag_err(uint32_t bgstat)
3806 {
3807 return (bgstat & BGS_APPTAG_ERR_MASK) >>
3808 BGS_APPTAG_ERR_SHIFT;
3809 }
3810
3811 static inline uint32_t
3812 lpfc_bgs_get_guard_err(uint32_t bgstat)
3813 {
3814 return (bgstat & BGS_GUARD_ERR_MASK) >>
3815 BGS_GUARD_ERR_SHIFT;
3816 }
3817
3818 #define LPFC_EXT_DATA_BDE_COUNT 3
3819 struct fcp_irw_ext {
3820 uint32_t io_tag64_low;
3821 uint32_t io_tag64_high;
3822 #ifdef __BIG_ENDIAN_BITFIELD
3823 uint8_t reserved1;
3824 uint8_t reserved2;
3825 uint8_t reserved3;
3826 uint8_t ebde_count;
3827 #else /* __LITTLE_ENDIAN */
3828 uint8_t ebde_count;
3829 uint8_t reserved3;
3830 uint8_t reserved2;
3831 uint8_t reserved1;
3832 #endif
3833 uint32_t reserved4;
3834 struct ulp_bde64 rbde; /* response bde */
3835 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3836 uint8_t icd[32]; /* immediate command data (32 bytes) */
3837 };
3838
3839 typedef struct _IOCB { /* IOCB structure */
3840 union {
3841 GENERIC_RSP grsp; /* Generic response */
3842 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3843 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3844 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3845 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3846 A_MXRI64 amxri; /* abort multiple xri command overlay */
3847 GET_RPI getrpi; /* GET_RPI template */
3848 FCPI_FIELDS fcpi; /* FCP Initiator template */
3849 FCPT_FIELDS fcpt; /* FCP target template */
3850
3851 /* SLI-2 structures */
3852
3853 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3854 * bde_64s */
3855 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3856 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3857 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3858 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3859 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3860 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
3861 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
3862 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
3863 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
3864 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
3865 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3866 } un;
3867 union {
3868 struct {
3869 #ifdef __BIG_ENDIAN_BITFIELD
3870 uint16_t ulpContext; /* High order bits word 6 */
3871 uint16_t ulpIoTag; /* Low order bits word 6 */
3872 #else /* __LITTLE_ENDIAN_BITFIELD */
3873 uint16_t ulpIoTag; /* Low order bits word 6 */
3874 uint16_t ulpContext; /* High order bits word 6 */
3875 #endif
3876 } t1;
3877 struct {
3878 #ifdef __BIG_ENDIAN_BITFIELD
3879 uint16_t ulpContext; /* High order bits word 6 */
3880 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3881 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3882 #else /* __LITTLE_ENDIAN_BITFIELD */
3883 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3884 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3885 uint16_t ulpContext; /* High order bits word 6 */
3886 #endif
3887 } t2;
3888 } un1;
3889 #define ulpContext un1.t1.ulpContext
3890 #define ulpIoTag un1.t1.ulpIoTag
3891 #define ulpIoTag0 un1.t2.ulpIoTag0
3892
3893 #ifdef __BIG_ENDIAN_BITFIELD
3894 uint32_t ulpTimeout:8;
3895 uint32_t ulpXS:1;
3896 uint32_t ulpFCP2Rcvy:1;
3897 uint32_t ulpPU:2;
3898 uint32_t ulpIr:1;
3899 uint32_t ulpClass:3;
3900 uint32_t ulpCommand:8;
3901 uint32_t ulpStatus:4;
3902 uint32_t ulpBdeCount:2;
3903 uint32_t ulpLe:1;
3904 uint32_t ulpOwner:1; /* Low order bit word 7 */
3905 #else /* __LITTLE_ENDIAN_BITFIELD */
3906 uint32_t ulpOwner:1; /* Low order bit word 7 */
3907 uint32_t ulpLe:1;
3908 uint32_t ulpBdeCount:2;
3909 uint32_t ulpStatus:4;
3910 uint32_t ulpCommand:8;
3911 uint32_t ulpClass:3;
3912 uint32_t ulpIr:1;
3913 uint32_t ulpPU:2;
3914 uint32_t ulpFCP2Rcvy:1;
3915 uint32_t ulpXS:1;
3916 uint32_t ulpTimeout:8;
3917 #endif
3918
3919 union {
3920 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3921
3922 /* words 8-31 used for que_xri_cx iocb */
3923 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
3924 struct fcp_irw_ext fcp_ext;
3925 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3926
3927 /* words 8-15 for BlockGuard */
3928 struct sli3_bg_fields sli3_bg;
3929 } unsli3;
3930
3931 #define ulpCt_h ulpXS
3932 #define ulpCt_l ulpFCP2Rcvy
3933
3934 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3935 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
3936 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
3937 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3938 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
3939 #define PARM_NPIV_DID 3
3940 #define CLASS1 0 /* Class 1 */
3941 #define CLASS2 1 /* Class 2 */
3942 #define CLASS3 2 /* Class 3 */
3943 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3944
3945 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3946 #define IOSTAT_FCP_RSP_ERROR 0x1
3947 #define IOSTAT_REMOTE_STOP 0x2
3948 #define IOSTAT_LOCAL_REJECT 0x3
3949 #define IOSTAT_NPORT_RJT 0x4
3950 #define IOSTAT_FABRIC_RJT 0x5
3951 #define IOSTAT_NPORT_BSY 0x6
3952 #define IOSTAT_FABRIC_BSY 0x7
3953 #define IOSTAT_INTERMED_RSP 0x8
3954 #define IOSTAT_LS_RJT 0x9
3955 #define IOSTAT_BA_RJT 0xA
3956 #define IOSTAT_RSVD1 0xB
3957 #define IOSTAT_RSVD2 0xC
3958 #define IOSTAT_RSVD3 0xD
3959 #define IOSTAT_RSVD4 0xE
3960 #define IOSTAT_NEED_BUFFER 0xF
3961 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3962 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3963 #define IOSTAT_CNT 0x11
3964
3965 } IOCB_t;
3966
3967
3968 #define SLI1_SLIM_SIZE (4 * 1024)
3969
3970 /* Up to 498 IOCBs will fit into 16k
3971 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3972 */
3973 #define SLI2_SLIM_SIZE (64 * 1024)
3974
3975 /* Maximum IOCBs that will fit in SLI2 slim */
3976 #define MAX_SLI2_IOCB 498
3977 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3978 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
3979 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
3980
3981 /* HBQ entries are 4 words each = 4k */
3982 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3983 lpfc_sli_hbq_count())
3984
3985 struct lpfc_sli2_slim {
3986 MAILBOX_t mbx;
3987 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
3988 PCB_t pcb;
3989 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3990 };
3991
3992 /*
3993 * This function checks PCI device to allow special handling for LC HBAs.
3994 *
3995 * Parameters:
3996 * device : struct pci_dev 's device field
3997 *
3998 * return 1 => TRUE
3999 * 0 => FALSE
4000 */
4001 static inline int
4002 lpfc_is_LC_HBA(unsigned short device)
4003 {
4004 if ((device == PCI_DEVICE_ID_TFLY) ||
4005 (device == PCI_DEVICE_ID_PFLY) ||
4006 (device == PCI_DEVICE_ID_LP101) ||
4007 (device == PCI_DEVICE_ID_BMID) ||
4008 (device == PCI_DEVICE_ID_BSMB) ||
4009 (device == PCI_DEVICE_ID_ZMID) ||
4010 (device == PCI_DEVICE_ID_ZSMB) ||
4011 (device == PCI_DEVICE_ID_SAT_MID) ||
4012 (device == PCI_DEVICE_ID_SAT_SMB) ||
4013 (device == PCI_DEVICE_ID_RFLY))
4014 return 1;
4015 else
4016 return 0;
4017 }
4018
4019 /*
4020 * Determine if an IOCB failed because of a link event or firmware reset.
4021 */
4022
4023 static inline int
4024 lpfc_error_lost_link(IOCB_t *iocbp)
4025 {
4026 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4027 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4028 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4029 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4030 }
4031
4032 #define MENLO_TRANSPORT_TYPE 0xfe
4033 #define MENLO_CONTEXT 0
4034 #define MENLO_PU 3
4035 #define MENLO_TIMEOUT 30
4036 #define SETVAR_MLOMNT 0x103107
4037 #define SETVAR_MLORST 0x103007
4038
4039 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
Linux with added FPC-III support