drivers/crypto/qat/qat_common/icp_qat_fw.h

   1 /*
   2   This file is provided under a dual BSD/GPLv2 license.  When using or
   3   redistributing this file, you may do so under either license.
   4
   5   GPL LICENSE SUMMARY
   6   Copyright(c) 2014 Intel Corporation.
   7   This program is free software; you can redistribute it and/or modify
   8   it under the terms of version 2 of the GNU General Public License as
   9   published by the Free Software Foundation.
  10
  11   This program is distributed in the hope that it will be useful, but
  12   WITHOUT ANY WARRANTY; without even the implied warranty of
  13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14   General Public License for more details.
  15
  16   Contact Information:
  17   qat-linux@intel.com
  18
  19   BSD LICENSE
  20   Copyright(c) 2014 Intel Corporation.
  21   Redistribution and use in source and binary forms, with or without
  22   modification, are permitted provided that the following conditions
  23   are met:
  24
  25     * Redistributions of source code must retain the above copyright
  26       notice, this list of conditions and the following disclaimer.
  27     * Redistributions in binary form must reproduce the above copyright
  28       notice, this list of conditions and the following disclaimer in
  29       the documentation and/or other materials provided with the
  30       distribution.
  31     * Neither the name of Intel Corporation nor the names of its
  32       contributors may be used to endorse or promote products derived
  33       from this software without specific prior written permission.
  34
  35   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  36   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  37   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  38   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  39   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  40   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  41   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  42   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  43   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  44   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  45   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  46 */
  47 #ifndef _ICP_QAT_FW_H_
  48 #define _ICP_QAT_FW_H_
  49 #include <linux/types.h>
  50 #include "icp_qat_hw.h"
  51
  52 #define QAT_FIELD_SET(flags, val, bitpos, mask) \
  53 { (flags) = (((flags) & (~((mask) << (bitpos)))) | \
  54                 (((val) & (mask)) << (bitpos))) ; }
  55
  56 #define QAT_FIELD_GET(flags, bitpos, mask) \
  57         (((flags) >> (bitpos)) & (mask))
  58
  59 #define ICP_QAT_FW_REQ_DEFAULT_SZ 128
  60 #define ICP_QAT_FW_RESP_DEFAULT_SZ 32
  61 #define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8
  62 #define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF
  63 #define ICP_QAT_FW_NUM_LONGWORDS_1 1
  64 #define ICP_QAT_FW_NUM_LONGWORDS_2 2
  65 #define ICP_QAT_FW_NUM_LONGWORDS_3 3
  66 #define ICP_QAT_FW_NUM_LONGWORDS_4 4
  67 #define ICP_QAT_FW_NUM_LONGWORDS_5 5
  68 #define ICP_QAT_FW_NUM_LONGWORDS_6 6
  69 #define ICP_QAT_FW_NUM_LONGWORDS_7 7
  70 #define ICP_QAT_FW_NUM_LONGWORDS_10 10
  71 #define ICP_QAT_FW_NUM_LONGWORDS_13 13
  72 #define ICP_QAT_FW_NULL_REQ_SERV_ID 1
  73
  74 enum icp_qat_fw_comn_resp_serv_id {
  75         ICP_QAT_FW_COMN_RESP_SERV_NULL,
  76         ICP_QAT_FW_COMN_RESP_SERV_CPM_FW,
  77         ICP_QAT_FW_COMN_RESP_SERV_DELIMITER
  78 };
  79
  80 enum icp_qat_fw_comn_request_id {
  81         ICP_QAT_FW_COMN_REQ_NULL = 0,
  82         ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3,
  83         ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4,
  84         ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7,
  85         ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9,
  86         ICP_QAT_FW_COMN_REQ_DELIMITER
  87 };
  88
  89 struct icp_qat_fw_comn_req_hdr_cd_pars {
  90         union {
  91                 struct {
  92                         uint64_t content_desc_addr;
  93                         uint16_t content_desc_resrvd1;
  94                         uint8_t content_desc_params_sz;
  95                         uint8_t content_desc_hdr_resrvd2;
  96                         uint32_t content_desc_resrvd3;
  97                 } s;
  98                 struct {
  99                         uint32_t serv_specif_fields[4];
 100                 } s1;
 101         } u;
 102 };
 103
 104 struct icp_qat_fw_comn_req_mid {
 105         uint64_t opaque_data;
 106         uint64_t src_data_addr;
 107         uint64_t dest_data_addr;
 108         uint32_t src_length;
 109         uint32_t dst_length;
 110 };
 111
 112 struct icp_qat_fw_comn_req_cd_ctrl {
 113         uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];
 114 };
 115
 116 struct icp_qat_fw_comn_req_hdr {
 117         uint8_t resrvd1;
 118         uint8_t service_cmd_id;
 119         uint8_t service_type;
 120         uint8_t hdr_flags;
 121         uint16_t serv_specif_flags;
 122         uint16_t comn_req_flags;
 123 };
 124
 125 struct icp_qat_fw_comn_req_rqpars {
 126         uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];
 127 };
 128
 129 struct icp_qat_fw_comn_req {
 130         struct icp_qat_fw_comn_req_hdr comn_hdr;
 131         struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
 132         struct icp_qat_fw_comn_req_mid comn_mid;
 133         struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
 134         struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
 135 };
 136
 137 struct icp_qat_fw_comn_error {
 138         uint8_t xlat_err_code;
 139         uint8_t cmp_err_code;
 140 };
 141
 142 struct icp_qat_fw_comn_resp_hdr {
 143         uint8_t resrvd1;
 144         uint8_t service_id;
 145         uint8_t response_type;
 146         uint8_t hdr_flags;
 147         struct icp_qat_fw_comn_error comn_error;
 148         uint8_t comn_status;
 149         uint8_t cmd_id;
 150 };
 151
 152 struct icp_qat_fw_comn_resp {
 153         struct icp_qat_fw_comn_resp_hdr comn_hdr;
 154         uint64_t opaque_data;
 155         uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
 156 };
 157
 158 #define ICP_QAT_FW_COMN_REQ_FLAG_SET 1
 159 #define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0
 160 #define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
 161 #define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
 162 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
 163
 164 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
 165         icp_qat_fw_comn_req_hdr_t.service_type
 166
 167 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \
 168         icp_qat_fw_comn_req_hdr_t.service_type = val
 169
 170 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \
 171         icp_qat_fw_comn_req_hdr_t.service_cmd_id
 172
 173 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \
 174         icp_qat_fw_comn_req_hdr_t.service_cmd_id = val
 175
 176 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
 177         ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
 178
 179 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
 180         ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
 181
 182 #define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \
 183         QAT_FIELD_GET(hdr_flags, \
 184         ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
 185         ICP_QAT_FW_COMN_VALID_FLAG_MASK)
 186
 187 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \
 188         (hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK)
 189
 190 #define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \
 191         QAT_FIELD_SET((hdr_t.hdr_flags), (val), \
 192         ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
 193         ICP_QAT_FW_COMN_VALID_FLAG_MASK)
 194
 195 #define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \
 196         (((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \
 197          ICP_QAT_FW_COMN_VALID_FLAG_BITPOS)
 198
 199 #define QAT_COMN_PTR_TYPE_BITPOS 0
 200 #define QAT_COMN_PTR_TYPE_MASK 0x1
 201 #define QAT_COMN_CD_FLD_TYPE_BITPOS 1
 202 #define QAT_COMN_CD_FLD_TYPE_MASK 0x1
 203 #define QAT_COMN_PTR_TYPE_FLAT 0x0
 204 #define QAT_COMN_PTR_TYPE_SGL 0x1
 205 #define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0
 206 #define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1
 207
 208 #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \
 209         ((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \
 210          | (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS))
 211
 212 #define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \
 213         QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK)
 214
 215 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \
 216         QAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \
 217                         QAT_COMN_CD_FLD_TYPE_MASK)
 218
 219 #define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \
 220         QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \
 221                         QAT_COMN_PTR_TYPE_MASK)
 222
 223 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \
 224         QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \
 225                         QAT_COMN_CD_FLD_TYPE_MASK)
 226
 227 #define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4
 228 #define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0
 229 #define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0
 230 #define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F
 231
 232 #define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \
 233         ((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
 234         >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
 235
 236 #define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
 237         { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
 238         & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
 239         ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
 240          & ICP_QAT_FW_COMN_NEXT_ID_MASK)); }
 241
 242 #define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \
 243         (((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK)
 244
 245 #define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \
 246         { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
 247         & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
 248         ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
 249
 250 #define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
 251 #define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
 252 #define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
 253 #define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
 254 #define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
 255 #define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
 256 #define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
 257 #define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
 258 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
 259 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
 260
 261 #define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \
 262         ((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \
 263         QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \
 264         (((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \
 265         QAT_COMN_RESP_CMP_STATUS_BITPOS) | \
 266         (((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \
 267         QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \
 268         (((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \
 269         QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS))
 270
 271 #define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
 272         QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
 273         QAT_COMN_RESP_CRYPTO_STATUS_MASK)
 274
 275 #define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
 276         QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
 277         QAT_COMN_RESP_CMP_STATUS_MASK)
 278
 279 #define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \
 280         QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
 281         QAT_COMN_RESP_XLAT_STATUS_MASK)
 282
 283 #define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
 284         QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
 285         QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
 286
 287 #define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
 288 #define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
 289 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
 290 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1
 291 #define ERR_CODE_NO_ERROR 0
 292 #define ERR_CODE_INVALID_BLOCK_TYPE -1
 293 #define ERR_CODE_NO_MATCH_ONES_COMP -2
 294 #define ERR_CODE_TOO_MANY_LEN_OR_DIS -3
 295 #define ERR_CODE_INCOMPLETE_LEN -4
 296 #define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5
 297 #define ERR_CODE_RPT_GT_SPEC_LEN -6
 298 #define ERR_CODE_INV_LIT_LEN_CODE_LEN -7
 299 #define ERR_CODE_INV_DIS_CODE_LEN -8
 300 #define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9
 301 #define ERR_CODE_DIS_TOO_FAR_BACK -10
 302 #define ERR_CODE_OVERFLOW_ERROR -11
 303 #define ERR_CODE_SOFT_ERROR -12
 304 #define ERR_CODE_FATAL_ERROR -13
 305 #define ERR_CODE_SSM_ERROR -14
 306 #define ERR_CODE_ENDPOINT_ERROR -15
 307
 308 enum icp_qat_fw_slice {
 309         ICP_QAT_FW_SLICE_NULL = 0,
 310         ICP_QAT_FW_SLICE_CIPHER = 1,
 311         ICP_QAT_FW_SLICE_AUTH = 2,
 312         ICP_QAT_FW_SLICE_DRAM_RD = 3,
 313         ICP_QAT_FW_SLICE_DRAM_WR = 4,
 314         ICP_QAT_FW_SLICE_COMP = 5,
 315         ICP_QAT_FW_SLICE_XLAT = 6,
 316         ICP_QAT_FW_SLICE_DELIMITER
 317 };
 318 #endif