drivers/gpu/drm/i915/gt/intel_ring.h

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2019 Intel Corporation
   5  */
   6
   7 #ifndef INTEL_RING_H
   8 #define INTEL_RING_H
   9
  10 #include "i915_gem.h" /* GEM_BUG_ON */
  11 #include "i915_request.h"
  12 #include "intel_ring_types.h"
  13
  14 struct intel_engine_cs;
  15
  16 struct intel_ring *
  17 intel_engine_create_ring(struct intel_engine_cs *engine, int size);
  18
  19 u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords);
  20 int intel_ring_cacheline_align(struct i915_request *rq);
  21
  22 unsigned int intel_ring_update_space(struct intel_ring *ring);
  23
  24 int intel_ring_pin(struct intel_ring *ring);
  25 void intel_ring_unpin(struct intel_ring *ring);
  26 void intel_ring_reset(struct intel_ring *ring, u32 tail);
  27
  28 void intel_ring_free(struct kref *ref);
  29
  30 static inline struct intel_ring *intel_ring_get(struct intel_ring *ring)
  31 {
  32         kref_get(&ring->ref);
  33         return ring;
  34 }
  35
  36 static inline void intel_ring_put(struct intel_ring *ring)
  37 {
  38         kref_put(&ring->ref, intel_ring_free);
  39 }
  40
  41 static inline void intel_ring_advance(struct i915_request *rq, u32 *cs)
  42 {
  43         /* Dummy function.
  44          *
  45          * This serves as a placeholder in the code so that the reader
  46          * can compare against the preceding intel_ring_begin() and
  47          * check that the number of dwords emitted matches the space
  48          * reserved for the command packet (i.e. the value passed to
  49          * intel_ring_begin()).
  50          */
  51         GEM_BUG_ON((rq->ring->vaddr + rq->ring->emit) != cs);
  52 }
  53
  54 static inline u32 intel_ring_wrap(const struct intel_ring *ring, u32 pos)
  55 {
  56         return pos & (ring->size - 1);
  57 }
  58
  59 static inline bool
  60 intel_ring_offset_valid(const struct intel_ring *ring,
  61                         unsigned int pos)
  62 {
  63         if (pos & -ring->size) /* must be strictly within the ring */
  64                 return false;
  65
  66         if (!IS_ALIGNED(pos, 8)) /* must be qword aligned */
  67                 return false;
  68
  69         return true;
  70 }
  71
  72 static inline u32 intel_ring_offset(const struct i915_request *rq, void *addr)
  73 {
  74         /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
  75         u32 offset = addr - rq->ring->vaddr;
  76         GEM_BUG_ON(offset > rq->ring->size);
  77         return intel_ring_wrap(rq->ring, offset);
  78 }
  79
  80 static inline void
  81 assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail)
  82 {
  83         GEM_BUG_ON(!intel_ring_offset_valid(ring, tail));
  84
  85         /*
  86          * "Ring Buffer Use"
  87          *      Gen2 BSpec "1. Programming Environment" / 1.4.4.6
  88          *      Gen3 BSpec "1c Memory Interface Functions" / 2.3.4.5
  89          *      Gen4+ BSpec "1c Memory Interface and Command Stream" / 5.3.4.5
  90          * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
  91          * same cacheline, the Head Pointer must not be greater than the Tail
  92          * Pointer."
  93          *
  94          * We use ring->head as the last known location of the actual RING_HEAD,
  95          * it may have advanced but in the worst case it is equally the same
  96          * as ring->head and so we should never program RING_TAIL to advance
  97          * into the same cacheline as ring->head.
  98          */
  99 #define cacheline(a) round_down(a, CACHELINE_BYTES)
 100         GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) &&
 101                    tail < ring->head);
 102 #undef cacheline
 103 }
 104
 105 static inline unsigned int
 106 intel_ring_set_tail(struct intel_ring *ring, unsigned int tail)
 107 {
 108         /* Whilst writes to the tail are strictly order, there is no
 109          * serialisation between readers and the writers. The tail may be
 110          * read by i915_request_retire() just as it is being updated
 111          * by execlists, as although the breadcrumb is complete, the context
 112          * switch hasn't been seen.
 113          */
 114         assert_ring_tail_valid(ring, tail);
 115         ring->tail = tail;
 116         return tail;
 117 }
 118
 119 static inline unsigned int
 120 __intel_ring_space(unsigned int head, unsigned int tail, unsigned int size)
 121 {
 122         /*
 123          * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
 124          * same cacheline, the Head Pointer must not be greater than the Tail
 125          * Pointer."
 126          */
 127         GEM_BUG_ON(!is_power_of_2(size));
 128         return (head - tail - CACHELINE_BYTES) & (size - 1);
 129 }
 130
 131 #endif /* INTEL_RING_H */