drivers/gpu/drm/i915/gvt/mmio_context.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eddie Dong <eddie.dong@intel.com>
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *
  27  * Contributors:
  28  *    Zhi Wang <zhi.a.wang@intel.com>
  29  *    Changbin Du <changbin.du@intel.com>
  30  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Bing Niu <bing.niu@intel.com>
  33  *
  34  */
  35
  36 #include "i915_drv.h"
  37 #include "gt/intel_context.h"
  38 #include "gt/intel_ring.h"
  39 #include "gvt.h"
  40 #include "trace.h"
  41
  42 #define GEN9_MOCS_SIZE          64
  43
  44 /* Raw offset is appened to each line for convenience. */
  45 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
  46         {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
  47         {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
  48         {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
  49         {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
  50         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
  51         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
  52         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
  53         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
  54         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
  55         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
  56         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
  57         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
  58         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
  59         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
  60         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
  61         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
  62         {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
  63         {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
  64         {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
  65         {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
  66         {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
  67         {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
  68
  69         {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
  70         {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
  71         {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
  72         {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
  73         {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
  74         {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
  75 };
  76
  77 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
  78         {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
  79         {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
  80         {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
  81         {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
  82         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
  83         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
  84         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
  85         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
  86         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
  87         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
  88         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
  89         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
  90         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
  91         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
  92         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
  93         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
  94         {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
  95         {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
  96         {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
  97         {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
  98         {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
  99         {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
 100
 101         {RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
 102         {RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
 103         {RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
 104         {RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
 105         {RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
 106         {RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
 107         {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
 108         {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
 109         {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
 110         {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
 111         {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
 112         {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
 113         {RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */
 114         {RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */
 115         {RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */
 116         {RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */
 117         {RCS0, TRVADR, 0, true}, /* 0x4df0 */
 118         {RCS0, TRTTE, 0, true}, /* 0x4df4 */
 119         {RCS0, _MMIO(0x4dfc), 0, true},
 120
 121         {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
 122         {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
 123         {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
 124         {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
 125         {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
 126
 127         {VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
 128
 129         {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
 130
 131         {RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
 132         {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
 133         {RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
 134         {RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
 135
 136         {RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
 137         {RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
 138         {RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */
 139
 140         {RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
 141         {RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
 142         {RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
 143         {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
 144 };
 145
 146 static struct {
 147         bool initialized;
 148         u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
 149         u32 l3cc_table[GEN9_MOCS_SIZE / 2];
 150 } gen9_render_mocs;
 151
 152 static u32 gen9_mocs_mmio_offset_list[] = {
 153         [RCS0]  = 0xc800,
 154         [VCS0]  = 0xc900,
 155         [VCS1]  = 0xca00,
 156         [BCS0]  = 0xcc00,
 157         [VECS0] = 0xcb00,
 158 };
 159
 160 static void load_render_mocs(struct drm_i915_private *dev_priv)
 161 {
 162         struct intel_gvt *gvt = dev_priv->gvt;
 163         i915_reg_t offset;
 164         u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt;
 165         u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list;
 166         int ring_id, i;
 167
 168         /* Platform doesn't have mocs mmios. */
 169         if (!regs)
 170                 return;
 171
 172         for (ring_id = 0; ring_id < cnt; ring_id++) {
 173                 if (!HAS_ENGINE(dev_priv, ring_id))
 174                         continue;
 175                 offset.reg = regs[ring_id];
 176                 for (i = 0; i < GEN9_MOCS_SIZE; i++) {
 177                         gen9_render_mocs.control_table[ring_id][i] =
 178                                 I915_READ_FW(offset);
 179                         offset.reg += 4;
 180                 }
 181         }
 182
 183         offset.reg = 0xb020;
 184         for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
 185                 gen9_render_mocs.l3cc_table[i] =
 186                         I915_READ_FW(offset);
 187                 offset.reg += 4;
 188         }
 189         gen9_render_mocs.initialized = true;
 190 }
 191
 192 static int
 193 restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu,
 194                                  struct i915_request *req)
 195 {
 196         u32 *cs;
 197         int ret;
 198         struct engine_mmio *mmio;
 199         struct intel_gvt *gvt = vgpu->gvt;
 200         int ring_id = req->engine->id;
 201         int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id];
 202
 203         if (count == 0)
 204                 return 0;
 205
 206         ret = req->engine->emit_flush(req, EMIT_BARRIER);
 207         if (ret)
 208                 return ret;
 209
 210         cs = intel_ring_begin(req, count * 2 + 2);
 211         if (IS_ERR(cs))
 212                 return PTR_ERR(cs);
 213
 214         *cs++ = MI_LOAD_REGISTER_IMM(count);
 215         for (mmio = gvt->engine_mmio_list.mmio;
 216              i915_mmio_reg_valid(mmio->reg); mmio++) {
 217                 if (mmio->ring_id != ring_id ||
 218                     !mmio->in_context)
 219                         continue;
 220
 221                 *cs++ = i915_mmio_reg_offset(mmio->reg);
 222                 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) |
 223                                 (mmio->mask << 16);
 224                 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
 225                               *(cs-2), *(cs-1), vgpu->id, ring_id);
 226         }
 227
 228         *cs++ = MI_NOOP;
 229         intel_ring_advance(req, cs);
 230
 231         ret = req->engine->emit_flush(req, EMIT_BARRIER);
 232         if (ret)
 233                 return ret;
 234
 235         return 0;
 236 }
 237
 238 static int
 239 restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu,
 240                                         struct i915_request *req)
 241 {
 242         unsigned int index;
 243         u32 *cs;
 244
 245         cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2);
 246         if (IS_ERR(cs))
 247                 return PTR_ERR(cs);
 248
 249         *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);
 250
 251         for (index = 0; index < GEN9_MOCS_SIZE; index++) {
 252                 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));
 253                 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));
 254                 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
 255                               *(cs-2), *(cs-1), vgpu->id, req->engine->id);
 256
 257         }
 258
 259         *cs++ = MI_NOOP;
 260         intel_ring_advance(req, cs);
 261
 262         return 0;
 263 }
 264
 265 static int
 266 restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu,
 267                                      struct i915_request *req)
 268 {
 269         unsigned int index;
 270         u32 *cs;
 271
 272         cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2);
 273         if (IS_ERR(cs))
 274                 return PTR_ERR(cs);
 275
 276         *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);
 277
 278         for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) {
 279                 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));
 280                 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));
 281                 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
 282                               *(cs-2), *(cs-1), vgpu->id, req->engine->id);
 283
 284         }
 285
 286         *cs++ = MI_NOOP;
 287         intel_ring_advance(req, cs);
 288
 289         return 0;
 290 }
 291
 292 /*
 293  * Use lri command to initialize the mmio which is in context state image for
 294  * inhibit context, it contains tracked engine mmio, render_mocs and
 295  * render_mocs_l3cc.
 296  */
 297 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
 298                                        struct i915_request *req)
 299 {
 300         int ret;
 301         u32 *cs;
 302
 303         cs = intel_ring_begin(req, 2);
 304         if (IS_ERR(cs))
 305                 return PTR_ERR(cs);
 306
 307         *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
 308         *cs++ = MI_NOOP;
 309         intel_ring_advance(req, cs);
 310
 311         ret = restore_context_mmio_for_inhibit(vgpu, req);
 312         if (ret)
 313                 goto out;
 314
 315         /* no MOCS register in context except render engine */
 316         if (req->engine->id != RCS0)
 317                 goto out;
 318
 319         ret = restore_render_mocs_control_for_inhibit(vgpu, req);
 320         if (ret)
 321                 goto out;
 322
 323         ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req);
 324         if (ret)
 325                 goto out;
 326
 327 out:
 328         cs = intel_ring_begin(req, 2);
 329         if (IS_ERR(cs))
 330                 return PTR_ERR(cs);
 331
 332         *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
 333         *cs++ = MI_NOOP;
 334         intel_ring_advance(req, cs);
 335
 336         return ret;
 337 }
 338
 339 static u32 gen8_tlb_mmio_offset_list[] = {
 340         [RCS0]  = 0x4260,
 341         [VCS0]  = 0x4264,
 342         [VCS1]  = 0x4268,
 343         [BCS0]  = 0x426c,
 344         [VECS0] = 0x4270,
 345 };
 346
 347 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
 348 {
 349         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 350         struct intel_uncore *uncore = &dev_priv->uncore;
 351         struct intel_vgpu_submission *s = &vgpu->submission;
 352         u32 *regs = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list;
 353         u32 cnt = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list_cnt;
 354         enum forcewake_domains fw;
 355         i915_reg_t reg;
 356
 357         if (!regs)
 358                 return;
 359
 360         if (WARN_ON(ring_id >= cnt))
 361                 return;
 362
 363         if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
 364                 return;
 365
 366         reg = _MMIO(regs[ring_id]);
 367
 368         /* WaForceWakeRenderDuringMmioTLBInvalidate:skl
 369          * we need to put a forcewake when invalidating RCS TLB caches,
 370          * otherwise device can go to RC6 state and interrupt invalidation
 371          * process
 372          */
 373         fw = intel_uncore_forcewake_for_reg(uncore, reg,
 374                                             FW_REG_READ | FW_REG_WRITE);
 375         if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9)
 376                 fw |= FORCEWAKE_RENDER;
 377
 378         intel_uncore_forcewake_get(uncore, fw);
 379
 380         intel_uncore_write_fw(uncore, reg, 0x1);
 381
 382         if (wait_for_atomic((intel_uncore_read_fw(uncore, reg) == 0), 50))
 383                 gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
 384         else
 385                 vgpu_vreg_t(vgpu, reg) = 0;
 386
 387         intel_uncore_forcewake_put(uncore, fw);
 388
 389         gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
 390 }
 391
 392 static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
 393                         int ring_id)
 394 {
 395         struct drm_i915_private *dev_priv;
 396         i915_reg_t offset, l3_offset;
 397         u32 old_v, new_v;
 398
 399         u32 regs[] = {
 400                 [RCS0]  = 0xc800,
 401                 [VCS0]  = 0xc900,
 402                 [VCS1]  = 0xca00,
 403                 [BCS0]  = 0xcc00,
 404                 [VECS0] = 0xcb00,
 405         };
 406         int i;
 407
 408         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
 409         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
 410                 return;
 411
 412         if (ring_id == RCS0 && IS_GEN(dev_priv, 9))
 413                 return;
 414
 415         if (!pre && !gen9_render_mocs.initialized)
 416                 load_render_mocs(dev_priv);
 417
 418         offset.reg = regs[ring_id];
 419         for (i = 0; i < GEN9_MOCS_SIZE; i++) {
 420                 if (pre)
 421                         old_v = vgpu_vreg_t(pre, offset);
 422                 else
 423                         old_v = gen9_render_mocs.control_table[ring_id][i];
 424                 if (next)
 425                         new_v = vgpu_vreg_t(next, offset);
 426                 else
 427                         new_v = gen9_render_mocs.control_table[ring_id][i];
 428
 429                 if (old_v != new_v)
 430                         I915_WRITE_FW(offset, new_v);
 431
 432                 offset.reg += 4;
 433         }
 434
 435         if (ring_id == RCS0) {
 436                 l3_offset.reg = 0xb020;
 437                 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
 438                         if (pre)
 439                                 old_v = vgpu_vreg_t(pre, l3_offset);
 440                         else
 441                                 old_v = gen9_render_mocs.l3cc_table[i];
 442                         if (next)
 443                                 new_v = vgpu_vreg_t(next, l3_offset);
 444                         else
 445                                 new_v = gen9_render_mocs.l3cc_table[i];
 446
 447                         if (old_v != new_v)
 448                                 I915_WRITE_FW(l3_offset, new_v);
 449
 450                         l3_offset.reg += 4;
 451                 }
 452         }
 453 }
 454
 455 #define CTX_CONTEXT_CONTROL_VAL 0x03
 456
 457 bool is_inhibit_context(struct intel_context *ce)
 458 {
 459         const u32 *reg_state = ce->lrc_reg_state;
 460         u32 inhibit_mask =
 461                 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
 462
 463         return inhibit_mask ==
 464                 (reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask);
 465 }
 466
 467 /* Switch ring mmio values (context). */
 468 static void switch_mmio(struct intel_vgpu *pre,
 469                         struct intel_vgpu *next,
 470                         int ring_id)
 471 {
 472         struct drm_i915_private *dev_priv;
 473         struct intel_vgpu_submission *s;
 474         struct engine_mmio *mmio;
 475         u32 old_v, new_v;
 476
 477         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
 478         if (INTEL_GEN(dev_priv) >= 9)
 479                 switch_mocs(pre, next, ring_id);
 480
 481         for (mmio = dev_priv->gvt->engine_mmio_list.mmio;
 482              i915_mmio_reg_valid(mmio->reg); mmio++) {
 483                 if (mmio->ring_id != ring_id)
 484                         continue;
 485                 /*
 486                  * No need to do save or restore of the mmio which is in context
 487                  * state image on gen9, it's initialized by lri command and
 488                  * save or restore with context together.
 489                  */
 490                 if (IS_GEN(dev_priv, 9) && mmio->in_context)
 491                         continue;
 492
 493                 // save
 494                 if (pre) {
 495                         vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg);
 496                         if (mmio->mask)
 497                                 vgpu_vreg_t(pre, mmio->reg) &=
 498                                                 ~(mmio->mask << 16);
 499                         old_v = vgpu_vreg_t(pre, mmio->reg);
 500                 } else
 501                         old_v = mmio->value = I915_READ_FW(mmio->reg);
 502
 503                 // restore
 504                 if (next) {
 505                         s = &next->submission;
 506                         /*
 507                          * No need to restore the mmio which is in context state
 508                          * image if it's not inhibit context, it will restore
 509                          * itself.
 510                          */
 511                         if (mmio->in_context &&
 512                             !is_inhibit_context(s->shadow[ring_id]))
 513                                 continue;
 514
 515                         if (mmio->mask)
 516                                 new_v = vgpu_vreg_t(next, mmio->reg) |
 517                                                         (mmio->mask << 16);
 518                         else
 519                                 new_v = vgpu_vreg_t(next, mmio->reg);
 520                 } else {
 521                         if (mmio->in_context)
 522                                 continue;
 523                         if (mmio->mask)
 524                                 new_v = mmio->value | (mmio->mask << 16);
 525                         else
 526                                 new_v = mmio->value;
 527                 }
 528
 529                 I915_WRITE_FW(mmio->reg, new_v);
 530
 531                 trace_render_mmio(pre ? pre->id : 0,
 532                                   next ? next->id : 0,
 533                                   "switch",
 534                                   i915_mmio_reg_offset(mmio->reg),
 535                                   old_v, new_v);
 536         }
 537
 538         if (next)
 539                 handle_tlb_pending_event(next, ring_id);
 540 }
 541
 542 /**
 543  * intel_gvt_switch_render_mmio - switch mmio context of specific engine
 544  * @pre: the last vGPU that own the engine
 545  * @next: the vGPU to switch to
 546  * @ring_id: specify the engine
 547  *
 548  * If pre is null indicates that host own the engine. If next is null
 549  * indicates that we are switching to host workload.
 550  */
 551 void intel_gvt_switch_mmio(struct intel_vgpu *pre,
 552                            struct intel_vgpu *next, int ring_id)
 553 {
 554         struct drm_i915_private *dev_priv;
 555
 556         if (WARN_ON(!pre && !next))
 557                 return;
 558
 559         gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
 560                        pre ? "vGPU" : "host", next ? "vGPU" : "HOST");
 561
 562         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
 563
 564         /**
 565          * We are using raw mmio access wrapper to improve the
 566          * performace for batch mmio read/write, so we need
 567          * handle forcewake mannually.
 568          */
 569         intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
 570         switch_mmio(pre, next, ring_id);
 571         intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
 572 }
 573
 574 /**
 575  * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
 576  * @gvt: GVT device
 577  *
 578  */
 579 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
 580 {
 581         struct engine_mmio *mmio;
 582
 583         if (INTEL_GEN(gvt->dev_priv) >= 9) {
 584                 gvt->engine_mmio_list.mmio = gen9_engine_mmio_list;
 585                 gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list;
 586                 gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list);
 587                 gvt->engine_mmio_list.mocs_mmio_offset_list = gen9_mocs_mmio_offset_list;
 588                 gvt->engine_mmio_list.mocs_mmio_offset_list_cnt = ARRAY_SIZE(gen9_mocs_mmio_offset_list);
 589         } else {
 590                 gvt->engine_mmio_list.mmio = gen8_engine_mmio_list;
 591                 gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list;
 592                 gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list);
 593         }
 594
 595         for (mmio = gvt->engine_mmio_list.mmio;
 596              i915_mmio_reg_valid(mmio->reg); mmio++) {
 597                 if (mmio->in_context) {
 598                         gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++;
 599                         intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg);
 600                 }
 601         }
 602 }