drivers/gpu/drm/i915/i915_reg.h

   1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   2  * All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #ifndef _I915_REG_H_
  26 #define _I915_REG_H_
  27
  28 #include <linux/bitfield.h>
  29 #include <linux/bits.h>
  30
  31 /**
  32  * DOC: The i915 register macro definition style guide
  33  *
  34  * Follow the style described here for new macros, and while changing existing
  35  * macros. Do **not** mass change existing definitions just to update the style.
  36  *
  37  * Layout
  38  * ~~~~~~
  39  *
  40  * Keep helper macros near the top. For example, _PIPE() and friends.
  41  *
  42  * Prefix macros that generally should not be used outside of this file with
  43  * underscore '_'. For example, _PIPE() and friends, single instances of
  44  * registers that are defined solely for the use by function-like macros.
  45  *
  46  * Avoid using the underscore prefixed macros outside of this file. There are
  47  * exceptions, but keep them to a minimum.
  48  *
  49  * There are two basic types of register definitions: Single registers and
  50  * register groups. Register groups are registers which have two or more
  51  * instances, for example one per pipe, port, transcoder, etc. Register groups
  52  * should be defined using function-like macros.
  53  *
  54  * For single registers, define the register offset first, followed by register
  55  * contents.
  56  *
  57  * For register groups, define the register instance offsets first, prefixed
  58  * with underscore, followed by a function-like macro choosing the right
  59  * instance based on the parameter, followed by register contents.
  60  *
  61  * Define the register contents (i.e. bit and bit field macros) from most
  62  * significant to least significant bit. Indent the register content macros
  63  * using two extra spaces between ``#define`` and the macro name.
  64  *
  65  * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
  66  * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
  67  * shifted in place, so they can be directly OR'd together. For convenience,
  68  * function-like macros may be used to define bit fields, but do note that the
  69  * macros may be needed to read as well as write the register contents.
  70  *
  71  * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
  72  *
  73  * Group the register and its contents together without blank lines, separate
  74  * from other registers and their contents with one blank line.
  75  *
  76  * Indent macro values from macro names using TABs. Align values vertically. Use
  77  * braces in macro values as needed to avoid unintended precedence after macro
  78  * substitution. Use spaces in macro values according to kernel coding
  79  * style. Use lower case in hexadecimal values.
  80  *
  81  * Naming
  82  * ~~~~~~
  83  *
  84  * Try to name registers according to the specs. If the register name changes in
  85  * the specs from platform to another, stick to the original name.
  86  *
  87  * Try to re-use existing register macro definitions. Only add new macros for
  88  * new register offsets, or when the register contents have changed enough to
  89  * warrant a full redefinition.
  90  *
  91  * When a register macro changes for a new platform, prefix the new macro using
  92  * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
  93  * prefix signifies the start platform/generation using the register.
  94  *
  95  * When a bit (field) macro changes or gets added for a new platform, while
  96  * retaining the existing register macro, add a platform acronym or generation
  97  * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
  98  *
  99  * Examples
 100  * ~~~~~~~~
 101  *
 102  * (Note that the values in the example are indented using spaces instead of
 103  * TABs to avoid misalignment in generated documentation. Use TABs in the
 104  * definitions.)::
 105  *
 106  *  #define _FOO_A                      0xf000
 107  *  #define _FOO_B                      0xf001
 108  *  #define FOO(pipe)                   _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
 109  *  #define   FOO_ENABLE                REG_BIT(31)
 110  *  #define   FOO_MODE_MASK             REG_GENMASK(19, 16)
 111  *  #define   FOO_MODE_BAR              REG_FIELD_PREP(FOO_MODE_MASK, 0)
 112  *  #define   FOO_MODE_BAZ              REG_FIELD_PREP(FOO_MODE_MASK, 1)
 113  *  #define   FOO_MODE_QUX_SNB          REG_FIELD_PREP(FOO_MODE_MASK, 2)
 114  *
 115  *  #define BAR                         _MMIO(0xb000)
 116  *  #define GEN8_BAR                    _MMIO(0xb888)
 117  */
 118
 119 /**
 120  * REG_BIT() - Prepare a u32 bit value
 121  * @__n: 0-based bit number
 122  *
 123  * Local wrapper for BIT() to force u32, with compile time checks.
 124  *
 125  * @return: Value with bit @__n set.
 126  */
 127 #define REG_BIT(__n)                                                    \
 128         ((u32)(BIT(__n) +                                               \
 129                BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&         \
 130                                  ((__n) < 0 || (__n) > 31))))
 131
 132 /**
 133  * REG_GENMASK() - Prepare a continuous u32 bitmask
 134  * @__high: 0-based high bit
 135  * @__low: 0-based low bit
 136  *
 137  * Local wrapper for GENMASK() to force u32, with compile time checks.
 138  *
 139  * @return: Continuous bitmask from @__high to @__low, inclusive.
 140  */
 141 #define REG_GENMASK(__high, __low)                                      \
 142         ((u32)(GENMASK(__high, __low) +                                 \
 143                BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&      \
 144                                  __is_constexpr(__low) &&               \
 145                                  ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
 146
 147 /*
 148  * Local integer constant expression version of is_power_of_2().
 149  */
 150 #define IS_POWER_OF_2(__x)              ((__x) && (((__x) & ((__x) - 1)) == 0))
 151
 152 /**
 153  * REG_FIELD_PREP() - Prepare a u32 bitfield value
 154  * @__mask: shifted mask defining the field's length and position
 155  * @__val: value to put in the field
 156  *
 157  * Local copy of FIELD_PREP() to generate an integer constant expression, force
 158  * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
 159  *
 160  * @return: @__val masked and shifted into the field defined by @__mask.
 161  */
 162 #define REG_FIELD_PREP(__mask, __val)                                           \
 163         ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +     \
 164                BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +             \
 165                BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) +         \
 166                BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
 167                BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
 168
 169 /**
 170  * REG_FIELD_GET() - Extract a u32 bitfield value
 171  * @__mask: shifted mask defining the field's length and position
 172  * @__val: value to extract the bitfield value from
 173  *
 174  * Local wrapper for FIELD_GET() to force u32 and for consistency with
 175  * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
 176  *
 177  * @return: Masked and shifted value of the field defined by @__mask in @__val.
 178  */
 179 #define REG_FIELD_GET(__mask, __val)    ((u32)FIELD_GET(__mask, __val))
 180
 181 typedef struct {
 182         u32 reg;
 183 } i915_reg_t;
 184
 185 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
 186
 187 #define INVALID_MMIO_REG _MMIO(0)
 188
 189 static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
 190 {
 191         return reg.reg;
 192 }
 193
 194 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
 195 {
 196         return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
 197 }
 198
 199 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 200 {
 201         return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
 202 }
 203
 204 #define VLV_DISPLAY_BASE                0x180000
 205 #define VLV_MIPI_BASE                   VLV_DISPLAY_BASE
 206 #define BXT_MIPI_BASE                   0x60000
 207
 208 #define DISPLAY_MMIO_BASE(dev_priv)     (INTEL_INFO(dev_priv)->display_mmio_offset)
 209
 210 /*
 211  * Given the first two numbers __a and __b of arbitrarily many evenly spaced
 212  * numbers, pick the 0-based __index'th value.
 213  *
 214  * Always prefer this over _PICK() if the numbers are evenly spaced.
 215  */
 216 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
 217
 218 /*
 219  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
 220  *
 221  * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
 222  */
 223 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
 224
 225 /*
 226  * Named helper wrappers around _PICK_EVEN() and _PICK().
 227  */
 228 #define _PIPE(pipe, a, b)               _PICK_EVEN(pipe, a, b)
 229 #define _PLANE(plane, a, b)             _PICK_EVEN(plane, a, b)
 230 #define _TRANS(tran, a, b)              _PICK_EVEN(tran, a, b)
 231 #define _PORT(port, a, b)               _PICK_EVEN(port, a, b)
 232 #define _PLL(pll, a, b)                 _PICK_EVEN(pll, a, b)
 233
 234 #define _MMIO_PIPE(pipe, a, b)          _MMIO(_PIPE(pipe, a, b))
 235 #define _MMIO_PLANE(plane, a, b)        _MMIO(_PLANE(plane, a, b))
 236 #define _MMIO_TRANS(tran, a, b)         _MMIO(_TRANS(tran, a, b))
 237 #define _MMIO_PORT(port, a, b)          _MMIO(_PORT(port, a, b))
 238 #define _MMIO_PLL(pll, a, b)            _MMIO(_PLL(pll, a, b))
 239
 240 #define _PHY3(phy, ...)                 _PICK(phy, __VA_ARGS__)
 241
 242 #define _MMIO_PIPE3(pipe, a, b, c)      _MMIO(_PICK(pipe, a, b, c))
 243 #define _MMIO_PORT3(pipe, a, b, c)      _MMIO(_PICK(pipe, a, b, c))
 244 #define _MMIO_PHY3(phy, a, b, c)        _MMIO(_PHY3(phy, a, b, c))
 245 #define _MMIO_PLL3(pll, a, b, c)        _MMIO(_PICK(pll, a, b, c))
 246
 247 /*
 248  * Device info offset array based helpers for groups of registers with unevenly
 249  * spaced base offsets.
 250  */
 251 #define _MMIO_PIPE2(pipe, reg)          _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
 252                                               INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
 253                                               DISPLAY_MMIO_BASE(dev_priv))
 254 #define _TRANS2(tran, reg)              (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
 255                                          INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
 256                                          DISPLAY_MMIO_BASE(dev_priv))
 257 #define _MMIO_TRANS2(tran, reg)         _MMIO(_TRANS2(tran, reg))
 258 #define _CURSOR2(pipe, reg)             _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
 259                                               INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
 260                                               DISPLAY_MMIO_BASE(dev_priv))
 261
 262 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
 263 #define _MASKED_FIELD(mask, value) ({                                      \
 264         if (__builtin_constant_p(mask))                                    \
 265                 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
 266         if (__builtin_constant_p(value))                                   \
 267                 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
 268         if (__builtin_constant_p(mask) && __builtin_constant_p(value))     \
 269                 BUILD_BUG_ON_MSG((value) & ~(mask),                        \
 270                                  "Incorrect value for mask");              \
 271         __MASKED_FIELD(mask, value); })
 272 #define _MASKED_BIT_ENABLE(a)   ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
 273 #define _MASKED_BIT_DISABLE(a)  (_MASKED_FIELD((a), 0))
 274
 275 /* PCI config space */
 276
 277 #define MCHBAR_I915 0x44
 278 #define MCHBAR_I965 0x48
 279 #define MCHBAR_SIZE (4 * 4096)
 280
 281 #define DEVEN 0x54
 282 #define   DEVEN_MCHBAR_EN (1 << 28)
 283
 284 /* BSM in include/drm/i915_drm.h */
 285
 286 #define HPLLCC  0xc0 /* 85x only */
 287 #define   GC_CLOCK_CONTROL_MASK         (0x7 << 0)
 288 #define   GC_CLOCK_133_200              (0 << 0)
 289 #define   GC_CLOCK_100_200              (1 << 0)
 290 #define   GC_CLOCK_100_133              (2 << 0)
 291 #define   GC_CLOCK_133_266              (3 << 0)
 292 #define   GC_CLOCK_133_200_2            (4 << 0)
 293 #define   GC_CLOCK_133_266_2            (5 << 0)
 294 #define   GC_CLOCK_166_266              (6 << 0)
 295 #define   GC_CLOCK_166_250              (7 << 0)
 296
 297 #define I915_GDRST 0xc0 /* PCI config register */
 298 #define   GRDOM_FULL            (0 << 2)
 299 #define   GRDOM_RENDER          (1 << 2)
 300 #define   GRDOM_MEDIA           (3 << 2)
 301 #define   GRDOM_MASK            (3 << 2)
 302 #define   GRDOM_RESET_STATUS    (1 << 1)
 303 #define   GRDOM_RESET_ENABLE    (1 << 0)
 304
 305 /* BSpec only has register offset, PCI device and bit found empirically */
 306 #define I830_CLOCK_GATE 0xc8 /* device 0 */
 307 #define   I830_L2_CACHE_CLOCK_GATE_DISABLE      (1 << 2)
 308
 309 #define GCDGMBUS 0xcc
 310
 311 #define GCFGC2  0xda
 312 #define GCFGC   0xf0 /* 915+ only */
 313 #define   GC_LOW_FREQUENCY_ENABLE       (1 << 7)
 314 #define   GC_DISPLAY_CLOCK_190_200_MHZ  (0 << 4)
 315 #define   GC_DISPLAY_CLOCK_333_320_MHZ  (4 << 4)
 316 #define   GC_DISPLAY_CLOCK_267_MHZ_PNV  (0 << 4)
 317 #define   GC_DISPLAY_CLOCK_333_MHZ_PNV  (1 << 4)
 318 #define   GC_DISPLAY_CLOCK_444_MHZ_PNV  (2 << 4)
 319 #define   GC_DISPLAY_CLOCK_200_MHZ_PNV  (5 << 4)
 320 #define   GC_DISPLAY_CLOCK_133_MHZ_PNV  (6 << 4)
 321 #define   GC_DISPLAY_CLOCK_167_MHZ_PNV  (7 << 4)
 322 #define   GC_DISPLAY_CLOCK_MASK         (7 << 4)
 323 #define   GM45_GC_RENDER_CLOCK_MASK     (0xf << 0)
 324 #define   GM45_GC_RENDER_CLOCK_266_MHZ  (8 << 0)
 325 #define   GM45_GC_RENDER_CLOCK_320_MHZ  (9 << 0)
 326 #define   GM45_GC_RENDER_CLOCK_400_MHZ  (0xb << 0)
 327 #define   GM45_GC_RENDER_CLOCK_533_MHZ  (0xc << 0)
 328 #define   I965_GC_RENDER_CLOCK_MASK     (0xf << 0)
 329 #define   I965_GC_RENDER_CLOCK_267_MHZ  (2 << 0)
 330 #define   I965_GC_RENDER_CLOCK_333_MHZ  (3 << 0)
 331 #define   I965_GC_RENDER_CLOCK_444_MHZ  (4 << 0)
 332 #define   I965_GC_RENDER_CLOCK_533_MHZ  (5 << 0)
 333 #define   I945_GC_RENDER_CLOCK_MASK     (7 << 0)
 334 #define   I945_GC_RENDER_CLOCK_166_MHZ  (0 << 0)
 335 #define   I945_GC_RENDER_CLOCK_200_MHZ  (1 << 0)
 336 #define   I945_GC_RENDER_CLOCK_250_MHZ  (3 << 0)
 337 #define   I945_GC_RENDER_CLOCK_400_MHZ  (5 << 0)
 338 #define   I915_GC_RENDER_CLOCK_MASK     (7 << 0)
 339 #define   I915_GC_RENDER_CLOCK_166_MHZ  (0 << 0)
 340 #define   I915_GC_RENDER_CLOCK_200_MHZ  (1 << 0)
 341 #define   I915_GC_RENDER_CLOCK_333_MHZ  (4 << 0)
 342
 343 #define ASLE    0xe4
 344 #define ASLS    0xfc
 345
 346 #define SWSCI   0xe8
 347 #define   SWSCI_SCISEL  (1 << 15)
 348 #define   SWSCI_GSSCIE  (1 << 0)
 349
 350 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
 351
 352
 353 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
 354 #define  ILK_GRDOM_FULL         (0 << 1)
 355 #define  ILK_GRDOM_RENDER       (1 << 1)
 356 #define  ILK_GRDOM_MEDIA        (3 << 1)
 357 #define  ILK_GRDOM_MASK         (3 << 1)
 358 #define  ILK_GRDOM_RESET_ENABLE (1 << 0)
 359
 360 #define GEN6_MBCUNIT_SNPCR      _MMIO(0x900c) /* for LLC config */
 361 #define   GEN6_MBC_SNPCR_SHIFT  21
 362 #define   GEN6_MBC_SNPCR_MASK   (3 << 21)
 363 #define   GEN6_MBC_SNPCR_MAX    (0 << 21)
 364 #define   GEN6_MBC_SNPCR_MED    (1 << 21)
 365 #define   GEN6_MBC_SNPCR_LOW    (2 << 21)
 366 #define   GEN6_MBC_SNPCR_MIN    (3 << 21) /* only 1/16th of the cache is shared */
 367
 368 #define VLV_G3DCTL              _MMIO(0x9024)
 369 #define VLV_GSCKGCTL            _MMIO(0x9028)
 370
 371 #define GEN6_MBCTL              _MMIO(0x0907c)
 372 #define   GEN6_MBCTL_ENABLE_BOOT_FETCH  (1 << 4)
 373 #define   GEN6_MBCTL_CTX_FETCH_NEEDED   (1 << 3)
 374 #define   GEN6_MBCTL_BME_UPDATE_ENABLE  (1 << 2)
 375 #define   GEN6_MBCTL_MAE_UPDATE_ENABLE  (1 << 1)
 376 #define   GEN6_MBCTL_BOOT_FETCH_MECH    (1 << 0)
 377
 378 #define GEN6_GDRST      _MMIO(0x941c)
 379 #define  GEN6_GRDOM_FULL                (1 << 0)
 380 #define  GEN6_GRDOM_RENDER              (1 << 1)
 381 #define  GEN6_GRDOM_MEDIA               (1 << 2)
 382 #define  GEN6_GRDOM_BLT                 (1 << 3)
 383 #define  GEN6_GRDOM_VECS                (1 << 4)
 384 #define  GEN9_GRDOM_GUC                 (1 << 5)
 385 #define  GEN8_GRDOM_MEDIA2              (1 << 7)
 386 /* GEN11 changed all bit defs except for FULL & RENDER */
 387 #define  GEN11_GRDOM_FULL               GEN6_GRDOM_FULL
 388 #define  GEN11_GRDOM_RENDER             GEN6_GRDOM_RENDER
 389 #define  GEN11_GRDOM_BLT                (1 << 2)
 390 #define  GEN11_GRDOM_GUC                (1 << 3)
 391 #define  GEN11_GRDOM_MEDIA              (1 << 5)
 392 #define  GEN11_GRDOM_MEDIA2             (1 << 6)
 393 #define  GEN11_GRDOM_MEDIA3             (1 << 7)
 394 #define  GEN11_GRDOM_MEDIA4             (1 << 8)
 395 #define  GEN11_GRDOM_VECS               (1 << 13)
 396 #define  GEN11_GRDOM_VECS2              (1 << 14)
 397 #define  GEN11_GRDOM_SFC0               (1 << 17)
 398 #define  GEN11_GRDOM_SFC1               (1 << 18)
 399
 400 #define  GEN11_VCS_SFC_RESET_BIT(instance)      (GEN11_GRDOM_SFC0 << ((instance) >> 1))
 401 #define  GEN11_VECS_SFC_RESET_BIT(instance)     (GEN11_GRDOM_SFC0 << (instance))
 402
 403 #define GEN11_VCS_SFC_FORCED_LOCK(engine)       _MMIO((engine)->mmio_base + 0x88C)
 404 #define   GEN11_VCS_SFC_FORCED_LOCK_BIT         (1 << 0)
 405 #define GEN11_VCS_SFC_LOCK_STATUS(engine)       _MMIO((engine)->mmio_base + 0x890)
 406 #define   GEN11_VCS_SFC_USAGE_BIT               (1 << 0)
 407 #define   GEN11_VCS_SFC_LOCK_ACK_BIT            (1 << 1)
 408
 409 #define GEN11_VECS_SFC_FORCED_LOCK(engine)      _MMIO((engine)->mmio_base + 0x201C)
 410 #define   GEN11_VECS_SFC_FORCED_LOCK_BIT        (1 << 0)
 411 #define GEN11_VECS_SFC_LOCK_ACK(engine)         _MMIO((engine)->mmio_base + 0x2018)
 412 #define   GEN11_VECS_SFC_LOCK_ACK_BIT           (1 << 0)
 413 #define GEN11_VECS_SFC_USAGE(engine)            _MMIO((engine)->mmio_base + 0x2014)
 414 #define   GEN11_VECS_SFC_USAGE_BIT              (1 << 0)
 415
 416 #define GEN12_SFC_DONE(n)               _MMIO(0x1cc00 + (n) * 0x100)
 417 #define GEN12_SFC_DONE_MAX              4
 418
 419 #define RING_PP_DIR_BASE(base)          _MMIO((base) + 0x228)
 420 #define RING_PP_DIR_BASE_READ(base)     _MMIO((base) + 0x518)
 421 #define RING_PP_DIR_DCLV(base)          _MMIO((base) + 0x220)
 422 #define   PP_DIR_DCLV_2G                0xffffffff
 423
 424 #define GEN8_RING_PDP_UDW(base, n)      _MMIO((base) + 0x270 + (n) * 8 + 4)
 425 #define GEN8_RING_PDP_LDW(base, n)      _MMIO((base) + 0x270 + (n) * 8)
 426
 427 #define GEN8_R_PWR_CLK_STATE            _MMIO(0x20C8)
 428 #define   GEN8_RPCS_ENABLE              (1 << 31)
 429 #define   GEN8_RPCS_S_CNT_ENABLE        (1 << 18)
 430 #define   GEN8_RPCS_S_CNT_SHIFT         15
 431 #define   GEN8_RPCS_S_CNT_MASK          (0x7 << GEN8_RPCS_S_CNT_SHIFT)
 432 #define   GEN11_RPCS_S_CNT_SHIFT        12
 433 #define   GEN11_RPCS_S_CNT_MASK         (0x3f << GEN11_RPCS_S_CNT_SHIFT)
 434 #define   GEN8_RPCS_SS_CNT_ENABLE       (1 << 11)
 435 #define   GEN8_RPCS_SS_CNT_SHIFT        8
 436 #define   GEN8_RPCS_SS_CNT_MASK         (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
 437 #define   GEN8_RPCS_EU_MAX_SHIFT        4
 438 #define   GEN8_RPCS_EU_MAX_MASK         (0xf << GEN8_RPCS_EU_MAX_SHIFT)
 439 #define   GEN8_RPCS_EU_MIN_SHIFT        0
 440 #define   GEN8_RPCS_EU_MIN_MASK         (0xf << GEN8_RPCS_EU_MIN_SHIFT)
 441
 442 #define WAIT_FOR_RC6_EXIT               _MMIO(0x20CC)
 443 /* HSW only */
 444 #define   HSW_SELECTIVE_READ_ADDRESSING_SHIFT           2
 445 #define   HSW_SELECTIVE_READ_ADDRESSING_MASK            (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
 446 #define   HSW_SELECTIVE_WRITE_ADDRESS_SHIFT             4
 447 #define   HSW_SELECTIVE_WRITE_ADDRESS_MASK              (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
 448 /* HSW+ */
 449 #define   HSW_WAIT_FOR_RC6_EXIT_ENABLE                  (1 << 0)
 450 #define   HSW_RCS_CONTEXT_ENABLE                        (1 << 7)
 451 #define   HSW_RCS_INHIBIT                               (1 << 8)
 452 /* Gen8 */
 453 #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT            4
 454 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK             (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
 455 #define   GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT            4
 456 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK             (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
 457 #define   GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE        (1 << 6)
 458 #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT     9
 459 #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK      (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
 460 #define   GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT        11
 461 #define   GEN8_SELECTIVE_READ_SLICE_SELECT_MASK         (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
 462 #define   GEN8_SELECTIVE_READ_ADDRESSING_ENABLE         (1 << 13)
 463
 464 #define GAM_ECOCHK                      _MMIO(0x4090)
 465 #define   BDW_DISABLE_HDC_INVALIDATION  (1 << 25)
 466 #define   ECOCHK_SNB_BIT                (1 << 10)
 467 #define   ECOCHK_DIS_TLB                (1 << 8)
 468 #define   HSW_ECOCHK_ARB_PRIO_SOL       (1 << 6)
 469 #define   ECOCHK_PPGTT_CACHE64B         (0x3 << 3)
 470 #define   ECOCHK_PPGTT_CACHE4B          (0x0 << 3)
 471 #define   ECOCHK_PPGTT_GFDT_IVB         (0x1 << 4)
 472 #define   ECOCHK_PPGTT_LLC_IVB          (0x1 << 3)
 473 #define   ECOCHK_PPGTT_UC_HSW           (0x1 << 3)
 474 #define   ECOCHK_PPGTT_WT_HSW           (0x2 << 3)
 475 #define   ECOCHK_PPGTT_WB_HSW           (0x3 << 3)
 476
 477 #define GEN8_RC6_CTX_INFO               _MMIO(0x8504)
 478
 479 #define GAC_ECO_BITS                    _MMIO(0x14090)
 480 #define   ECOBITS_SNB_BIT               (1 << 13)
 481 #define   ECOBITS_PPGTT_CACHE64B        (3 << 8)
 482 #define   ECOBITS_PPGTT_CACHE4B         (0 << 8)
 483
 484 #define GAB_CTL                         _MMIO(0x24000)
 485 #define   GAB_CTL_CONT_AFTER_PAGEFAULT  (1 << 8)
 486
 487 #define GEN6_STOLEN_RESERVED            _MMIO(0x1082C0)
 488 #define GEN6_STOLEN_RESERVED_ADDR_MASK  (0xFFF << 20)
 489 #define GEN7_STOLEN_RESERVED_ADDR_MASK  (0x3FFF << 18)
 490 #define GEN6_STOLEN_RESERVED_SIZE_MASK  (3 << 4)
 491 #define GEN6_STOLEN_RESERVED_1M         (0 << 4)
 492 #define GEN6_STOLEN_RESERVED_512K       (1 << 4)
 493 #define GEN6_STOLEN_RESERVED_256K       (2 << 4)
 494 #define GEN6_STOLEN_RESERVED_128K       (3 << 4)
 495 #define GEN7_STOLEN_RESERVED_SIZE_MASK  (1 << 5)
 496 #define GEN7_STOLEN_RESERVED_1M         (0 << 5)
 497 #define GEN7_STOLEN_RESERVED_256K       (1 << 5)
 498 #define GEN8_STOLEN_RESERVED_SIZE_MASK  (3 << 7)
 499 #define GEN8_STOLEN_RESERVED_1M         (0 << 7)
 500 #define GEN8_STOLEN_RESERVED_2M         (1 << 7)
 501 #define GEN8_STOLEN_RESERVED_4M         (2 << 7)
 502 #define GEN8_STOLEN_RESERVED_8M         (3 << 7)
 503 #define GEN6_STOLEN_RESERVED_ENABLE     (1 << 0)
 504 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
 505
 506 /* VGA stuff */
 507
 508 #define VGA_ST01_MDA 0x3ba
 509 #define VGA_ST01_CGA 0x3da
 510
 511 #define _VGA_MSR_WRITE _MMIO(0x3c2)
 512 #define VGA_MSR_WRITE 0x3c2
 513 #define VGA_MSR_READ 0x3cc
 514 #define   VGA_MSR_MEM_EN (1 << 1)
 515 #define   VGA_MSR_CGA_MODE (1 << 0)
 516
 517 #define VGA_SR_INDEX 0x3c4
 518 #define SR01                    1
 519 #define VGA_SR_DATA 0x3c5
 520
 521 #define VGA_AR_INDEX 0x3c0
 522 #define   VGA_AR_VID_EN (1 << 5)
 523 #define VGA_AR_DATA_WRITE 0x3c0
 524 #define VGA_AR_DATA_READ 0x3c1
 525
 526 #define VGA_GR_INDEX 0x3ce
 527 #define VGA_GR_DATA 0x3cf
 528 /* GR05 */
 529 #define   VGA_GR_MEM_READ_MODE_SHIFT 3
 530 #define     VGA_GR_MEM_READ_MODE_PLANE 1
 531 /* GR06 */
 532 #define   VGA_GR_MEM_MODE_MASK 0xc
 533 #define   VGA_GR_MEM_MODE_SHIFT 2
 534 #define   VGA_GR_MEM_A0000_AFFFF 0
 535 #define   VGA_GR_MEM_A0000_BFFFF 1
 536 #define   VGA_GR_MEM_B0000_B7FFF 2
 537 #define   VGA_GR_MEM_B0000_BFFFF 3
 538
 539 #define VGA_DACMASK 0x3c6
 540 #define VGA_DACRX 0x3c7
 541 #define VGA_DACWX 0x3c8
 542 #define VGA_DACDATA 0x3c9
 543
 544 #define VGA_CR_INDEX_MDA 0x3b4
 545 #define VGA_CR_DATA_MDA 0x3b5
 546 #define VGA_CR_INDEX_CGA 0x3d4
 547 #define VGA_CR_DATA_CGA 0x3d5
 548
 549 #define MI_PREDICATE_SRC0       _MMIO(0x2400)
 550 #define MI_PREDICATE_SRC0_UDW   _MMIO(0x2400 + 4)
 551 #define MI_PREDICATE_SRC1       _MMIO(0x2408)
 552 #define MI_PREDICATE_SRC1_UDW   _MMIO(0x2408 + 4)
 553 #define MI_PREDICATE_DATA       _MMIO(0x2410)
 554 #define MI_PREDICATE_RESULT     _MMIO(0x2418)
 555 #define MI_PREDICATE_RESULT_1   _MMIO(0x241c)
 556 #define MI_PREDICATE_RESULT_2   _MMIO(0x2214)
 557 #define  LOWER_SLICE_ENABLED    (1 << 0)
 558 #define  LOWER_SLICE_DISABLED   (0 << 0)
 559
 560 /*
 561  * Registers used only by the command parser
 562  */
 563 #define BCS_SWCTRL _MMIO(0x22200)
 564
 565 /* There are 16 GPR registers */
 566 #define BCS_GPR(n)      _MMIO(0x22600 + (n) * 8)
 567 #define BCS_GPR_UDW(n)  _MMIO(0x22600 + (n) * 8 + 4)
 568
 569 #define GPGPU_THREADS_DISPATCHED        _MMIO(0x2290)
 570 #define GPGPU_THREADS_DISPATCHED_UDW    _MMIO(0x2290 + 4)
 571 #define HS_INVOCATION_COUNT             _MMIO(0x2300)
 572 #define HS_INVOCATION_COUNT_UDW         _MMIO(0x2300 + 4)
 573 #define DS_INVOCATION_COUNT             _MMIO(0x2308)
 574 #define DS_INVOCATION_COUNT_UDW         _MMIO(0x2308 + 4)
 575 #define IA_VERTICES_COUNT               _MMIO(0x2310)
 576 #define IA_VERTICES_COUNT_UDW           _MMIO(0x2310 + 4)
 577 #define IA_PRIMITIVES_COUNT             _MMIO(0x2318)
 578 #define IA_PRIMITIVES_COUNT_UDW         _MMIO(0x2318 + 4)
 579 #define VS_INVOCATION_COUNT             _MMIO(0x2320)
 580 #define VS_INVOCATION_COUNT_UDW         _MMIO(0x2320 + 4)
 581 #define GS_INVOCATION_COUNT             _MMIO(0x2328)
 582 #define GS_INVOCATION_COUNT_UDW         _MMIO(0x2328 + 4)
 583 #define GS_PRIMITIVES_COUNT             _MMIO(0x2330)
 584 #define GS_PRIMITIVES_COUNT_UDW         _MMIO(0x2330 + 4)
 585 #define CL_INVOCATION_COUNT             _MMIO(0x2338)
 586 #define CL_INVOCATION_COUNT_UDW         _MMIO(0x2338 + 4)
 587 #define CL_PRIMITIVES_COUNT             _MMIO(0x2340)
 588 #define CL_PRIMITIVES_COUNT_UDW         _MMIO(0x2340 + 4)
 589 #define PS_INVOCATION_COUNT             _MMIO(0x2348)
 590 #define PS_INVOCATION_COUNT_UDW         _MMIO(0x2348 + 4)
 591 #define PS_DEPTH_COUNT                  _MMIO(0x2350)
 592 #define PS_DEPTH_COUNT_UDW              _MMIO(0x2350 + 4)
 593
 594 /* There are the 4 64-bit counter registers, one for each stream output */
 595 #define GEN7_SO_NUM_PRIMS_WRITTEN(n)            _MMIO(0x5200 + (n) * 8)
 596 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)        _MMIO(0x5200 + (n) * 8 + 4)
 597
 598 #define GEN7_SO_PRIM_STORAGE_NEEDED(n)          _MMIO(0x5240 + (n) * 8)
 599 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n)      _MMIO(0x5240 + (n) * 8 + 4)
 600
 601 #define GEN7_3DPRIM_END_OFFSET          _MMIO(0x2420)
 602 #define GEN7_3DPRIM_START_VERTEX        _MMIO(0x2430)
 603 #define GEN7_3DPRIM_VERTEX_COUNT        _MMIO(0x2434)
 604 #define GEN7_3DPRIM_INSTANCE_COUNT      _MMIO(0x2438)
 605 #define GEN7_3DPRIM_START_INSTANCE      _MMIO(0x243C)
 606 #define GEN7_3DPRIM_BASE_VERTEX         _MMIO(0x2440)
 607
 608 #define GEN7_GPGPU_DISPATCHDIMX         _MMIO(0x2500)
 609 #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
 610 #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
 611
 612 /* There are the 16 64-bit CS General Purpose Registers */
 613 #define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
 614 #define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
 615
 616 #define GEN7_OACONTROL _MMIO(0x2360)
 617 #define  GEN7_OACONTROL_CTX_MASK            0xFFFFF000
 618 #define  GEN7_OACONTROL_TIMER_PERIOD_MASK   0x3F
 619 #define  GEN7_OACONTROL_TIMER_PERIOD_SHIFT  6
 620 #define  GEN7_OACONTROL_TIMER_ENABLE        (1 << 5)
 621 #define  GEN7_OACONTROL_FORMAT_A13          (0 << 2)
 622 #define  GEN7_OACONTROL_FORMAT_A29          (1 << 2)
 623 #define  GEN7_OACONTROL_FORMAT_A13_B8_C8    (2 << 2)
 624 #define  GEN7_OACONTROL_FORMAT_A29_B8_C8    (3 << 2)
 625 #define  GEN7_OACONTROL_FORMAT_B4_C8        (4 << 2)
 626 #define  GEN7_OACONTROL_FORMAT_A45_B8_C8    (5 << 2)
 627 #define  GEN7_OACONTROL_FORMAT_B4_C8_A16    (6 << 2)
 628 #define  GEN7_OACONTROL_FORMAT_C4_B8        (7 << 2)
 629 #define  GEN7_OACONTROL_FORMAT_SHIFT        2
 630 #define  GEN7_OACONTROL_PER_CTX_ENABLE      (1 << 1)
 631 #define  GEN7_OACONTROL_ENABLE              (1 << 0)
 632
 633 #define GEN8_OACTXID _MMIO(0x2364)
 634
 635 #define GEN8_OA_DEBUG _MMIO(0x2B04)
 636 #define  GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS    (1 << 5)
 637 #define  GEN9_OA_DEBUG_INCLUDE_CLK_RATIO            (1 << 6)
 638 #define  GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS       (1 << 2)
 639 #define  GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS   (1 << 1)
 640
 641 #define GEN8_OACONTROL _MMIO(0x2B00)
 642 #define  GEN8_OA_REPORT_FORMAT_A12          (0 << 2)
 643 #define  GEN8_OA_REPORT_FORMAT_A12_B8_C8    (2 << 2)
 644 #define  GEN8_OA_REPORT_FORMAT_A36_B8_C8    (5 << 2)
 645 #define  GEN8_OA_REPORT_FORMAT_C4_B8        (7 << 2)
 646 #define  GEN8_OA_REPORT_FORMAT_SHIFT        2
 647 #define  GEN8_OA_SPECIFIC_CONTEXT_ENABLE    (1 << 1)
 648 #define  GEN8_OA_COUNTER_ENABLE             (1 << 0)
 649
 650 #define GEN8_OACTXCONTROL _MMIO(0x2360)
 651 #define  GEN8_OA_TIMER_PERIOD_MASK          0x3F
 652 #define  GEN8_OA_TIMER_PERIOD_SHIFT         2
 653 #define  GEN8_OA_TIMER_ENABLE               (1 << 1)
 654 #define  GEN8_OA_COUNTER_RESUME             (1 << 0)
 655
 656 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
 657 #define  GEN7_OABUFFER_OVERRUN_DISABLE      (1 << 3)
 658 #define  GEN7_OABUFFER_EDGE_TRIGGER         (1 << 2)
 659 #define  GEN7_OABUFFER_STOP_RESUME_ENABLE   (1 << 1)
 660 #define  GEN7_OABUFFER_RESUME               (1 << 0)
 661
 662 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
 663 #define GEN8_OABUFFER _MMIO(0x2b14)
 664 #define  GEN8_OABUFFER_MEM_SELECT_GGTT      (1 << 0)  /* 0: PPGTT, 1: GGTT */
 665
 666 #define GEN7_OASTATUS1 _MMIO(0x2364)
 667 #define  GEN7_OASTATUS1_TAIL_MASK           0xffffffc0
 668 #define  GEN7_OASTATUS1_COUNTER_OVERFLOW    (1 << 2)
 669 #define  GEN7_OASTATUS1_OABUFFER_OVERFLOW   (1 << 1)
 670 #define  GEN7_OASTATUS1_REPORT_LOST         (1 << 0)
 671
 672 #define GEN7_OASTATUS2 _MMIO(0x2368)
 673 #define  GEN7_OASTATUS2_HEAD_MASK           0xffffffc0
 674 #define  GEN7_OASTATUS2_MEM_SELECT_GGTT     (1 << 0) /* 0: PPGTT, 1: GGTT */
 675
 676 #define GEN8_OASTATUS _MMIO(0x2b08)
 677 #define  GEN8_OASTATUS_OVERRUN_STATUS       (1 << 3)
 678 #define  GEN8_OASTATUS_COUNTER_OVERFLOW     (1 << 2)
 679 #define  GEN8_OASTATUS_OABUFFER_OVERFLOW    (1 << 1)
 680 #define  GEN8_OASTATUS_REPORT_LOST          (1 << 0)
 681
 682 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
 683 #define GEN8_OAHEADPTR_MASK    0xffffffc0
 684 #define GEN8_OATAILPTR _MMIO(0x2B10)
 685 #define GEN8_OATAILPTR_MASK    0xffffffc0
 686
 687 #define OABUFFER_SIZE_128K  (0 << 3)
 688 #define OABUFFER_SIZE_256K  (1 << 3)
 689 #define OABUFFER_SIZE_512K  (2 << 3)
 690 #define OABUFFER_SIZE_1M    (3 << 3)
 691 #define OABUFFER_SIZE_2M    (4 << 3)
 692 #define OABUFFER_SIZE_4M    (5 << 3)
 693 #define OABUFFER_SIZE_8M    (6 << 3)
 694 #define OABUFFER_SIZE_16M   (7 << 3)
 695
 696 /* Gen12 OAR unit */
 697 #define GEN12_OAR_OACONTROL _MMIO(0x2960)
 698 #define  GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
 699 #define  GEN12_OAR_OACONTROL_COUNTER_ENABLE       (1 << 0)
 700
 701 #define GEN12_OACTXCONTROL _MMIO(0x2360)
 702 #define GEN12_OAR_OASTATUS _MMIO(0x2968)
 703
 704 /* Gen12 OAG unit */
 705 #define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
 706 #define  GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
 707 #define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
 708 #define  GEN12_OAG_OATAILPTR_MASK 0xffffffc0
 709
 710 #define GEN12_OAG_OABUFFER  _MMIO(0xdb08)
 711 #define  GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK  (0x7)
 712 #define  GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
 713 #define  GEN12_OAG_OABUFFER_MEMORY_SELECT     (1 << 0) /* 0: PPGTT, 1: GGTT */
 714
 715 #define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
 716 #define  GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
 717 #define  GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE       (1 << 1)
 718 #define  GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME     (1 << 0)
 719
 720 #define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
 721 #define  GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
 722 #define  GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE       (1 << 0)
 723
 724 #define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
 725 #define  GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO          (1 << 6)
 726 #define  GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS  (1 << 5)
 727 #define  GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS     (1 << 2)
 728 #define  GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
 729
 730 #define GEN12_OAG_OASTATUS _MMIO(0xdafc)
 731 #define  GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
 732 #define  GEN12_OAG_OASTATUS_BUFFER_OVERFLOW  (1 << 1)
 733 #define  GEN12_OAG_OASTATUS_REPORT_LOST      (1 << 0)
 734
 735 /*
 736  * Flexible, Aggregate EU Counter Registers.
 737  * Note: these aren't contiguous
 738  */
 739 #define EU_PERF_CNTL0       _MMIO(0xe458)
 740 #define EU_PERF_CNTL1       _MMIO(0xe558)
 741 #define EU_PERF_CNTL2       _MMIO(0xe658)
 742 #define EU_PERF_CNTL3       _MMIO(0xe758)
 743 #define EU_PERF_CNTL4       _MMIO(0xe45c)
 744 #define EU_PERF_CNTL5       _MMIO(0xe55c)
 745 #define EU_PERF_CNTL6       _MMIO(0xe65c)
 746
 747 /*
 748  * OA Boolean state
 749  */
 750
 751 #define OASTARTTRIG1 _MMIO(0x2710)
 752 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
 753 #define OASTARTTRIG1_THRESHOLD_MASK           0xffff
 754
 755 #define OASTARTTRIG2 _MMIO(0x2714)
 756 #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
 757 #define OASTARTTRIG2_INVERT_A_1 (1 << 1)
 758 #define OASTARTTRIG2_INVERT_A_2 (1 << 2)
 759 #define OASTARTTRIG2_INVERT_A_3 (1 << 3)
 760 #define OASTARTTRIG2_INVERT_A_4 (1 << 4)
 761 #define OASTARTTRIG2_INVERT_A_5 (1 << 5)
 762 #define OASTARTTRIG2_INVERT_A_6 (1 << 6)
 763 #define OASTARTTRIG2_INVERT_A_7 (1 << 7)
 764 #define OASTARTTRIG2_INVERT_A_8 (1 << 8)
 765 #define OASTARTTRIG2_INVERT_A_9 (1 << 9)
 766 #define OASTARTTRIG2_INVERT_A_10 (1 << 10)
 767 #define OASTARTTRIG2_INVERT_A_11 (1 << 11)
 768 #define OASTARTTRIG2_INVERT_A_12 (1 << 12)
 769 #define OASTARTTRIG2_INVERT_A_13 (1 << 13)
 770 #define OASTARTTRIG2_INVERT_A_14 (1 << 14)
 771 #define OASTARTTRIG2_INVERT_A_15 (1 << 15)
 772 #define OASTARTTRIG2_INVERT_B_0 (1 << 16)
 773 #define OASTARTTRIG2_INVERT_B_1 (1 << 17)
 774 #define OASTARTTRIG2_INVERT_B_2 (1 << 18)
 775 #define OASTARTTRIG2_INVERT_B_3 (1 << 19)
 776 #define OASTARTTRIG2_INVERT_C_0 (1 << 20)
 777 #define OASTARTTRIG2_INVERT_C_1 (1 << 21)
 778 #define OASTARTTRIG2_INVERT_D_0 (1 << 22)
 779 #define OASTARTTRIG2_THRESHOLD_ENABLE       (1 << 23)
 780 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ    (1 << 24)
 781 #define OASTARTTRIG2_EVENT_SELECT_0  (1 << 28)
 782 #define OASTARTTRIG2_EVENT_SELECT_1  (1 << 29)
 783 #define OASTARTTRIG2_EVENT_SELECT_2  (1 << 30)
 784 #define OASTARTTRIG2_EVENT_SELECT_3  (1 << 31)
 785
 786 #define OASTARTTRIG3 _MMIO(0x2718)
 787 #define OASTARTTRIG3_NOA_SELECT_MASK       0xf
 788 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT    0
 789 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT    4
 790 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT   8
 791 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT   12
 792 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT   16
 793 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT   20
 794 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT   24
 795 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT   28
 796
 797 #define OASTARTTRIG4 _MMIO(0x271c)
 798 #define OASTARTTRIG4_NOA_SELECT_MASK        0xf
 799 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT    0
 800 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT    4
 801 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT    8
 802 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT    12
 803 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT    16
 804 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT    20
 805 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT    24
 806 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT    28
 807
 808 #define OASTARTTRIG5 _MMIO(0x2720)
 809 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
 810 #define OASTARTTRIG5_THRESHOLD_MASK           0xffff
 811
 812 #define OASTARTTRIG6 _MMIO(0x2724)
 813 #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
 814 #define OASTARTTRIG6_INVERT_A_1 (1 << 1)
 815 #define OASTARTTRIG6_INVERT_A_2 (1 << 2)
 816 #define OASTARTTRIG6_INVERT_A_3 (1 << 3)
 817 #define OASTARTTRIG6_INVERT_A_4 (1 << 4)
 818 #define OASTARTTRIG6_INVERT_A_5 (1 << 5)
 819 #define OASTARTTRIG6_INVERT_A_6 (1 << 6)
 820 #define OASTARTTRIG6_INVERT_A_7 (1 << 7)
 821 #define OASTARTTRIG6_INVERT_A_8 (1 << 8)
 822 #define OASTARTTRIG6_INVERT_A_9 (1 << 9)
 823 #define OASTARTTRIG6_INVERT_A_10 (1 << 10)
 824 #define OASTARTTRIG6_INVERT_A_11 (1 << 11)
 825 #define OASTARTTRIG6_INVERT_A_12 (1 << 12)
 826 #define OASTARTTRIG6_INVERT_A_13 (1 << 13)
 827 #define OASTARTTRIG6_INVERT_A_14 (1 << 14)
 828 #define OASTARTTRIG6_INVERT_A_15 (1 << 15)
 829 #define OASTARTTRIG6_INVERT_B_0 (1 << 16)
 830 #define OASTARTTRIG6_INVERT_B_1 (1 << 17)
 831 #define OASTARTTRIG6_INVERT_B_2 (1 << 18)
 832 #define OASTARTTRIG6_INVERT_B_3 (1 << 19)
 833 #define OASTARTTRIG6_INVERT_C_0 (1 << 20)
 834 #define OASTARTTRIG6_INVERT_C_1 (1 << 21)
 835 #define OASTARTTRIG6_INVERT_D_0 (1 << 22)
 836 #define OASTARTTRIG6_THRESHOLD_ENABLE       (1 << 23)
 837 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ    (1 << 24)
 838 #define OASTARTTRIG6_EVENT_SELECT_4  (1 << 28)
 839 #define OASTARTTRIG6_EVENT_SELECT_5  (1 << 29)
 840 #define OASTARTTRIG6_EVENT_SELECT_6  (1 << 30)
 841 #define OASTARTTRIG6_EVENT_SELECT_7  (1 << 31)
 842
 843 #define OASTARTTRIG7 _MMIO(0x2728)
 844 #define OASTARTTRIG7_NOA_SELECT_MASK       0xf
 845 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT    0
 846 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT    4
 847 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT   8
 848 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT   12
 849 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT   16
 850 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT   20
 851 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT   24
 852 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT   28
 853
 854 #define OASTARTTRIG8 _MMIO(0x272c)
 855 #define OASTARTTRIG8_NOA_SELECT_MASK       0xf
 856 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT    0
 857 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT    4
 858 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT    8
 859 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT    12
 860 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT    16
 861 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT    20
 862 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT    24
 863 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT    28
 864
 865 #define OAREPORTTRIG1 _MMIO(0x2740)
 866 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
 867 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
 868
 869 #define OAREPORTTRIG2 _MMIO(0x2744)
 870 #define OAREPORTTRIG2_INVERT_A_0  (1 << 0)
 871 #define OAREPORTTRIG2_INVERT_A_1  (1 << 1)
 872 #define OAREPORTTRIG2_INVERT_A_2  (1 << 2)
 873 #define OAREPORTTRIG2_INVERT_A_3  (1 << 3)
 874 #define OAREPORTTRIG2_INVERT_A_4  (1 << 4)
 875 #define OAREPORTTRIG2_INVERT_A_5  (1 << 5)
 876 #define OAREPORTTRIG2_INVERT_A_6  (1 << 6)
 877 #define OAREPORTTRIG2_INVERT_A_7  (1 << 7)
 878 #define OAREPORTTRIG2_INVERT_A_8  (1 << 8)
 879 #define OAREPORTTRIG2_INVERT_A_9  (1 << 9)
 880 #define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
 881 #define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
 882 #define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
 883 #define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
 884 #define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
 885 #define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
 886 #define OAREPORTTRIG2_INVERT_B_0  (1 << 16)
 887 #define OAREPORTTRIG2_INVERT_B_1  (1 << 17)
 888 #define OAREPORTTRIG2_INVERT_B_2  (1 << 18)
 889 #define OAREPORTTRIG2_INVERT_B_3  (1 << 19)
 890 #define OAREPORTTRIG2_INVERT_C_0  (1 << 20)
 891 #define OAREPORTTRIG2_INVERT_C_1  (1 << 21)
 892 #define OAREPORTTRIG2_INVERT_D_0  (1 << 22)
 893 #define OAREPORTTRIG2_THRESHOLD_ENABLE      (1 << 23)
 894 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
 895
 896 #define OAREPORTTRIG3 _MMIO(0x2748)
 897 #define OAREPORTTRIG3_NOA_SELECT_MASK       0xf
 898 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT    0
 899 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT    4
 900 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT   8
 901 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT   12
 902 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT   16
 903 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT   20
 904 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT   24
 905 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT   28
 906
 907 #define OAREPORTTRIG4 _MMIO(0x274c)
 908 #define OAREPORTTRIG4_NOA_SELECT_MASK       0xf
 909 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT    0
 910 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT    4
 911 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT    8
 912 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT    12
 913 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT    16
 914 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT    20
 915 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT    24
 916 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT    28
 917
 918 #define OAREPORTTRIG5 _MMIO(0x2750)
 919 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
 920 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
 921
 922 #define OAREPORTTRIG6 _MMIO(0x2754)
 923 #define OAREPORTTRIG6_INVERT_A_0  (1 << 0)
 924 #define OAREPORTTRIG6_INVERT_A_1  (1 << 1)
 925 #define OAREPORTTRIG6_INVERT_A_2  (1 << 2)
 926 #define OAREPORTTRIG6_INVERT_A_3  (1 << 3)
 927 #define OAREPORTTRIG6_INVERT_A_4  (1 << 4)
 928 #define OAREPORTTRIG6_INVERT_A_5  (1 << 5)
 929 #define OAREPORTTRIG6_INVERT_A_6  (1 << 6)
 930 #define OAREPORTTRIG6_INVERT_A_7  (1 << 7)
 931 #define OAREPORTTRIG6_INVERT_A_8  (1 << 8)
 932 #define OAREPORTTRIG6_INVERT_A_9  (1 << 9)
 933 #define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
 934 #define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
 935 #define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
 936 #define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
 937 #define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
 938 #define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
 939 #define OAREPORTTRIG6_INVERT_B_0  (1 << 16)
 940 #define OAREPORTTRIG6_INVERT_B_1  (1 << 17)
 941 #define OAREPORTTRIG6_INVERT_B_2  (1 << 18)
 942 #define OAREPORTTRIG6_INVERT_B_3  (1 << 19)
 943 #define OAREPORTTRIG6_INVERT_C_0  (1 << 20)
 944 #define OAREPORTTRIG6_INVERT_C_1  (1 << 21)
 945 #define OAREPORTTRIG6_INVERT_D_0  (1 << 22)
 946 #define OAREPORTTRIG6_THRESHOLD_ENABLE      (1 << 23)
 947 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
 948
 949 #define OAREPORTTRIG7 _MMIO(0x2758)
 950 #define OAREPORTTRIG7_NOA_SELECT_MASK       0xf
 951 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT    0
 952 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT    4
 953 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT   8
 954 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT   12
 955 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT   16
 956 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT   20
 957 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT   24
 958 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT   28
 959
 960 #define OAREPORTTRIG8 _MMIO(0x275c)
 961 #define OAREPORTTRIG8_NOA_SELECT_MASK       0xf
 962 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT    0
 963 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT    4
 964 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT    8
 965 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT    12
 966 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT    16
 967 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT    20
 968 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT    24
 969 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT    28
 970
 971 /* Same layout as OASTARTTRIGX */
 972 #define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
 973 #define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
 974 #define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
 975 #define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
 976 #define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
 977 #define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
 978 #define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
 979 #define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
 980
 981 /* Same layout as OAREPORTTRIGX */
 982 #define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
 983 #define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
 984 #define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
 985 #define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
 986 #define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
 987 #define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
 988 #define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
 989 #define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
 990
 991 /* CECX_0 */
 992 #define OACEC_COMPARE_LESS_OR_EQUAL     6
 993 #define OACEC_COMPARE_NOT_EQUAL         5
 994 #define OACEC_COMPARE_LESS_THAN         4
 995 #define OACEC_COMPARE_GREATER_OR_EQUAL  3
 996 #define OACEC_COMPARE_EQUAL             2
 997 #define OACEC_COMPARE_GREATER_THAN      1
 998 #define OACEC_COMPARE_ANY_EQUAL         0
 999
1000 #define OACEC_COMPARE_VALUE_MASK    0xffff
1001 #define OACEC_COMPARE_VALUE_SHIFT   3
1002
1003 #define OACEC_SELECT_NOA        (0 << 19)
1004 #define OACEC_SELECT_PREV       (1 << 19)
1005 #define OACEC_SELECT_BOOLEAN    (2 << 19)
1006
1007 /* 11-bit array 0: pass-through, 1: negated */
1008 #define GEN12_OASCEC_NEGATE_MASK  0x7ff
1009 #define GEN12_OASCEC_NEGATE_SHIFT 21
1010
1011 /* CECX_1 */
1012 #define OACEC_MASK_MASK             0xffff
1013 #define OACEC_CONSIDERATIONS_MASK   0xffff
1014 #define OACEC_CONSIDERATIONS_SHIFT  16
1015
1016 #define OACEC0_0 _MMIO(0x2770)
1017 #define OACEC0_1 _MMIO(0x2774)
1018 #define OACEC1_0 _MMIO(0x2778)
1019 #define OACEC1_1 _MMIO(0x277c)
1020 #define OACEC2_0 _MMIO(0x2780)
1021 #define OACEC2_1 _MMIO(0x2784)
1022 #define OACEC3_0 _MMIO(0x2788)
1023 #define OACEC3_1 _MMIO(0x278c)
1024 #define OACEC4_0 _MMIO(0x2790)
1025 #define OACEC4_1 _MMIO(0x2794)
1026 #define OACEC5_0 _MMIO(0x2798)
1027 #define OACEC5_1 _MMIO(0x279c)
1028 #define OACEC6_0 _MMIO(0x27a0)
1029 #define OACEC6_1 _MMIO(0x27a4)
1030 #define OACEC7_0 _MMIO(0x27a8)
1031 #define OACEC7_1 _MMIO(0x27ac)
1032
1033 /* Same layout as CECX_Y */
1034 #define GEN12_OAG_CEC0_0 _MMIO(0xd940)
1035 #define GEN12_OAG_CEC0_1 _MMIO(0xd944)
1036 #define GEN12_OAG_CEC1_0 _MMIO(0xd948)
1037 #define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
1038 #define GEN12_OAG_CEC2_0 _MMIO(0xd950)
1039 #define GEN12_OAG_CEC2_1 _MMIO(0xd954)
1040 #define GEN12_OAG_CEC3_0 _MMIO(0xd958)
1041 #define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
1042 #define GEN12_OAG_CEC4_0 _MMIO(0xd960)
1043 #define GEN12_OAG_CEC4_1 _MMIO(0xd964)
1044 #define GEN12_OAG_CEC5_0 _MMIO(0xd968)
1045 #define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
1046 #define GEN12_OAG_CEC6_0 _MMIO(0xd970)
1047 #define GEN12_OAG_CEC6_1 _MMIO(0xd974)
1048 #define GEN12_OAG_CEC7_0 _MMIO(0xd978)
1049 #define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
1050
1051 /* Same layout as CECX_Y + negate 11-bit array */
1052 #define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
1053 #define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
1054 #define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
1055 #define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
1056 #define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
1057 #define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
1058 #define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
1059 #define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
1060 #define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
1061 #define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
1062 #define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
1063 #define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
1064 #define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
1065 #define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
1066 #define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
1067 #define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
1068
1069 /* OA perf counters */
1070 #define OA_PERFCNT1_LO      _MMIO(0x91B8)
1071 #define OA_PERFCNT1_HI      _MMIO(0x91BC)
1072 #define OA_PERFCNT2_LO      _MMIO(0x91C0)
1073 #define OA_PERFCNT2_HI      _MMIO(0x91C4)
1074 #define OA_PERFCNT3_LO      _MMIO(0x91C8)
1075 #define OA_PERFCNT3_HI      _MMIO(0x91CC)
1076 #define OA_PERFCNT4_LO      _MMIO(0x91D8)
1077 #define OA_PERFCNT4_HI      _MMIO(0x91DC)
1078
1079 #define OA_PERFMATRIX_LO    _MMIO(0x91C8)
1080 #define OA_PERFMATRIX_HI    _MMIO(0x91CC)
1081
1082 /* RPM unit config (Gen8+) */
1083 #define RPM_CONFIG0         _MMIO(0x0D00)
1084 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT      3
1085 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK       (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1086 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ   0
1087 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ     1
1088 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT     3
1089 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK      (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1090 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ    0
1091 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ  1
1092 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ  2
1093 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ    3
1094 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT    1
1095 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK     (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1096
1097 #define RPM_CONFIG1         _MMIO(0x0D04)
1098 #define  GEN10_GT_NOA_ENABLE  (1 << 9)
1099
1100 /* GPM unit config (Gen9+) */
1101 #define CTC_MODE                        _MMIO(0xA26C)
1102 #define  CTC_SOURCE_PARAMETER_MASK 1
1103 #define  CTC_SOURCE_CRYSTAL_CLOCK       0
1104 #define  CTC_SOURCE_DIVIDE_LOGIC        1
1105 #define  CTC_SHIFT_PARAMETER_SHIFT      1
1106 #define  CTC_SHIFT_PARAMETER_MASK       (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1107
1108 /* RCP unit config (Gen8+) */
1109 #define RCP_CONFIG          _MMIO(0x0D08)
1110
1111 /* NOA (HSW) */
1112 #define HSW_MBVID2_NOA0         _MMIO(0x9E80)
1113 #define HSW_MBVID2_NOA1         _MMIO(0x9E84)
1114 #define HSW_MBVID2_NOA2         _MMIO(0x9E88)
1115 #define HSW_MBVID2_NOA3         _MMIO(0x9E8C)
1116 #define HSW_MBVID2_NOA4         _MMIO(0x9E90)
1117 #define HSW_MBVID2_NOA5         _MMIO(0x9E94)
1118 #define HSW_MBVID2_NOA6         _MMIO(0x9E98)
1119 #define HSW_MBVID2_NOA7         _MMIO(0x9E9C)
1120 #define HSW_MBVID2_NOA8         _MMIO(0x9EA0)
1121 #define HSW_MBVID2_NOA9         _MMIO(0x9EA4)
1122
1123 #define HSW_MBVID2_MISR0        _MMIO(0x9EC0)
1124
1125 /* NOA (Gen8+) */
1126 #define NOA_CONFIG(i)       _MMIO(0x0D0C + (i) * 4)
1127
1128 #define MICRO_BP0_0         _MMIO(0x9800)
1129 #define MICRO_BP0_2         _MMIO(0x9804)
1130 #define MICRO_BP0_1         _MMIO(0x9808)
1131
1132 #define MICRO_BP1_0         _MMIO(0x980C)
1133 #define MICRO_BP1_2         _MMIO(0x9810)
1134 #define MICRO_BP1_1         _MMIO(0x9814)
1135
1136 #define MICRO_BP2_0         _MMIO(0x9818)
1137 #define MICRO_BP2_2         _MMIO(0x981C)
1138 #define MICRO_BP2_1         _MMIO(0x9820)
1139
1140 #define MICRO_BP3_0         _MMIO(0x9824)
1141 #define MICRO_BP3_2         _MMIO(0x9828)
1142 #define MICRO_BP3_1         _MMIO(0x982C)
1143
1144 #define MICRO_BP_TRIGGER                _MMIO(0x9830)
1145 #define MICRO_BP3_COUNT_STATUS01        _MMIO(0x9834)
1146 #define MICRO_BP3_COUNT_STATUS23        _MMIO(0x9838)
1147 #define MICRO_BP_FIRED_ARMED            _MMIO(0x983C)
1148
1149 #define GEN12_OAA_DBG_REG _MMIO(0xdc44)
1150 #define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
1151 #define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
1152
1153 #define GDT_CHICKEN_BITS    _MMIO(0x9840)
1154 #define   GT_NOA_ENABLE     0x00000080
1155
1156 #define NOA_DATA            _MMIO(0x986C)
1157 #define NOA_WRITE           _MMIO(0x9888)
1158 #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
1159
1160 #define _GEN7_PIPEA_DE_LOAD_SL  0x70068
1161 #define _GEN7_PIPEB_DE_LOAD_SL  0x71068
1162 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
1163
1164 /*
1165  * Reset registers
1166  */
1167 #define DEBUG_RESET_I830                _MMIO(0x6070)
1168 #define  DEBUG_RESET_FULL               (1 << 7)
1169 #define  DEBUG_RESET_RENDER             (1 << 8)
1170 #define  DEBUG_RESET_DISPLAY            (1 << 9)
1171
1172 /*
1173  * IOSF sideband
1174  */
1175 #define VLV_IOSF_DOORBELL_REQ                   _MMIO(VLV_DISPLAY_BASE + 0x2100)
1176 #define   IOSF_DEVFN_SHIFT                      24
1177 #define   IOSF_OPCODE_SHIFT                     16
1178 #define   IOSF_PORT_SHIFT                       8
1179 #define   IOSF_BYTE_ENABLES_SHIFT               4
1180 #define   IOSF_BAR_SHIFT                        1
1181 #define   IOSF_SB_BUSY                          (1 << 0)
1182 #define   IOSF_PORT_BUNIT                       0x03
1183 #define   IOSF_PORT_PUNIT                       0x04
1184 #define   IOSF_PORT_NC                          0x11
1185 #define   IOSF_PORT_DPIO                        0x12
1186 #define   IOSF_PORT_GPIO_NC                     0x13
1187 #define   IOSF_PORT_CCK                         0x14
1188 #define   IOSF_PORT_DPIO_2                      0x1a
1189 #define   IOSF_PORT_FLISDSI                     0x1b
1190 #define   IOSF_PORT_GPIO_SC                     0x48
1191 #define   IOSF_PORT_GPIO_SUS                    0xa8
1192 #define   IOSF_PORT_CCU                         0xa9
1193 #define   CHV_IOSF_PORT_GPIO_N                  0x13
1194 #define   CHV_IOSF_PORT_GPIO_SE                 0x48
1195 #define   CHV_IOSF_PORT_GPIO_E                  0xa8
1196 #define   CHV_IOSF_PORT_GPIO_SW                 0xb2
1197 #define VLV_IOSF_DATA                           _MMIO(VLV_DISPLAY_BASE + 0x2104)
1198 #define VLV_IOSF_ADDR                           _MMIO(VLV_DISPLAY_BASE + 0x2108)
1199
1200 /* See configdb bunit SB addr map */
1201 #define BUNIT_REG_BISOC                         0x11
1202
1203 /* PUNIT_REG_*SSPM0 */
1204 #define   _SSPM0_SSC(val)                       ((val) << 0)
1205 #define   SSPM0_SSC_MASK                        _SSPM0_SSC(0x3)
1206 #define   SSPM0_SSC_PWR_ON                      _SSPM0_SSC(0x0)
1207 #define   SSPM0_SSC_CLK_GATE                    _SSPM0_SSC(0x1)
1208 #define   SSPM0_SSC_RESET                       _SSPM0_SSC(0x2)
1209 #define   SSPM0_SSC_PWR_GATE                    _SSPM0_SSC(0x3)
1210 #define   _SSPM0_SSS(val)                       ((val) << 24)
1211 #define   SSPM0_SSS_MASK                        _SSPM0_SSS(0x3)
1212 #define   SSPM0_SSS_PWR_ON                      _SSPM0_SSS(0x0)
1213 #define   SSPM0_SSS_CLK_GATE                    _SSPM0_SSS(0x1)
1214 #define   SSPM0_SSS_RESET                       _SSPM0_SSS(0x2)
1215 #define   SSPM0_SSS_PWR_GATE                    _SSPM0_SSS(0x3)
1216
1217 /* PUNIT_REG_*SSPM1 */
1218 #define   SSPM1_FREQSTAT_SHIFT                  24
1219 #define   SSPM1_FREQSTAT_MASK                   (0x1f << SSPM1_FREQSTAT_SHIFT)
1220 #define   SSPM1_FREQGUAR_SHIFT                  8
1221 #define   SSPM1_FREQGUAR_MASK                   (0x1f << SSPM1_FREQGUAR_SHIFT)
1222 #define   SSPM1_FREQ_SHIFT                      0
1223 #define   SSPM1_FREQ_MASK                       (0x1f << SSPM1_FREQ_SHIFT)
1224
1225 #define PUNIT_REG_VEDSSPM0                      0x32
1226 #define PUNIT_REG_VEDSSPM1                      0x33
1227
1228 #define PUNIT_REG_DSPSSPM                       0x36
1229 #define   DSPFREQSTAT_SHIFT_CHV                 24
1230 #define   DSPFREQSTAT_MASK_CHV                  (0x1f << DSPFREQSTAT_SHIFT_CHV)
1231 #define   DSPFREQGUAR_SHIFT_CHV                 8
1232 #define   DSPFREQGUAR_MASK_CHV                  (0x1f << DSPFREQGUAR_SHIFT_CHV)
1233 #define   DSPFREQSTAT_SHIFT                     30
1234 #define   DSPFREQSTAT_MASK                      (0x3 << DSPFREQSTAT_SHIFT)
1235 #define   DSPFREQGUAR_SHIFT                     14
1236 #define   DSPFREQGUAR_MASK                      (0x3 << DSPFREQGUAR_SHIFT)
1237 #define   DSP_MAXFIFO_PM5_STATUS                (1 << 22) /* chv */
1238 #define   DSP_AUTO_CDCLK_GATE_DISABLE           (1 << 7) /* chv */
1239 #define   DSP_MAXFIFO_PM5_ENABLE                (1 << 6) /* chv */
1240 #define   _DP_SSC(val, pipe)                    ((val) << (2 * (pipe)))
1241 #define   DP_SSC_MASK(pipe)                     _DP_SSC(0x3, (pipe))
1242 #define   DP_SSC_PWR_ON(pipe)                   _DP_SSC(0x0, (pipe))
1243 #define   DP_SSC_CLK_GATE(pipe)                 _DP_SSC(0x1, (pipe))
1244 #define   DP_SSC_RESET(pipe)                    _DP_SSC(0x2, (pipe))
1245 #define   DP_SSC_PWR_GATE(pipe)                 _DP_SSC(0x3, (pipe))
1246 #define   _DP_SSS(val, pipe)                    ((val) << (2 * (pipe) + 16))
1247 #define   DP_SSS_MASK(pipe)                     _DP_SSS(0x3, (pipe))
1248 #define   DP_SSS_PWR_ON(pipe)                   _DP_SSS(0x0, (pipe))
1249 #define   DP_SSS_CLK_GATE(pipe)                 _DP_SSS(0x1, (pipe))
1250 #define   DP_SSS_RESET(pipe)                    _DP_SSS(0x2, (pipe))
1251 #define   DP_SSS_PWR_GATE(pipe)                 _DP_SSS(0x3, (pipe))
1252
1253 #define PUNIT_REG_ISPSSPM0                      0x39
1254 #define PUNIT_REG_ISPSSPM1                      0x3a
1255
1256 #define PUNIT_REG_PWRGT_CTRL                    0x60
1257 #define PUNIT_REG_PWRGT_STATUS                  0x61
1258 #define   PUNIT_PWRGT_MASK(pw_idx)              (3 << ((pw_idx) * 2))
1259 #define   PUNIT_PWRGT_PWR_ON(pw_idx)            (0 << ((pw_idx) * 2))
1260 #define   PUNIT_PWRGT_CLK_GATE(pw_idx)          (1 << ((pw_idx) * 2))
1261 #define   PUNIT_PWRGT_RESET(pw_idx)             (2 << ((pw_idx) * 2))
1262 #define   PUNIT_PWRGT_PWR_GATE(pw_idx)          (3 << ((pw_idx) * 2))
1263
1264 #define PUNIT_PWGT_IDX_RENDER                   0
1265 #define PUNIT_PWGT_IDX_MEDIA                    1
1266 #define PUNIT_PWGT_IDX_DISP2D                   3
1267 #define PUNIT_PWGT_IDX_DPIO_CMN_BC              5
1268 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01       6
1269 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23       7
1270 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01       8
1271 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23       9
1272 #define PUNIT_PWGT_IDX_DPIO_RX0                 10
1273 #define PUNIT_PWGT_IDX_DPIO_RX1                 11
1274 #define PUNIT_PWGT_IDX_DPIO_CMN_D               12
1275
1276 #define PUNIT_REG_GPU_LFM                       0xd3
1277 #define PUNIT_REG_GPU_FREQ_REQ                  0xd4
1278 #define PUNIT_REG_GPU_FREQ_STS                  0xd8
1279 #define   GPLLENABLE                            (1 << 4)
1280 #define   GENFREQSTATUS                         (1 << 0)
1281 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ          0xdc
1282 #define PUNIT_REG_CZ_TIMESTAMP                  0xce
1283
1284 #define PUNIT_FUSE_BUS2                         0xf6 /* bits 47:40 */
1285 #define PUNIT_FUSE_BUS1                         0xf5 /* bits 55:48 */
1286
1287 #define FB_GFX_FMAX_AT_VMAX_FUSE                0x136
1288 #define FB_GFX_FREQ_FUSE_MASK                   0xff
1289 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT   24
1290 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT   16
1291 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT   8
1292
1293 #define FB_GFX_FMIN_AT_VMIN_FUSE                0x137
1294 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT          8
1295
1296 #define PUNIT_REG_DDR_SETUP2                    0x139
1297 #define   FORCE_DDR_FREQ_REQ_ACK                (1 << 8)
1298 #define   FORCE_DDR_LOW_FREQ                    (1 << 1)
1299 #define   FORCE_DDR_HIGH_FREQ                   (1 << 0)
1300
1301 #define PUNIT_GPU_STATUS_REG                    0xdb
1302 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1303 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK          0xff
1304 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT     8
1305 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK      0xff
1306
1307 #define PUNIT_GPU_DUTYCYCLE_REG         0xdf
1308 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT      8
1309 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK       0xff
1310
1311 #define IOSF_NC_FB_GFX_FREQ_FUSE                0x1c
1312 #define   FB_GFX_MAX_FREQ_FUSE_SHIFT            3
1313 #define   FB_GFX_MAX_FREQ_FUSE_MASK             0x000007f8
1314 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT    11
1315 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK     0x0007f800
1316 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI             0x34
1317 #define   FB_FMAX_VMIN_FREQ_HI_MASK             0x00000007
1318 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO             0x30
1319 #define   FB_FMAX_VMIN_FREQ_LO_SHIFT            27
1320 #define   FB_FMAX_VMIN_FREQ_LO_MASK             0xf8000000
1321
1322 #define VLV_TURBO_SOC_OVERRIDE          0x04
1323 #define   VLV_OVERRIDE_EN               1
1324 #define   VLV_SOC_TDP_EN                (1 << 1)
1325 #define   VLV_BIAS_CPU_125_SOC_875      (6 << 2)
1326 #define   CHV_BIAS_CPU_50_SOC_50        (3 << 2)
1327
1328 /* vlv2 north clock has */
1329 #define CCK_FUSE_REG                            0x8
1330 #define  CCK_FUSE_HPLL_FREQ_MASK                0x3
1331 #define CCK_REG_DSI_PLL_FUSE                    0x44
1332 #define CCK_REG_DSI_PLL_CONTROL                 0x48
1333 #define  DSI_PLL_VCO_EN                         (1 << 31)
1334 #define  DSI_PLL_LDO_GATE                       (1 << 30)
1335 #define  DSI_PLL_P1_POST_DIV_SHIFT              17
1336 #define  DSI_PLL_P1_POST_DIV_MASK               (0x1ff << 17)
1337 #define  DSI_PLL_P2_MUX_DSI0_DIV2               (1 << 13)
1338 #define  DSI_PLL_P3_MUX_DSI1_DIV2               (1 << 12)
1339 #define  DSI_PLL_MUX_MASK                       (3 << 9)
1340 #define  DSI_PLL_MUX_DSI0_DSIPLL                (0 << 10)
1341 #define  DSI_PLL_MUX_DSI0_CCK                   (1 << 10)
1342 #define  DSI_PLL_MUX_DSI1_DSIPLL                (0 << 9)
1343 #define  DSI_PLL_MUX_DSI1_CCK                   (1 << 9)
1344 #define  DSI_PLL_CLK_GATE_MASK                  (0xf << 5)
1345 #define  DSI_PLL_CLK_GATE_DSI0_DSIPLL           (1 << 8)
1346 #define  DSI_PLL_CLK_GATE_DSI1_DSIPLL           (1 << 7)
1347 #define  DSI_PLL_CLK_GATE_DSI0_CCK              (1 << 6)
1348 #define  DSI_PLL_CLK_GATE_DSI1_CCK              (1 << 5)
1349 #define  DSI_PLL_LOCK                           (1 << 0)
1350 #define CCK_REG_DSI_PLL_DIVIDER                 0x4c
1351 #define  DSI_PLL_LFSR                           (1 << 31)
1352 #define  DSI_PLL_FRACTION_EN                    (1 << 30)
1353 #define  DSI_PLL_FRAC_COUNTER_SHIFT             27
1354 #define  DSI_PLL_FRAC_COUNTER_MASK              (7 << 27)
1355 #define  DSI_PLL_USYNC_CNT_SHIFT                18
1356 #define  DSI_PLL_USYNC_CNT_MASK                 (0x1ff << 18)
1357 #define  DSI_PLL_N1_DIV_SHIFT                   16
1358 #define  DSI_PLL_N1_DIV_MASK                    (3 << 16)
1359 #define  DSI_PLL_M1_DIV_SHIFT                   0
1360 #define  DSI_PLL_M1_DIV_MASK                    (0x1ff << 0)
1361 #define CCK_CZ_CLOCK_CONTROL                    0x62
1362 #define CCK_GPLL_CLOCK_CONTROL                  0x67
1363 #define CCK_DISPLAY_CLOCK_CONTROL               0x6b
1364 #define CCK_DISPLAY_REF_CLOCK_CONTROL           0x6c
1365 #define  CCK_TRUNK_FORCE_ON                     (1 << 17)
1366 #define  CCK_TRUNK_FORCE_OFF                    (1 << 16)
1367 #define  CCK_FREQUENCY_STATUS                   (0x1f << 8)
1368 #define  CCK_FREQUENCY_STATUS_SHIFT             8
1369 #define  CCK_FREQUENCY_VALUES                   (0x1f << 0)
1370
1371 /* DPIO registers */
1372 #define DPIO_DEVFN                      0
1373
1374 #define DPIO_CTL                        _MMIO(VLV_DISPLAY_BASE + 0x2110)
1375 #define  DPIO_MODSEL1                   (1 << 3) /* if ref clk b == 27 */
1376 #define  DPIO_MODSEL0                   (1 << 2) /* if ref clk a == 27 */
1377 #define  DPIO_SFR_BYPASS                (1 << 1)
1378 #define  DPIO_CMNRST                    (1 << 0)
1379
1380 #define DPIO_PHY(pipe)                  ((pipe) >> 1)
1381 #define DPIO_PHY_IOSF_PORT(phy)         (dev_priv->dpio_phy_iosf_port[phy])
1382
1383 /*
1384  * Per pipe/PLL DPIO regs
1385  */
1386 #define _VLV_PLL_DW3_CH0                0x800c
1387 #define   DPIO_POST_DIV_SHIFT           (28) /* 3 bits */
1388 #define   DPIO_POST_DIV_DAC             0
1389 #define   DPIO_POST_DIV_HDMIDP          1 /* DAC 225-400M rate */
1390 #define   DPIO_POST_DIV_LVDS1           2
1391 #define   DPIO_POST_DIV_LVDS2           3
1392 #define   DPIO_K_SHIFT                  (24) /* 4 bits */
1393 #define   DPIO_P1_SHIFT                 (21) /* 3 bits */
1394 #define   DPIO_P2_SHIFT                 (16) /* 5 bits */
1395 #define   DPIO_N_SHIFT                  (12) /* 4 bits */
1396 #define   DPIO_ENABLE_CALIBRATION       (1 << 11)
1397 #define   DPIO_M1DIV_SHIFT              (8) /* 3 bits */
1398 #define   DPIO_M2DIV_MASK               0xff
1399 #define _VLV_PLL_DW3_CH1                0x802c
1400 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1401
1402 #define _VLV_PLL_DW5_CH0                0x8014
1403 #define   DPIO_REFSEL_OVERRIDE          27
1404 #define   DPIO_PLL_MODESEL_SHIFT        24 /* 3 bits */
1405 #define   DPIO_BIAS_CURRENT_CTL_SHIFT   21 /* 3 bits, always 0x7 */
1406 #define   DPIO_PLL_REFCLK_SEL_SHIFT     16 /* 2 bits */
1407 #define   DPIO_PLL_REFCLK_SEL_MASK      3
1408 #define   DPIO_DRIVER_CTL_SHIFT         12 /* always set to 0x8 */
1409 #define   DPIO_CLK_BIAS_CTL_SHIFT       8 /* always set to 0x5 */
1410 #define _VLV_PLL_DW5_CH1                0x8034
1411 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1412
1413 #define _VLV_PLL_DW7_CH0                0x801c
1414 #define _VLV_PLL_DW7_CH1                0x803c
1415 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1416
1417 #define _VLV_PLL_DW8_CH0                0x8040
1418 #define _VLV_PLL_DW8_CH1                0x8060
1419 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1420
1421 #define VLV_PLL_DW9_BCAST               0xc044
1422 #define _VLV_PLL_DW9_CH0                0x8044
1423 #define _VLV_PLL_DW9_CH1                0x8064
1424 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1425
1426 #define _VLV_PLL_DW10_CH0               0x8048
1427 #define _VLV_PLL_DW10_CH1               0x8068
1428 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1429
1430 #define _VLV_PLL_DW11_CH0               0x804c
1431 #define _VLV_PLL_DW11_CH1               0x806c
1432 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1433
1434 /* Spec for ref block start counts at DW10 */
1435 #define VLV_REF_DW13                    0x80ac
1436
1437 #define VLV_CMN_DW0                     0x8100
1438
1439 /*
1440  * Per DDI channel DPIO regs
1441  */
1442
1443 #define _VLV_PCS_DW0_CH0                0x8200
1444 #define _VLV_PCS_DW0_CH1                0x8400
1445 #define   DPIO_PCS_TX_LANE2_RESET       (1 << 16)
1446 #define   DPIO_PCS_TX_LANE1_RESET       (1 << 7)
1447 #define   DPIO_LEFT_TXFIFO_RST_MASTER2  (1 << 4)
1448 #define   DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
1449 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1450
1451 #define _VLV_PCS01_DW0_CH0              0x200
1452 #define _VLV_PCS23_DW0_CH0              0x400
1453 #define _VLV_PCS01_DW0_CH1              0x2600
1454 #define _VLV_PCS23_DW0_CH1              0x2800
1455 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1456 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1457
1458 #define _VLV_PCS_DW1_CH0                0x8204
1459 #define _VLV_PCS_DW1_CH1                0x8404
1460 #define   CHV_PCS_REQ_SOFTRESET_EN      (1 << 23)
1461 #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
1462 #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
1463 #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT  (6)
1464 #define   DPIO_PCS_CLK_SOFT_RESET       (1 << 5)
1465 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1466
1467 #define _VLV_PCS01_DW1_CH0              0x204
1468 #define _VLV_PCS23_DW1_CH0              0x404
1469 #define _VLV_PCS01_DW1_CH1              0x2604
1470 #define _VLV_PCS23_DW1_CH1              0x2804
1471 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1472 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1473
1474 #define _VLV_PCS_DW8_CH0                0x8220
1475 #define _VLV_PCS_DW8_CH1                0x8420
1476 #define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE        (1 << 20)
1477 #define   CHV_PCS_USEDCLKCHANNEL                (1 << 21)
1478 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1479
1480 #define _VLV_PCS01_DW8_CH0              0x0220
1481 #define _VLV_PCS23_DW8_CH0              0x0420
1482 #define _VLV_PCS01_DW8_CH1              0x2620
1483 #define _VLV_PCS23_DW8_CH1              0x2820
1484 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1485 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1486
1487 #define _VLV_PCS_DW9_CH0                0x8224
1488 #define _VLV_PCS_DW9_CH1                0x8424
1489 #define   DPIO_PCS_TX2MARGIN_MASK       (0x7 << 13)
1490 #define   DPIO_PCS_TX2MARGIN_000        (0 << 13)
1491 #define   DPIO_PCS_TX2MARGIN_101        (1 << 13)
1492 #define   DPIO_PCS_TX1MARGIN_MASK       (0x7 << 10)
1493 #define   DPIO_PCS_TX1MARGIN_000        (0 << 10)
1494 #define   DPIO_PCS_TX1MARGIN_101        (1 << 10)
1495 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1496
1497 #define _VLV_PCS01_DW9_CH0              0x224
1498 #define _VLV_PCS23_DW9_CH0              0x424
1499 #define _VLV_PCS01_DW9_CH1              0x2624
1500 #define _VLV_PCS23_DW9_CH1              0x2824
1501 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1502 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1503
1504 #define _CHV_PCS_DW10_CH0               0x8228
1505 #define _CHV_PCS_DW10_CH1               0x8428
1506 #define   DPIO_PCS_SWING_CALC_TX0_TX2   (1 << 30)
1507 #define   DPIO_PCS_SWING_CALC_TX1_TX3   (1 << 31)
1508 #define   DPIO_PCS_TX2DEEMP_MASK        (0xf << 24)
1509 #define   DPIO_PCS_TX2DEEMP_9P5         (0 << 24)
1510 #define   DPIO_PCS_TX2DEEMP_6P0         (2 << 24)
1511 #define   DPIO_PCS_TX1DEEMP_MASK        (0xf << 16)
1512 #define   DPIO_PCS_TX1DEEMP_9P5         (0 << 16)
1513 #define   DPIO_PCS_TX1DEEMP_6P0         (2 << 16)
1514 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1515
1516 #define _VLV_PCS01_DW10_CH0             0x0228
1517 #define _VLV_PCS23_DW10_CH0             0x0428
1518 #define _VLV_PCS01_DW10_CH1             0x2628
1519 #define _VLV_PCS23_DW10_CH1             0x2828
1520 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1521 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1522
1523 #define _VLV_PCS_DW11_CH0               0x822c
1524 #define _VLV_PCS_DW11_CH1               0x842c
1525 #define   DPIO_TX2_STAGGER_MASK(x)      ((x) << 24)
1526 #define   DPIO_LANEDESKEW_STRAP_OVRD    (1 << 3)
1527 #define   DPIO_LEFT_TXFIFO_RST_MASTER   (1 << 1)
1528 #define   DPIO_RIGHT_TXFIFO_RST_MASTER  (1 << 0)
1529 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1530
1531 #define _VLV_PCS01_DW11_CH0             0x022c
1532 #define _VLV_PCS23_DW11_CH0             0x042c
1533 #define _VLV_PCS01_DW11_CH1             0x262c
1534 #define _VLV_PCS23_DW11_CH1             0x282c
1535 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1536 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1537
1538 #define _VLV_PCS01_DW12_CH0             0x0230
1539 #define _VLV_PCS23_DW12_CH0             0x0430
1540 #define _VLV_PCS01_DW12_CH1             0x2630
1541 #define _VLV_PCS23_DW12_CH1             0x2830
1542 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1543 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1544
1545 #define _VLV_PCS_DW12_CH0               0x8230
1546 #define _VLV_PCS_DW12_CH1               0x8430
1547 #define   DPIO_TX2_STAGGER_MULT(x)      ((x) << 20)
1548 #define   DPIO_TX1_STAGGER_MULT(x)      ((x) << 16)
1549 #define   DPIO_TX1_STAGGER_MASK(x)      ((x) << 8)
1550 #define   DPIO_LANESTAGGER_STRAP_OVRD   (1 << 6)
1551 #define   DPIO_LANESTAGGER_STRAP(x)     ((x) << 0)
1552 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1553
1554 #define _VLV_PCS_DW14_CH0               0x8238
1555 #define _VLV_PCS_DW14_CH1               0x8438
1556 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1557
1558 #define _VLV_PCS_DW23_CH0               0x825c
1559 #define _VLV_PCS_DW23_CH1               0x845c
1560 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1561
1562 #define _VLV_TX_DW2_CH0                 0x8288
1563 #define _VLV_TX_DW2_CH1                 0x8488
1564 #define   DPIO_SWING_MARGIN000_SHIFT    16
1565 #define   DPIO_SWING_MARGIN000_MASK     (0xff << DPIO_SWING_MARGIN000_SHIFT)
1566 #define   DPIO_UNIQ_TRANS_SCALE_SHIFT   8
1567 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1568
1569 #define _VLV_TX_DW3_CH0                 0x828c
1570 #define _VLV_TX_DW3_CH1                 0x848c
1571 /* The following bit for CHV phy */
1572 #define   DPIO_TX_UNIQ_TRANS_SCALE_EN   (1 << 27)
1573 #define   DPIO_SWING_MARGIN101_SHIFT    16
1574 #define   DPIO_SWING_MARGIN101_MASK     (0xff << DPIO_SWING_MARGIN101_SHIFT)
1575 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1576
1577 #define _VLV_TX_DW4_CH0                 0x8290
1578 #define _VLV_TX_DW4_CH1                 0x8490
1579 #define   DPIO_SWING_DEEMPH9P5_SHIFT    24
1580 #define   DPIO_SWING_DEEMPH9P5_MASK     (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1581 #define   DPIO_SWING_DEEMPH6P0_SHIFT    16
1582 #define   DPIO_SWING_DEEMPH6P0_MASK     (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1583 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1584
1585 #define _VLV_TX3_DW4_CH0                0x690
1586 #define _VLV_TX3_DW4_CH1                0x2a90
1587 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1588
1589 #define _VLV_TX_DW5_CH0                 0x8294
1590 #define _VLV_TX_DW5_CH1                 0x8494
1591 #define   DPIO_TX_OCALINIT_EN           (1 << 31)
1592 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1593
1594 #define _VLV_TX_DW11_CH0                0x82ac
1595 #define _VLV_TX_DW11_CH1                0x84ac
1596 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1597
1598 #define _VLV_TX_DW14_CH0                0x82b8
1599 #define _VLV_TX_DW14_CH1                0x84b8
1600 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1601
1602 /* CHV dpPhy registers */
1603 #define _CHV_PLL_DW0_CH0                0x8000
1604 #define _CHV_PLL_DW0_CH1                0x8180
1605 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1606
1607 #define _CHV_PLL_DW1_CH0                0x8004
1608 #define _CHV_PLL_DW1_CH1                0x8184
1609 #define   DPIO_CHV_N_DIV_SHIFT          8
1610 #define   DPIO_CHV_M1_DIV_BY_2          (0 << 0)
1611 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1612
1613 #define _CHV_PLL_DW2_CH0                0x8008
1614 #define _CHV_PLL_DW2_CH1                0x8188
1615 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1616
1617 #define _CHV_PLL_DW3_CH0                0x800c
1618 #define _CHV_PLL_DW3_CH1                0x818c
1619 #define  DPIO_CHV_FRAC_DIV_EN           (1 << 16)
1620 #define  DPIO_CHV_FIRST_MOD             (0 << 8)
1621 #define  DPIO_CHV_SECOND_MOD            (1 << 8)
1622 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT    0
1623 #define  DPIO_CHV_FEEDFWD_GAIN_MASK             (0xF << 0)
1624 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1625
1626 #define _CHV_PLL_DW6_CH0                0x8018
1627 #define _CHV_PLL_DW6_CH1                0x8198
1628 #define   DPIO_CHV_GAIN_CTRL_SHIFT      16
1629 #define   DPIO_CHV_INT_COEFF_SHIFT      8
1630 #define   DPIO_CHV_PROP_COEFF_SHIFT     0
1631 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1632
1633 #define _CHV_PLL_DW8_CH0                0x8020
1634 #define _CHV_PLL_DW8_CH1                0x81A0
1635 #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1636 #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
1637 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1638
1639 #define _CHV_PLL_DW9_CH0                0x8024
1640 #define _CHV_PLL_DW9_CH1                0x81A4
1641 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT              1 /* 3 bits */
1642 #define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK               (7 << 1)
1643 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine  */
1644 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1645
1646 #define _CHV_CMN_DW0_CH0               0x8100
1647 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0        19
1648 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0        18
1649 #define   DPIO_ALLDL_POWERDOWN                  (1 << 1)
1650 #define   DPIO_ANYDL_POWERDOWN                  (1 << 0)
1651
1652 #define _CHV_CMN_DW5_CH0               0x8114
1653 #define   CHV_BUFRIGHTENA1_DISABLE      (0 << 20)
1654 #define   CHV_BUFRIGHTENA1_NORMAL       (1 << 20)
1655 #define   CHV_BUFRIGHTENA1_FORCE        (3 << 20)
1656 #define   CHV_BUFRIGHTENA1_MASK         (3 << 20)
1657 #define   CHV_BUFLEFTENA1_DISABLE       (0 << 22)
1658 #define   CHV_BUFLEFTENA1_NORMAL        (1 << 22)
1659 #define   CHV_BUFLEFTENA1_FORCE         (3 << 22)
1660 #define   CHV_BUFLEFTENA1_MASK          (3 << 22)
1661
1662 #define _CHV_CMN_DW13_CH0               0x8134
1663 #define _CHV_CMN_DW0_CH1                0x8080
1664 #define   DPIO_CHV_S1_DIV_SHIFT         21
1665 #define   DPIO_CHV_P1_DIV_SHIFT         13 /* 3 bits */
1666 #define   DPIO_CHV_P2_DIV_SHIFT         8  /* 5 bits */
1667 #define   DPIO_CHV_K_DIV_SHIFT          4
1668 #define   DPIO_PLL_FREQLOCK             (1 << 1)
1669 #define   DPIO_PLL_LOCK                 (1 << 0)
1670 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1671
1672 #define _CHV_CMN_DW14_CH0               0x8138
1673 #define _CHV_CMN_DW1_CH1                0x8084
1674 #define   DPIO_AFC_RECAL                (1 << 14)
1675 #define   DPIO_DCLKP_EN                 (1 << 13)
1676 #define   CHV_BUFLEFTENA2_DISABLE       (0 << 17) /* CL2 DW1 only */
1677 #define   CHV_BUFLEFTENA2_NORMAL        (1 << 17) /* CL2 DW1 only */
1678 #define   CHV_BUFLEFTENA2_FORCE         (3 << 17) /* CL2 DW1 only */
1679 #define   CHV_BUFLEFTENA2_MASK          (3 << 17) /* CL2 DW1 only */
1680 #define   CHV_BUFRIGHTENA2_DISABLE      (0 << 19) /* CL2 DW1 only */
1681 #define   CHV_BUFRIGHTENA2_NORMAL       (1 << 19) /* CL2 DW1 only */
1682 #define   CHV_BUFRIGHTENA2_FORCE        (3 << 19) /* CL2 DW1 only */
1683 #define   CHV_BUFRIGHTENA2_MASK         (3 << 19) /* CL2 DW1 only */
1684 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1685
1686 #define _CHV_CMN_DW19_CH0               0x814c
1687 #define _CHV_CMN_DW6_CH1                0x8098
1688 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1        30 /* CL2 DW6 only */
1689 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1        29 /* CL2 DW6 only */
1690 #define   DPIO_DYNPWRDOWNEN_CH1         (1 << 28) /* CL2 DW6 only */
1691 #define   CHV_CMN_USEDCLKCHANNEL        (1 << 13)
1692
1693 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1694
1695 #define CHV_CMN_DW28                    0x8170
1696 #define   DPIO_CL1POWERDOWNEN           (1 << 23)
1697 #define   DPIO_DYNPWRDOWNEN_CH0         (1 << 22)
1698 #define   DPIO_SUS_CLK_CONFIG_ON                (0 << 0)
1699 #define   DPIO_SUS_CLK_CONFIG_CLKREQ            (1 << 0)
1700 #define   DPIO_SUS_CLK_CONFIG_GATE              (2 << 0)
1701 #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ       (3 << 0)
1702
1703 #define CHV_CMN_DW30                    0x8178
1704 #define   DPIO_CL2_LDOFUSE_PWRENB       (1 << 6)
1705 #define   DPIO_LRC_BYPASS               (1 << 3)
1706
1707 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1708                                         (lane) * 0x200 + (offset))
1709
1710 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1711 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1712 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1713 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1714 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1715 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1716 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1717 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1718 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1719 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1720 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1721 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1722 #define   DPIO_FRC_LATENCY_SHFIT        8
1723 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1724 #define   DPIO_UPAR_SHIFT               30
1725
1726 /* BXT PHY registers */
1727 #define _BXT_PHY0_BASE                  0x6C000
1728 #define _BXT_PHY1_BASE                  0x162000
1729 #define _BXT_PHY2_BASE                  0x163000
1730 #define BXT_PHY_BASE(phy)               _PHY3((phy), _BXT_PHY0_BASE, \
1731                                                      _BXT_PHY1_BASE, \
1732                                                      _BXT_PHY2_BASE)
1733
1734 #define _BXT_PHY(phy, reg)                                              \
1735         _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1736
1737 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)          \
1738         (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE,    \
1739                                          (reg_ch1) - _BXT_PHY0_BASE))
1740 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)             \
1741         _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1742
1743 #define BXT_P_CR_GT_DISP_PWRON          _MMIO(0x138090)
1744 #define  MIPIO_RST_CTRL                         (1 << 2)
1745
1746 #define _BXT_PHY_CTL_DDI_A              0x64C00
1747 #define _BXT_PHY_CTL_DDI_B              0x64C10
1748 #define _BXT_PHY_CTL_DDI_C              0x64C20
1749 #define   BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1750 #define   BXT_PHY_LANE_POWERDOWN_ACK    (1 << 9)
1751 #define   BXT_PHY_LANE_ENABLED          (1 << 8)
1752 #define BXT_PHY_CTL(port)               _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1753                                                          _BXT_PHY_CTL_DDI_B)
1754
1755 #define _PHY_CTL_FAMILY_EDP             0x64C80
1756 #define _PHY_CTL_FAMILY_DDI             0x64C90
1757 #define _PHY_CTL_FAMILY_DDI_C           0x64CA0
1758 #define   COMMON_RESET_DIS              (1 << 31)
1759 #define BXT_PHY_CTL_FAMILY(phy)         _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1760                                                           _PHY_CTL_FAMILY_EDP, \
1761                                                           _PHY_CTL_FAMILY_DDI_C)
1762
1763 /* BXT PHY PLL registers */
1764 #define _PORT_PLL_A                     0x46074
1765 #define _PORT_PLL_B                     0x46078
1766 #define _PORT_PLL_C                     0x4607c
1767 #define   PORT_PLL_ENABLE               (1 << 31)
1768 #define   PORT_PLL_LOCK                 (1 << 30)
1769 #define   PORT_PLL_REF_SEL              (1 << 27)
1770 #define   PORT_PLL_POWER_ENABLE         (1 << 26)
1771 #define   PORT_PLL_POWER_STATE          (1 << 25)
1772 #define BXT_PORT_PLL_ENABLE(port)       _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1773
1774 #define _PORT_PLL_EBB_0_A               0x162034
1775 #define _PORT_PLL_EBB_0_B               0x6C034
1776 #define _PORT_PLL_EBB_0_C               0x6C340
1777 #define   PORT_PLL_P1_SHIFT             13
1778 #define   PORT_PLL_P1_MASK              (0x07 << PORT_PLL_P1_SHIFT)
1779 #define   PORT_PLL_P1(x)                ((x)  << PORT_PLL_P1_SHIFT)
1780 #define   PORT_PLL_P2_SHIFT             8
1781 #define   PORT_PLL_P2_MASK              (0x1f << PORT_PLL_P2_SHIFT)
1782 #define   PORT_PLL_P2(x)                ((x)  << PORT_PLL_P2_SHIFT)
1783 #define BXT_PORT_PLL_EBB_0(phy, ch)     _MMIO_BXT_PHY_CH(phy, ch, \
1784                                                          _PORT_PLL_EBB_0_B, \
1785                                                          _PORT_PLL_EBB_0_C)
1786
1787 #define _PORT_PLL_EBB_4_A               0x162038
1788 #define _PORT_PLL_EBB_4_B               0x6C038
1789 #define _PORT_PLL_EBB_4_C               0x6C344
1790 #define   PORT_PLL_10BIT_CLK_ENABLE     (1 << 13)
1791 #define   PORT_PLL_RECALIBRATE          (1 << 14)
1792 #define BXT_PORT_PLL_EBB_4(phy, ch)     _MMIO_BXT_PHY_CH(phy, ch, \
1793                                                          _PORT_PLL_EBB_4_B, \
1794                                                          _PORT_PLL_EBB_4_C)
1795
1796 #define _PORT_PLL_0_A                   0x162100
1797 #define _PORT_PLL_0_B                   0x6C100
1798 #define _PORT_PLL_0_C                   0x6C380
1799 /* PORT_PLL_0_A */
1800 #define   PORT_PLL_M2_MASK              0xFF
1801 /* PORT_PLL_1_A */
1802 #define   PORT_PLL_N_SHIFT              8
1803 #define   PORT_PLL_N_MASK               (0x0F << PORT_PLL_N_SHIFT)
1804 #define   PORT_PLL_N(x)                 ((x) << PORT_PLL_N_SHIFT)
1805 /* PORT_PLL_2_A */
1806 #define   PORT_PLL_M2_FRAC_MASK         0x3FFFFF
1807 /* PORT_PLL_3_A */
1808 #define   PORT_PLL_M2_FRAC_ENABLE       (1 << 16)
1809 /* PORT_PLL_6_A */
1810 #define   PORT_PLL_PROP_COEFF_MASK      0xF
1811 #define   PORT_PLL_INT_COEFF_MASK       (0x1F << 8)
1812 #define   PORT_PLL_INT_COEFF(x)         ((x)  << 8)
1813 #define   PORT_PLL_GAIN_CTL_MASK        (0x07 << 16)
1814 #define   PORT_PLL_GAIN_CTL(x)          ((x)  << 16)
1815 /* PORT_PLL_8_A */
1816 #define   PORT_PLL_TARGET_CNT_MASK      0x3FF
1817 /* PORT_PLL_9_A */
1818 #define  PORT_PLL_LOCK_THRESHOLD_SHIFT  1
1819 #define  PORT_PLL_LOCK_THRESHOLD_MASK   (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1820 /* PORT_PLL_10_A */
1821 #define  PORT_PLL_DCO_AMP_OVR_EN_H      (1 << 27)
1822 #define  PORT_PLL_DCO_AMP_DEFAULT       15
1823 #define  PORT_PLL_DCO_AMP_MASK          0x3c00
1824 #define  PORT_PLL_DCO_AMP(x)            ((x) << 10)
1825 #define _PORT_PLL_BASE(phy, ch)         _BXT_PHY_CH(phy, ch, \
1826                                                     _PORT_PLL_0_B, \
1827                                                     _PORT_PLL_0_C)
1828 #define BXT_PORT_PLL(phy, ch, idx)      _MMIO(_PORT_PLL_BASE(phy, ch) + \
1829                                               (idx) * 4)
1830
1831 /* BXT PHY common lane registers */
1832 #define _PORT_CL1CM_DW0_A               0x162000
1833 #define _PORT_CL1CM_DW0_BC              0x6C000
1834 #define   PHY_POWER_GOOD                (1 << 16)
1835 #define   PHY_RESERVED                  (1 << 7)
1836 #define BXT_PORT_CL1CM_DW0(phy)         _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1837
1838 #define _PORT_CL1CM_DW9_A               0x162024
1839 #define _PORT_CL1CM_DW9_BC              0x6C024
1840 #define   IREF0RC_OFFSET_SHIFT          8
1841 #define   IREF0RC_OFFSET_MASK           (0xFF << IREF0RC_OFFSET_SHIFT)
1842 #define BXT_PORT_CL1CM_DW9(phy)         _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1843
1844 #define _PORT_CL1CM_DW10_A              0x162028
1845 #define _PORT_CL1CM_DW10_BC             0x6C028
1846 #define   IREF1RC_OFFSET_SHIFT          8
1847 #define   IREF1RC_OFFSET_MASK           (0xFF << IREF1RC_OFFSET_SHIFT)
1848 #define BXT_PORT_CL1CM_DW10(phy)        _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1849
1850 #define _PORT_CL1CM_DW28_A              0x162070
1851 #define _PORT_CL1CM_DW28_BC             0x6C070
1852 #define   OCL1_POWER_DOWN_EN            (1 << 23)
1853 #define   DW28_OLDO_DYN_PWR_DOWN_EN     (1 << 22)
1854 #define   SUS_CLK_CONFIG                0x3
1855 #define BXT_PORT_CL1CM_DW28(phy)        _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1856
1857 #define _PORT_CL1CM_DW30_A              0x162078
1858 #define _PORT_CL1CM_DW30_BC             0x6C078
1859 #define   OCL2_LDOFUSE_PWR_DIS          (1 << 6)
1860 #define BXT_PORT_CL1CM_DW30(phy)        _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1861
1862 /*
1863  * CNL/ICL Port/COMBO-PHY Registers
1864  */
1865 #define _ICL_COMBOPHY_A                 0x162000
1866 #define _ICL_COMBOPHY_B                 0x6C000
1867 #define _EHL_COMBOPHY_C                 0x160000
1868 #define _ICL_COMBOPHY(phy)              _PICK(phy, _ICL_COMBOPHY_A, \
1869                                               _ICL_COMBOPHY_B, \
1870                                               _EHL_COMBOPHY_C)
1871
1872 /* CNL/ICL Port CL_DW registers */
1873 #define _ICL_PORT_CL_DW(dw, phy)        (_ICL_COMBOPHY(phy) + \
1874                                          4 * (dw))
1875
1876 #define CNL_PORT_CL1CM_DW5              _MMIO(0x162014)
1877 #define ICL_PORT_CL_DW5(phy)            _MMIO(_ICL_PORT_CL_DW(5, phy))
1878 #define   CL_POWER_DOWN_ENABLE          (1 << 4)
1879 #define   SUS_CLOCK_CONFIG              (3 << 0)
1880
1881 #define ICL_PORT_CL_DW10(phy)           _MMIO(_ICL_PORT_CL_DW(10, phy))
1882 #define  PG_SEQ_DELAY_OVERRIDE_MASK     (3 << 25)
1883 #define  PG_SEQ_DELAY_OVERRIDE_SHIFT    25
1884 #define  PG_SEQ_DELAY_OVERRIDE_ENABLE   (1 << 24)
1885 #define  PWR_UP_ALL_LANES               (0x0 << 4)
1886 #define  PWR_DOWN_LN_3_2_1              (0xe << 4)
1887 #define  PWR_DOWN_LN_3_2                (0xc << 4)
1888 #define  PWR_DOWN_LN_3                  (0x8 << 4)
1889 #define  PWR_DOWN_LN_2_1_0              (0x7 << 4)
1890 #define  PWR_DOWN_LN_1_0                (0x3 << 4)
1891 #define  PWR_DOWN_LN_3_1                (0xa << 4)
1892 #define  PWR_DOWN_LN_3_1_0              (0xb << 4)
1893 #define  PWR_DOWN_LN_MASK               (0xf << 4)
1894 #define  PWR_DOWN_LN_SHIFT              4
1895
1896 #define ICL_PORT_CL_DW12(phy)           _MMIO(_ICL_PORT_CL_DW(12, phy))
1897 #define   ICL_LANE_ENABLE_AUX           (1 << 0)
1898
1899 /* CNL/ICL Port COMP_DW registers */
1900 #define _ICL_PORT_COMP                  0x100
1901 #define _ICL_PORT_COMP_DW(dw, phy)      (_ICL_COMBOPHY(phy) + \
1902                                          _ICL_PORT_COMP + 4 * (dw))
1903
1904 #define CNL_PORT_COMP_DW0               _MMIO(0x162100)
1905 #define ICL_PORT_COMP_DW0(phy)          _MMIO(_ICL_PORT_COMP_DW(0, phy))
1906 #define   COMP_INIT                     (1 << 31)
1907
1908 #define CNL_PORT_COMP_DW1               _MMIO(0x162104)
1909 #define ICL_PORT_COMP_DW1(phy)          _MMIO(_ICL_PORT_COMP_DW(1, phy))
1910
1911 #define CNL_PORT_COMP_DW3               _MMIO(0x16210c)
1912 #define ICL_PORT_COMP_DW3(phy)          _MMIO(_ICL_PORT_COMP_DW(3, phy))
1913 #define   PROCESS_INFO_DOT_0            (0 << 26)
1914 #define   PROCESS_INFO_DOT_1            (1 << 26)
1915 #define   PROCESS_INFO_DOT_4            (2 << 26)
1916 #define   PROCESS_INFO_MASK             (7 << 26)
1917 #define   PROCESS_INFO_SHIFT            26
1918 #define   VOLTAGE_INFO_0_85V            (0 << 24)
1919 #define   VOLTAGE_INFO_0_95V            (1 << 24)
1920 #define   VOLTAGE_INFO_1_05V            (2 << 24)
1921 #define   VOLTAGE_INFO_MASK             (3 << 24)
1922 #define   VOLTAGE_INFO_SHIFT            24
1923
1924 #define ICL_PORT_COMP_DW8(phy)          _MMIO(_ICL_PORT_COMP_DW(8, phy))
1925 #define   IREFGEN                       (1 << 24)
1926
1927 #define CNL_PORT_COMP_DW9               _MMIO(0x162124)
1928 #define ICL_PORT_COMP_DW9(phy)          _MMIO(_ICL_PORT_COMP_DW(9, phy))
1929
1930 #define CNL_PORT_COMP_DW10              _MMIO(0x162128)
1931 #define ICL_PORT_COMP_DW10(phy)         _MMIO(_ICL_PORT_COMP_DW(10, phy))
1932
1933 /* CNL/ICL Port PCS registers */
1934 #define _CNL_PORT_PCS_DW1_GRP_AE        0x162304
1935 #define _CNL_PORT_PCS_DW1_GRP_B         0x162384
1936 #define _CNL_PORT_PCS_DW1_GRP_C         0x162B04
1937 #define _CNL_PORT_PCS_DW1_GRP_D         0x162B84
1938 #define _CNL_PORT_PCS_DW1_GRP_F         0x162A04
1939 #define _CNL_PORT_PCS_DW1_LN0_AE        0x162404
1940 #define _CNL_PORT_PCS_DW1_LN0_B         0x162604
1941 #define _CNL_PORT_PCS_DW1_LN0_C         0x162C04
1942 #define _CNL_PORT_PCS_DW1_LN0_D         0x162E04
1943 #define _CNL_PORT_PCS_DW1_LN0_F         0x162804
1944 #define CNL_PORT_PCS_DW1_GRP(phy)       _MMIO(_PICK(phy, \
1945                                                     _CNL_PORT_PCS_DW1_GRP_AE, \
1946                                                     _CNL_PORT_PCS_DW1_GRP_B, \
1947                                                     _CNL_PORT_PCS_DW1_GRP_C, \
1948                                                     _CNL_PORT_PCS_DW1_GRP_D, \
1949                                                     _CNL_PORT_PCS_DW1_GRP_AE, \
1950                                                     _CNL_PORT_PCS_DW1_GRP_F))
1951 #define CNL_PORT_PCS_DW1_LN0(phy)       _MMIO(_PICK(phy, \
1952                                                     _CNL_PORT_PCS_DW1_LN0_AE, \
1953                                                     _CNL_PORT_PCS_DW1_LN0_B, \
1954                                                     _CNL_PORT_PCS_DW1_LN0_C, \
1955                                                     _CNL_PORT_PCS_DW1_LN0_D, \
1956                                                     _CNL_PORT_PCS_DW1_LN0_AE, \
1957                                                     _CNL_PORT_PCS_DW1_LN0_F))
1958
1959 #define _ICL_PORT_PCS_AUX               0x300
1960 #define _ICL_PORT_PCS_GRP               0x600
1961 #define _ICL_PORT_PCS_LN(ln)            (0x800 + (ln) * 0x100)
1962 #define _ICL_PORT_PCS_DW_AUX(dw, phy)   (_ICL_COMBOPHY(phy) + \
1963                                          _ICL_PORT_PCS_AUX + 4 * (dw))
1964 #define _ICL_PORT_PCS_DW_GRP(dw, phy)   (_ICL_COMBOPHY(phy) + \
1965                                          _ICL_PORT_PCS_GRP + 4 * (dw))
1966 #define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1967                                           _ICL_PORT_PCS_LN(ln) + 4 * (dw))
1968 #define ICL_PORT_PCS_DW1_AUX(phy)       _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
1969 #define ICL_PORT_PCS_DW1_GRP(phy)       _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
1970 #define ICL_PORT_PCS_DW1_LN0(phy)       _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
1971 #define   COMMON_KEEPER_EN              (1 << 26)
1972 #define   LATENCY_OPTIM_MASK            (0x3 << 2)
1973 #define   LATENCY_OPTIM_VAL(x)          ((x) << 2)
1974
1975 /* CNL/ICL Port TX registers */
1976 #define _CNL_PORT_TX_AE_GRP_OFFSET              0x162340
1977 #define _CNL_PORT_TX_B_GRP_OFFSET               0x1623C0
1978 #define _CNL_PORT_TX_C_GRP_OFFSET               0x162B40
1979 #define _CNL_PORT_TX_D_GRP_OFFSET               0x162BC0
1980 #define _CNL_PORT_TX_F_GRP_OFFSET               0x162A40
1981 #define _CNL_PORT_TX_AE_LN0_OFFSET              0x162440
1982 #define _CNL_PORT_TX_B_LN0_OFFSET               0x162640
1983 #define _CNL_PORT_TX_C_LN0_OFFSET               0x162C40
1984 #define _CNL_PORT_TX_D_LN0_OFFSET               0x162E40
1985 #define _CNL_PORT_TX_F_LN0_OFFSET               0x162840
1986 #define _CNL_PORT_TX_DW_GRP(dw, port)   (_PICK((port), \
1987                                                _CNL_PORT_TX_AE_GRP_OFFSET, \
1988                                                _CNL_PORT_TX_B_GRP_OFFSET, \
1989                                                _CNL_PORT_TX_B_GRP_OFFSET, \
1990                                                _CNL_PORT_TX_D_GRP_OFFSET, \
1991                                                _CNL_PORT_TX_AE_GRP_OFFSET, \
1992                                                _CNL_PORT_TX_F_GRP_OFFSET) + \
1993                                                4 * (dw))
1994 #define _CNL_PORT_TX_DW_LN0(dw, port)   (_PICK((port), \
1995                                                _CNL_PORT_TX_AE_LN0_OFFSET, \
1996                                                _CNL_PORT_TX_B_LN0_OFFSET, \
1997                                                _CNL_PORT_TX_B_LN0_OFFSET, \
1998                                                _CNL_PORT_TX_D_LN0_OFFSET, \
1999                                                _CNL_PORT_TX_AE_LN0_OFFSET, \
2000                                                _CNL_PORT_TX_F_LN0_OFFSET) + \
2001                                                4 * (dw))
2002
2003 #define _ICL_PORT_TX_AUX                0x380
2004 #define _ICL_PORT_TX_GRP                0x680
2005 #define _ICL_PORT_TX_LN(ln)             (0x880 + (ln) * 0x100)
2006
2007 #define _ICL_PORT_TX_DW_AUX(dw, phy)    (_ICL_COMBOPHY(phy) + \
2008                                          _ICL_PORT_TX_AUX + 4 * (dw))
2009 #define _ICL_PORT_TX_DW_GRP(dw, phy)    (_ICL_COMBOPHY(phy) + \
2010                                          _ICL_PORT_TX_GRP + 4 * (dw))
2011 #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
2012                                           _ICL_PORT_TX_LN(ln) + 4 * (dw))
2013
2014 #define CNL_PORT_TX_DW2_GRP(port)       _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
2015 #define CNL_PORT_TX_DW2_LN0(port)       _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
2016 #define ICL_PORT_TX_DW2_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
2017 #define ICL_PORT_TX_DW2_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
2018 #define ICL_PORT_TX_DW2_LN0(phy)        _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
2019 #define   SWING_SEL_UPPER(x)            (((x) >> 3) << 15)
2020 #define   SWING_SEL_UPPER_MASK          (1 << 15)
2021 #define   SWING_SEL_LOWER(x)            (((x) & 0x7) << 11)
2022 #define   SWING_SEL_LOWER_MASK          (0x7 << 11)
2023 #define   FRC_LATENCY_OPTIM_MASK        (0x7 << 8)
2024 #define   FRC_LATENCY_OPTIM_VAL(x)      ((x) << 8)
2025 #define   RCOMP_SCALAR(x)               ((x) << 0)
2026 #define   RCOMP_SCALAR_MASK             (0xFF << 0)
2027
2028 #define _CNL_PORT_TX_DW4_LN0_AE         0x162450
2029 #define _CNL_PORT_TX_DW4_LN1_AE         0x1624D0
2030 #define CNL_PORT_TX_DW4_GRP(port)       _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
2031 #define CNL_PORT_TX_DW4_LN0(port)       _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
2032 #define CNL_PORT_TX_DW4_LN(ln, port)   _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
2033                                            ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
2034                                                     _CNL_PORT_TX_DW4_LN0_AE)))
2035 #define ICL_PORT_TX_DW4_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
2036 #define ICL_PORT_TX_DW4_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
2037 #define ICL_PORT_TX_DW4_LN0(phy)        _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
2038 #define ICL_PORT_TX_DW4_LN(ln, phy)     _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
2039 #define   LOADGEN_SELECT                (1 << 31)
2040 #define   POST_CURSOR_1(x)              ((x) << 12)
2041 #define   POST_CURSOR_1_MASK            (0x3F << 12)
2042 #define   POST_CURSOR_2(x)              ((x) << 6)
2043 #define   POST_CURSOR_2_MASK            (0x3F << 6)
2044 #define   CURSOR_COEFF(x)               ((x) << 0)
2045 #define   CURSOR_COEFF_MASK             (0x3F << 0)
2046
2047 #define CNL_PORT_TX_DW5_GRP(port)       _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
2048 #define CNL_PORT_TX_DW5_LN0(port)       _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
2049 #define ICL_PORT_TX_DW5_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
2050 #define ICL_PORT_TX_DW5_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
2051 #define ICL_PORT_TX_DW5_LN0(phy)        _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
2052 #define   TX_TRAINING_EN                (1 << 31)
2053 #define   TAP2_DISABLE                  (1 << 30)
2054 #define   TAP3_DISABLE                  (1 << 29)
2055 #define   SCALING_MODE_SEL(x)           ((x) << 18)
2056 #define   SCALING_MODE_SEL_MASK         (0x7 << 18)
2057 #define   RTERM_SELECT(x)               ((x) << 3)
2058 #define   RTERM_SELECT_MASK             (0x7 << 3)
2059
2060 #define CNL_PORT_TX_DW7_GRP(port)       _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
2061 #define CNL_PORT_TX_DW7_LN0(port)       _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
2062 #define ICL_PORT_TX_DW7_AUX(phy)        _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
2063 #define ICL_PORT_TX_DW7_GRP(phy)        _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
2064 #define ICL_PORT_TX_DW7_LN0(phy)        _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
2065 #define ICL_PORT_TX_DW7_LN(ln, phy)     _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
2066 #define   N_SCALAR(x)                   ((x) << 24)
2067 #define   N_SCALAR_MASK                 (0x7F << 24)
2068
2069 #define _ICL_DPHY_CHKN_REG                      0x194
2070 #define ICL_DPHY_CHKN(port)                     _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
2071 #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP      REG_BIT(7)
2072
2073 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
2074         _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
2075
2076 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1          0x16812C
2077 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1          0x16852C
2078 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2          0x16912C
2079 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2          0x16952C
2080 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3          0x16A12C
2081 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3          0x16A52C
2082 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4          0x16B12C
2083 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4          0x16B52C
2084 #define MG_TX1_LINK_PARAMS(ln, tc_port) \
2085         MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
2086                                     MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
2087                                     MG_TX_LINK_PARAMS_TX1LN1_PORT1)
2088
2089 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1          0x1680AC
2090 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1          0x1684AC
2091 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2          0x1690AC
2092 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2          0x1694AC
2093 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3          0x16A0AC
2094 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3          0x16A4AC
2095 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4          0x16B0AC
2096 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4          0x16B4AC
2097 #define MG_TX2_LINK_PARAMS(ln, tc_port) \
2098         MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
2099                                     MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
2100                                     MG_TX_LINK_PARAMS_TX2LN1_PORT1)
2101 #define   CRI_USE_FS32                  (1 << 5)
2102
2103 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1                0x16814C
2104 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1                0x16854C
2105 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2                0x16914C
2106 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2                0x16954C
2107 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3                0x16A14C
2108 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3                0x16A54C
2109 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4                0x16B14C
2110 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4                0x16B54C
2111 #define MG_TX1_PISO_READLOAD(ln, tc_port) \
2112         MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
2113                                     MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
2114                                     MG_TX_PISO_READLOAD_TX1LN1_PORT1)
2115
2116 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1                0x1680CC
2117 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1                0x1684CC
2118 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2                0x1690CC
2119 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2                0x1694CC
2120 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3                0x16A0CC
2121 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3                0x16A4CC
2122 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4                0x16B0CC
2123 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4                0x16B4CC
2124 #define MG_TX2_PISO_READLOAD(ln, tc_port) \
2125         MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
2126                                     MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
2127                                     MG_TX_PISO_READLOAD_TX2LN1_PORT1)
2128 #define   CRI_CALCINIT                                  (1 << 1)
2129
2130 #define MG_TX_SWINGCTRL_TX1LN0_PORT1            0x168148
2131 #define MG_TX_SWINGCTRL_TX1LN1_PORT1            0x168548
2132 #define MG_TX_SWINGCTRL_TX1LN0_PORT2            0x169148
2133 #define MG_TX_SWINGCTRL_TX1LN1_PORT2            0x169548
2134 #define MG_TX_SWINGCTRL_TX1LN0_PORT3            0x16A148
2135 #define MG_TX_SWINGCTRL_TX1LN1_PORT3            0x16A548
2136 #define MG_TX_SWINGCTRL_TX1LN0_PORT4            0x16B148
2137 #define MG_TX_SWINGCTRL_TX1LN1_PORT4            0x16B548
2138 #define MG_TX1_SWINGCTRL(ln, tc_port) \
2139         MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2140                                     MG_TX_SWINGCTRL_TX1LN0_PORT2, \
2141                                     MG_TX_SWINGCTRL_TX1LN1_PORT1)
2142
2143 #define MG_TX_SWINGCTRL_TX2LN0_PORT1            0x1680C8
2144 #define MG_TX_SWINGCTRL_TX2LN1_PORT1            0x1684C8
2145 #define MG_TX_SWINGCTRL_TX2LN0_PORT2            0x1690C8
2146 #define MG_TX_SWINGCTRL_TX2LN1_PORT2            0x1694C8
2147 #define MG_TX_SWINGCTRL_TX2LN0_PORT3            0x16A0C8
2148 #define MG_TX_SWINGCTRL_TX2LN1_PORT3            0x16A4C8
2149 #define MG_TX_SWINGCTRL_TX2LN0_PORT4            0x16B0C8
2150 #define MG_TX_SWINGCTRL_TX2LN1_PORT4            0x16B4C8
2151 #define MG_TX2_SWINGCTRL(ln, tc_port) \
2152         MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2153                                     MG_TX_SWINGCTRL_TX2LN0_PORT2, \
2154                                     MG_TX_SWINGCTRL_TX2LN1_PORT1)
2155 #define   CRI_TXDEEMPH_OVERRIDE_17_12(x)                ((x) << 0)
2156 #define   CRI_TXDEEMPH_OVERRIDE_17_12_MASK              (0x3F << 0)
2157
2158 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1                    0x168144
2159 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1                    0x168544
2160 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2                    0x169144
2161 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2                    0x169544
2162 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3                    0x16A144
2163 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3                    0x16A544
2164 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4                    0x16B144
2165 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4                    0x16B544
2166 #define MG_TX1_DRVCTRL(ln, tc_port) \
2167         MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
2168                                     MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
2169                                     MG_TX_DRVCTRL_TX1LN1_TXPORT1)
2170
2171 #define MG_TX_DRVCTRL_TX2LN0_PORT1                      0x1680C4
2172 #define MG_TX_DRVCTRL_TX2LN1_PORT1                      0x1684C4
2173 #define MG_TX_DRVCTRL_TX2LN0_PORT2                      0x1690C4
2174 #define MG_TX_DRVCTRL_TX2LN1_PORT2                      0x1694C4
2175 #define MG_TX_DRVCTRL_TX2LN0_PORT3                      0x16A0C4
2176 #define MG_TX_DRVCTRL_TX2LN1_PORT3                      0x16A4C4
2177 #define MG_TX_DRVCTRL_TX2LN0_PORT4                      0x16B0C4
2178 #define MG_TX_DRVCTRL_TX2LN1_PORT4                      0x16B4C4
2179 #define MG_TX2_DRVCTRL(ln, tc_port) \
2180         MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
2181                                     MG_TX_DRVCTRL_TX2LN0_PORT2, \
2182                                     MG_TX_DRVCTRL_TX2LN1_PORT1)
2183 #define   CRI_TXDEEMPH_OVERRIDE_11_6(x)                 ((x) << 24)
2184 #define   CRI_TXDEEMPH_OVERRIDE_11_6_MASK               (0x3F << 24)
2185 #define   CRI_TXDEEMPH_OVERRIDE_EN                      (1 << 22)
2186 #define   CRI_TXDEEMPH_OVERRIDE_5_0(x)                  ((x) << 16)
2187 #define   CRI_TXDEEMPH_OVERRIDE_5_0_MASK                (0x3F << 16)
2188 #define   CRI_LOADGEN_SEL(x)                            ((x) << 12)
2189 #define   CRI_LOADGEN_SEL_MASK                          (0x3 << 12)
2190
2191 #define MG_CLKHUB_LN0_PORT1                     0x16839C
2192 #define MG_CLKHUB_LN1_PORT1                     0x16879C
2193 #define MG_CLKHUB_LN0_PORT2                     0x16939C
2194 #define MG_CLKHUB_LN1_PORT2                     0x16979C
2195 #define MG_CLKHUB_LN0_PORT3                     0x16A39C
2196 #define MG_CLKHUB_LN1_PORT3                     0x16A79C
2197 #define MG_CLKHUB_LN0_PORT4                     0x16B39C
2198 #define MG_CLKHUB_LN1_PORT4                     0x16B79C
2199 #define MG_CLKHUB(ln, tc_port) \
2200         MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
2201                                     MG_CLKHUB_LN0_PORT2, \
2202                                     MG_CLKHUB_LN1_PORT1)
2203 #define   CFG_LOW_RATE_LKREN_EN                         (1 << 11)
2204
2205 #define MG_TX_DCC_TX1LN0_PORT1                  0x168110
2206 #define MG_TX_DCC_TX1LN1_PORT1                  0x168510
2207 #define MG_TX_DCC_TX1LN0_PORT2                  0x169110
2208 #define MG_TX_DCC_TX1LN1_PORT2                  0x169510
2209 #define MG_TX_DCC_TX1LN0_PORT3                  0x16A110
2210 #define MG_TX_DCC_TX1LN1_PORT3                  0x16A510
2211 #define MG_TX_DCC_TX1LN0_PORT4                  0x16B110
2212 #define MG_TX_DCC_TX1LN1_PORT4                  0x16B510
2213 #define MG_TX1_DCC(ln, tc_port) \
2214         MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
2215                                     MG_TX_DCC_TX1LN0_PORT2, \
2216                                     MG_TX_DCC_TX1LN1_PORT1)
2217 #define MG_TX_DCC_TX2LN0_PORT1                  0x168090
2218 #define MG_TX_DCC_TX2LN1_PORT1                  0x168490
2219 #define MG_TX_DCC_TX2LN0_PORT2                  0x169090
2220 #define MG_TX_DCC_TX2LN1_PORT2                  0x169490
2221 #define MG_TX_DCC_TX2LN0_PORT3                  0x16A090
2222 #define MG_TX_DCC_TX2LN1_PORT3                  0x16A490
2223 #define MG_TX_DCC_TX2LN0_PORT4                  0x16B090
2224 #define MG_TX_DCC_TX2LN1_PORT4                  0x16B490
2225 #define MG_TX2_DCC(ln, tc_port) \
2226         MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
2227                                     MG_TX_DCC_TX2LN0_PORT2, \
2228                                     MG_TX_DCC_TX2LN1_PORT1)
2229 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL(x)        ((x) << 25)
2230 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK      (0x3 << 25)
2231 #define   CFG_AMI_CK_DIV_OVERRIDE_EN            (1 << 24)
2232
2233 #define MG_DP_MODE_LN0_ACU_PORT1                        0x1683A0
2234 #define MG_DP_MODE_LN1_ACU_PORT1                        0x1687A0
2235 #define MG_DP_MODE_LN0_ACU_PORT2                        0x1693A0
2236 #define MG_DP_MODE_LN1_ACU_PORT2                        0x1697A0
2237 #define MG_DP_MODE_LN0_ACU_PORT3                        0x16A3A0
2238 #define MG_DP_MODE_LN1_ACU_PORT3                        0x16A7A0
2239 #define MG_DP_MODE_LN0_ACU_PORT4                        0x16B3A0
2240 #define MG_DP_MODE_LN1_ACU_PORT4                        0x16B7A0
2241 #define MG_DP_MODE(ln, tc_port) \
2242         MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
2243                                     MG_DP_MODE_LN0_ACU_PORT2, \
2244                                     MG_DP_MODE_LN1_ACU_PORT1)
2245 #define   MG_DP_MODE_CFG_DP_X2_MODE                     (1 << 7)
2246 #define   MG_DP_MODE_CFG_DP_X1_MODE                     (1 << 6)
2247
2248 /* The spec defines this only for BXT PHY0, but lets assume that this
2249  * would exist for PHY1 too if it had a second channel.
2250  */
2251 #define _PORT_CL2CM_DW6_A               0x162358
2252 #define _PORT_CL2CM_DW6_BC              0x6C358
2253 #define BXT_PORT_CL2CM_DW6(phy)         _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2254 #define   DW6_OLDO_DYN_PWR_DOWN_EN      (1 << 28)
2255
2256 #define FIA1_BASE                       0x163000
2257 #define FIA2_BASE                       0x16E000
2258 #define FIA3_BASE                       0x16F000
2259 #define _FIA(fia)                       _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
2260 #define _MMIO_FIA(fia, off)             _MMIO(_FIA(fia) + (off))
2261
2262 /* ICL PHY DFLEX registers */
2263 #define PORT_TX_DFLEXDPMLE1(fia)                _MMIO_FIA((fia),  0x008C0)
2264 #define   DFLEXDPMLE1_DPMLETC_MASK(idx)         (0xf << (4 * (idx)))
2265 #define   DFLEXDPMLE1_DPMLETC_ML0(idx)          (1 << (4 * (idx)))
2266 #define   DFLEXDPMLE1_DPMLETC_ML1_0(idx)        (3 << (4 * (idx)))
2267 #define   DFLEXDPMLE1_DPMLETC_ML3(idx)          (8 << (4 * (idx)))
2268 #define   DFLEXDPMLE1_DPMLETC_ML3_2(idx)        (12 << (4 * (idx)))
2269 #define   DFLEXDPMLE1_DPMLETC_ML3_0(idx)        (15 << (4 * (idx)))
2270
2271 /* BXT PHY Ref registers */
2272 #define _PORT_REF_DW3_A                 0x16218C
2273 #define _PORT_REF_DW3_BC                0x6C18C
2274 #define   GRC_DONE                      (1 << 22)
2275 #define BXT_PORT_REF_DW3(phy)           _BXT_PHY((phy), _PORT_REF_DW3_BC)
2276
2277 #define _PORT_REF_DW6_A                 0x162198
2278 #define _PORT_REF_DW6_BC                0x6C198
2279 #define   GRC_CODE_SHIFT                24
2280 #define   GRC_CODE_MASK                 (0xFF << GRC_CODE_SHIFT)
2281 #define   GRC_CODE_FAST_SHIFT           16
2282 #define   GRC_CODE_FAST_MASK            (0xFF << GRC_CODE_FAST_SHIFT)
2283 #define   GRC_CODE_SLOW_SHIFT           8
2284 #define   GRC_CODE_SLOW_MASK            (0xFF << GRC_CODE_SLOW_SHIFT)
2285 #define   GRC_CODE_NOM_MASK             0xFF
2286 #define BXT_PORT_REF_DW6(phy)           _BXT_PHY((phy), _PORT_REF_DW6_BC)
2287
2288 #define _PORT_REF_DW8_A                 0x1621A0
2289 #define _PORT_REF_DW8_BC                0x6C1A0
2290 #define   GRC_DIS                       (1 << 15)
2291 #define   GRC_RDY_OVRD                  (1 << 1)
2292 #define BXT_PORT_REF_DW8(phy)           _BXT_PHY((phy), _PORT_REF_DW8_BC)
2293
2294 /* BXT PHY PCS registers */
2295 #define _PORT_PCS_DW10_LN01_A           0x162428
2296 #define _PORT_PCS_DW10_LN01_B           0x6C428
2297 #define _PORT_PCS_DW10_LN01_C           0x6C828
2298 #define _PORT_PCS_DW10_GRP_A            0x162C28
2299 #define _PORT_PCS_DW10_GRP_B            0x6CC28
2300 #define _PORT_PCS_DW10_GRP_C            0x6CE28
2301 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2302                                                          _PORT_PCS_DW10_LN01_B, \
2303                                                          _PORT_PCS_DW10_LN01_C)
2304 #define BXT_PORT_PCS_DW10_GRP(phy, ch)  _MMIO_BXT_PHY_CH(phy, ch, \
2305                                                          _PORT_PCS_DW10_GRP_B, \
2306                                                          _PORT_PCS_DW10_GRP_C)
2307
2308 #define   TX2_SWING_CALC_INIT           (1 << 31)
2309 #define   TX1_SWING_CALC_INIT           (1 << 30)
2310
2311 #define _PORT_PCS_DW12_LN01_A           0x162430
2312 #define _PORT_PCS_DW12_LN01_B           0x6C430
2313 #define _PORT_PCS_DW12_LN01_C           0x6C830
2314 #define _PORT_PCS_DW12_LN23_A           0x162630
2315 #define _PORT_PCS_DW12_LN23_B           0x6C630
2316 #define _PORT_PCS_DW12_LN23_C           0x6CA30
2317 #define _PORT_PCS_DW12_GRP_A            0x162c30
2318 #define _PORT_PCS_DW12_GRP_B            0x6CC30
2319 #define _PORT_PCS_DW12_GRP_C            0x6CE30
2320 #define   LANESTAGGER_STRAP_OVRD        (1 << 6)
2321 #define   LANE_STAGGER_MASK             0x1F
2322 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2323                                                          _PORT_PCS_DW12_LN01_B, \
2324                                                          _PORT_PCS_DW12_LN01_C)
2325 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2326                                                          _PORT_PCS_DW12_LN23_B, \
2327                                                          _PORT_PCS_DW12_LN23_C)
2328 #define BXT_PORT_PCS_DW12_GRP(phy, ch)  _MMIO_BXT_PHY_CH(phy, ch, \
2329                                                          _PORT_PCS_DW12_GRP_B, \
2330                                                          _PORT_PCS_DW12_GRP_C)
2331
2332 /* BXT PHY TX registers */
2333 #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +       \
2334                                           ((lane) & 1) * 0x80)
2335
2336 #define _PORT_TX_DW2_LN0_A              0x162508
2337 #define _PORT_TX_DW2_LN0_B              0x6C508
2338 #define _PORT_TX_DW2_LN0_C              0x6C908
2339 #define _PORT_TX_DW2_GRP_A              0x162D08
2340 #define _PORT_TX_DW2_GRP_B              0x6CD08
2341 #define _PORT_TX_DW2_GRP_C              0x6CF08
2342 #define BXT_PORT_TX_DW2_LN0(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2343                                                          _PORT_TX_DW2_LN0_B, \
2344                                                          _PORT_TX_DW2_LN0_C)
2345 #define BXT_PORT_TX_DW2_GRP(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2346                                                          _PORT_TX_DW2_GRP_B, \
2347                                                          _PORT_TX_DW2_GRP_C)
2348 #define   MARGIN_000_SHIFT              16
2349 #define   MARGIN_000                    (0xFF << MARGIN_000_SHIFT)
2350 #define   UNIQ_TRANS_SCALE_SHIFT        8
2351 #define   UNIQ_TRANS_SCALE              (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2352
2353 #define _PORT_TX_DW3_LN0_A              0x16250C
2354 #define _PORT_TX_DW3_LN0_B              0x6C50C
2355 #define _PORT_TX_DW3_LN0_C              0x6C90C
2356 #define _PORT_TX_DW3_GRP_A              0x162D0C
2357 #define _PORT_TX_DW3_GRP_B              0x6CD0C
2358 #define _PORT_TX_DW3_GRP_C              0x6CF0C
2359 #define BXT_PORT_TX_DW3_LN0(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2360                                                          _PORT_TX_DW3_LN0_B, \
2361                                                          _PORT_TX_DW3_LN0_C)
2362 #define BXT_PORT_TX_DW3_GRP(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2363                                                          _PORT_TX_DW3_GRP_B, \
2364                                                          _PORT_TX_DW3_GRP_C)
2365 #define   SCALE_DCOMP_METHOD            (1 << 26)
2366 #define   UNIQUE_TRANGE_EN_METHOD       (1 << 27)
2367
2368 #define _PORT_TX_DW4_LN0_A              0x162510
2369 #define _PORT_TX_DW4_LN0_B              0x6C510
2370 #define _PORT_TX_DW4_LN0_C              0x6C910
2371 #define _PORT_TX_DW4_GRP_A              0x162D10
2372 #define _PORT_TX_DW4_GRP_B              0x6CD10
2373 #define _PORT_TX_DW4_GRP_C              0x6CF10
2374 #define BXT_PORT_TX_DW4_LN0(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2375                                                          _PORT_TX_DW4_LN0_B, \
2376                                                          _PORT_TX_DW4_LN0_C)
2377 #define BXT_PORT_TX_DW4_GRP(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2378                                                          _PORT_TX_DW4_GRP_B, \
2379                                                          _PORT_TX_DW4_GRP_C)
2380 #define   DEEMPH_SHIFT                  24
2381 #define   DE_EMPHASIS                   (0xFF << DEEMPH_SHIFT)
2382
2383 #define _PORT_TX_DW5_LN0_A              0x162514
2384 #define _PORT_TX_DW5_LN0_B              0x6C514
2385 #define _PORT_TX_DW5_LN0_C              0x6C914
2386 #define _PORT_TX_DW5_GRP_A              0x162D14
2387 #define _PORT_TX_DW5_GRP_B              0x6CD14
2388 #define _PORT_TX_DW5_GRP_C              0x6CF14
2389 #define BXT_PORT_TX_DW5_LN0(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2390                                                          _PORT_TX_DW5_LN0_B, \
2391                                                          _PORT_TX_DW5_LN0_C)
2392 #define BXT_PORT_TX_DW5_GRP(phy, ch)    _MMIO_BXT_PHY_CH(phy, ch, \
2393                                                          _PORT_TX_DW5_GRP_B, \
2394                                                          _PORT_TX_DW5_GRP_C)
2395 #define   DCC_DELAY_RANGE_1             (1 << 9)
2396 #define   DCC_DELAY_RANGE_2             (1 << 8)
2397
2398 #define _PORT_TX_DW14_LN0_A             0x162538
2399 #define _PORT_TX_DW14_LN0_B             0x6C538
2400 #define _PORT_TX_DW14_LN0_C             0x6C938
2401 #define   LATENCY_OPTIM_SHIFT           30
2402 #define   LATENCY_OPTIM                 (1 << LATENCY_OPTIM_SHIFT)
2403 #define BXT_PORT_TX_DW14_LN(phy, ch, lane)                              \
2404         _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B,                 \
2405                                    _PORT_TX_DW14_LN0_C) +               \
2406               _BXT_LANE_OFFSET(lane))
2407
2408 /* UAIMI scratch pad register 1 */
2409 #define UAIMI_SPR1                      _MMIO(0x4F074)
2410 /* SKL VccIO mask */
2411 #define SKL_VCCIO_MASK                  0x1
2412 /* SKL balance leg register */
2413 #define DISPIO_CR_TX_BMU_CR0            _MMIO(0x6C00C)
2414 /* I_boost values */
2415 #define BALANCE_LEG_SHIFT(port)         (8 + 3 * (port))
2416 #define BALANCE_LEG_MASK(port)          (7 << (8 + 3 * (port)))
2417 /* Balance leg disable bits */
2418 #define BALANCE_LEG_DISABLE_SHIFT       23
2419 #define BALANCE_LEG_DISABLE(port)       (1 << (23 + (port)))
2420
2421 /*
2422  * Fence registers
2423  * [0-7]  @ 0x2000 gen2,gen3
2424  * [8-15] @ 0x3000 945,g33,pnv
2425  *
2426  * [0-15] @ 0x3000 gen4,gen5
2427  *
2428  * [0-15] @ 0x100000 gen6,vlv,chv
2429  * [0-31] @ 0x100000 gen7+
2430  */
2431 #define FENCE_REG(i)                    _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2432 #define   I830_FENCE_START_MASK         0x07f80000
2433 #define   I830_FENCE_TILING_Y_SHIFT     12
2434 #define   I830_FENCE_SIZE_BITS(size)    ((ffs((size) >> 19) - 1) << 8)
2435 #define   I830_FENCE_PITCH_SHIFT        4
2436 #define   I830_FENCE_REG_VALID          (1 << 0)
2437 #define   I915_FENCE_MAX_PITCH_VAL      4
2438 #define   I830_FENCE_MAX_PITCH_VAL      6
2439 #define   I830_FENCE_MAX_SIZE_VAL       (1 << 8)
2440
2441 #define   I915_FENCE_START_MASK         0x0ff00000
2442 #define   I915_FENCE_SIZE_BITS(size)    ((ffs((size) >> 20) - 1) << 8)
2443
2444 #define FENCE_REG_965_LO(i)             _MMIO(0x03000 + (i) * 8)
2445 #define FENCE_REG_965_HI(i)             _MMIO(0x03000 + (i) * 8 + 4)
2446 #define   I965_FENCE_PITCH_SHIFT        2
2447 #define   I965_FENCE_TILING_Y_SHIFT     1
2448 #define   I965_FENCE_REG_VALID          (1 << 0)
2449 #define   I965_FENCE_MAX_PITCH_VAL      0x0400
2450
2451 #define FENCE_REG_GEN6_LO(i)            _MMIO(0x100000 + (i) * 8)
2452 #define FENCE_REG_GEN6_HI(i)            _MMIO(0x100000 + (i) * 8 + 4)
2453 #define   GEN6_FENCE_PITCH_SHIFT        32
2454 #define   GEN7_FENCE_MAX_PITCH_VAL      0x0800
2455
2456
2457 /* control register for cpu gtt access */
2458 #define TILECTL                         _MMIO(0x101000)
2459 #define   TILECTL_SWZCTL                        (1 << 0)
2460 #define   TILECTL_TLBPF                 (1 << 1)
2461 #define   TILECTL_TLB_PREFETCH_DIS      (1 << 2)
2462 #define   TILECTL_BACKSNOOP_DIS         (1 << 3)
2463
2464 /*
2465  * Instruction and interrupt control regs
2466  */
2467 #define PGTBL_CTL       _MMIO(0x02020)
2468 #define   PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
2469 #define   PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
2470 #define PGTBL_ER        _MMIO(0x02024)
2471 #define PRB0_BASE       (0x2030 - 0x30)
2472 #define PRB1_BASE       (0x2040 - 0x30) /* 830,gen3 */
2473 #define PRB2_BASE       (0x2050 - 0x30) /* gen3 */
2474 #define SRB0_BASE       (0x2100 - 0x30) /* gen2 */
2475 #define SRB1_BASE       (0x2110 - 0x30) /* gen2 */
2476 #define SRB2_BASE       (0x2120 - 0x30) /* 830 */
2477 #define SRB3_BASE       (0x2130 - 0x30) /* 830 */
2478 #define RENDER_RING_BASE        0x02000
2479 #define BSD_RING_BASE           0x04000
2480 #define GEN6_BSD_RING_BASE      0x12000
2481 #define GEN8_BSD2_RING_BASE     0x1c000
2482 #define GEN11_BSD_RING_BASE     0x1c0000
2483 #define GEN11_BSD2_RING_BASE    0x1c4000
2484 #define GEN11_BSD3_RING_BASE    0x1d0000
2485 #define GEN11_BSD4_RING_BASE    0x1d4000
2486 #define VEBOX_RING_BASE         0x1a000
2487 #define GEN11_VEBOX_RING_BASE           0x1c8000
2488 #define GEN11_VEBOX2_RING_BASE          0x1d8000
2489 #define BLT_RING_BASE           0x22000
2490 #define RING_TAIL(base)         _MMIO((base) + 0x30)
2491 #define RING_HEAD(base)         _MMIO((base) + 0x34)
2492 #define RING_START(base)        _MMIO((base) + 0x38)
2493 #define RING_CTL(base)          _MMIO((base) + 0x3c)
2494 #define   RING_CTL_SIZE(size)   ((size) - PAGE_SIZE) /* in bytes -> pages */
2495 #define RING_SYNC_0(base)       _MMIO((base) + 0x40)
2496 #define RING_SYNC_1(base)       _MMIO((base) + 0x44)
2497 #define RING_SYNC_2(base)       _MMIO((base) + 0x48)
2498 #define GEN6_RVSYNC     (RING_SYNC_0(RENDER_RING_BASE))
2499 #define GEN6_RBSYNC     (RING_SYNC_1(RENDER_RING_BASE))
2500 #define GEN6_RVESYNC    (RING_SYNC_2(RENDER_RING_BASE))
2501 #define GEN6_VBSYNC     (RING_SYNC_0(GEN6_BSD_RING_BASE))
2502 #define GEN6_VRSYNC     (RING_SYNC_1(GEN6_BSD_RING_BASE))
2503 #define GEN6_VVESYNC    (RING_SYNC_2(GEN6_BSD_RING_BASE))
2504 #define GEN6_BRSYNC     (RING_SYNC_0(BLT_RING_BASE))
2505 #define GEN6_BVSYNC     (RING_SYNC_1(BLT_RING_BASE))
2506 #define GEN6_BVESYNC    (RING_SYNC_2(BLT_RING_BASE))
2507 #define GEN6_VEBSYNC    (RING_SYNC_0(VEBOX_RING_BASE))
2508 #define GEN6_VERSYNC    (RING_SYNC_1(VEBOX_RING_BASE))
2509 #define GEN6_VEVSYNC    (RING_SYNC_2(VEBOX_RING_BASE))
2510 #define GEN6_NOSYNC     INVALID_MMIO_REG
2511 #define RING_PSMI_CTL(base)     _MMIO((base) + 0x50)
2512 #define RING_MAX_IDLE(base)     _MMIO((base) + 0x54)
2513 #define RING_HWS_PGA(base)      _MMIO((base) + 0x80)
2514 #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
2515 #define RING_RESET_CTL(base)    _MMIO((base) + 0xd0)
2516 #define   RESET_CTL_CAT_ERROR      REG_BIT(2)
2517 #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
2518 #define   RESET_CTL_REQUEST_RESET  REG_BIT(0)
2519
2520 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2521
2522 #define HSW_GTT_CACHE_EN        _MMIO(0x4024)
2523 #define   GTT_CACHE_EN_ALL      0xF0007FFF
2524 #define GEN7_WR_WATERMARK       _MMIO(0x4028)
2525 #define GEN7_GFX_PRIO_CTRL      _MMIO(0x402C)
2526 #define ARB_MODE                _MMIO(0x4030)
2527 #define   ARB_MODE_SWIZZLE_SNB  (1 << 4)
2528 #define   ARB_MODE_SWIZZLE_IVB  (1 << 5)
2529 #define GEN7_GFX_PEND_TLB0      _MMIO(0x4034)
2530 #define GEN7_GFX_PEND_TLB1      _MMIO(0x4038)
2531 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2532 #define GEN7_LRA_LIMITS(i)      _MMIO(0x403C + (i) * 4)
2533 #define GEN7_LRA_LIMITS_REG_NUM 13
2534 #define GEN7_MEDIA_MAX_REQ_COUNT        _MMIO(0x4070)
2535 #define GEN7_GFX_MAX_REQ_COUNT          _MMIO(0x4074)
2536
2537 #define GAMTARBMODE             _MMIO(0x04a08)
2538 #define   ARB_MODE_BWGTLB_DISABLE (1 << 9)
2539 #define   ARB_MODE_SWIZZLE_BDW  (1 << 1)
2540 #define RENDER_HWS_PGA_GEN7     _MMIO(0x04080)
2541 #define RING_FAULT_REG(engine)  _MMIO(0x4094 + 0x100 * (engine)->hw_id)
2542 #define GEN8_RING_FAULT_REG     _MMIO(0x4094)
2543 #define GEN12_RING_FAULT_REG    _MMIO(0xcec4)
2544 #define   GEN8_RING_FAULT_ENGINE_ID(x)  (((x) >> 12) & 0x7)
2545 #define   RING_FAULT_GTTSEL_MASK (1 << 11)
2546 #define   RING_FAULT_SRCID(x)   (((x) >> 3) & 0xff)
2547 #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2548 #define   RING_FAULT_VALID      (1 << 0)
2549 #define DONE_REG                _MMIO(0x40b0)
2550 #define GEN12_GAM_DONE          _MMIO(0xcf68)
2551 #define GEN8_PRIVATE_PAT_LO     _MMIO(0x40e0)
2552 #define GEN8_PRIVATE_PAT_HI     _MMIO(0x40e0 + 4)
2553 #define GEN10_PAT_INDEX(index)  _MMIO(0x40e0 + (index) * 4)
2554 #define GEN12_PAT_INDEX(index)  _MMIO(0x4800 + (index) * 4)
2555 #define BSD_HWS_PGA_GEN7        _MMIO(0x04180)
2556 #define BLT_HWS_PGA_GEN7        _MMIO(0x04280)
2557 #define VEBOX_HWS_PGA_GEN7      _MMIO(0x04380)
2558 #define RING_ACTHD(base)        _MMIO((base) + 0x74)
2559 #define RING_ACTHD_UDW(base)    _MMIO((base) + 0x5c)
2560 #define RING_NOPID(base)        _MMIO((base) + 0x94)
2561 #define RING_IMR(base)          _MMIO((base) + 0xa8)
2562 #define RING_HWSTAM(base)       _MMIO((base) + 0x98)
2563 #define RING_TIMESTAMP(base)            _MMIO((base) + 0x358)
2564 #define RING_TIMESTAMP_UDW(base)        _MMIO((base) + 0x358 + 4)
2565 #define   TAIL_ADDR             0x001FFFF8
2566 #define   HEAD_WRAP_COUNT       0xFFE00000
2567 #define   HEAD_WRAP_ONE         0x00200000
2568 #define   HEAD_ADDR             0x001FFFFC
2569 #define   RING_NR_PAGES         0x001FF000
2570 #define   RING_REPORT_MASK      0x00000006
2571 #define   RING_REPORT_64K       0x00000002
2572 #define   RING_REPORT_128K      0x00000004
2573 #define   RING_NO_REPORT        0x00000000
2574 #define   RING_VALID_MASK       0x00000001
2575 #define   RING_VALID            0x00000001
2576 #define   RING_INVALID          0x00000000
2577 #define   RING_WAIT_I8XX        (1 << 0) /* gen2, PRBx_HEAD */
2578 #define   RING_WAIT             (1 << 11) /* gen3+, PRBx_CTL */
2579 #define   RING_WAIT_SEMAPHORE   (1 << 10) /* gen6+ */
2580
2581 /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
2582 #define GEN8_RING_CS_GPR(base, n)       _MMIO((base) + 0x600 + (n) * 8)
2583 #define GEN8_RING_CS_GPR_UDW(base, n)   _MMIO((base) + 0x600 + (n) * 8 + 4)
2584
2585 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2586 #define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK    REG_GENMASK(25, 2)
2587 #define   RING_FORCE_TO_NONPRIV_ACCESS_RW       (0 << 28)    /* CFL+ & Gen11+ */
2588 #define   RING_FORCE_TO_NONPRIV_ACCESS_RD       (1 << 28)
2589 #define   RING_FORCE_TO_NONPRIV_ACCESS_WR       (2 << 28)
2590 #define   RING_FORCE_TO_NONPRIV_ACCESS_INVALID  (3 << 28)
2591 #define   RING_FORCE_TO_NONPRIV_ACCESS_MASK     (3 << 28)
2592 #define   RING_FORCE_TO_NONPRIV_RANGE_1         (0 << 0)     /* CFL+ & Gen11+ */
2593 #define   RING_FORCE_TO_NONPRIV_RANGE_4         (1 << 0)
2594 #define   RING_FORCE_TO_NONPRIV_RANGE_16        (2 << 0)
2595 #define   RING_FORCE_TO_NONPRIV_RANGE_64        (3 << 0)
2596 #define   RING_FORCE_TO_NONPRIV_RANGE_MASK      (3 << 0)
2597 #define   RING_FORCE_TO_NONPRIV_MASK_VALID      \
2598                                         (RING_FORCE_TO_NONPRIV_RANGE_MASK \
2599                                         | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
2600 #define   RING_MAX_NONPRIV_SLOTS  12
2601
2602 #define GEN7_TLB_RD_ADDR        _MMIO(0x4700)
2603
2604 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2605 #define   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS   (1 << 18)
2606
2607 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2608 #define   GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2609 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE       (1 << 7)
2610
2611 #define GAMT_CHKN_BIT_REG       _MMIO(0x4ab8)
2612 #define   GAMT_CHKN_DISABLE_L3_COH_PIPE                 (1 << 31)
2613 #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING      (1 << 28)
2614 #define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT        (1 << 24)
2615
2616 #if 0
2617 #define PRB0_TAIL       _MMIO(0x2030)
2618 #define PRB0_HEAD       _MMIO(0x2034)
2619 #define PRB0_START      _MMIO(0x2038)
2620 #define PRB0_CTL        _MMIO(0x203c)
2621 #define PRB1_TAIL       _MMIO(0x2040) /* 915+ only */
2622 #define PRB1_HEAD       _MMIO(0x2044) /* 915+ only */
2623 #define PRB1_START      _MMIO(0x2048) /* 915+ only */
2624 #define PRB1_CTL        _MMIO(0x204c) /* 915+ only */
2625 #endif
2626 #define IPEIR_I965      _MMIO(0x2064)
2627 #define IPEHR_I965      _MMIO(0x2068)
2628 #define GEN7_SC_INSTDONE        _MMIO(0x7100)
2629 #define GEN7_SAMPLER_INSTDONE   _MMIO(0xe160)
2630 #define GEN7_ROW_INSTDONE       _MMIO(0xe164)
2631 #define GEN8_MCR_SELECTOR               _MMIO(0xfdc)
2632 #define   GEN8_MCR_SLICE(slice)         (((slice) & 3) << 26)
2633 #define   GEN8_MCR_SLICE_MASK           GEN8_MCR_SLICE(3)
2634 #define   GEN8_MCR_SUBSLICE(subslice)   (((subslice) & 3) << 24)
2635 #define   GEN8_MCR_SUBSLICE_MASK        GEN8_MCR_SUBSLICE(3)
2636 #define   GEN11_MCR_SLICE(slice)        (((slice) & 0xf) << 27)
2637 #define   GEN11_MCR_SLICE_MASK          GEN11_MCR_SLICE(0xf)
2638 #define   GEN11_MCR_SUBSLICE(subslice)  (((subslice) & 0x7) << 24)
2639 #define   GEN11_MCR_SUBSLICE_MASK       GEN11_MCR_SUBSLICE(0x7)
2640 #define RING_IPEIR(base)        _MMIO((base) + 0x64)
2641 #define RING_IPEHR(base)        _MMIO((base) + 0x68)
2642 /*
2643  * On GEN4, only the render ring INSTDONE exists and has a different
2644  * layout than the GEN7+ version.
2645  * The GEN2 counterpart of this register is GEN2_INSTDONE.
2646  */
2647 #define RING_INSTDONE(base)     _MMIO((base) + 0x6c)
2648 #define RING_INSTPS(base)       _MMIO((base) + 0x70)
2649 #define RING_DMA_FADD(base)     _MMIO((base) + 0x78)
2650 #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
2651 #define RING_INSTPM(base)       _MMIO((base) + 0xc0)
2652 #define RING_MI_MODE(base)      _MMIO((base) + 0x9c)
2653 #define INSTPS          _MMIO(0x2070) /* 965+ only */
2654 #define GEN4_INSTDONE1  _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2655 #define ACTHD_I965      _MMIO(0x2074)
2656 #define HWS_PGA         _MMIO(0x2080)
2657 #define HWS_ADDRESS_MASK        0xfffff000
2658 #define HWS_START_ADDRESS_SHIFT 4
2659 #define PWRCTXA         _MMIO(0x2088) /* 965GM+ only */
2660 #define   PWRCTX_EN     (1 << 0)
2661 #define IPEIR(base)     _MMIO((base) + 0x88)
2662 #define IPEHR(base)     _MMIO((base) + 0x8c)
2663 #define GEN2_INSTDONE   _MMIO(0x2090)
2664 #define NOPID           _MMIO(0x2094)
2665 #define HWSTAM          _MMIO(0x2098)
2666 #define DMA_FADD_I8XX(base)     _MMIO((base) + 0xd0)
2667 #define RING_BBSTATE(base)      _MMIO((base) + 0x110)
2668 #define   RING_BB_PPGTT         (1 << 5)
2669 #define RING_SBBADDR(base)      _MMIO((base) + 0x114) /* hsw+ */
2670 #define RING_SBBSTATE(base)     _MMIO((base) + 0x118) /* hsw+ */
2671 #define RING_SBBADDR_UDW(base)  _MMIO((base) + 0x11c) /* gen8+ */
2672 #define RING_BBADDR(base)       _MMIO((base) + 0x140)
2673 #define RING_BBADDR_UDW(base)   _MMIO((base) + 0x168) /* gen8+ */
2674 #define RING_BB_PER_CTX_PTR(base)       _MMIO((base) + 0x1c0) /* gen8+ */
2675 #define RING_INDIRECT_CTX(base)         _MMIO((base) + 0x1c4) /* gen8+ */
2676 #define RING_INDIRECT_CTX_OFFSET(base)  _MMIO((base) + 0x1c8) /* gen8+ */
2677 #define RING_CTX_TIMESTAMP(base)        _MMIO((base) + 0x3a8) /* gen8+ */
2678
2679 #define ERROR_GEN6      _MMIO(0x40a0)
2680 #define GEN7_ERR_INT    _MMIO(0x44040)
2681 #define   ERR_INT_POISON                (1 << 31)
2682 #define   ERR_INT_MMIO_UNCLAIMED        (1 << 13)
2683 #define   ERR_INT_PIPE_CRC_DONE_C       (1 << 8)
2684 #define   ERR_INT_FIFO_UNDERRUN_C       (1 << 6)
2685 #define   ERR_INT_PIPE_CRC_DONE_B       (1 << 5)
2686 #define   ERR_INT_FIFO_UNDERRUN_B       (1 << 3)
2687 #define   ERR_INT_PIPE_CRC_DONE_A       (1 << 2)
2688 #define   ERR_INT_PIPE_CRC_DONE(pipe)   (1 << (2 + (pipe) * 3))
2689 #define   ERR_INT_FIFO_UNDERRUN_A       (1 << 0)
2690 #define   ERR_INT_FIFO_UNDERRUN(pipe)   (1 << ((pipe) * 3))
2691
2692 #define GEN8_FAULT_TLB_DATA0            _MMIO(0x4b10)
2693 #define GEN8_FAULT_TLB_DATA1            _MMIO(0x4b14)
2694 #define GEN12_FAULT_TLB_DATA0           _MMIO(0xceb8)
2695 #define GEN12_FAULT_TLB_DATA1           _MMIO(0xcebc)
2696 #define   FAULT_VA_HIGH_BITS            (0xf << 0)
2697 #define   FAULT_GTT_SEL                 (1 << 4)
2698
2699 #define GEN12_AUX_ERR_DBG               _MMIO(0x43f4)
2700
2701 #define FPGA_DBG                _MMIO(0x42300)
2702 #define   FPGA_DBG_RM_NOCLAIM   (1 << 31)
2703
2704 #define CLAIM_ER                _MMIO(VLV_DISPLAY_BASE + 0x2028)
2705 #define   CLAIM_ER_CLR          (1 << 31)
2706 #define   CLAIM_ER_OVERFLOW     (1 << 16)
2707 #define   CLAIM_ER_CTR_MASK     0xffff
2708
2709 #define DERRMR          _MMIO(0x44050)
2710 /* Note that HBLANK events are reserved on bdw+ */
2711 #define   DERRMR_PIPEA_SCANLINE         (1 << 0)
2712 #define   DERRMR_PIPEA_PRI_FLIP_DONE    (1 << 1)
2713 #define   DERRMR_PIPEA_SPR_FLIP_DONE    (1 << 2)
2714 #define   DERRMR_PIPEA_VBLANK           (1 << 3)
2715 #define   DERRMR_PIPEA_HBLANK           (1 << 5)
2716 #define   DERRMR_PIPEB_SCANLINE         (1 << 8)
2717 #define   DERRMR_PIPEB_PRI_FLIP_DONE    (1 << 9)
2718 #define   DERRMR_PIPEB_SPR_FLIP_DONE    (1 << 10)
2719 #define   DERRMR_PIPEB_VBLANK           (1 << 11)
2720 #define   DERRMR_PIPEB_HBLANK           (1 << 13)
2721 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2722 #define   DERRMR_PIPEC_SCANLINE         (1 << 14)
2723 #define   DERRMR_PIPEC_PRI_FLIP_DONE    (1 << 15)
2724 #define   DERRMR_PIPEC_SPR_FLIP_DONE    (1 << 20)
2725 #define   DERRMR_PIPEC_VBLANK           (1 << 21)
2726 #define   DERRMR_PIPEC_HBLANK           (1 << 22)
2727
2728
2729 /* GM45+ chicken bits -- debug workaround bits that may be required
2730  * for various sorts of correct behavior.  The top 16 bits of each are
2731  * the enables for writing to the corresponding low bit.
2732  */
2733 #define _3D_CHICKEN     _MMIO(0x2084)
2734 #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB      (1 << 10)
2735 #define _3D_CHICKEN2    _MMIO(0x208c)
2736
2737 #define FF_SLICE_CHICKEN        _MMIO(0x2088)
2738 #define  FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX       (1 << 1)
2739
2740 /* Disables pipelining of read flushes past the SF-WIZ interface.
2741  * Required on all Ironlake steppings according to the B-Spec, but the
2742  * particular danger of not doing so is not specified.
2743  */
2744 # define _3D_CHICKEN2_WM_READ_PIPELINED                 (1 << 14)
2745 #define _3D_CHICKEN3    _MMIO(0x2090)
2746 #define  _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX            (1 << 12)
2747 #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL             (1 << 10)
2748 #define  _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE        (1 << 5)
2749 #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL          (1 << 5)
2750 #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)       ((x) << 1) /* gen8+ */
2751 #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH   (1 << 1) /* gen6 */
2752
2753 #define MI_MODE         _MMIO(0x209c)
2754 # define VS_TIMER_DISPATCH                              (1 << 6)
2755 # define MI_FLUSH_ENABLE                                (1 << 12)
2756 # define ASYNC_FLIP_PERF_DISABLE                        (1 << 14)
2757 # define MODE_IDLE                                      (1 << 9)
2758 # define STOP_RING                                      (1 << 8)
2759
2760 #define GEN6_GT_MODE    _MMIO(0x20d0)
2761 #define GEN7_GT_MODE    _MMIO(0x7008)
2762 #define   GEN6_WIZ_HASHING(hi, lo)                      (((hi) << 9) | ((lo) << 7))
2763 #define   GEN6_WIZ_HASHING_8x8                          GEN6_WIZ_HASHING(0, 0)
2764 #define   GEN6_WIZ_HASHING_8x4                          GEN6_WIZ_HASHING(0, 1)
2765 #define   GEN6_WIZ_HASHING_16x4                         GEN6_WIZ_HASHING(1, 0)
2766 #define   GEN6_WIZ_HASHING_MASK                         GEN6_WIZ_HASHING(1, 1)
2767 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE             (1 << 5)
2768 #define   GEN9_IZ_HASHING_MASK(slice)                   (0x3 << ((slice) * 2))
2769 #define   GEN9_IZ_HASHING(slice, val)                   ((val) << ((slice) * 2))
2770
2771 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2772 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2773 #define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2774 #define   GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2775
2776 /* WaClearTdlStateAckDirtyBits */
2777 #define GEN8_STATE_ACK          _MMIO(0x20F0)
2778 #define GEN9_STATE_ACK_SLICE1   _MMIO(0x20F8)
2779 #define GEN9_STATE_ACK_SLICE2   _MMIO(0x2100)
2780 #define   GEN9_STATE_ACK_TDL0 (1 << 12)
2781 #define   GEN9_STATE_ACK_TDL1 (1 << 13)
2782 #define   GEN9_STATE_ACK_TDL2 (1 << 14)
2783 #define   GEN9_STATE_ACK_TDL3 (1 << 15)
2784 #define   GEN9_SUBSLICE_TDL_ACK_BITS \
2785         (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2786          GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2787
2788 #define GFX_MODE        _MMIO(0x2520)
2789 #define GFX_MODE_GEN7   _MMIO(0x229c)
2790 #define RING_MODE_GEN7(base)    _MMIO((base) + 0x29c)
2791 #define   GFX_RUN_LIST_ENABLE           (1 << 15)
2792 #define   GFX_INTERRUPT_STEERING        (1 << 14)
2793 #define   GFX_TLB_INVALIDATE_EXPLICIT   (1 << 13)
2794 #define   GFX_SURFACE_FAULT_ENABLE      (1 << 12)
2795 #define   GFX_REPLAY_MODE               (1 << 11)
2796 #define   GFX_PSMI_GRANULARITY          (1 << 10)
2797 #define   GFX_PPGTT_ENABLE              (1 << 9)
2798 #define   GEN8_GFX_PPGTT_48B            (1 << 7)
2799
2800 #define   GFX_FORWARD_VBLANK_MASK       (3 << 5)
2801 #define   GFX_FORWARD_VBLANK_NEVER      (0 << 5)
2802 #define   GFX_FORWARD_VBLANK_ALWAYS     (1 << 5)
2803 #define   GFX_FORWARD_VBLANK_COND       (2 << 5)
2804
2805 #define   GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
2806
2807 #define VLV_GU_CTL0     _MMIO(VLV_DISPLAY_BASE + 0x2030)
2808 #define VLV_GU_CTL1     _MMIO(VLV_DISPLAY_BASE + 0x2034)
2809 #define SCPD0           _MMIO(0x209c) /* 915+ only */
2810 #define  CSTATE_RENDER_CLOCK_GATE_DISABLE       (1 << 5)
2811 #define GEN2_IER        _MMIO(0x20a0)
2812 #define GEN2_IIR        _MMIO(0x20a4)
2813 #define GEN2_IMR        _MMIO(0x20a8)
2814 #define GEN2_ISR        _MMIO(0x20ac)
2815 #define VLV_GUNIT_CLOCK_GATE    _MMIO(VLV_DISPLAY_BASE + 0x2060)
2816 #define   GINT_DIS              (1 << 22)
2817 #define   GCFG_DIS              (1 << 8)
2818 #define VLV_GUNIT_CLOCK_GATE2   _MMIO(VLV_DISPLAY_BASE + 0x2064)
2819 #define VLV_IIR_RW      _MMIO(VLV_DISPLAY_BASE + 0x2084)
2820 #define VLV_IER         _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2821 #define VLV_IIR         _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2822 #define VLV_IMR         _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2823 #define VLV_ISR         _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2824 #define VLV_PCBR        _MMIO(VLV_DISPLAY_BASE + 0x2120)
2825 #define VLV_PCBR_ADDR_SHIFT     12
2826
2827 #define   DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
2828 #define EIR             _MMIO(0x20b0)
2829 #define EMR             _MMIO(0x20b4)
2830 #define ESR             _MMIO(0x20b8)
2831 #define   GM45_ERROR_PAGE_TABLE                         (1 << 5)
2832 #define   GM45_ERROR_MEM_PRIV                           (1 << 4)
2833 #define   I915_ERROR_PAGE_TABLE                         (1 << 4)
2834 #define   GM45_ERROR_CP_PRIV                            (1 << 3)
2835 #define   I915_ERROR_MEMORY_REFRESH                     (1 << 1)
2836 #define   I915_ERROR_INSTRUCTION                        (1 << 0)
2837 #define INSTPM          _MMIO(0x20c0)
2838 #define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
2839 #define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
2840                                         will not assert AGPBUSY# and will only
2841                                         be delivered when out of C3. */
2842 #define   INSTPM_FORCE_ORDERING                         (1 << 7) /* GEN6+ */
2843 #define   INSTPM_TLB_INVALIDATE (1 << 9)
2844 #define   INSTPM_SYNC_FLUSH     (1 << 5)
2845 #define ACTHD(base)     _MMIO((base) + 0xc8)
2846 #define MEM_MODE        _MMIO(0x20cc)
2847 #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
2848 #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
2849 #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
2850 #define FW_BLC          _MMIO(0x20d8)
2851 #define FW_BLC2         _MMIO(0x20dc)
2852 #define FW_BLC_SELF     _MMIO(0x20e0) /* 915+ only */
2853 #define   FW_BLC_SELF_EN_MASK      (1 << 31)
2854 #define   FW_BLC_SELF_FIFO_MASK    (1 << 16) /* 945 only */
2855 #define   FW_BLC_SELF_EN           (1 << 15) /* 945 only */
2856 #define MM_BURST_LENGTH     0x00700000
2857 #define MM_FIFO_WATERMARK   0x0001F000
2858 #define LM_BURST_LENGTH     0x00000700
2859 #define LM_FIFO_WATERMARK   0x0000001F
2860 #define MI_ARB_STATE    _MMIO(0x20e4) /* 915+ only */
2861
2862 #define MBUS_ABOX_CTL                   _MMIO(0x45038)
2863 #define MBUS_ABOX_BW_CREDIT_MASK        (3 << 20)
2864 #define MBUS_ABOX_BW_CREDIT(x)          ((x) << 20)
2865 #define MBUS_ABOX_B_CREDIT_MASK         (0xF << 16)
2866 #define MBUS_ABOX_B_CREDIT(x)           ((x) << 16)
2867 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK  (0x1F << 8)
2868 #define MBUS_ABOX_BT_CREDIT_POOL2(x)    ((x) << 8)
2869 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK  (0x1F << 0)
2870 #define MBUS_ABOX_BT_CREDIT_POOL1(x)    ((x) << 0)
2871
2872 #define _PIPEA_MBUS_DBOX_CTL            0x7003C
2873 #define _PIPEB_MBUS_DBOX_CTL            0x7103C
2874 #define PIPE_MBUS_DBOX_CTL(pipe)        _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2875                                                    _PIPEB_MBUS_DBOX_CTL)
2876 #define MBUS_DBOX_BW_CREDIT_MASK        (3 << 14)
2877 #define MBUS_DBOX_BW_CREDIT(x)          ((x) << 14)
2878 #define MBUS_DBOX_B_CREDIT_MASK         (0x1F << 8)
2879 #define MBUS_DBOX_B_CREDIT(x)           ((x) << 8)
2880 #define MBUS_DBOX_A_CREDIT_MASK         (0xF << 0)
2881 #define MBUS_DBOX_A_CREDIT(x)           ((x) << 0)
2882
2883 #define MBUS_UBOX_CTL                   _MMIO(0x4503C)
2884 #define MBUS_BBOX_CTL_S1                _MMIO(0x45040)
2885 #define MBUS_BBOX_CTL_S2                _MMIO(0x45044)
2886
2887 /* Make render/texture TLB fetches lower priorty than associated data
2888  *   fetches. This is not turned on by default
2889  */
2890 #define   MI_ARB_RENDER_TLB_LOW_PRIORITY        (1 << 15)
2891
2892 /* Isoch request wait on GTT enable (Display A/B/C streams).
2893  * Make isoch requests stall on the TLB update. May cause
2894  * display underruns (test mode only)
2895  */
2896 #define   MI_ARB_ISOCH_WAIT_GTT                 (1 << 14)
2897
2898 /* Block grant count for isoch requests when block count is
2899  * set to a finite value.
2900  */
2901 #define   MI_ARB_BLOCK_GRANT_MASK               (3 << 12)
2902 #define   MI_ARB_BLOCK_GRANT_8                  (0 << 12)       /* for 3 display planes */
2903 #define   MI_ARB_BLOCK_GRANT_4                  (1 << 12)       /* for 2 display planes */
2904 #define   MI_ARB_BLOCK_GRANT_2                  (2 << 12)       /* for 1 display plane */
2905 #define   MI_ARB_BLOCK_GRANT_0                  (3 << 12)       /* don't use */
2906
2907 /* Enable render writes to complete in C2/C3/C4 power states.
2908  * If this isn't enabled, render writes are prevented in low
2909  * power states. That seems bad to me.
2910  */
2911 #define   MI_ARB_C3_LP_WRITE_ENABLE             (1 << 11)
2912
2913 /* This acknowledges an async flip immediately instead
2914  * of waiting for 2TLB fetches.
2915  */
2916 #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE       (1 << 10)
2917
2918 /* Enables non-sequential data reads through arbiter
2919  */
2920 #define   MI_ARB_DUAL_DATA_PHASE_DISABLE        (1 << 9)
2921
2922 /* Disable FSB snooping of cacheable write cycles from binner/render
2923  * command stream
2924  */
2925 #define   MI_ARB_CACHE_SNOOP_DISABLE            (1 << 8)
2926
2927 /* Arbiter time slice for non-isoch streams */
2928 #define   MI_ARB_TIME_SLICE_MASK                (7 << 5)
2929 #define   MI_ARB_TIME_SLICE_1                   (0 << 5)
2930 #define   MI_ARB_TIME_SLICE_2                   (1 << 5)
2931 #define   MI_ARB_TIME_SLICE_4                   (2 << 5)
2932 #define   MI_ARB_TIME_SLICE_6                   (3 << 5)
2933 #define   MI_ARB_TIME_SLICE_8                   (4 << 5)
2934 #define   MI_ARB_TIME_SLICE_10                  (5 << 5)
2935 #define   MI_ARB_TIME_SLICE_14                  (6 << 5)
2936 #define   MI_ARB_TIME_SLICE_16                  (7 << 5)
2937
2938 /* Low priority grace period page size */
2939 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB         (0 << 4)        /* default */
2940 #define   MI_ARB_LOW_PRIORITY_GRACE_8KB         (1 << 4)
2941
2942 /* Disable display A/B trickle feed */
2943 #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE   (1 << 2)
2944
2945 /* Set display plane priority */
2946 #define   MI_ARB_DISPLAY_PRIORITY_A_B           (0 << 0)        /* display A > display B */
2947 #define   MI_ARB_DISPLAY_PRIORITY_B_A           (1 << 0)        /* display B > display A */
2948
2949 #define MI_STATE        _MMIO(0x20e4) /* gen2 only */
2950 #define   MI_AGPBUSY_INT_EN                     (1 << 1) /* 85x only */
2951 #define   MI_AGPBUSY_830_MODE                   (1 << 0) /* 85x only */
2952
2953 #define CACHE_MODE_0    _MMIO(0x2120) /* 915+ only */
2954 #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
2955 #define   CM0_IZ_OPT_DISABLE      (1 << 6)
2956 #define   CM0_ZR_OPT_DISABLE      (1 << 5)
2957 #define   CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
2958 #define   CM0_DEPTH_EVICT_DISABLE (1 << 4)
2959 #define   CM0_COLOR_EVICT_DISABLE (1 << 3)
2960 #define   CM0_DEPTH_WRITE_DISABLE (1 << 1)
2961 #define   CM0_RC_OP_FLUSH_DISABLE (1 << 0)
2962 #define GFX_FLSH_CNTL   _MMIO(0x2170) /* 915+ only */
2963 #define GFX_FLSH_CNTL_GEN6      _MMIO(0x101008)
2964 #define   GFX_FLSH_CNTL_EN      (1 << 0)
2965 #define ECOSKPD         _MMIO(0x21d0)
2966 #define   ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
2967 #define   ECO_GATING_CX_ONLY    (1 << 3)
2968 #define   ECO_FLIP_DONE         (1 << 0)
2969
2970 #define CACHE_MODE_0_GEN7       _MMIO(0x7000) /* IVB+ */
2971 #define RC_OP_FLUSH_ENABLE (1 << 0)
2972 #define   HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
2973 #define CACHE_MODE_1            _MMIO(0x7004) /* IVB+ */
2974 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE     (1 << 6)
2975 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE     (1 << 6)
2976 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE    (1 << 1)
2977
2978 #define GEN6_BLITTER_ECOSKPD    _MMIO(0x221d0)
2979 #define   GEN6_BLITTER_LOCK_SHIFT                       16
2980 #define   GEN6_BLITTER_FBC_NOTIFY                       (1 << 3)
2981
2982 #define GEN6_RC_SLEEP_PSMI_CONTROL      _MMIO(0x2050)
2983 #define   GEN6_PSMI_SLEEP_MSG_DISABLE   (1 << 0)
2984 #define   GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
2985 #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
2986 #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE        (1 << 10)
2987
2988 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2989 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2990
2991 #define GEN10_CACHE_MODE_SS                     _MMIO(0xe420)
2992 #define   FLOAT_BLEND_OPTIMIZATION_ENABLE       (1 << 4)
2993
2994 /* Fuse readout registers for GT */
2995 #define HSW_PAVP_FUSE1                  _MMIO(0x911C)
2996 #define   HSW_F1_EU_DIS_SHIFT           16
2997 #define   HSW_F1_EU_DIS_MASK            (0x3 << HSW_F1_EU_DIS_SHIFT)
2998 #define   HSW_F1_EU_DIS_10EUS           0
2999 #define   HSW_F1_EU_DIS_8EUS            1
3000 #define   HSW_F1_EU_DIS_6EUS            2
3001
3002 #define CHV_FUSE_GT                     _MMIO(VLV_DISPLAY_BASE + 0x2168)
3003 #define   CHV_FGT_DISABLE_SS0           (1 << 10)
3004 #define   CHV_FGT_DISABLE_SS1           (1 << 11)
3005 #define   CHV_FGT_EU_DIS_SS0_R0_SHIFT   16
3006 #define   CHV_FGT_EU_DIS_SS0_R0_MASK    (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
3007 #define   CHV_FGT_EU_DIS_SS0_R1_SHIFT   20
3008 #define   CHV_FGT_EU_DIS_SS0_R1_MASK    (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
3009 #define   CHV_FGT_EU_DIS_SS1_R0_SHIFT   24
3010 #define   CHV_FGT_EU_DIS_SS1_R0_MASK    (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
3011 #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT   28
3012 #define   CHV_FGT_EU_DIS_SS1_R1_MASK    (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
3013
3014 #define GEN8_FUSE2                      _MMIO(0x9120)
3015 #define   GEN8_F2_SS_DIS_SHIFT          21
3016 #define   GEN8_F2_SS_DIS_MASK           (0x7 << GEN8_F2_SS_DIS_SHIFT)
3017 #define   GEN8_F2_S_ENA_SHIFT           25
3018 #define   GEN8_F2_S_ENA_MASK            (0x7 << GEN8_F2_S_ENA_SHIFT)
3019
3020 #define   GEN9_F2_SS_DIS_SHIFT          20
3021 #define   GEN9_F2_SS_DIS_MASK           (0xf << GEN9_F2_SS_DIS_SHIFT)
3022
3023 #define   GEN10_F2_S_ENA_SHIFT          22
3024 #define   GEN10_F2_S_ENA_MASK           (0x3f << GEN10_F2_S_ENA_SHIFT)
3025 #define   GEN10_F2_SS_DIS_SHIFT         18
3026 #define   GEN10_F2_SS_DIS_MASK          (0xf << GEN10_F2_SS_DIS_SHIFT)
3027
3028 #define GEN10_MIRROR_FUSE3              _MMIO(0x9118)
3029 #define GEN10_L3BANK_PAIR_COUNT     4
3030 #define GEN10_L3BANK_MASK   0x0F
3031
3032 #define GEN8_EU_DISABLE0                _MMIO(0x9134)
3033 #define   GEN8_EU_DIS0_S0_MASK          0xffffff
3034 #define   GEN8_EU_DIS0_S1_SHIFT         24
3035 #define   GEN8_EU_DIS0_S1_MASK          (0xff << GEN8_EU_DIS0_S1_SHIFT)
3036
3037 #define GEN8_EU_DISABLE1                _MMIO(0x9138)
3038 #define   GEN8_EU_DIS1_S1_MASK          0xffff
3039 #define   GEN8_EU_DIS1_S2_SHIFT         16
3040 #define   GEN8_EU_DIS1_S2_MASK          (0xffff << GEN8_EU_DIS1_S2_SHIFT)
3041
3042 #define GEN8_EU_DISABLE2                _MMIO(0x913c)
3043 #define   GEN8_EU_DIS2_S2_MASK          0xff
3044
3045 #define GEN9_EU_DISABLE(slice)          _MMIO(0x9134 + (slice) * 0x4)
3046
3047 #define GEN10_EU_DISABLE3               _MMIO(0x9140)
3048 #define   GEN10_EU_DIS_SS_MASK          0xff
3049
3050 #define GEN11_GT_VEBOX_VDBOX_DISABLE    _MMIO(0x9140)
3051 #define   GEN11_GT_VDBOX_DISABLE_MASK   0xff
3052 #define   GEN11_GT_VEBOX_DISABLE_SHIFT  16
3053 #define   GEN11_GT_VEBOX_DISABLE_MASK   (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
3054
3055 #define GEN11_EU_DISABLE _MMIO(0x9134)
3056 #define GEN11_EU_DIS_MASK 0xFF
3057
3058 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
3059 #define GEN11_GT_S_ENA_MASK 0xFF
3060
3061 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
3062
3063 #define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
3064
3065 #define GEN6_BSD_SLEEP_PSMI_CONTROL     _MMIO(0x12050)
3066 #define   GEN6_BSD_SLEEP_MSG_DISABLE    (1 << 0)
3067 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE  (1 << 2)
3068 #define   GEN6_BSD_SLEEP_INDICATOR      (1 << 3)
3069 #define   GEN6_BSD_GO_INDICATOR         (1 << 4)
3070
3071 /* On modern GEN architectures interrupt control consists of two sets
3072  * of registers. The first set pertains to the ring generating the
3073  * interrupt. The second control is for the functional block generating the
3074  * interrupt. These are PM, GT, DE, etc.
3075  *
3076  * Luckily *knocks on wood* all the ring interrupt bits match up with the
3077  * GT interrupt bits, so we don't need to duplicate the defines.
3078  *
3079  * These defines should cover us well from SNB->HSW with minor exceptions
3080  * it can also work on ILK.
3081  */
3082 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT         (1 << 26)
3083 #define GT_BLT_CS_ERROR_INTERRUPT               (1 << 25)
3084 #define GT_BLT_USER_INTERRUPT                   (1 << 22)
3085 #define GT_BSD_CS_ERROR_INTERRUPT               (1 << 15)
3086 #define GT_BSD_USER_INTERRUPT                   (1 << 12)
3087 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1  (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
3088 #define GT_CONTEXT_SWITCH_INTERRUPT             (1 <<  8)
3089 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT     (1 <<  5) /* !snb */
3090 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT      (1 <<  4)
3091 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT     (1 <<  3)
3092 #define GT_RENDER_SYNC_STATUS_INTERRUPT         (1 <<  2)
3093 #define GT_RENDER_DEBUG_INTERRUPT               (1 <<  1)
3094 #define GT_RENDER_USER_INTERRUPT                (1 <<  0)
3095
3096 #define PM_VEBOX_CS_ERROR_INTERRUPT             (1 << 12) /* hsw+ */
3097 #define PM_VEBOX_USER_INTERRUPT                 (1 << 10) /* hsw+ */
3098
3099 #define GT_PARITY_ERROR(dev_priv) \
3100         (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
3101          (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
3102
3103 /* These are all the "old" interrupts */
3104 #define ILK_BSD_USER_INTERRUPT                          (1 << 5)
3105
3106 #define I915_PM_INTERRUPT                               (1 << 31)
3107 #define I915_ISP_INTERRUPT                              (1 << 22)
3108 #define I915_LPE_PIPE_B_INTERRUPT                       (1 << 21)
3109 #define I915_LPE_PIPE_A_INTERRUPT                       (1 << 20)
3110 #define I915_MIPIC_INTERRUPT                            (1 << 19)
3111 #define I915_MIPIA_INTERRUPT                            (1 << 18)
3112 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT              (1 << 18)
3113 #define I915_DISPLAY_PORT_INTERRUPT                     (1 << 17)
3114 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT            (1 << 16)
3115 #define I915_MASTER_ERROR_INTERRUPT                     (1 << 15)
3116 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT            (1 << 14)
3117 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT        (1 << 14) /* p-state */
3118 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT            (1 << 13)
3119 #define I915_HWB_OOM_INTERRUPT                          (1 << 13)
3120 #define I915_LPE_PIPE_C_INTERRUPT                       (1 << 12)
3121 #define I915_SYNC_STATUS_INTERRUPT                      (1 << 12)
3122 #define I915_MISC_INTERRUPT                             (1 << 11)
3123 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT     (1 << 11)
3124 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT            (1 << 10)
3125 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT     (1 << 10)
3126 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT             (1 << 9)
3127 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT       (1 << 9)
3128 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT              (1 << 8)
3129 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT     (1 << 8)
3130 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT            (1 << 7)
3131 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT             (1 << 6)
3132 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT            (1 << 5)
3133 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT             (1 << 4)
3134 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT              (1 << 3)
3135 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT              (1 << 2)
3136 #define I915_DEBUG_INTERRUPT                            (1 << 2)
3137 #define I915_WINVALID_INTERRUPT                         (1 << 1)
3138 #define I915_USER_INTERRUPT                             (1 << 1)
3139 #define I915_ASLE_INTERRUPT                             (1 << 0)
3140 #define I915_BSD_USER_INTERRUPT                         (1 << 25)
3141
3142 #define I915_HDMI_LPE_AUDIO_BASE        (VLV_DISPLAY_BASE + 0x65000)
3143 #define I915_HDMI_LPE_AUDIO_SIZE        0x1000
3144
3145 /* DisplayPort Audio w/ LPE */
3146 #define VLV_AUD_CHICKEN_BIT_REG         _MMIO(VLV_DISPLAY_BASE + 0x62F38)
3147 #define VLV_CHICKEN_BIT_DBG_ENABLE      (1 << 0)
3148
3149 #define _VLV_AUD_PORT_EN_B_DBG          (VLV_DISPLAY_BASE + 0x62F20)
3150 #define _VLV_AUD_PORT_EN_C_DBG          (VLV_DISPLAY_BASE + 0x62F30)
3151 #define _VLV_AUD_PORT_EN_D_DBG          (VLV_DISPLAY_BASE + 0x62F34)
3152 #define VLV_AUD_PORT_EN_DBG(port)       _MMIO_PORT3((port) - PORT_B,       \
3153                                                     _VLV_AUD_PORT_EN_B_DBG, \
3154                                                     _VLV_AUD_PORT_EN_C_DBG, \
3155                                                     _VLV_AUD_PORT_EN_D_DBG)
3156 #define VLV_AMP_MUTE                    (1 << 1)
3157
3158 #define GEN6_BSD_RNCID                  _MMIO(0x12198)
3159
3160 #define GEN7_FF_THREAD_MODE             _MMIO(0x20a0)
3161 #define   GEN7_FF_SCHED_MASK            0x0077070
3162 #define   GEN8_FF_DS_REF_CNT_FFME       (1 << 19)
3163 #define   GEN7_FF_TS_SCHED_HS1          (0x5 << 16)
3164 #define   GEN7_FF_TS_SCHED_HS0          (0x3 << 16)
3165 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
3166 #define   GEN7_FF_TS_SCHED_HW           (0x0 << 16) /* Default */
3167 #define   GEN7_FF_VS_REF_CNT_FFME       (1 << 15)
3168 #define   GEN7_FF_VS_SCHED_HS1          (0x5 << 12)
3169 #define   GEN7_FF_VS_SCHED_HS0          (0x3 << 12)
3170 #define   GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
3171 #define   GEN7_FF_VS_SCHED_HW           (0x0 << 12)
3172 #define   GEN7_FF_DS_SCHED_HS1          (0x5 << 4)
3173 #define   GEN7_FF_DS_SCHED_HS0          (0x3 << 4)
3174 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4)  /* Default */
3175 #define   GEN7_FF_DS_SCHED_HW           (0x0 << 4)
3176
3177 /*
3178  * Framebuffer compression (915+ only)
3179  */
3180
3181 #define FBC_CFB_BASE            _MMIO(0x3200) /* 4k page aligned */
3182 #define FBC_LL_BASE             _MMIO(0x3204) /* 4k page aligned */
3183 #define FBC_CONTROL             _MMIO(0x3208)
3184 #define   FBC_CTL_EN            (1 << 31)
3185 #define   FBC_CTL_PERIODIC      (1 << 30)
3186 #define   FBC_CTL_INTERVAL_SHIFT (16)
3187 #define   FBC_CTL_UNCOMPRESSIBLE (1 << 14)
3188 #define   FBC_CTL_C3_IDLE       (1 << 13)
3189 #define   FBC_CTL_STRIDE_SHIFT  (5)
3190 #define   FBC_CTL_FENCENO_SHIFT (0)
3191 #define FBC_COMMAND             _MMIO(0x320c)
3192 #define   FBC_CMD_COMPRESS      (1 << 0)
3193 #define FBC_STATUS              _MMIO(0x3210)
3194 #define   FBC_STAT_COMPRESSING  (1 << 31)
3195 #define   FBC_STAT_COMPRESSED   (1 << 30)
3196 #define   FBC_STAT_MODIFIED     (1 << 29)
3197 #define   FBC_STAT_CURRENT_LINE_SHIFT   (0)
3198 #define FBC_CONTROL2            _MMIO(0x3214)
3199 #define   FBC_CTL_FENCE_DBL     (0 << 4)
3200 #define   FBC_CTL_IDLE_IMM      (0 << 2)
3201 #define   FBC_CTL_IDLE_FULL     (1 << 2)
3202 #define   FBC_CTL_IDLE_LINE     (2 << 2)
3203 #define   FBC_CTL_IDLE_DEBUG    (3 << 2)
3204 #define   FBC_CTL_CPU_FENCE     (1 << 1)
3205 #define   FBC_CTL_PLANE(plane)  ((plane) << 0)
3206 #define FBC_FENCE_OFF           _MMIO(0x3218) /* BSpec typo has 321Bh */
3207 #define FBC_TAG(i)              _MMIO(0x3300 + (i) * 4)
3208
3209 #define FBC_LL_SIZE             (1536)
3210
3211 #define FBC_LLC_READ_CTRL       _MMIO(0x9044)
3212 #define   FBC_LLC_FULLY_OPEN    (1 << 30)
3213
3214 /* Framebuffer compression for GM45+ */
3215 #define DPFC_CB_BASE            _MMIO(0x3200)
3216 #define DPFC_CONTROL            _MMIO(0x3208)
3217 #define   DPFC_CTL_EN           (1 << 31)
3218 #define   DPFC_CTL_PLANE(plane) ((plane) << 30)
3219 #define   IVB_DPFC_CTL_PLANE(plane)     ((plane) << 29)
3220 #define   DPFC_CTL_FENCE_EN     (1 << 29)
3221 #define   IVB_DPFC_CTL_FENCE_EN (1 << 28)
3222 #define   DPFC_CTL_PERSISTENT_MODE      (1 << 25)
3223 #define   DPFC_SR_EN            (1 << 10)
3224 #define   DPFC_CTL_LIMIT_1X     (0 << 6)
3225 #define   DPFC_CTL_LIMIT_2X     (1 << 6)
3226 #define   DPFC_CTL_LIMIT_4X     (2 << 6)
3227 #define DPFC_RECOMP_CTL         _MMIO(0x320c)
3228 #define   DPFC_RECOMP_STALL_EN  (1 << 27)
3229 #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
3230 #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3231 #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3232 #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3233 #define DPFC_STATUS             _MMIO(0x3210)
3234 #define   DPFC_INVAL_SEG_SHIFT  (16)
3235 #define   DPFC_INVAL_SEG_MASK   (0x07ff0000)
3236 #define   DPFC_COMP_SEG_SHIFT   (0)
3237 #define   DPFC_COMP_SEG_MASK    (0x000007ff)
3238 #define DPFC_STATUS2            _MMIO(0x3214)
3239 #define DPFC_FENCE_YOFF         _MMIO(0x3218)
3240 #define DPFC_CHICKEN            _MMIO(0x3224)
3241 #define   DPFC_HT_MODIFY        (1 << 31)
3242
3243 /* Framebuffer compression for Ironlake */
3244 #define ILK_DPFC_CB_BASE        _MMIO(0x43200)
3245 #define ILK_DPFC_CONTROL        _MMIO(0x43208)
3246 #define   FBC_CTL_FALSE_COLOR   (1 << 10)
3247 /* The bit 28-8 is reserved */
3248 #define   DPFC_RESERVED         (0x1FFFFF00)
3249 #define ILK_DPFC_RECOMP_CTL     _MMIO(0x4320c)
3250 #define ILK_DPFC_STATUS         _MMIO(0x43210)
3251 #define  ILK_DPFC_COMP_SEG_MASK 0x7ff
3252 #define IVB_FBC_STATUS2         _MMIO(0x43214)
3253 #define  IVB_FBC_COMP_SEG_MASK  0x7ff
3254 #define  BDW_FBC_COMP_SEG_MASK  0xfff
3255 #define ILK_DPFC_FENCE_YOFF     _MMIO(0x43218)
3256 #define ILK_DPFC_CHICKEN        _MMIO(0x43224)
3257 #define   ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
3258 #define   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL     (1 << 14)
3259 #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION     (1 << 23)
3260 #define ILK_FBC_RT_BASE         _MMIO(0x2128)
3261 #define   ILK_FBC_RT_VALID      (1 << 0)
3262 #define   SNB_FBC_FRONT_BUFFER  (1 << 1)
3263
3264 #define ILK_DISPLAY_CHICKEN1    _MMIO(0x42000)
3265 #define   ILK_FBCQ_DIS          (1 << 22)
3266 #define   ILK_PABSTRETCH_DIS    (1 << 21)
3267
3268
3269 /*
3270  * Framebuffer compression for Sandybridge
3271  *
3272  * The following two registers are of type GTTMMADR
3273  */
3274 #define SNB_DPFC_CTL_SA         _MMIO(0x100100)
3275 #define   SNB_CPU_FENCE_ENABLE  (1 << 29)
3276 #define DPFC_CPU_FENCE_OFFSET   _MMIO(0x100104)
3277
3278 /* Framebuffer compression for Ivybridge */
3279 #define IVB_FBC_RT_BASE                 _MMIO(0x7020)
3280
3281 #define IPS_CTL         _MMIO(0x43408)
3282 #define   IPS_ENABLE    (1 << 31)
3283
3284 #define MSG_FBC_REND_STATE      _MMIO(0x50380)
3285 #define   FBC_REND_NUKE         (1 << 2)
3286 #define   FBC_REND_CACHE_CLEAN  (1 << 1)
3287
3288 /*
3289  * GPIO regs
3290  */
3291 #define GPIO(gpio)              _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3292                                       4 * (gpio))
3293
3294 # define GPIO_CLOCK_DIR_MASK            (1 << 0)
3295 # define GPIO_CLOCK_DIR_IN              (0 << 1)
3296 # define GPIO_CLOCK_DIR_OUT             (1 << 1)
3297 # define GPIO_CLOCK_VAL_MASK            (1 << 2)
3298 # define GPIO_CLOCK_VAL_OUT             (1 << 3)
3299 # define GPIO_CLOCK_VAL_IN              (1 << 4)
3300 # define GPIO_CLOCK_PULLUP_DISABLE      (1 << 5)
3301 # define GPIO_DATA_DIR_MASK             (1 << 8)
3302 # define GPIO_DATA_DIR_IN               (0 << 9)
3303 # define GPIO_DATA_DIR_OUT              (1 << 9)
3304 # define GPIO_DATA_VAL_MASK             (1 << 10)
3305 # define GPIO_DATA_VAL_OUT              (1 << 11)
3306 # define GPIO_DATA_VAL_IN               (1 << 12)
3307 # define GPIO_DATA_PULLUP_DISABLE       (1 << 13)
3308
3309 #define GMBUS0                  _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3310 #define   GMBUS_AKSV_SELECT     (1 << 11)
3311 #define   GMBUS_RATE_100KHZ     (0 << 8)
3312 #define   GMBUS_RATE_50KHZ      (1 << 8)
3313 #define   GMBUS_RATE_400KHZ     (2 << 8) /* reserved on Pineview */
3314 #define   GMBUS_RATE_1MHZ       (3 << 8) /* reserved on Pineview */
3315 #define   GMBUS_HOLD_EXT        (1 << 7) /* 300ns hold time, rsvd on Pineview */
3316 #define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3317
3318 #define GMBUS1                  _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3319 #define   GMBUS_SW_CLR_INT      (1 << 31)
3320 #define   GMBUS_SW_RDY          (1 << 30)
3321 #define   GMBUS_ENT             (1 << 29) /* enable timeout */
3322 #define   GMBUS_CYCLE_NONE      (0 << 25)
3323 #define   GMBUS_CYCLE_WAIT      (1 << 25)
3324 #define   GMBUS_CYCLE_INDEX     (2 << 25)
3325 #define   GMBUS_CYCLE_STOP      (4 << 25)
3326 #define   GMBUS_BYTE_COUNT_SHIFT 16
3327 #define   GMBUS_BYTE_COUNT_MAX   256U
3328 #define   GEN9_GMBUS_BYTE_COUNT_MAX 511U
3329 #define   GMBUS_SLAVE_INDEX_SHIFT 8
3330 #define   GMBUS_SLAVE_ADDR_SHIFT 1
3331 #define   GMBUS_SLAVE_READ      (1 << 0)
3332 #define   GMBUS_SLAVE_WRITE     (0 << 0)
3333 #define GMBUS2                  _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3334 #define   GMBUS_INUSE           (1 << 15)
3335 #define   GMBUS_HW_WAIT_PHASE   (1 << 14)
3336 #define   GMBUS_STALL_TIMEOUT   (1 << 13)
3337 #define   GMBUS_INT             (1 << 12)
3338 #define   GMBUS_HW_RDY          (1 << 11)
3339 #define   GMBUS_SATOER          (1 << 10)
3340 #define   GMBUS_ACTIVE          (1 << 9)
3341 #define GMBUS3                  _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3342 #define GMBUS4                  _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3343 #define   GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3344 #define   GMBUS_NAK_EN          (1 << 3)
3345 #define   GMBUS_IDLE_EN         (1 << 2)
3346 #define   GMBUS_HW_WAIT_EN      (1 << 1)
3347 #define   GMBUS_HW_RDY_EN       (1 << 0)
3348 #define GMBUS5                  _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3349 #define   GMBUS_2BYTE_INDEX_EN  (1 << 31)
3350
3351 /*
3352  * Clock control & power management
3353  */
3354 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
3355 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
3356 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
3357 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3358
3359 #define VGA0    _MMIO(0x6000)
3360 #define VGA1    _MMIO(0x6004)
3361 #define VGA_PD  _MMIO(0x6010)
3362 #define   VGA0_PD_P2_DIV_4      (1 << 7)
3363 #define   VGA0_PD_P1_DIV_2      (1 << 5)
3364 #define   VGA0_PD_P1_SHIFT      0
3365 #define   VGA0_PD_P1_MASK       (0x1f << 0)
3366 #define   VGA1_PD_P2_DIV_4      (1 << 15)
3367 #define   VGA1_PD_P1_DIV_2      (1 << 13)
3368 #define   VGA1_PD_P1_SHIFT      8
3369 #define   VGA1_PD_P1_MASK       (0x1f << 8)
3370 #define   DPLL_VCO_ENABLE               (1 << 31)
3371 #define   DPLL_SDVO_HIGH_SPEED          (1 << 30)
3372 #define   DPLL_DVO_2X_MODE              (1 << 30)
3373 #define   DPLL_EXT_BUFFER_ENABLE_VLV    (1 << 30)
3374 #define   DPLL_SYNCLOCK_ENABLE          (1 << 29)
3375 #define   DPLL_REF_CLK_ENABLE_VLV       (1 << 29)
3376 #define   DPLL_VGA_MODE_DIS             (1 << 28)
3377 #define   DPLLB_MODE_DAC_SERIAL         (1 << 26) /* i915 */
3378 #define   DPLLB_MODE_LVDS               (2 << 26) /* i915 */
3379 #define   DPLL_MODE_MASK                (3 << 26)
3380 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3381 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3382 #define   DPLLB_LVDS_P2_CLOCK_DIV_14    (0 << 24) /* i915 */
3383 #define   DPLLB_LVDS_P2_CLOCK_DIV_7     (1 << 24) /* i915 */
3384 #define   DPLL_P2_CLOCK_DIV_MASK        0x03000000 /* i915 */
3385 #define   DPLL_FPA01_P1_POST_DIV_MASK   0x00ff0000 /* i915 */
3386 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW  0x00ff8000 /* Pineview */
3387 #define   DPLL_LOCK_VLV                 (1 << 15)
3388 #define   DPLL_INTEGRATED_CRI_CLK_VLV   (1 << 14)
3389 #define   DPLL_INTEGRATED_REF_CLK_VLV   (1 << 13)
3390 #define   DPLL_SSC_REF_CLK_CHV          (1 << 13)
3391 #define   DPLL_PORTC_READY_MASK         (0xf << 4)
3392 #define   DPLL_PORTB_READY_MASK         (0xf)
3393
3394 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830      0x001f0000
3395
3396 /* Additional CHV pll/phy registers */
3397 #define DPIO_PHY_STATUS                 _MMIO(VLV_DISPLAY_BASE + 0x6240)
3398 #define   DPLL_PORTD_READY_MASK         (0xf)
3399 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3400 #define   PHY_CH_POWER_DOWN_OVRD_EN(phy, ch)    (1 << (2 * (phy) + (ch) + 27))
3401 #define   PHY_LDO_DELAY_0NS                     0x0
3402 #define   PHY_LDO_DELAY_200NS                   0x1
3403 #define   PHY_LDO_DELAY_600NS                   0x2
3404 #define   PHY_LDO_SEQ_DELAY(delay, phy)         ((delay) << (2 * (phy) + 23))
3405 #define   PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
3406 #define   PHY_CH_SU_PSR                         0x1
3407 #define   PHY_CH_DEEP_PSR                       0x7
3408 #define   PHY_CH_POWER_MODE(mode, phy, ch)      ((mode) << (6 * (phy) + 3 * (ch) + 2))
3409 #define   PHY_COM_LANE_RESET_DEASSERT(phy)      (1 << (phy))
3410 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3411 #define   PHY_POWERGOOD(phy)    (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3412 #define   PHY_STATUS_CMN_LDO(phy, ch)                   (1 << (6 - (6 * (phy) + 3 * (ch))))
3413 #define   PHY_STATUS_SPLINE_LDO(phy, ch, spline)        (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3414
3415 /*
3416  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3417  * this field (only one bit may be set).
3418  */
3419 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3420 #define   DPLL_FPA01_P1_POST_DIV_SHIFT  16
3421 #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3422 /* i830, required in DVO non-gang */
3423 #define   PLL_P2_DIVIDE_BY_4            (1 << 23)
3424 #define   PLL_P1_DIVIDE_BY_TWO          (1 << 21) /* i830 */
3425 #define   PLL_REF_INPUT_DREFCLK         (0 << 13)
3426 #define   PLL_REF_INPUT_TVCLKINA        (1 << 13) /* i830 */
3427 #define   PLL_REF_INPUT_TVCLKINBC       (2 << 13) /* SDVO TVCLKIN */
3428 #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3429 #define   PLL_REF_INPUT_MASK            (3 << 13)
3430 #define   PLL_LOAD_PULSE_PHASE_SHIFT            9
3431 /* Ironlake */
3432 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
3433 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
3434 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)        (((x) - 1) << 9)
3435 # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
3436 # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
3437
3438 /*
3439  * Parallel to Serial Load Pulse phase selection.
3440  * Selects the phase for the 10X DPLL clock for the PCIe
3441  * digital display port. The range is 4 to 13; 10 or more
3442  * is just a flip delay. The default is 6
3443  */
3444 #define   PLL_LOAD_PULSE_PHASE_MASK             (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3445 #define   DISPLAY_RATE_SELECT_FPA1              (1 << 8)
3446 /*
3447  * SDVO multiplier for 945G/GM. Not used on 965.
3448  */
3449 #define   SDVO_MULTIPLIER_MASK                  0x000000ff
3450 #define   SDVO_MULTIPLIER_SHIFT_HIRES           4
3451 #define   SDVO_MULTIPLIER_SHIFT_VGA             0
3452
3453 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
3454 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
3455 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
3456 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3457
3458 /*
3459  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3460  *
3461  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
3462  */
3463 #define   DPLL_MD_UDI_DIVIDER_MASK              0x3f000000
3464 #define   DPLL_MD_UDI_DIVIDER_SHIFT             24
3465 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3466 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK          0x003f0000
3467 #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT         16
3468 /*
3469  * SDVO/UDI pixel multiplier.
3470  *
3471  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3472  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
3473  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3474  * dummy bytes in the datastream at an increased clock rate, with both sides of
3475  * the link knowing how many bytes are fill.
3476  *
3477  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3478  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
3479  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3480  * through an SDVO command.
3481  *
3482  * This register field has values of multiplication factor minus 1, with
3483  * a maximum multiplier of 5 for SDVO.
3484  */
3485 #define   DPLL_MD_UDI_MULTIPLIER_MASK           0x00003f00
3486 #define   DPLL_MD_UDI_MULTIPLIER_SHIFT          8
3487 /*
3488  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3489  * This best be set to the default value (3) or the CRT won't work. No,
3490  * I don't entirely understand what this does...
3491  */
3492 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK       0x0000003f
3493 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT      0
3494
3495 #define RAWCLK_FREQ_VLV         _MMIO(VLV_DISPLAY_BASE + 0x6024)
3496
3497 #define _FPA0   0x6040
3498 #define _FPA1   0x6044
3499 #define _FPB0   0x6048
3500 #define _FPB1   0x604c
3501 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3502 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3503 #define   FP_N_DIV_MASK         0x003f0000
3504 #define   FP_N_PINEVIEW_DIV_MASK        0x00ff0000
3505 #define   FP_N_DIV_SHIFT                16
3506 #define   FP_M1_DIV_MASK        0x00003f00
3507 #define   FP_M1_DIV_SHIFT                8
3508 #define   FP_M2_DIV_MASK        0x0000003f
3509 #define   FP_M2_PINEVIEW_DIV_MASK       0x000000ff
3510 #define   FP_M2_DIV_SHIFT                0
3511 #define DPLL_TEST       _MMIO(0x606c)
3512 #define   DPLLB_TEST_SDVO_DIV_1         (0 << 22)
3513 #define   DPLLB_TEST_SDVO_DIV_2         (1 << 22)
3514 #define   DPLLB_TEST_SDVO_DIV_4         (2 << 22)
3515 #define   DPLLB_TEST_SDVO_DIV_MASK      (3 << 22)
3516 #define   DPLLB_TEST_N_BYPASS           (1 << 19)
3517 #define   DPLLB_TEST_M_BYPASS           (1 << 18)
3518 #define   DPLLB_INPUT_BUFFER_ENABLE     (1 << 16)
3519 #define   DPLLA_TEST_N_BYPASS           (1 << 3)
3520 #define   DPLLA_TEST_M_BYPASS           (1 << 2)
3521 #define   DPLLA_INPUT_BUFFER_ENABLE     (1 << 0)
3522 #define D_STATE         _MMIO(0x6104)
3523 #define  DSTATE_GFX_RESET_I830                  (1 << 6)
3524 #define  DSTATE_PLL_D3_OFF                      (1 << 3)
3525 #define  DSTATE_GFX_CLOCK_GATING                (1 << 1)
3526 #define  DSTATE_DOT_CLOCK_GATING                (1 << 0)
3527 #define DSPCLK_GATE_D   _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
3528 # define DPUNIT_B_CLOCK_GATE_DISABLE            (1 << 30) /* 965 */
3529 # define VSUNIT_CLOCK_GATE_DISABLE              (1 << 29) /* 965 */
3530 # define VRHUNIT_CLOCK_GATE_DISABLE             (1 << 28) /* 965 */
3531 # define VRDUNIT_CLOCK_GATE_DISABLE             (1 << 27) /* 965 */
3532 # define AUDUNIT_CLOCK_GATE_DISABLE             (1 << 26) /* 965 */
3533 # define DPUNIT_A_CLOCK_GATE_DISABLE            (1 << 25) /* 965 */
3534 # define DPCUNIT_CLOCK_GATE_DISABLE             (1 << 24) /* 965 */
3535 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE       (1 << 24) /* pnv */
3536 # define TVRUNIT_CLOCK_GATE_DISABLE             (1 << 23) /* 915-945 */
3537 # define TVCUNIT_CLOCK_GATE_DISABLE             (1 << 22) /* 915-945 */
3538 # define TVFUNIT_CLOCK_GATE_DISABLE             (1 << 21) /* 915-945 */
3539 # define TVEUNIT_CLOCK_GATE_DISABLE             (1 << 20) /* 915-945 */
3540 # define DVSUNIT_CLOCK_GATE_DISABLE             (1 << 19) /* 915-945 */
3541 # define DSSUNIT_CLOCK_GATE_DISABLE             (1 << 18) /* 915-945 */
3542 # define DDBUNIT_CLOCK_GATE_DISABLE             (1 << 17) /* 915-945 */
3543 # define DPRUNIT_CLOCK_GATE_DISABLE             (1 << 16) /* 915-945 */
3544 # define DPFUNIT_CLOCK_GATE_DISABLE             (1 << 15) /* 915-945 */
3545 # define DPBMUNIT_CLOCK_GATE_DISABLE            (1 << 14) /* 915-945 */
3546 # define DPLSUNIT_CLOCK_GATE_DISABLE            (1 << 13) /* 915-945 */
3547 # define DPLUNIT_CLOCK_GATE_DISABLE             (1 << 12) /* 915-945 */
3548 # define DPOUNIT_CLOCK_GATE_DISABLE             (1 << 11)
3549 # define DPBUNIT_CLOCK_GATE_DISABLE             (1 << 10)
3550 # define DCUNIT_CLOCK_GATE_DISABLE              (1 << 9)
3551 # define DPUNIT_CLOCK_GATE_DISABLE              (1 << 8)
3552 # define VRUNIT_CLOCK_GATE_DISABLE              (1 << 7) /* 915+: reserved */
3553 # define OVHUNIT_CLOCK_GATE_DISABLE             (1 << 6) /* 830-865 */
3554 # define DPIOUNIT_CLOCK_GATE_DISABLE            (1 << 6) /* 915-945 */
3555 # define OVFUNIT_CLOCK_GATE_DISABLE             (1 << 5)
3556 # define OVBUNIT_CLOCK_GATE_DISABLE             (1 << 4)
3557 /*
3558  * This bit must be set on the 830 to prevent hangs when turning off the
3559  * overlay scaler.
3560  */
3561 # define OVRUNIT_CLOCK_GATE_DISABLE             (1 << 3)
3562 # define OVCUNIT_CLOCK_GATE_DISABLE             (1 << 2)
3563 # define OVUUNIT_CLOCK_GATE_DISABLE             (1 << 1)
3564 # define ZVUNIT_CLOCK_GATE_DISABLE              (1 << 0) /* 830 */
3565 # define OVLUNIT_CLOCK_GATE_DISABLE             (1 << 0) /* 845,865 */
3566
3567 #define RENCLK_GATE_D1          _MMIO(0x6204)
3568 # define BLITTER_CLOCK_GATE_DISABLE             (1 << 13) /* 945GM only */
3569 # define MPEG_CLOCK_GATE_DISABLE                (1 << 12) /* 945GM only */
3570 # define PC_FE_CLOCK_GATE_DISABLE               (1 << 11)
3571 # define PC_BE_CLOCK_GATE_DISABLE               (1 << 10)
3572 # define WINDOWER_CLOCK_GATE_DISABLE            (1 << 9)
3573 # define INTERPOLATOR_CLOCK_GATE_DISABLE        (1 << 8)
3574 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE    (1 << 7)
3575 # define MOTION_COMP_CLOCK_GATE_DISABLE         (1 << 6)
3576 # define MAG_CLOCK_GATE_DISABLE                 (1 << 5)
3577 /* This bit must be unset on 855,865 */
3578 # define MECI_CLOCK_GATE_DISABLE                (1 << 4)
3579 # define DCMP_CLOCK_GATE_DISABLE                (1 << 3)
3580 # define MEC_CLOCK_GATE_DISABLE                 (1 << 2)
3581 # define MECO_CLOCK_GATE_DISABLE                (1 << 1)
3582 /* This bit must be set on 855,865. */
3583 # define SV_CLOCK_GATE_DISABLE                  (1 << 0)
3584 # define I915_MPEG_CLOCK_GATE_DISABLE           (1 << 16)
3585 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE      (1 << 15)
3586 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE    (1 << 14)
3587 # define I915_BD_BF_CLOCK_GATE_DISABLE          (1 << 13)
3588 # define I915_SF_SE_CLOCK_GATE_DISABLE          (1 << 12)
3589 # define I915_WM_CLOCK_GATE_DISABLE             (1 << 11)
3590 # define I915_IZ_CLOCK_GATE_DISABLE             (1 << 10)
3591 # define I915_PI_CLOCK_GATE_DISABLE             (1 << 9)
3592 # define I915_DI_CLOCK_GATE_DISABLE             (1 << 8)
3593 # define I915_SH_SV_CLOCK_GATE_DISABLE          (1 << 7)
3594 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE    (1 << 6)
3595 # define I915_SC_CLOCK_GATE_DISABLE             (1 << 5)
3596 # define I915_FL_CLOCK_GATE_DISABLE             (1 << 4)
3597 # define I915_DM_CLOCK_GATE_DISABLE             (1 << 3)
3598 # define I915_PS_CLOCK_GATE_DISABLE             (1 << 2)
3599 # define I915_CC_CLOCK_GATE_DISABLE             (1 << 1)
3600 # define I915_BY_CLOCK_GATE_DISABLE             (1 << 0)
3601
3602 # define I965_RCZ_CLOCK_GATE_DISABLE            (1 << 30)
3603 /* This bit must always be set on 965G/965GM */
3604 # define I965_RCC_CLOCK_GATE_DISABLE            (1 << 29)
3605 # define I965_RCPB_CLOCK_GATE_DISABLE           (1 << 28)
3606 # define I965_DAP_CLOCK_GATE_DISABLE            (1 << 27)
3607 # define I965_ROC_CLOCK_GATE_DISABLE            (1 << 26)
3608 # define I965_GW_CLOCK_GATE_DISABLE             (1 << 25)
3609 # define I965_TD_CLOCK_GATE_DISABLE             (1 << 24)
3610 /* This bit must always be set on 965G */
3611 # define I965_ISC_CLOCK_GATE_DISABLE            (1 << 23)
3612 # define I965_IC_CLOCK_GATE_DISABLE             (1 << 22)
3613 # define I965_EU_CLOCK_GATE_DISABLE             (1 << 21)
3614 # define I965_IF_CLOCK_GATE_DISABLE             (1 << 20)
3615 # define I965_TC_CLOCK_GATE_DISABLE             (1 << 19)
3616 # define I965_SO_CLOCK_GATE_DISABLE             (1 << 17)
3617 # define I965_FBC_CLOCK_GATE_DISABLE            (1 << 16)
3618 # define I965_MARI_CLOCK_GATE_DISABLE           (1 << 15)
3619 # define I965_MASF_CLOCK_GATE_DISABLE           (1 << 14)
3620 # define I965_MAWB_CLOCK_GATE_DISABLE           (1 << 13)
3621 # define I965_EM_CLOCK_GATE_DISABLE             (1 << 12)
3622 # define I965_UC_CLOCK_GATE_DISABLE             (1 << 11)
3623 # define I965_SI_CLOCK_GATE_DISABLE             (1 << 6)
3624 # define I965_MT_CLOCK_GATE_DISABLE             (1 << 5)
3625 # define I965_PL_CLOCK_GATE_DISABLE             (1 << 4)
3626 # define I965_DG_CLOCK_GATE_DISABLE             (1 << 3)
3627 # define I965_QC_CLOCK_GATE_DISABLE             (1 << 2)
3628 # define I965_FT_CLOCK_GATE_DISABLE             (1 << 1)
3629 # define I965_DM_CLOCK_GATE_DISABLE             (1 << 0)
3630
3631 #define RENCLK_GATE_D2          _MMIO(0x6208)
3632 #define VF_UNIT_CLOCK_GATE_DISABLE              (1 << 9)
3633 #define GS_UNIT_CLOCK_GATE_DISABLE              (1 << 7)
3634 #define CL_UNIT_CLOCK_GATE_DISABLE              (1 << 6)
3635
3636 #define VDECCLK_GATE_D          _MMIO(0x620C)           /* g4x only */
3637 #define  VCP_UNIT_CLOCK_GATE_DISABLE            (1 << 4)
3638
3639 #define RAMCLK_GATE_D           _MMIO(0x6210)           /* CRL only */
3640 #define DEUC                    _MMIO(0x6214)          /* CRL only */
3641
3642 #define FW_BLC_SELF_VLV         _MMIO(VLV_DISPLAY_BASE + 0x6500)
3643 #define  FW_CSPWRDWNEN          (1 << 15)
3644
3645 #define MI_ARB_VLV              _MMIO(VLV_DISPLAY_BASE + 0x6504)
3646
3647 #define CZCLK_CDCLK_FREQ_RATIO  _MMIO(VLV_DISPLAY_BASE + 0x6508)
3648 #define   CDCLK_FREQ_SHIFT      4
3649 #define   CDCLK_FREQ_MASK       (0x1f << CDCLK_FREQ_SHIFT)
3650 #define   CZCLK_FREQ_MASK       0xf
3651
3652 #define GCI_CONTROL             _MMIO(VLV_DISPLAY_BASE + 0x650C)
3653 #define   PFI_CREDIT_63         (9 << 28)               /* chv only */
3654 #define   PFI_CREDIT_31         (8 << 28)               /* chv only */
3655 #define   PFI_CREDIT(x)         (((x) - 8) << 28)       /* 8-15 */
3656 #define   PFI_CREDIT_RESEND     (1 << 27)
3657 #define   VGA_FAST_MODE_DISABLE (1 << 14)
3658
3659 #define GMBUSFREQ_VLV           _MMIO(VLV_DISPLAY_BASE + 0x6510)
3660
3661 /*
3662  * Palette regs
3663  */
3664 #define _PALETTE_A              0xa000
3665 #define _PALETTE_B              0xa800
3666 #define _CHV_PALETTE_C          0xc000
3667 #define PALETTE_RED_MASK        REG_GENMASK(23, 16)
3668 #define PALETTE_GREEN_MASK      REG_GENMASK(15, 8)
3669 #define PALETTE_BLUE_MASK       REG_GENMASK(7, 0)
3670 #define PALETTE(pipe, i)        _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
3671                                       _PICK((pipe), _PALETTE_A,         \
3672                                             _PALETTE_B, _CHV_PALETTE_C) + \
3673                                       (i) * 4)
3674
3675 /* MCH MMIO space */
3676
3677 /*
3678  * MCHBAR mirror.
3679  *
3680  * This mirrors the MCHBAR MMIO space whose location is determined by
3681  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3682  * every way.  It is not accessible from the CP register read instructions.
3683  *
3684  * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3685  * just read.
3686  */
3687 #define MCHBAR_MIRROR_BASE      0x10000
3688
3689 #define MCHBAR_MIRROR_BASE_SNB  0x140000
3690
3691 #define CTG_STOLEN_RESERVED             _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3692 #define ELK_STOLEN_RESERVED             _MMIO(MCHBAR_MIRROR_BASE + 0x48)
3693 #define G4X_STOLEN_RESERVED_ADDR1_MASK  (0xFFFF << 16)
3694 #define G4X_STOLEN_RESERVED_ADDR2_MASK  (0xFFF << 4)
3695 #define G4X_STOLEN_RESERVED_ENABLE      (1 << 0)
3696
3697 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3698 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3699
3700 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3701 #define DCC                     _MMIO(MCHBAR_MIRROR_BASE + 0x200)
3702 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL              (0 << 0)
3703 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC     (1 << 0)
3704 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED    (2 << 0)
3705 #define DCC_ADDRESSING_MODE_MASK                        (3 << 0)
3706 #define DCC_CHANNEL_XOR_DISABLE                         (1 << 10)
3707 #define DCC_CHANNEL_XOR_BIT_17                          (1 << 9)
3708 #define DCC2                    _MMIO(MCHBAR_MIRROR_BASE + 0x204)
3709 #define DCC2_MODIFIED_ENHANCED_DISABLE                  (1 << 20)
3710
3711 /* Pineview MCH register contains DDR3 setting */
3712 #define CSHRDDR3CTL            _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3713 #define CSHRDDR3CTL_DDR3       (1 << 2)
3714
3715 /* 965 MCH register controlling DRAM channel configuration */
3716 #define C0DRB3                  _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3717 #define C1DRB3                  _MMIO(MCHBAR_MIRROR_BASE + 0x606)
3718
3719 /* snb MCH registers for reading the DRAM channel configuration */
3720 #define MAD_DIMM_C0                     _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3721 #define MAD_DIMM_C1                     _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3722 #define MAD_DIMM_C2                     _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3723 #define   MAD_DIMM_ECC_MASK             (0x3 << 24)
3724 #define   MAD_DIMM_ECC_OFF              (0x0 << 24)
3725 #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF  (0x1 << 24)
3726 #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON  (0x2 << 24)
3727 #define   MAD_DIMM_ECC_ON               (0x3 << 24)
3728 #define   MAD_DIMM_ENH_INTERLEAVE       (0x1 << 22)
3729 #define   MAD_DIMM_RANK_INTERLEAVE      (0x1 << 21)
3730 #define   MAD_DIMM_B_WIDTH_X16          (0x1 << 20) /* X8 chips if unset */
3731 #define   MAD_DIMM_A_WIDTH_X16          (0x1 << 19) /* X8 chips if unset */
3732 #define   MAD_DIMM_B_DUAL_RANK          (0x1 << 18)
3733 #define   MAD_DIMM_A_DUAL_RANK          (0x1 << 17)
3734 #define   MAD_DIMM_A_SELECT             (0x1 << 16)
3735 /* DIMM sizes are in multiples of 256mb. */
3736 #define   MAD_DIMM_B_SIZE_SHIFT         8
3737 #define   MAD_DIMM_B_SIZE_MASK          (0xff << MAD_DIMM_B_SIZE_SHIFT)
3738 #define   MAD_DIMM_A_SIZE_SHIFT         0
3739 #define   MAD_DIMM_A_SIZE_MASK          (0xff << MAD_DIMM_A_SIZE_SHIFT)
3740
3741 /* snb MCH registers for priority tuning */
3742 #define MCH_SSKPD                       _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3743 #define   MCH_SSKPD_WM0_MASK            0x3f
3744 #define   MCH_SSKPD_WM0_VAL             0xc
3745
3746 #define MCH_SECP_NRG_STTS               _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
3747
3748 /* Clocking configuration register */
3749 #define CLKCFG                  _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3750 #define CLKCFG_FSB_400                                  (5 << 0)        /* hrawclk 100 */
3751 #define CLKCFG_FSB_533                                  (1 << 0)        /* hrawclk 133 */
3752 #define CLKCFG_FSB_667                                  (3 << 0)        /* hrawclk 166 */
3753 #define CLKCFG_FSB_800                                  (2 << 0)        /* hrawclk 200 */
3754 #define CLKCFG_FSB_1067                                 (6 << 0)        /* hrawclk 266 */
3755 #define CLKCFG_FSB_1067_ALT                             (0 << 0)        /* hrawclk 266 */
3756 #define CLKCFG_FSB_1333                                 (7 << 0)        /* hrawclk 333 */
3757 /*
3758  * Note that on at least on ELK the below value is reported for both
3759  * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3760  * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3761  */
3762 #define CLKCFG_FSB_1333_ALT                             (4 << 0)        /* hrawclk 333 */
3763 #define CLKCFG_FSB_MASK                                 (7 << 0)
3764 #define CLKCFG_MEM_533                                  (1 << 4)
3765 #define CLKCFG_MEM_667                                  (2 << 4)
3766 #define CLKCFG_MEM_800                                  (3 << 4)
3767 #define CLKCFG_MEM_MASK                                 (7 << 4)
3768
3769 #define HPLLVCO                 _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3770 #define HPLLVCO_MOBILE          _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3771
3772 #define TSC1                    _MMIO(0x11001)
3773 #define   TSE                   (1 << 0)
3774 #define TR1                     _MMIO(0x11006)
3775 #define TSFS                    _MMIO(0x11020)
3776 #define   TSFS_SLOPE_MASK       0x0000ff00
3777 #define   TSFS_SLOPE_SHIFT      8
3778 #define   TSFS_INTR_MASK        0x000000ff
3779
3780 #define CRSTANDVID              _MMIO(0x11100)
3781 #define PXVFREQ(fstart)         _MMIO(0x11110 + (fstart) * 4)  /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3782 #define   PXVFREQ_PX_MASK       0x7f000000
3783 #define   PXVFREQ_PX_SHIFT      24
3784 #define VIDFREQ_BASE            _MMIO(0x11110)
3785 #define VIDFREQ1                _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3786 #define VIDFREQ2                _MMIO(0x11114)
3787 #define VIDFREQ3                _MMIO(0x11118)
3788 #define VIDFREQ4                _MMIO(0x1111c)
3789 #define   VIDFREQ_P0_MASK       0x1f000000
3790 #define   VIDFREQ_P0_SHIFT      24
3791 #define   VIDFREQ_P0_CSCLK_MASK 0x00f00000
3792 #define   VIDFREQ_P0_CSCLK_SHIFT 20
3793 #define   VIDFREQ_P0_CRCLK_MASK 0x000f0000
3794 #define   VIDFREQ_P0_CRCLK_SHIFT 16
3795 #define   VIDFREQ_P1_MASK       0x00001f00
3796 #define   VIDFREQ_P1_SHIFT      8
3797 #define   VIDFREQ_P1_CSCLK_MASK 0x000000f0
3798 #define   VIDFREQ_P1_CSCLK_SHIFT 4
3799 #define   VIDFREQ_P1_CRCLK_MASK 0x0000000f
3800 #define INTTOEXT_BASE_ILK       _MMIO(0x11300)
3801 #define INTTOEXT_BASE           _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3802 #define   INTTOEXT_MAP3_SHIFT   24
3803 #define   INTTOEXT_MAP3_MASK    (0x1f << INTTOEXT_MAP3_SHIFT)
3804 #define   INTTOEXT_MAP2_SHIFT   16
3805 #define   INTTOEXT_MAP2_MASK    (0x1f << INTTOEXT_MAP2_SHIFT)
3806 #define   INTTOEXT_MAP1_SHIFT   8
3807 #define   INTTOEXT_MAP1_MASK    (0x1f << INTTOEXT_MAP1_SHIFT)
3808 #define   INTTOEXT_MAP0_SHIFT   0
3809 #define   INTTOEXT_MAP0_MASK    (0x1f << INTTOEXT_MAP0_SHIFT)
3810 #define MEMSWCTL                _MMIO(0x11170) /* Ironlake only */
3811 #define   MEMCTL_CMD_MASK       0xe000
3812 #define   MEMCTL_CMD_SHIFT      13
3813 #define   MEMCTL_CMD_RCLK_OFF   0
3814 #define   MEMCTL_CMD_RCLK_ON    1
3815 #define   MEMCTL_CMD_CHFREQ     2
3816 #define   MEMCTL_CMD_CHVID      3
3817 #define   MEMCTL_CMD_VMMOFF     4
3818 #define   MEMCTL_CMD_VMMON      5
3819 #define   MEMCTL_CMD_STS        (1 << 12) /* write 1 triggers command, clears
3820                                            when command complete */
3821 #define   MEMCTL_FREQ_MASK      0x0f00 /* jitter, from 0-15 */
3822 #define   MEMCTL_FREQ_SHIFT     8
3823 #define   MEMCTL_SFCAVM         (1 << 7)
3824 #define   MEMCTL_TGT_VID_MASK   0x007f
3825 #define MEMIHYST                _MMIO(0x1117c)
3826 #define MEMINTREN               _MMIO(0x11180) /* 16 bits */
3827 #define   MEMINT_RSEXIT_EN      (1 << 8)
3828 #define   MEMINT_CX_SUPR_EN     (1 << 7)
3829 #define   MEMINT_CONT_BUSY_EN   (1 << 6)
3830 #define   MEMINT_AVG_BUSY_EN    (1 << 5)
3831 #define   MEMINT_EVAL_CHG_EN    (1 << 4)
3832 #define   MEMINT_MON_IDLE_EN    (1 << 3)
3833 #define   MEMINT_UP_EVAL_EN     (1 << 2)
3834 #define   MEMINT_DOWN_EVAL_EN   (1 << 1)
3835 #define   MEMINT_SW_CMD_EN      (1 << 0)
3836 #define MEMINTRSTR              _MMIO(0x11182) /* 16 bits */
3837 #define   MEM_RSEXIT_MASK       0xc000
3838 #define   MEM_RSEXIT_SHIFT      14
3839 #define   MEM_CONT_BUSY_MASK    0x3000
3840 #define   MEM_CONT_BUSY_SHIFT   12
3841 #define   MEM_AVG_BUSY_MASK     0x0c00
3842 #define   MEM_AVG_BUSY_SHIFT    10
3843 #define   MEM_EVAL_CHG_MASK     0x0300
3844 #define   MEM_EVAL_BUSY_SHIFT   8
3845 #define   MEM_MON_IDLE_MASK     0x00c0
3846 #define   MEM_MON_IDLE_SHIFT    6
3847 #define   MEM_UP_EVAL_MASK      0x0030
3848 #define   MEM_UP_EVAL_SHIFT     4
3849 #define   MEM_DOWN_EVAL_MASK    0x000c
3850 #define   MEM_DOWN_EVAL_SHIFT   2
3851 #define   MEM_SW_CMD_MASK       0x0003
3852 #define   MEM_INT_STEER_GFX     0
3853 #define   MEM_INT_STEER_CMR     1
3854 #define   MEM_INT_STEER_SMI     2
3855 #define   MEM_INT_STEER_SCI     3
3856 #define MEMINTRSTS              _MMIO(0x11184)
3857 #define   MEMINT_RSEXIT         (1 << 7)
3858 #define   MEMINT_CONT_BUSY      (1 << 6)
3859 #define   MEMINT_AVG_BUSY       (1 << 5)
3860 #define   MEMINT_EVAL_CHG       (1 << 4)
3861 #define   MEMINT_MON_IDLE       (1 << 3)
3862 #define   MEMINT_UP_EVAL        (1 << 2)
3863 #define   MEMINT_DOWN_EVAL      (1 << 1)
3864 #define   MEMINT_SW_CMD         (1 << 0)
3865 #define MEMMODECTL              _MMIO(0x11190)
3866 #define   MEMMODE_BOOST_EN      (1 << 31)
3867 #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3868 #define   MEMMODE_BOOST_FREQ_SHIFT 24
3869 #define   MEMMODE_IDLE_MODE_MASK 0x00030000
3870 #define   MEMMODE_IDLE_MODE_SHIFT 16
3871 #define   MEMMODE_IDLE_MODE_EVAL 0
3872 #define   MEMMODE_IDLE_MODE_CONT 1
3873 #define   MEMMODE_HWIDLE_EN     (1 << 15)
3874 #define   MEMMODE_SWMODE_EN     (1 << 14)
3875 #define   MEMMODE_RCLK_GATE     (1 << 13)
3876 #define   MEMMODE_HW_UPDATE     (1 << 12)
3877 #define   MEMMODE_FSTART_MASK   0x00000f00 /* starting jitter, 0-15 */
3878 #define   MEMMODE_FSTART_SHIFT  8
3879 #define   MEMMODE_FMAX_MASK     0x000000f0 /* max jitter, 0-15 */
3880 #define   MEMMODE_FMAX_SHIFT    4
3881 #define   MEMMODE_FMIN_MASK     0x0000000f /* min jitter, 0-15 */
3882 #define RCBMAXAVG               _MMIO(0x1119c)
3883 #define MEMSWCTL2               _MMIO(0x1119e) /* Cantiga only */
3884 #define   SWMEMCMD_RENDER_OFF   (0 << 13)
3885 #define   SWMEMCMD_RENDER_ON    (1 << 13)
3886 #define   SWMEMCMD_SWFREQ       (2 << 13)
3887 #define   SWMEMCMD_TARVID       (3 << 13)
3888 #define   SWMEMCMD_VRM_OFF      (4 << 13)
3889 #define   SWMEMCMD_VRM_ON       (5 << 13)
3890 #define   CMDSTS                (1 << 12)
3891 #define   SFCAVM                (1 << 11)
3892 #define   SWFREQ_MASK           0x0380 /* P0-7 */
3893 #define   SWFREQ_SHIFT          7
3894 #define   TARVID_MASK           0x001f
3895 #define MEMSTAT_CTG             _MMIO(0x111a0)
3896 #define RCBMINAVG               _MMIO(0x111a0)
3897 #define RCUPEI                  _MMIO(0x111b0)
3898 #define RCDNEI                  _MMIO(0x111b4)
3899 #define RSTDBYCTL               _MMIO(0x111b8)
3900 #define   RS1EN                 (1 << 31)
3901 #define   RS2EN                 (1 << 30)
3902 #define   RS3EN                 (1 << 29)
3903 #define   D3RS3EN               (1 << 28) /* Display D3 imlies RS3 */
3904 #define   SWPROMORSX            (1 << 27) /* RSx promotion timers ignored */
3905 #define   RCWAKERW              (1 << 26) /* Resetwarn from PCH causes wakeup */
3906 #define   DPRSLPVREN            (1 << 25) /* Fast voltage ramp enable */
3907 #define   GFXTGHYST             (1 << 24) /* Hysteresis to allow trunk gating */
3908 #define   RCX_SW_EXIT           (1 << 23) /* Leave RSx and prevent re-entry */
3909 #define   RSX_STATUS_MASK       (7 << 20)
3910 #define   RSX_STATUS_ON         (0 << 20)
3911 #define   RSX_STATUS_RC1        (1 << 20)
3912 #define   RSX_STATUS_RC1E       (2 << 20)
3913 #define   RSX_STATUS_RS1        (3 << 20)
3914 #define   RSX_STATUS_RS2        (4 << 20) /* aka rc6 */
3915 #define   RSX_STATUS_RSVD       (5 << 20) /* deep rc6 unsupported on ilk */
3916 #define   RSX_STATUS_RS3        (6 << 20) /* rs3 unsupported on ilk */
3917 #define   RSX_STATUS_RSVD2      (7 << 20)
3918 #define   UWRCRSXE              (1 << 19) /* wake counter limit prevents rsx */
3919 #define   RSCRP                 (1 << 18) /* rs requests control on rs1/2 reqs */
3920 #define   JRSC                  (1 << 17) /* rsx coupled to cpu c-state */
3921 #define   RS2INC0               (1 << 16) /* allow rs2 in cpu c0 */
3922 #define   RS1CONTSAV_MASK       (3 << 14)
3923 #define   RS1CONTSAV_NO_RS1     (0 << 14) /* rs1 doesn't save/restore context */
3924 #define   RS1CONTSAV_RSVD       (1 << 14)
3925 #define   RS1CONTSAV_SAVE_RS1   (2 << 14) /* rs1 saves context */
3926 #define   RS1CONTSAV_FULL_RS1   (3 << 14) /* rs1 saves and restores context */
3927 #define   NORMSLEXLAT_MASK      (3 << 12)
3928 #define   SLOW_RS123            (0 << 12)
3929 #define   SLOW_RS23             (1 << 12)
3930 #define   SLOW_RS3              (2 << 12)
3931 #define   NORMAL_RS123          (3 << 12)
3932 #define   RCMODE_TIMEOUT        (1 << 11) /* 0 is eval interval method */
3933 #define   IMPROMOEN             (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3934 #define   RCENTSYNC             (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
3935 #define   STATELOCK             (1 << 7) /* locked to rs_cstate if 0 */
3936 #define   RS_CSTATE_MASK        (3 << 4)
3937 #define   RS_CSTATE_C367_RS1    (0 << 4)
3938 #define   RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
3939 #define   RS_CSTATE_RSVD        (2 << 4)
3940 #define   RS_CSTATE_C367_RS2    (3 << 4)
3941 #define   REDSAVES              (1 << 3) /* no context save if was idle during rs0 */
3942 #define   REDRESTORES           (1 << 2) /* no restore if was idle during rs0 */
3943 #define VIDCTL                  _MMIO(0x111c0)
3944 #define VIDSTS                  _MMIO(0x111c8)
3945 #define VIDSTART                _MMIO(0x111cc) /* 8 bits */
3946 #define MEMSTAT_ILK             _MMIO(0x111f8)
3947 #define   MEMSTAT_VID_MASK      0x7f00
3948 #define   MEMSTAT_VID_SHIFT     8
3949 #define   MEMSTAT_PSTATE_MASK   0x00f8
3950 #define   MEMSTAT_PSTATE_SHIFT  3
3951 #define   MEMSTAT_MON_ACTV      (1 << 2)
3952 #define   MEMSTAT_SRC_CTL_MASK  0x0003
3953 #define   MEMSTAT_SRC_CTL_CORE  0
3954 #define   MEMSTAT_SRC_CTL_TRB   1
3955 #define   MEMSTAT_SRC_CTL_THM   2
3956 #define   MEMSTAT_SRC_CTL_STDBY 3
3957 #define RCPREVBSYTUPAVG         _MMIO(0x113b8)
3958 #define RCPREVBSYTDNAVG         _MMIO(0x113bc)
3959 #define PMMISC                  _MMIO(0x11214)
3960 #define   MCPPCE_EN             (1 << 0) /* enable PM_MSG from PCH->MPC */
3961 #define SDEW                    _MMIO(0x1124c)
3962 #define CSIEW0                  _MMIO(0x11250)
3963 #define CSIEW1                  _MMIO(0x11254)
3964 #define CSIEW2                  _MMIO(0x11258)
3965 #define PEW(i)                  _MMIO(0x1125c + (i) * 4) /* 5 registers */
3966 #define DEW(i)                  _MMIO(0x11270 + (i) * 4) /* 3 registers */
3967 #define MCHAFE                  _MMIO(0x112c0)
3968 #define CSIEC                   _MMIO(0x112e0)
3969 #define DMIEC                   _MMIO(0x112e4)
3970 #define DDREC                   _MMIO(0x112e8)
3971 #define PEG0EC                  _MMIO(0x112ec)
3972 #define PEG1EC                  _MMIO(0x112f0)
3973 #define GFXEC                   _MMIO(0x112f4)
3974 #define RPPREVBSYTUPAVG         _MMIO(0x113b8)
3975 #define RPPREVBSYTDNAVG         _MMIO(0x113bc)
3976 #define ECR                     _MMIO(0x11600)
3977 #define   ECR_GPFE              (1 << 31)
3978 #define   ECR_IMONE             (1 << 30)
3979 #define   ECR_CAP_MASK          0x0000001f /* Event range, 0-31 */
3980 #define OGW0                    _MMIO(0x11608)
3981 #define OGW1                    _MMIO(0x1160c)
3982 #define EG0                     _MMIO(0x11610)
3983 #define EG1                     _MMIO(0x11614)
3984 #define EG2                     _MMIO(0x11618)
3985 #define EG3                     _MMIO(0x1161c)
3986 #define EG4                     _MMIO(0x11620)
3987 #define EG5                     _MMIO(0x11624)
3988 #define EG6                     _MMIO(0x11628)
3989 #define EG7                     _MMIO(0x1162c)
3990 #define PXW(i)                  _MMIO(0x11664 + (i) * 4) /* 4 registers */
3991 #define PXWL(i)                 _MMIO(0x11680 + (i) * 8) /* 8 registers */
3992 #define LCFUSE02                _MMIO(0x116c0)
3993 #define   LCFUSE_HIV_MASK       0x000000ff
3994 #define CSIPLL0                 _MMIO(0x12c10)
3995 #define DDRMPLL1                _MMIO(0X12c20)
3996 #define PEG_BAND_GAP_DATA       _MMIO(0x14d68)
3997
3998 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
3999 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
4000
4001 #define GEN6_GT_PERF_STATUS     _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
4002 #define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
4003 #define GEN6_RP_STATE_LIMITS    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
4004 #define GEN6_RP_STATE_CAP       _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
4005 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
4006
4007 /*
4008  * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
4009  * 8300) freezing up around GPU hangs. Looks as if even
4010  * scheduling/timer interrupts start misbehaving if the RPS
4011  * EI/thresholds are "bad", leading to a very sluggish or even
4012  * frozen machine.
4013  */
4014 #define INTERVAL_1_28_US(us)    roundup(((us) * 100) >> 7, 25)
4015 #define INTERVAL_1_33_US(us)    (((us) * 3)   >> 2)
4016 #define INTERVAL_0_833_US(us)   (((us) * 6) / 5)
4017 #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
4018                                 (IS_GEN9_LP(dev_priv) ? \
4019                                 INTERVAL_0_833_US(us) : \
4020                                 INTERVAL_1_33_US(us)) : \
4021                                 INTERVAL_1_28_US(us))
4022
4023 #define INTERVAL_1_28_TO_US(interval)  (((interval) << 7) / 100)
4024 #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
4025 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
4026 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
4027                            (IS_GEN9_LP(dev_priv) ? \
4028                            INTERVAL_0_833_TO_US(interval) : \
4029                            INTERVAL_1_33_TO_US(interval)) : \
4030                            INTERVAL_1_28_TO_US(interval))
4031
4032 /*
4033  * Logical Context regs
4034  */
4035 #define CCID(base)                      _MMIO((base) + 0x180)
4036 #define   CCID_EN                       BIT(0)
4037 #define   CCID_EXTENDED_STATE_RESTORE   BIT(2)
4038 #define   CCID_EXTENDED_STATE_SAVE      BIT(3)
4039 /*
4040  * Notes on SNB/IVB/VLV context size:
4041  * - Power context is saved elsewhere (LLC or stolen)
4042  * - Ring/execlist context is saved on SNB, not on IVB
4043  * - Extended context size already includes render context size
4044  * - We always need to follow the extended context size.
4045  *   SNB BSpec has comments indicating that we should use the
4046  *   render context size instead if execlists are disabled, but
4047  *   based on empirical testing that's just nonsense.
4048  * - Pipelined/VF state is saved on SNB/IVB respectively
4049  * - GT1 size just indicates how much of render context
4050  *   doesn't need saving on GT1
4051  */
4052 #define CXT_SIZE                _MMIO(0x21a0)
4053 #define GEN6_CXT_POWER_SIZE(cxt_reg)    (((cxt_reg) >> 24) & 0x3f)
4054 #define GEN6_CXT_RING_SIZE(cxt_reg)     (((cxt_reg) >> 18) & 0x3f)
4055 #define GEN6_CXT_RENDER_SIZE(cxt_reg)   (((cxt_reg) >> 12) & 0x3f)
4056 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
4057 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
4058 #define GEN6_CXT_TOTAL_SIZE(cxt_reg)    (GEN6_CXT_RING_SIZE(cxt_reg) + \
4059                                         GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
4060                                         GEN6_CXT_PIPELINE_SIZE(cxt_reg))
4061 #define GEN7_CXT_SIZE           _MMIO(0x21a8)
4062 #define GEN7_CXT_POWER_SIZE(ctx_reg)    (((ctx_reg) >> 25) & 0x7f)
4063 #define GEN7_CXT_RING_SIZE(ctx_reg)     (((ctx_reg) >> 22) & 0x7)
4064 #define GEN7_CXT_RENDER_SIZE(ctx_reg)   (((ctx_reg) >> 16) & 0x3f)
4065 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
4066 #define GEN7_CXT_GT1_SIZE(ctx_reg)      (((ctx_reg) >> 6) & 0x7)
4067 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)  (((ctx_reg) >> 0) & 0x3f)
4068 #define GEN7_CXT_TOTAL_SIZE(ctx_reg)    (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
4069                                          GEN7_CXT_VFSTATE_SIZE(ctx_reg))
4070
4071 enum {
4072         INTEL_ADVANCED_CONTEXT = 0,
4073         INTEL_LEGACY_32B_CONTEXT,
4074         INTEL_ADVANCED_AD_CONTEXT,
4075         INTEL_LEGACY_64B_CONTEXT
4076 };
4077
4078 enum {
4079         FAULT_AND_HANG = 0,
4080         FAULT_AND_HALT, /* Debug only */
4081         FAULT_AND_STREAM,
4082         FAULT_AND_CONTINUE /* Unsupported */
4083 };
4084
4085 #define GEN8_CTX_VALID (1 << 0)
4086 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
4087 #define GEN8_CTX_FORCE_RESTORE (1 << 2)
4088 #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
4089 #define GEN8_CTX_PRIVILEGE (1 << 8)
4090 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
4091
4092 #define GEN8_CTX_ID_SHIFT 32
4093 #define GEN8_CTX_ID_WIDTH 21
4094 #define GEN11_SW_CTX_ID_SHIFT 37
4095 #define GEN11_SW_CTX_ID_WIDTH 11
4096 #define GEN11_ENGINE_CLASS_SHIFT 61
4097 #define GEN11_ENGINE_CLASS_WIDTH 3
4098 #define GEN11_ENGINE_INSTANCE_SHIFT 48
4099 #define GEN11_ENGINE_INSTANCE_WIDTH 6
4100
4101 #define CHV_CLK_CTL1                    _MMIO(0x101100)
4102 #define VLV_CLK_CTL2                    _MMIO(0x101104)
4103 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT   28
4104
4105 /*
4106  * Overlay regs
4107  */
4108
4109 #define OVADD                   _MMIO(0x30000)
4110 #define DOVSTA                  _MMIO(0x30008)
4111 #define OC_BUF                  (0x3 << 20)
4112 #define OGAMC5                  _MMIO(0x30010)
4113 #define OGAMC4                  _MMIO(0x30014)
4114 #define OGAMC3                  _MMIO(0x30018)
4115 #define OGAMC2                  _MMIO(0x3001c)
4116 #define OGAMC1                  _MMIO(0x30020)
4117 #define OGAMC0                  _MMIO(0x30024)
4118
4119 /*
4120  * GEN9 clock gating regs
4121  */
4122 #define GEN9_CLKGATE_DIS_0              _MMIO(0x46530)
4123 #define   DARBF_GATING_DIS              (1 << 27)
4124 #define   PWM2_GATING_DIS               (1 << 14)
4125 #define   PWM1_GATING_DIS               (1 << 13)
4126
4127 #define GEN9_CLKGATE_DIS_4              _MMIO(0x4653C)
4128 #define   BXT_GMBUS_GATING_DIS          (1 << 14)
4129
4130 #define _CLKGATE_DIS_PSL_A              0x46520
4131 #define _CLKGATE_DIS_PSL_B              0x46524
4132 #define _CLKGATE_DIS_PSL_C              0x46528
4133 #define   DUPS1_GATING_DIS              (1 << 15)
4134 #define   DUPS2_GATING_DIS              (1 << 19)
4135 #define   DUPS3_GATING_DIS              (1 << 23)
4136 #define   DPF_GATING_DIS                (1 << 10)
4137 #define   DPF_RAM_GATING_DIS            (1 << 9)
4138 #define   DPFR_GATING_DIS               (1 << 8)
4139
4140 #define CLKGATE_DIS_PSL(pipe) \
4141         _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
4142
4143 /*
4144  * GEN10 clock gating regs
4145  */
4146 #define SLICE_UNIT_LEVEL_CLKGATE        _MMIO(0x94d4)
4147 #define  SARBUNIT_CLKGATE_DIS           (1 << 5)
4148 #define  RCCUNIT_CLKGATE_DIS            (1 << 7)
4149 #define  MSCUNIT_CLKGATE_DIS            (1 << 10)
4150 #define  L3_CLKGATE_DIS                 REG_BIT(16)
4151 #define  L3_CR2X_CLKGATE_DIS            REG_BIT(17)
4152
4153 #define SUBSLICE_UNIT_LEVEL_CLKGATE     _MMIO(0x9524)
4154 #define  GWUNIT_CLKGATE_DIS             (1 << 16)
4155
4156 #define SUBSLICE_UNIT_LEVEL_CLKGATE2    _MMIO(0x9528)
4157 #define  CPSSUNIT_CLKGATE_DIS           REG_BIT(9)
4158
4159 #define UNSLICE_UNIT_LEVEL_CLKGATE      _MMIO(0x9434)
4160 #define   VFUNIT_CLKGATE_DIS            REG_BIT(20)
4161 #define   HSUNIT_CLKGATE_DIS            REG_BIT(8)
4162 #define   VSUNIT_CLKGATE_DIS            REG_BIT(3)
4163
4164 #define UNSLICE_UNIT_LEVEL_CLKGATE2     _MMIO(0x94e4)
4165 #define   VSUNIT_CLKGATE_DIS_TGL        REG_BIT(19)
4166 #define   PSDUNIT_CLKGATE_DIS           REG_BIT(5)
4167
4168 #define INF_UNIT_LEVEL_CLKGATE          _MMIO(0x9560)
4169 #define   CGPSF_CLKGATE_DIS             (1 << 3)
4170
4171 /*
4172  * Display engine regs
4173  */
4174
4175 /* Pipe A CRC regs */
4176 #define _PIPE_CRC_CTL_A                 0x60050
4177 #define   PIPE_CRC_ENABLE               (1 << 31)
4178 /* skl+ source selection */
4179 #define   PIPE_CRC_SOURCE_PLANE_1_SKL   (0 << 28)
4180 #define   PIPE_CRC_SOURCE_PLANE_2_SKL   (2 << 28)
4181 #define   PIPE_CRC_SOURCE_DMUX_SKL      (4 << 28)
4182 #define   PIPE_CRC_SOURCE_PLANE_3_SKL   (6 << 28)
4183 #define   PIPE_CRC_SOURCE_PLANE_4_SKL   (7 << 28)
4184 #define   PIPE_CRC_SOURCE_PLANE_5_SKL   (5 << 28)
4185 #define   PIPE_CRC_SOURCE_PLANE_6_SKL   (3 << 28)
4186 #define   PIPE_CRC_SOURCE_PLANE_7_SKL   (1 << 28)
4187 /* ivb+ source selection */
4188 #define   PIPE_CRC_SOURCE_PRIMARY_IVB   (0 << 29)
4189 #define   PIPE_CRC_SOURCE_SPRITE_IVB    (1 << 29)
4190 #define   PIPE_CRC_SOURCE_PF_IVB        (2 << 29)
4191 /* ilk+ source selection */
4192 #define   PIPE_CRC_SOURCE_PRIMARY_ILK   (0 << 28)
4193 #define   PIPE_CRC_SOURCE_SPRITE_ILK    (1 << 28)
4194 #define   PIPE_CRC_SOURCE_PIPE_ILK      (2 << 28)
4195 /* embedded DP port on the north display block, reserved on ivb */
4196 #define   PIPE_CRC_SOURCE_PORT_A_ILK    (4 << 28)
4197 #define   PIPE_CRC_SOURCE_FDI_ILK       (5 << 28) /* reserved on ivb */
4198 /* vlv source selection */
4199 #define   PIPE_CRC_SOURCE_PIPE_VLV      (0 << 27)
4200 #define   PIPE_CRC_SOURCE_HDMIB_VLV     (1 << 27)
4201 #define   PIPE_CRC_SOURCE_HDMIC_VLV     (2 << 27)
4202 /* with DP port the pipe source is invalid */
4203 #define   PIPE_CRC_SOURCE_DP_D_VLV      (3 << 27)
4204 #define   PIPE_CRC_SOURCE_DP_B_VLV      (6 << 27)
4205 #define   PIPE_CRC_SOURCE_DP_C_VLV      (7 << 27)
4206 /* gen3+ source selection */
4207 #define   PIPE_CRC_SOURCE_PIPE_I9XX     (0 << 28)
4208 #define   PIPE_CRC_SOURCE_SDVOB_I9XX    (1 << 28)
4209 #define   PIPE_CRC_SOURCE_SDVOC_I9XX    (2 << 28)
4210 /* with DP/TV port the pipe source is invalid */
4211 #define   PIPE_CRC_SOURCE_DP_D_G4X      (3 << 28)
4212 #define   PIPE_CRC_SOURCE_TV_PRE        (4 << 28)
4213 #define   PIPE_CRC_SOURCE_TV_POST       (5 << 28)
4214 #define   PIPE_CRC_SOURCE_DP_B_G4X      (6 << 28)
4215 #define   PIPE_CRC_SOURCE_DP_C_G4X      (7 << 28)
4216 /* gen2 doesn't have source selection bits */
4217 #define   PIPE_CRC_INCLUDE_BORDER_I8XX  (1 << 30)
4218
4219 #define _PIPE_CRC_RES_1_A_IVB           0x60064
4220 #define _PIPE_CRC_RES_2_A_IVB           0x60068
4221 #define _PIPE_CRC_RES_3_A_IVB           0x6006c
4222 #define _PIPE_CRC_RES_4_A_IVB           0x60070
4223 #define _PIPE_CRC_RES_5_A_IVB           0x60074
4224
4225 #define _PIPE_CRC_RES_RED_A             0x60060
4226 #define _PIPE_CRC_RES_GREEN_A           0x60064
4227 #define _PIPE_CRC_RES_BLUE_A            0x60068
4228 #define _PIPE_CRC_RES_RES1_A_I915       0x6006c
4229 #define _PIPE_CRC_RES_RES2_A_G4X        0x60080
4230
4231 /* Pipe B CRC regs */
4232 #define _PIPE_CRC_RES_1_B_IVB           0x61064
4233 #define _PIPE_CRC_RES_2_B_IVB           0x61068
4234 #define _PIPE_CRC_RES_3_B_IVB           0x6106c
4235 #define _PIPE_CRC_RES_4_B_IVB           0x61070
4236 #define _PIPE_CRC_RES_5_B_IVB           0x61074
4237
4238 #define PIPE_CRC_CTL(pipe)              _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4239 #define PIPE_CRC_RES_1_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4240 #define PIPE_CRC_RES_2_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4241 #define PIPE_CRC_RES_3_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4242 #define PIPE_CRC_RES_4_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4243 #define PIPE_CRC_RES_5_IVB(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4244
4245 #define PIPE_CRC_RES_RED(pipe)          _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4246 #define PIPE_CRC_RES_GREEN(pipe)        _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4247 #define PIPE_CRC_RES_BLUE(pipe)         _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4248 #define PIPE_CRC_RES_RES1_I915(pipe)    _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4249 #define PIPE_CRC_RES_RES2_G4X(pipe)     _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4250
4251 /* Pipe A timing regs */
4252 #define _HTOTAL_A       0x60000
4253 #define _HBLANK_A       0x60004
4254 #define _HSYNC_A        0x60008
4255 #define _VTOTAL_A       0x6000c
4256 #define _VBLANK_A       0x60010
4257 #define _VSYNC_A        0x60014
4258 #define _EXITLINE_A     0x60018
4259 #define _PIPEASRC       0x6001c
4260 #define _BCLRPAT_A      0x60020
4261 #define _VSYNCSHIFT_A   0x60028
4262 #define _PIPE_MULT_A    0x6002c
4263
4264 /* Pipe B timing regs */
4265 #define _HTOTAL_B       0x61000
4266 #define _HBLANK_B       0x61004
4267 #define _HSYNC_B        0x61008
4268 #define _VTOTAL_B       0x6100c
4269 #define _VBLANK_B       0x61010
4270 #define _VSYNC_B        0x61014
4271 #define _PIPEBSRC       0x6101c
4272 #define _BCLRPAT_B      0x61020
4273 #define _VSYNCSHIFT_B   0x61028
4274 #define _PIPE_MULT_B    0x6102c
4275
4276 /* DSI 0 timing regs */
4277 #define _HTOTAL_DSI0            0x6b000
4278 #define _HSYNC_DSI0             0x6b008
4279 #define _VTOTAL_DSI0            0x6b00c
4280 #define _VSYNC_DSI0             0x6b014
4281 #define _VSYNCSHIFT_DSI0        0x6b028
4282
4283 /* DSI 1 timing regs */
4284 #define _HTOTAL_DSI1            0x6b800
4285 #define _HSYNC_DSI1             0x6b808
4286 #define _VTOTAL_DSI1            0x6b80c
4287 #define _VSYNC_DSI1             0x6b814
4288 #define _VSYNCSHIFT_DSI1        0x6b828
4289
4290 #define TRANSCODER_A_OFFSET 0x60000
4291 #define TRANSCODER_B_OFFSET 0x61000
4292 #define TRANSCODER_C_OFFSET 0x62000
4293 #define CHV_TRANSCODER_C_OFFSET 0x63000
4294 #define TRANSCODER_D_OFFSET 0x63000
4295 #define TRANSCODER_EDP_OFFSET 0x6f000
4296 #define TRANSCODER_DSI0_OFFSET  0x6b000
4297 #define TRANSCODER_DSI1_OFFSET  0x6b800
4298
4299 #define HTOTAL(trans)           _MMIO_TRANS2(trans, _HTOTAL_A)
4300 #define HBLANK(trans)           _MMIO_TRANS2(trans, _HBLANK_A)
4301 #define HSYNC(trans)            _MMIO_TRANS2(trans, _HSYNC_A)
4302 #define VTOTAL(trans)           _MMIO_TRANS2(trans, _VTOTAL_A)
4303 #define VBLANK(trans)           _MMIO_TRANS2(trans, _VBLANK_A)
4304 #define VSYNC(trans)            _MMIO_TRANS2(trans, _VSYNC_A)
4305 #define BCLRPAT(trans)          _MMIO_TRANS2(trans, _BCLRPAT_A)
4306 #define VSYNCSHIFT(trans)       _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4307 #define PIPESRC(trans)          _MMIO_TRANS2(trans, _PIPEASRC)
4308 #define PIPE_MULT(trans)        _MMIO_TRANS2(trans, _PIPE_MULT_A)
4309
4310 #define EXITLINE(trans)         _MMIO_TRANS2(trans, _EXITLINE_A)
4311 #define   EXITLINE_ENABLE       REG_BIT(31)
4312 #define   EXITLINE_MASK         REG_GENMASK(12, 0)
4313 #define   EXITLINE_SHIFT        0
4314
4315 /*
4316  * HSW+ eDP PSR registers
4317  *
4318  * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
4319  * instance of it
4320  */
4321 #define _HSW_EDP_PSR_BASE                       0x64800
4322 #define _SRD_CTL_A                              0x60800
4323 #define _SRD_CTL_EDP                            0x6f800
4324 #define _PSR_ADJ(tran, reg)                     (_TRANS2(tran, reg) - dev_priv->hsw_psr_mmio_adjust)
4325 #define EDP_PSR_CTL(tran)                       _MMIO(_PSR_ADJ(tran, _SRD_CTL_A))
4326 #define   EDP_PSR_ENABLE                        (1 << 31)
4327 #define   BDW_PSR_SINGLE_FRAME                  (1 << 30)
4328 #define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK   (1 << 29) /* SW can't modify */
4329 #define   EDP_PSR_LINK_STANDBY                  (1 << 27)
4330 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK      (3 << 25)
4331 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES   (0 << 25)
4332 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES   (1 << 25)
4333 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES   (2 << 25)
4334 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES   (3 << 25)
4335 #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT          20
4336 #define   EDP_PSR_SKIP_AUX_EXIT                 (1 << 12)
4337 #define   EDP_PSR_TP1_TP2_SEL                   (0 << 11)
4338 #define   EDP_PSR_TP1_TP3_SEL                   (1 << 11)
4339 #define   EDP_PSR_CRC_ENABLE                    (1 << 10) /* BDW+ */
4340 #define   EDP_PSR_TP2_TP3_TIME_500us            (0 << 8)
4341 #define   EDP_PSR_TP2_TP3_TIME_100us            (1 << 8)
4342 #define   EDP_PSR_TP2_TP3_TIME_2500us           (2 << 8)
4343 #define   EDP_PSR_TP2_TP3_TIME_0us              (3 << 8)
4344 #define   EDP_PSR_TP4_TIME_0US                  (3 << 6) /* ICL+ */
4345 #define   EDP_PSR_TP1_TIME_500us                (0 << 4)
4346 #define   EDP_PSR_TP1_TIME_100us                (1 << 4)
4347 #define   EDP_PSR_TP1_TIME_2500us               (2 << 4)
4348 #define   EDP_PSR_TP1_TIME_0us                  (3 << 4)
4349 #define   EDP_PSR_IDLE_FRAME_SHIFT              0
4350
4351 /*
4352  * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
4353  * to transcoder and bits defined for each one as if using no shift (i.e. as if
4354  * it was for TRANSCODER_EDP)
4355  */
4356 #define EDP_PSR_IMR                             _MMIO(0x64834)
4357 #define EDP_PSR_IIR                             _MMIO(0x64838)
4358 #define _PSR_IMR_A                              0x60814
4359 #define _PSR_IIR_A                              0x60818
4360 #define TRANS_PSR_IMR(tran)                     _MMIO_TRANS2(tran, _PSR_IMR_A)
4361 #define TRANS_PSR_IIR(tran)                     _MMIO_TRANS2(tran, _PSR_IIR_A)
4362 #define   _EDP_PSR_TRANS_SHIFT(trans)           ((trans) == TRANSCODER_EDP ? \
4363                                                  0 : ((trans) - TRANSCODER_A + 1) * 8)
4364 #define   EDP_PSR_TRANS_MASK(trans)             (0x7 << _EDP_PSR_TRANS_SHIFT(trans))
4365 #define   EDP_PSR_ERROR(trans)                  (0x4 << _EDP_PSR_TRANS_SHIFT(trans))
4366 #define   EDP_PSR_POST_EXIT(trans)              (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
4367 #define   EDP_PSR_PRE_ENTRY(trans)              (0x1 << _EDP_PSR_TRANS_SHIFT(trans))
4368
4369 #define _SRD_AUX_CTL_A                          0x60810
4370 #define _SRD_AUX_CTL_EDP                        0x6f810
4371 #define EDP_PSR_AUX_CTL(tran)                   _MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A))
4372 #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK         (3 << 26)
4373 #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK     (0x1f << 20)
4374 #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK    (0xf << 16)
4375 #define   EDP_PSR_AUX_CTL_ERROR_INTERRUPT       (1 << 11)
4376 #define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK     (0x7ff)
4377
4378 #define _SRD_AUX_DATA_A                         0x60814
4379 #define _SRD_AUX_DATA_EDP                       0x6f814
4380 #define EDP_PSR_AUX_DATA(tran, i)               _MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
4381
4382 #define _SRD_STATUS_A                           0x60840
4383 #define _SRD_STATUS_EDP                         0x6f840
4384 #define EDP_PSR_STATUS(tran)                    _MMIO(_PSR_ADJ(tran, _SRD_STATUS_A))
4385 #define   EDP_PSR_STATUS_STATE_MASK             (7 << 29)
4386 #define   EDP_PSR_STATUS_STATE_SHIFT            29
4387 #define   EDP_PSR_STATUS_STATE_IDLE             (0 << 29)
4388 #define   EDP_PSR_STATUS_STATE_SRDONACK         (1 << 29)
4389 #define   EDP_PSR_STATUS_STATE_SRDENT           (2 << 29)
4390 #define   EDP_PSR_STATUS_STATE_BUFOFF           (3 << 29)
4391 #define   EDP_PSR_STATUS_STATE_BUFON            (4 << 29)
4392 #define   EDP_PSR_STATUS_STATE_AUXACK           (5 << 29)
4393 #define   EDP_PSR_STATUS_STATE_SRDOFFACK        (6 << 29)
4394 #define   EDP_PSR_STATUS_LINK_MASK              (3 << 26)
4395 #define   EDP_PSR_STATUS_LINK_FULL_OFF          (0 << 26)
4396 #define   EDP_PSR_STATUS_LINK_FULL_ON           (1 << 26)
4397 #define   EDP_PSR_STATUS_LINK_STANDBY           (2 << 26)
4398 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT  20
4399 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK   0x1f
4400 #define   EDP_PSR_STATUS_COUNT_SHIFT            16
4401 #define   EDP_PSR_STATUS_COUNT_MASK             0xf
4402 #define   EDP_PSR_STATUS_AUX_ERROR              (1 << 15)
4403 #define   EDP_PSR_STATUS_AUX_SENDING            (1 << 12)
4404 #define   EDP_PSR_STATUS_SENDING_IDLE           (1 << 9)
4405 #define   EDP_PSR_STATUS_SENDING_TP2_TP3        (1 << 8)
4406 #define   EDP_PSR_STATUS_SENDING_TP1            (1 << 4)
4407 #define   EDP_PSR_STATUS_IDLE_MASK              0xf
4408
4409 #define _SRD_PERF_CNT_A                 0x60844
4410 #define _SRD_PERF_CNT_EDP               0x6f844
4411 #define EDP_PSR_PERF_CNT(tran)          _MMIO(_PSR_ADJ(tran, _SRD_PERF_CNT_A))
4412 #define   EDP_PSR_PERF_CNT_MASK         0xffffff
4413
4414 /* PSR_MASK on SKL+ */
4415 #define _SRD_DEBUG_A                            0x60860
4416 #define _SRD_DEBUG_EDP                          0x6f860
4417 #define EDP_PSR_DEBUG(tran)                     _MMIO(_PSR_ADJ(tran, _SRD_DEBUG_A))
4418 #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1 << 28)
4419 #define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
4420 #define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
4421 #define   EDP_PSR_DEBUG_MASK_HPD               (1 << 25)
4422 #define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16) /* Reserved in ICL+ */
4423 #define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
4424
4425 #define _PSR2_CTL_A                     0x60900
4426 #define _PSR2_CTL_EDP                   0x6f900
4427 #define EDP_PSR2_CTL(tran)              _MMIO_TRANS2(tran, _PSR2_CTL_A)
4428 #define   EDP_PSR2_ENABLE               (1 << 31)
4429 #define   EDP_SU_TRACK_ENABLE           (1 << 30)
4430 #define   EDP_Y_COORDINATE_VALID        (1 << 26) /* GLK and CNL+ */
4431 #define   EDP_Y_COORDINATE_ENABLE       (1 << 25) /* GLK and CNL+ */
4432 #define   EDP_MAX_SU_DISABLE_TIME(t)    ((t) << 20)
4433 #define   EDP_MAX_SU_DISABLE_TIME_MASK  (0x1f << 20)
4434 #define   EDP_PSR2_TP2_TIME_500us       (0 << 8)
4435 #define   EDP_PSR2_TP2_TIME_100us       (1 << 8)
4436 #define   EDP_PSR2_TP2_TIME_2500us      (2 << 8)
4437 #define   EDP_PSR2_TP2_TIME_50us        (3 << 8)
4438 #define   EDP_PSR2_TP2_TIME_MASK        (3 << 8)
4439 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4440 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
4441 #define   EDP_PSR2_FRAME_BEFORE_SU(a)   ((a) << 4)
4442 #define   EDP_PSR2_IDLE_FRAME_MASK      0xf
4443 #define   EDP_PSR2_IDLE_FRAME_SHIFT     0
4444
4445 #define _PSR_EVENT_TRANS_A                      0x60848
4446 #define _PSR_EVENT_TRANS_B                      0x61848
4447 #define _PSR_EVENT_TRANS_C                      0x62848
4448 #define _PSR_EVENT_TRANS_D                      0x63848
4449 #define _PSR_EVENT_TRANS_EDP                    0x6f848
4450 #define PSR_EVENT(tran)                         _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
4451 #define  PSR_EVENT_PSR2_WD_TIMER_EXPIRE         (1 << 17)
4452 #define  PSR_EVENT_PSR2_DISABLED                (1 << 16)
4453 #define  PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN       (1 << 15)
4454 #define  PSR_EVENT_SU_CRC_FIFO_UNDERRUN         (1 << 14)
4455 #define  PSR_EVENT_GRAPHICS_RESET               (1 << 12)
4456 #define  PSR_EVENT_PCH_INTERRUPT                (1 << 11)
4457 #define  PSR_EVENT_MEMORY_UP                    (1 << 10)
4458 #define  PSR_EVENT_FRONT_BUFFER_MODIFY          (1 << 9)
4459 #define  PSR_EVENT_WD_TIMER_EXPIRE              (1 << 8)
4460 #define  PSR_EVENT_PIPE_REGISTERS_UPDATE        (1 << 6)
4461 #define  PSR_EVENT_REGISTER_UPDATE              (1 << 5) /* Reserved in ICL+ */
4462 #define  PSR_EVENT_HDCP_ENABLE                  (1 << 4)
4463 #define  PSR_EVENT_KVMR_SESSION_ENABLE          (1 << 3)
4464 #define  PSR_EVENT_VBI_ENABLE                   (1 << 2)
4465 #define  PSR_EVENT_LPSP_MODE_EXIT               (1 << 1)
4466 #define  PSR_EVENT_PSR_DISABLE                  (1 << 0)
4467
4468 #define _PSR2_STATUS_A                  0x60940
4469 #define _PSR2_STATUS_EDP                0x6f940
4470 #define EDP_PSR2_STATUS(tran)           _MMIO_TRANS2(tran, _PSR2_STATUS_A)
4471 #define EDP_PSR2_STATUS_STATE_MASK     (0xf << 28)
4472 #define EDP_PSR2_STATUS_STATE_SHIFT    28
4473
4474 #define _PSR2_SU_STATUS_A               0x60914
4475 #define _PSR2_SU_STATUS_EDP             0x6f914
4476 #define _PSR2_SU_STATUS(tran, index)    _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
4477 #define PSR2_SU_STATUS(tran, frame)     (_PSR2_SU_STATUS(tran, (frame) / 3))
4478 #define PSR2_SU_STATUS_SHIFT(frame)     (((frame) % 3) * 10)
4479 #define PSR2_SU_STATUS_MASK(frame)      (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
4480 #define PSR2_SU_STATUS_FRAMES           8
4481
4482 /* VGA port control */
4483 #define ADPA                    _MMIO(0x61100)
4484 #define PCH_ADPA                _MMIO(0xe1100)
4485 #define VLV_ADPA                _MMIO(VLV_DISPLAY_BASE + 0x61100)
4486
4487 #define   ADPA_DAC_ENABLE       (1 << 31)
4488 #define   ADPA_DAC_DISABLE      0
4489 #define   ADPA_PIPE_SEL_SHIFT           30
4490 #define   ADPA_PIPE_SEL_MASK            (1 << 30)
4491 #define   ADPA_PIPE_SEL(pipe)           ((pipe) << 30)
4492 #define   ADPA_PIPE_SEL_SHIFT_CPT       29
4493 #define   ADPA_PIPE_SEL_MASK_CPT        (3 << 29)
4494 #define   ADPA_PIPE_SEL_CPT(pipe)       ((pipe) << 29)
4495 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
4496 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0 << 24)
4497 #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3 << 24)
4498 #define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4499 #define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2 << 24)
4500 #define   ADPA_CRT_HOTPLUG_ENABLE        (1 << 23)
4501 #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0 << 22)
4502 #define   ADPA_CRT_HOTPLUG_PERIOD_128    (1 << 22)
4503 #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0 << 21)
4504 #define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1 << 21)
4505 #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0 << 20)
4506 #define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1 << 20)
4507 #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0 << 18)
4508 #define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1 << 18)
4509 #define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2 << 18)
4510 #define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3 << 18)
4511 #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0 << 17)
4512 #define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1 << 17)
4513 #define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4514 #define   ADPA_USE_VGA_HVPOLARITY (1 << 15)
4515 #define   ADPA_SETS_HVPOLARITY  0
4516 #define   ADPA_VSYNC_CNTL_DISABLE (1 << 10)
4517 #define   ADPA_VSYNC_CNTL_ENABLE 0
4518 #define   ADPA_HSYNC_CNTL_DISABLE (1 << 11)
4519 #define   ADPA_HSYNC_CNTL_ENABLE 0
4520 #define   ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
4521 #define   ADPA_VSYNC_ACTIVE_LOW 0
4522 #define   ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
4523 #define   ADPA_HSYNC_ACTIVE_LOW 0
4524 #define   ADPA_DPMS_MASK        (~(3 << 10))
4525 #define   ADPA_DPMS_ON          (0 << 10)
4526 #define   ADPA_DPMS_SUSPEND     (1 << 10)
4527 #define   ADPA_DPMS_STANDBY     (2 << 10)
4528 #define   ADPA_DPMS_OFF         (3 << 10)
4529
4530
4531 /* Hotplug control (945+ only) */
4532 #define PORT_HOTPLUG_EN         _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
4533 #define   PORTB_HOTPLUG_INT_EN                  (1 << 29)
4534 #define   PORTC_HOTPLUG_INT_EN                  (1 << 28)
4535 #define   PORTD_HOTPLUG_INT_EN                  (1 << 27)
4536 #define   SDVOB_HOTPLUG_INT_EN                  (1 << 26)
4537 #define   SDVOC_HOTPLUG_INT_EN                  (1 << 25)
4538 #define   TV_HOTPLUG_INT_EN                     (1 << 18)
4539 #define   CRT_HOTPLUG_INT_EN                    (1 << 9)
4540 #define HOTPLUG_INT_EN_MASK                     (PORTB_HOTPLUG_INT_EN | \
4541                                                  PORTC_HOTPLUG_INT_EN | \
4542                                                  PORTD_HOTPLUG_INT_EN | \
4543                                                  SDVOC_HOTPLUG_INT_EN | \
4544                                                  SDVOB_HOTPLUG_INT_EN | \
4545                                                  CRT_HOTPLUG_INT_EN)
4546 #define   CRT_HOTPLUG_FORCE_DETECT              (1 << 3)
4547 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32        (0 << 8)
4548 /* must use period 64 on GM45 according to docs */
4549 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64        (1 << 8)
4550 #define CRT_HOTPLUG_DAC_ON_TIME_2M              (0 << 7)
4551 #define CRT_HOTPLUG_DAC_ON_TIME_4M              (1 << 7)
4552 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40          (0 << 5)
4553 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50          (1 << 5)
4554 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60          (2 << 5)
4555 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70          (3 << 5)
4556 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK        (3 << 5)
4557 #define CRT_HOTPLUG_DETECT_DELAY_1G             (0 << 4)
4558 #define CRT_HOTPLUG_DETECT_DELAY_2G             (1 << 4)
4559 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV        (0 << 2)
4560 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV        (1 << 2)
4561
4562 #define PORT_HOTPLUG_STAT       _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
4563 /*
4564  * HDMI/DP bits are g4x+
4565  *
4566  * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4567  * Please check the detailed lore in the commit message for for experimental
4568  * evidence.
4569  */
4570 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4571 #define   PORTD_HOTPLUG_LIVE_STATUS_GM45        (1 << 29)
4572 #define   PORTC_HOTPLUG_LIVE_STATUS_GM45        (1 << 28)
4573 #define   PORTB_HOTPLUG_LIVE_STATUS_GM45        (1 << 27)
4574 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4575 #define   PORTD_HOTPLUG_LIVE_STATUS_G4X         (1 << 27)
4576 #define   PORTC_HOTPLUG_LIVE_STATUS_G4X         (1 << 28)
4577 #define   PORTB_HOTPLUG_LIVE_STATUS_G4X         (1 << 29)
4578 #define   PORTD_HOTPLUG_INT_STATUS              (3 << 21)
4579 #define   PORTD_HOTPLUG_INT_LONG_PULSE          (2 << 21)
4580 #define   PORTD_HOTPLUG_INT_SHORT_PULSE         (1 << 21)
4581 #define   PORTC_HOTPLUG_INT_STATUS              (3 << 19)
4582 #define   PORTC_HOTPLUG_INT_LONG_PULSE          (2 << 19)
4583 #define   PORTC_HOTPLUG_INT_SHORT_PULSE         (1 << 19)
4584 #define   PORTB_HOTPLUG_INT_STATUS              (3 << 17)
4585 #define   PORTB_HOTPLUG_INT_LONG_PULSE          (2 << 17)
4586 #define   PORTB_HOTPLUG_INT_SHORT_PLUSE         (1 << 17)
4587 /* CRT/TV common between gen3+ */
4588 #define   CRT_HOTPLUG_INT_STATUS                (1 << 11)
4589 #define   TV_HOTPLUG_INT_STATUS                 (1 << 10)
4590 #define   CRT_HOTPLUG_MONITOR_MASK              (3 << 8)
4591 #define   CRT_HOTPLUG_MONITOR_COLOR             (3 << 8)
4592 #define   CRT_HOTPLUG_MONITOR_MONO              (2 << 8)
4593 #define   CRT_HOTPLUG_MONITOR_NONE              (0 << 8)
4594 #define   DP_AUX_CHANNEL_D_INT_STATUS_G4X       (1 << 6)
4595 #define   DP_AUX_CHANNEL_C_INT_STATUS_G4X       (1 << 5)
4596 #define   DP_AUX_CHANNEL_B_INT_STATUS_G4X       (1 << 4)
4597 #define   DP_AUX_CHANNEL_MASK_INT_STATUS_G4X    (7 << 4)
4598
4599 /* SDVO is different across gen3/4 */
4600 #define   SDVOC_HOTPLUG_INT_STATUS_G4X          (1 << 3)
4601 #define   SDVOB_HOTPLUG_INT_STATUS_G4X          (1 << 2)
4602 /*
4603  * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4604  * since reality corrobates that they're the same as on gen3. But keep these
4605  * bits here (and the comment!) to help any other lost wanderers back onto the
4606  * right tracks.
4607  */
4608 #define   SDVOC_HOTPLUG_INT_STATUS_I965         (3 << 4)
4609 #define   SDVOB_HOTPLUG_INT_STATUS_I965         (3 << 2)
4610 #define   SDVOC_HOTPLUG_INT_STATUS_I915         (1 << 7)
4611 #define   SDVOB_HOTPLUG_INT_STATUS_I915         (1 << 6)
4612 #define   HOTPLUG_INT_STATUS_G4X                (CRT_HOTPLUG_INT_STATUS | \
4613                                                  SDVOB_HOTPLUG_INT_STATUS_G4X | \
4614                                                  SDVOC_HOTPLUG_INT_STATUS_G4X | \
4615                                                  PORTB_HOTPLUG_INT_STATUS | \
4616                                                  PORTC_HOTPLUG_INT_STATUS | \
4617                                                  PORTD_HOTPLUG_INT_STATUS)
4618
4619 #define HOTPLUG_INT_STATUS_I915                 (CRT_HOTPLUG_INT_STATUS | \
4620                                                  SDVOB_HOTPLUG_INT_STATUS_I915 | \
4621                                                  SDVOC_HOTPLUG_INT_STATUS_I915 | \
4622                                                  PORTB_HOTPLUG_INT_STATUS | \
4623                                                  PORTC_HOTPLUG_INT_STATUS | \
4624                                                  PORTD_HOTPLUG_INT_STATUS)
4625
4626 /* SDVO and HDMI port control.
4627  * The same register may be used for SDVO or HDMI */
4628 #define _GEN3_SDVOB     0x61140
4629 #define _GEN3_SDVOC     0x61160
4630 #define GEN3_SDVOB      _MMIO(_GEN3_SDVOB)
4631 #define GEN3_SDVOC      _MMIO(_GEN3_SDVOC)
4632 #define GEN4_HDMIB      GEN3_SDVOB
4633 #define GEN4_HDMIC      GEN3_SDVOC
4634 #define VLV_HDMIB       _MMIO(VLV_DISPLAY_BASE + 0x61140)
4635 #define VLV_HDMIC       _MMIO(VLV_DISPLAY_BASE + 0x61160)
4636 #define CHV_HDMID       _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4637 #define PCH_SDVOB       _MMIO(0xe1140)
4638 #define PCH_HDMIB       PCH_SDVOB
4639 #define PCH_HDMIC       _MMIO(0xe1150)
4640 #define PCH_HDMID       _MMIO(0xe1160)
4641
4642 #define PORT_DFT_I9XX                           _MMIO(0x61150)
4643 #define   DC_BALANCE_RESET                      (1 << 25)
4644 #define PORT_DFT2_G4X           _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
4645 #define   DC_BALANCE_RESET_VLV                  (1 << 31)
4646 #define   PIPE_SCRAMBLE_RESET_MASK              ((1 << 14) | (0x3 << 0))
4647 #define   PIPE_C_SCRAMBLE_RESET                 (1 << 14) /* chv */
4648 #define   PIPE_B_SCRAMBLE_RESET                 (1 << 1)
4649 #define   PIPE_A_SCRAMBLE_RESET                 (1 << 0)
4650
4651 /* Gen 3 SDVO bits: */
4652 #define   SDVO_ENABLE                           (1 << 31)
4653 #define   SDVO_PIPE_SEL_SHIFT                   30
4654 #define   SDVO_PIPE_SEL_MASK                    (1 << 30)
4655 #define   SDVO_PIPE_SEL(pipe)                   ((pipe) << 30)
4656 #define   SDVO_STALL_SELECT                     (1 << 29)
4657 #define   SDVO_INTERRUPT_ENABLE                 (1 << 26)
4658 /*
4659  * 915G/GM SDVO pixel multiplier.
4660  * Programmed value is multiplier - 1, up to 5x.
4661  * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4662  */
4663 #define   SDVO_PORT_MULTIPLY_MASK               (7 << 23)
4664 #define   SDVO_PORT_MULTIPLY_SHIFT              23
4665 #define   SDVO_PHASE_SELECT_MASK                (15 << 19)
4666 #define   SDVO_PHASE_SELECT_DEFAULT             (6 << 19)
4667 #define   SDVO_CLOCK_OUTPUT_INVERT              (1 << 18)
4668 #define   SDVOC_GANG_MODE                       (1 << 16) /* Port C only */
4669 #define   SDVO_BORDER_ENABLE                    (1 << 7) /* SDVO only */
4670 #define   SDVOB_PCIE_CONCURRENCY                (1 << 3) /* Port B only */
4671 #define   SDVO_DETECTED                         (1 << 2)
4672 /* Bits to be preserved when writing */
4673 #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4674                                SDVO_INTERRUPT_ENABLE)
4675 #define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4676
4677 /* Gen 4 SDVO/HDMI bits: */
4678 #define   SDVO_COLOR_FORMAT_8bpc                (0 << 26)
4679 #define   SDVO_COLOR_FORMAT_MASK                (7 << 26)
4680 #define   SDVO_ENCODING_SDVO                    (0 << 10)
4681 #define   SDVO_ENCODING_HDMI                    (2 << 10)
4682 #define   HDMI_MODE_SELECT_HDMI                 (1 << 9) /* HDMI only */
4683 #define   HDMI_MODE_SELECT_DVI                  (0 << 9) /* HDMI only */
4684 #define   HDMI_COLOR_RANGE_16_235               (1 << 8) /* HDMI only */
4685 #define   HDMI_AUDIO_ENABLE                     (1 << 6) /* HDMI only */
4686 /* VSYNC/HSYNC bits new with 965, default is to be set */
4687 #define   SDVO_VSYNC_ACTIVE_HIGH                (1 << 4)
4688 #define   SDVO_HSYNC_ACTIVE_HIGH                (1 << 3)
4689
4690 /* Gen 5 (IBX) SDVO/HDMI bits: */
4691 #define   HDMI_COLOR_FORMAT_12bpc               (3 << 26) /* HDMI only */
4692 #define   SDVOB_HOTPLUG_ENABLE                  (1 << 23) /* SDVO only */
4693
4694 /* Gen 6 (CPT) SDVO/HDMI bits: */
4695 #define   SDVO_PIPE_SEL_SHIFT_CPT               29
4696 #define   SDVO_PIPE_SEL_MASK_CPT                (3 << 29)
4697 #define   SDVO_PIPE_SEL_CPT(pipe)               ((pipe) << 29)
4698
4699 /* CHV SDVO/HDMI bits: */
4700 #define   SDVO_PIPE_SEL_SHIFT_CHV               24
4701 #define   SDVO_PIPE_SEL_MASK_CHV                (3 << 24)
4702 #define   SDVO_PIPE_SEL_CHV(pipe)               ((pipe) << 24)
4703
4704
4705 /* DVO port control */
4706 #define _DVOA                   0x61120
4707 #define DVOA                    _MMIO(_DVOA)
4708 #define _DVOB                   0x61140
4709 #define DVOB                    _MMIO(_DVOB)
4710 #define _DVOC                   0x61160
4711 #define DVOC                    _MMIO(_DVOC)
4712 #define   DVO_ENABLE                    (1 << 31)
4713 #define   DVO_PIPE_SEL_SHIFT            30
4714 #define   DVO_PIPE_SEL_MASK             (1 << 30)
4715 #define   DVO_PIPE_SEL(pipe)            ((pipe) << 30)
4716 #define   DVO_PIPE_STALL_UNUSED         (0 << 28)
4717 #define   DVO_PIPE_STALL                (1 << 28)
4718 #define   DVO_PIPE_STALL_TV             (2 << 28)
4719 #define   DVO_PIPE_STALL_MASK           (3 << 28)
4720 #define   DVO_USE_VGA_SYNC              (1 << 15)
4721 #define   DVO_DATA_ORDER_I740           (0 << 14)
4722 #define   DVO_DATA_ORDER_FP             (1 << 14)
4723 #define   DVO_VSYNC_DISABLE             (1 << 11)
4724 #define   DVO_HSYNC_DISABLE             (1 << 10)
4725 #define   DVO_VSYNC_TRISTATE            (1 << 9)
4726 #define   DVO_HSYNC_TRISTATE            (1 << 8)
4727 #define   DVO_BORDER_ENABLE             (1 << 7)
4728 #define   DVO_DATA_ORDER_GBRG           (1 << 6)
4729 #define   DVO_DATA_ORDER_RGGB           (0 << 6)
4730 #define   DVO_DATA_ORDER_GBRG_ERRATA    (0 << 6)
4731 #define   DVO_DATA_ORDER_RGGB_ERRATA    (1 << 6)
4732 #define   DVO_VSYNC_ACTIVE_HIGH         (1 << 4)
4733 #define   DVO_HSYNC_ACTIVE_HIGH         (1 << 3)
4734 #define   DVO_BLANK_ACTIVE_HIGH         (1 << 2)
4735 #define   DVO_OUTPUT_CSTATE_PIXELS      (1 << 1)        /* SDG only */
4736 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0)        /* SDG only */
4737 #define   DVO_PRESERVE_MASK             (0x7 << 24)
4738 #define DVOA_SRCDIM             _MMIO(0x61124)
4739 #define DVOB_SRCDIM             _MMIO(0x61144)
4740 #define DVOC_SRCDIM             _MMIO(0x61164)
4741 #define   DVO_SRCDIM_HORIZONTAL_SHIFT   12
4742 #define   DVO_SRCDIM_VERTICAL_SHIFT     0
4743
4744 /* LVDS port control */
4745 #define LVDS                    _MMIO(0x61180)
4746 /*
4747  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
4748  * the DPLL semantics change when the LVDS is assigned to that pipe.
4749  */
4750 #define   LVDS_PORT_EN                  (1 << 31)
4751 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
4752 #define   LVDS_PIPE_SEL_SHIFT           30
4753 #define   LVDS_PIPE_SEL_MASK            (1 << 30)
4754 #define   LVDS_PIPE_SEL(pipe)           ((pipe) << 30)
4755 #define   LVDS_PIPE_SEL_SHIFT_CPT       29
4756 #define   LVDS_PIPE_SEL_MASK_CPT        (3 << 29)
4757 #define   LVDS_PIPE_SEL_CPT(pipe)       ((pipe) << 29)
4758 /* LVDS dithering flag on 965/g4x platform */
4759 #define   LVDS_ENABLE_DITHER            (1 << 25)
4760 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
4761 #define   LVDS_VSYNC_POLARITY           (1 << 21)
4762 #define   LVDS_HSYNC_POLARITY           (1 << 20)
4763
4764 /* Enable border for unscaled (or aspect-scaled) display */
4765 #define   LVDS_BORDER_ENABLE            (1 << 15)
4766 /*
4767  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4768  * pixel.
4769  */
4770 #define   LVDS_A0A2_CLKA_POWER_MASK     (3 << 8)
4771 #define   LVDS_A0A2_CLKA_POWER_DOWN     (0 << 8)
4772 #define   LVDS_A0A2_CLKA_POWER_UP       (3 << 8)
4773 /*
4774  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4775  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4776  * on.
4777  */
4778 #define   LVDS_A3_POWER_MASK            (3 << 6)
4779 #define   LVDS_A3_POWER_DOWN            (0 << 6)
4780 #define   LVDS_A3_POWER_UP              (3 << 6)
4781 /*
4782  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
4783  * is set.
4784  */
4785 #define   LVDS_CLKB_POWER_MASK          (3 << 4)
4786 #define   LVDS_CLKB_POWER_DOWN          (0 << 4)
4787 #define   LVDS_CLKB_POWER_UP            (3 << 4)
4788 /*
4789  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
4790  * setting for whether we are in dual-channel mode.  The B3 pair will
4791  * additionally only be powered up when LVDS_A3_POWER_UP is set.
4792  */
4793 #define   LVDS_B0B3_POWER_MASK          (3 << 2)
4794 #define   LVDS_B0B3_POWER_DOWN          (0 << 2)
4795 #define   LVDS_B0B3_POWER_UP            (3 << 2)
4796
4797 /* Video Data Island Packet control */
4798 #define VIDEO_DIP_DATA          _MMIO(0x61178)
4799 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
4800  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4801  * of the infoframe structure specified by CEA-861. */
4802 #define   VIDEO_DIP_DATA_SIZE   32
4803 #define   VIDEO_DIP_GMP_DATA_SIZE       36
4804 #define   VIDEO_DIP_VSC_DATA_SIZE       36
4805 #define   VIDEO_DIP_PPS_DATA_SIZE       132
4806 #define VIDEO_DIP_CTL           _MMIO(0x61170)
4807 /* Pre HSW: */
4808 #define   VIDEO_DIP_ENABLE              (1 << 31)
4809 #define   VIDEO_DIP_PORT(port)          ((port) << 29)
4810 #define   VIDEO_DIP_PORT_MASK           (3 << 29)
4811 #define   VIDEO_DIP_ENABLE_GCP          (1 << 25) /* ilk+ */
4812 #define   VIDEO_DIP_ENABLE_AVI          (1 << 21)
4813 #define   VIDEO_DIP_ENABLE_VENDOR       (2 << 21)
4814 #define   VIDEO_DIP_ENABLE_GAMUT        (4 << 21) /* ilk+ */
4815 #define   VIDEO_DIP_ENABLE_SPD          (8 << 21)
4816 #define   VIDEO_DIP_SELECT_AVI          (0 << 19)
4817 #define   VIDEO_DIP_SELECT_VENDOR       (1 << 19)
4818 #define   VIDEO_DIP_SELECT_GAMUT        (2 << 19)
4819 #define   VIDEO_DIP_SELECT_SPD          (3 << 19)
4820 #define   VIDEO_DIP_SELECT_MASK         (3 << 19)
4821 #define   VIDEO_DIP_FREQ_ONCE           (0 << 16)
4822 #define   VIDEO_DIP_FREQ_VSYNC          (1 << 16)
4823 #define   VIDEO_DIP_FREQ_2VSYNC         (2 << 16)
4824 #define   VIDEO_DIP_FREQ_MASK           (3 << 16)
4825 /* HSW and later: */
4826 #define   VIDEO_DIP_ENABLE_DRM_GLK      (1 << 28)
4827 #define   PSR_VSC_BIT_7_SET             (1 << 27)
4828 #define   VSC_SELECT_MASK               (0x3 << 25)
4829 #define   VSC_SELECT_SHIFT              25
4830 #define   VSC_DIP_HW_HEA_DATA           (0 << 25)
4831 #define   VSC_DIP_HW_HEA_SW_DATA        (1 << 25)
4832 #define   VSC_DIP_HW_DATA_SW_HEA        (2 << 25)
4833 #define   VSC_DIP_SW_HEA_DATA           (3 << 25)
4834 #define   VDIP_ENABLE_PPS               (1 << 24)
4835 #define   VIDEO_DIP_ENABLE_VSC_HSW      (1 << 20)
4836 #define   VIDEO_DIP_ENABLE_GCP_HSW      (1 << 16)
4837 #define   VIDEO_DIP_ENABLE_AVI_HSW      (1 << 12)
4838 #define   VIDEO_DIP_ENABLE_VS_HSW       (1 << 8)
4839 #define   VIDEO_DIP_ENABLE_GMP_HSW      (1 << 4)
4840 #define   VIDEO_DIP_ENABLE_SPD_HSW      (1 << 0)
4841
4842 /* Panel power sequencing */
4843 #define PPS_BASE                        0x61200
4844 #define VLV_PPS_BASE                    (VLV_DISPLAY_BASE + PPS_BASE)
4845 #define PCH_PPS_BASE                    0xC7200
4846
4847 #define _MMIO_PPS(pps_idx, reg)         _MMIO(dev_priv->pps_mmio_base - \
4848                                               PPS_BASE + (reg) +        \
4849                                               (pps_idx) * 0x100)
4850
4851 #define _PP_STATUS                      0x61200
4852 #define PP_STATUS(pps_idx)              _MMIO_PPS(pps_idx, _PP_STATUS)
4853 #define   PP_ON                         REG_BIT(31)
4854
4855 #define _PP_CONTROL_1                   0xc7204
4856 #define _PP_CONTROL_2                   0xc7304
4857 #define ICP_PP_CONTROL(x)               _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
4858                                               _PP_CONTROL_2)
4859 #define  POWER_CYCLE_DELAY_MASK         REG_GENMASK(8, 4)
4860 #define  VDD_OVERRIDE_FORCE             REG_BIT(3)
4861 #define  BACKLIGHT_ENABLE               REG_BIT(2)
4862 #define  PWR_DOWN_ON_RESET              REG_BIT(1)
4863 #define  PWR_STATE_TARGET               REG_BIT(0)
4864 /*
4865  * Indicates that all dependencies of the panel are on:
4866  *
4867  * - PLL enabled
4868  * - pipe enabled
4869  * - LVDS/DVOB/DVOC on
4870  */
4871 #define   PP_READY                      REG_BIT(30)
4872 #define   PP_SEQUENCE_MASK              REG_GENMASK(29, 28)
4873 #define   PP_SEQUENCE_NONE              REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
4874 #define   PP_SEQUENCE_POWER_UP          REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
4875 #define   PP_SEQUENCE_POWER_DOWN        REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
4876 #define   PP_CYCLE_DELAY_ACTIVE         REG_BIT(27)
4877 #define   PP_SEQUENCE_STATE_MASK        REG_GENMASK(3, 0)
4878 #define   PP_SEQUENCE_STATE_OFF_IDLE    REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
4879 #define   PP_SEQUENCE_STATE_OFF_S0_1    REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
4880 #define   PP_SEQUENCE_STATE_OFF_S0_2    REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
4881 #define   PP_SEQUENCE_STATE_OFF_S0_3    REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
4882 #define   PP_SEQUENCE_STATE_ON_IDLE     REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
4883 #define   PP_SEQUENCE_STATE_ON_S1_1     REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
4884 #define   PP_SEQUENCE_STATE_ON_S1_2     REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
4885 #define   PP_SEQUENCE_STATE_ON_S1_3     REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
4886 #define   PP_SEQUENCE_STATE_RESET       REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
4887
4888 #define _PP_CONTROL                     0x61204
4889 #define PP_CONTROL(pps_idx)             _MMIO_PPS(pps_idx, _PP_CONTROL)
4890 #define  PANEL_UNLOCK_MASK              REG_GENMASK(31, 16)
4891 #define  PANEL_UNLOCK_REGS              REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
4892 #define  BXT_POWER_CYCLE_DELAY_MASK     REG_GENMASK(8, 4)
4893 #define  EDP_FORCE_VDD                  REG_BIT(3)
4894 #define  EDP_BLC_ENABLE                 REG_BIT(2)
4895 #define  PANEL_POWER_RESET              REG_BIT(1)
4896 #define  PANEL_POWER_ON                 REG_BIT(0)
4897
4898 #define _PP_ON_DELAYS                   0x61208
4899 #define PP_ON_DELAYS(pps_idx)           _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4900 #define  PANEL_PORT_SELECT_MASK         REG_GENMASK(31, 30)
4901 #define  PANEL_PORT_SELECT_LVDS         REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
4902 #define  PANEL_PORT_SELECT_DPA          REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
4903 #define  PANEL_PORT_SELECT_DPC          REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
4904 #define  PANEL_PORT_SELECT_DPD          REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
4905 #define  PANEL_PORT_SELECT_VLV(port)    REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
4906 #define  PANEL_POWER_UP_DELAY_MASK      REG_GENMASK(28, 16)
4907 #define  PANEL_LIGHT_ON_DELAY_MASK      REG_GENMASK(12, 0)
4908
4909 #define _PP_OFF_DELAYS                  0x6120C
4910 #define PP_OFF_DELAYS(pps_idx)          _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4911 #define  PANEL_POWER_DOWN_DELAY_MASK    REG_GENMASK(28, 16)
4912 #define  PANEL_LIGHT_OFF_DELAY_MASK     REG_GENMASK(12, 0)
4913
4914 #define _PP_DIVISOR                     0x61210
4915 #define PP_DIVISOR(pps_idx)             _MMIO_PPS(pps_idx, _PP_DIVISOR)
4916 #define  PP_REFERENCE_DIVIDER_MASK      REG_GENMASK(31, 8)
4917 #define  PANEL_POWER_CYCLE_DELAY_MASK   REG_GENMASK(4, 0)
4918
4919 /* Panel fitting */
4920 #define PFIT_CONTROL    _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
4921 #define   PFIT_ENABLE           (1 << 31)
4922 #define   PFIT_PIPE_MASK        (3 << 29)
4923 #define   PFIT_PIPE_SHIFT       29
4924 #define   VERT_INTERP_DISABLE   (0 << 10)
4925 #define   VERT_INTERP_BILINEAR  (1 << 10)
4926 #define   VERT_INTERP_MASK      (3 << 10)
4927 #define   VERT_AUTO_SCALE       (1 << 9)
4928 #define   HORIZ_INTERP_DISABLE  (0 << 6)
4929 #define   HORIZ_INTERP_BILINEAR (1 << 6)
4930 #define   HORIZ_INTERP_MASK     (3 << 6)
4931 #define   HORIZ_AUTO_SCALE      (1 << 5)
4932 #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
4933 #define   PFIT_FILTER_FUZZY     (0 << 24)
4934 #define   PFIT_SCALING_AUTO     (0 << 26)
4935 #define   PFIT_SCALING_PROGRAMMED (1 << 26)
4936 #define   PFIT_SCALING_PILLAR   (2 << 26)
4937 #define   PFIT_SCALING_LETTER   (3 << 26)
4938 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
4939 /* Pre-965 */
4940 #define         PFIT_VERT_SCALE_SHIFT           20
4941 #define         PFIT_VERT_SCALE_MASK            0xfff00000
4942 #define         PFIT_HORIZ_SCALE_SHIFT          4
4943 #define         PFIT_HORIZ_SCALE_MASK           0x0000fff0
4944 /* 965+ */
4945 #define         PFIT_VERT_SCALE_SHIFT_965       16
4946 #define         PFIT_VERT_SCALE_MASK_965        0x1fff0000
4947 #define         PFIT_HORIZ_SCALE_SHIFT_965      0
4948 #define         PFIT_HORIZ_SCALE_MASK_965       0x00001fff
4949
4950 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
4951
4952 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
4953 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
4954 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4955                                          _VLV_BLC_PWM_CTL2_B)
4956
4957 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4958 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
4959 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4960                                         _VLV_BLC_PWM_CTL_B)
4961
4962 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
4963 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
4964 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4965                                          _VLV_BLC_HIST_CTL_B)
4966
4967 /* Backlight control */
4968 #define BLC_PWM_CTL2    _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
4969 #define   BLM_PWM_ENABLE                (1 << 31)
4970 #define   BLM_COMBINATION_MODE          (1 << 30) /* gen4 only */
4971 #define   BLM_PIPE_SELECT               (1 << 29)
4972 #define   BLM_PIPE_SELECT_IVB           (3 << 29)
4973 #define   BLM_PIPE_A                    (0 << 29)
4974 #define   BLM_PIPE_B                    (1 << 29)
4975 #define   BLM_PIPE_C                    (2 << 29) /* ivb + */
4976 #define   BLM_TRANSCODER_A              BLM_PIPE_A /* hsw */
4977 #define   BLM_TRANSCODER_B              BLM_PIPE_B
4978 #define   BLM_TRANSCODER_C              BLM_PIPE_C
4979 #define   BLM_TRANSCODER_EDP            (3 << 29)
4980 #define   BLM_PIPE(pipe)                ((pipe) << 29)
4981 #define   BLM_POLARITY_I965             (1 << 28) /* gen4 only */
4982 #define   BLM_PHASE_IN_INTERUPT_STATUS  (1 << 26)
4983 #define   BLM_PHASE_IN_ENABLE           (1 << 25)
4984 #define   BLM_PHASE_IN_INTERUPT_ENABL   (1 << 24)
4985 #define   BLM_PHASE_IN_TIME_BASE_SHIFT  (16)
4986 #define   BLM_PHASE_IN_TIME_BASE_MASK   (0xff << 16)
4987 #define   BLM_PHASE_IN_COUNT_SHIFT      (8)
4988 #define   BLM_PHASE_IN_COUNT_MASK       (0xff << 8)
4989 #define   BLM_PHASE_IN_INCR_SHIFT       (0)
4990 #define   BLM_PHASE_IN_INCR_MASK        (0xff << 0)
4991 #define BLC_PWM_CTL     _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4992 /*
4993  * This is the most significant 15 bits of the number of backlight cycles in a
4994  * complete cycle of the modulated backlight control.
4995  *
4996  * The actual value is this field multiplied by two.
4997  */
4998 #define   BACKLIGHT_MODULATION_FREQ_SHIFT       (17)
4999 #define   BACKLIGHT_MODULATION_FREQ_MASK        (0x7fff << 17)
5000 #define   BLM_LEGACY_MODE                       (1 << 16) /* gen2 only */
5001 /*
5002  * This is the number of cycles out of the backlight modulation cycle for which
5003  * the backlight is on.
5004  *
5005  * This field must be no greater than the number of cycles in the complete
5006  * backlight modulation cycle.
5007  */
5008 #define   BACKLIGHT_DUTY_CYCLE_SHIFT            (0)
5009 #define   BACKLIGHT_DUTY_CYCLE_MASK             (0xffff)
5010 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV         (0xfffe)
5011 #define   BLM_POLARITY_PNV                      (1 << 0) /* pnv only */
5012
5013 #define BLC_HIST_CTL    _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5014 #define  BLM_HISTOGRAM_ENABLE                   (1 << 31)
5015
5016 /* New registers for PCH-split platforms. Safe where new bits show up, the
5017  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
5018 #define BLC_PWM_CPU_CTL2        _MMIO(0x48250)
5019 #define BLC_PWM_CPU_CTL         _MMIO(0x48254)
5020
5021 #define HSW_BLC_PWM2_CTL        _MMIO(0x48350)
5022
5023 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
5024  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
5025 #define BLC_PWM_PCH_CTL1        _MMIO(0xc8250)
5026 #define   BLM_PCH_PWM_ENABLE                    (1 << 31)
5027 #define   BLM_PCH_OVERRIDE_ENABLE               (1 << 30)
5028 #define   BLM_PCH_POLARITY                      (1 << 29)
5029 #define BLC_PWM_PCH_CTL2        _MMIO(0xc8254)
5030
5031 #define UTIL_PIN_CTL                    _MMIO(0x48400)
5032 #define   UTIL_PIN_ENABLE               (1 << 31)
5033 #define   UTIL_PIN_PIPE_MASK            (3 << 29)
5034 #define   UTIL_PIN_PIPE(x)              ((x) << 29)
5035 #define   UTIL_PIN_MODE_MASK            (0xf << 24)
5036 #define   UTIL_PIN_MODE_DATA            (0 << 24)
5037 #define   UTIL_PIN_MODE_PWM             (1 << 24)
5038 #define   UTIL_PIN_MODE_VBLANK          (4 << 24)
5039 #define   UTIL_PIN_MODE_VSYNC           (5 << 24)
5040 #define   UTIL_PIN_MODE_EYE_LEVEL       (8 << 24)
5041 #define   UTIL_PIN_OUTPUT_DATA          (1 << 23)
5042 #define   UTIL_PIN_POLARITY             (1 << 22)
5043 #define   UTIL_PIN_DIRECTION_INPUT      (1 << 19)
5044 #define   UTIL_PIN_INPUT_DATA           (1 << 16)
5045
5046 /* BXT backlight register definition. */
5047 #define _BXT_BLC_PWM_CTL1                       0xC8250
5048 #define   BXT_BLC_PWM_ENABLE                    (1 << 31)
5049 #define   BXT_BLC_PWM_POLARITY                  (1 << 29)
5050 #define _BXT_BLC_PWM_FREQ1                      0xC8254
5051 #define _BXT_BLC_PWM_DUTY1                      0xC8258
5052
5053 #define _BXT_BLC_PWM_CTL2                       0xC8350
5054 #define _BXT_BLC_PWM_FREQ2                      0xC8354
5055 #define _BXT_BLC_PWM_DUTY2                      0xC8358
5056
5057 #define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,           \
5058                                         _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
5059 #define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
5060                                         _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
5061 #define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
5062                                         _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
5063
5064 #define PCH_GTC_CTL             _MMIO(0xe7000)
5065 #define   PCH_GTC_ENABLE        (1 << 31)
5066
5067 /* TV port control */
5068 #define TV_CTL                  _MMIO(0x68000)
5069 /* Enables the TV encoder */
5070 # define TV_ENC_ENABLE                  (1 << 31)
5071 /* Sources the TV encoder input from pipe B instead of A. */
5072 # define TV_ENC_PIPE_SEL_SHIFT          30
5073 # define TV_ENC_PIPE_SEL_MASK           (1 << 30)
5074 # define TV_ENC_PIPE_SEL(pipe)          ((pipe) << 30)
5075 /* Outputs composite video (DAC A only) */
5076 # define TV_ENC_OUTPUT_COMPOSITE        (0 << 28)
5077 /* Outputs SVideo video (DAC B/C) */
5078 # define TV_ENC_OUTPUT_SVIDEO           (1 << 28)
5079 /* Outputs Component video (DAC A/B/C) */
5080 # define TV_ENC_OUTPUT_COMPONENT        (2 << 28)
5081 /* Outputs Composite and SVideo (DAC A/B/C) */
5082 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
5083 # define TV_TRILEVEL_SYNC               (1 << 21)
5084 /* Enables slow sync generation (945GM only) */
5085 # define TV_SLOW_SYNC                   (1 << 20)
5086 /* Selects 4x oversampling for 480i and 576p */
5087 # define TV_OVERSAMPLE_4X               (0 << 18)
5088 /* Selects 2x oversampling for 720p and 1080i */
5089 # define TV_OVERSAMPLE_2X               (1 << 18)
5090 /* Selects no oversampling for 1080p */
5091 # define TV_OVERSAMPLE_NONE             (2 << 18)
5092 /* Selects 8x oversampling */
5093 # define TV_OVERSAMPLE_8X               (3 << 18)
5094 # define TV_OVERSAMPLE_MASK             (3 << 18)
5095 /* Selects progressive mode rather than interlaced */
5096 # define TV_PROGRESSIVE                 (1 << 17)
5097 /* Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
5098 # define TV_PAL_BURST                   (1 << 16)
5099 /* Field for setting delay of Y compared to C */
5100 # define TV_YC_SKEW_MASK                (7 << 12)
5101 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
5102 # define TV_ENC_SDP_FIX                 (1 << 11)
5103 /*
5104  * Enables a fix for the 915GM only.
5105  *
5106  * Not sure what it does.
5107  */
5108 # define TV_ENC_C0_FIX                  (1 << 10)
5109 /* Bits that must be preserved by software */
5110 # define TV_CTL_SAVE                    ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
5111 # define TV_FUSE_STATE_MASK             (3 << 4)
5112 /* Read-only state that reports all features enabled */
5113 # define TV_FUSE_STATE_ENABLED          (0 << 4)
5114 /* Read-only state that reports that Macrovision is disabled in hardware*/
5115 # define TV_FUSE_STATE_NO_MACROVISION   (1 << 4)
5116 /* Read-only state that reports that TV-out is disabled in hardware. */
5117 # define TV_FUSE_STATE_DISABLED         (2 << 4)
5118 /* Normal operation */
5119 # define TV_TEST_MODE_NORMAL            (0 << 0)
5120 /* Encoder test pattern 1 - combo pattern */
5121 # define TV_TEST_MODE_PATTERN_1         (1 << 0)
5122 /* Encoder test pattern 2 - full screen vertical 75% color bars */
5123 # define TV_TEST_MODE_PATTERN_2         (2 << 0)
5124 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
5125 # define TV_TEST_MODE_PATTERN_3         (3 << 0)
5126 /* Encoder test pattern 4 - random noise */
5127 # define TV_TEST_MODE_PATTERN_4         (4 << 0)
5128 /* Encoder test pattern 5 - linear color ramps */
5129 # define TV_TEST_MODE_PATTERN_5         (5 << 0)
5130 /*
5131  * This test mode forces the DACs to 50% of full output.
5132  *
5133  * This is used for load detection in combination with TVDAC_SENSE_MASK
5134  */
5135 # define TV_TEST_MODE_MONITOR_DETECT    (7 << 0)
5136 # define TV_TEST_MODE_MASK              (7 << 0)
5137
5138 #define TV_DAC                  _MMIO(0x68004)
5139 # define TV_DAC_SAVE            0x00ffff00
5140 /*
5141  * Reports that DAC state change logic has reported change (RO).
5142  *
5143  * This gets cleared when TV_DAC_STATE_EN is cleared
5144 */
5145 # define TVDAC_STATE_CHG                (1 << 31)
5146 # define TVDAC_SENSE_MASK               (7 << 28)
5147 /* Reports that DAC A voltage is above the detect threshold */
5148 # define TVDAC_A_SENSE                  (1 << 30)
5149 /* Reports that DAC B voltage is above the detect threshold */
5150 # define TVDAC_B_SENSE                  (1 << 29)
5151 /* Reports that DAC C voltage is above the detect threshold */
5152 # define TVDAC_C_SENSE                  (1 << 28)
5153 /*
5154  * Enables DAC state detection logic, for load-based TV detection.
5155  *
5156  * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
5157  * to off, for load detection to work.
5158  */
5159 # define TVDAC_STATE_CHG_EN             (1 << 27)
5160 /* Sets the DAC A sense value to high */
5161 # define TVDAC_A_SENSE_CTL              (1 << 26)
5162 /* Sets the DAC B sense value to high */
5163 # define TVDAC_B_SENSE_CTL              (1 << 25)
5164 /* Sets the DAC C sense value to high */
5165 # define TVDAC_C_SENSE_CTL              (1 << 24)
5166 /* Overrides the ENC_ENABLE and DAC voltage levels */
5167 # define DAC_CTL_OVERRIDE               (1 << 7)
5168 /* Sets the slew rate.  Must be preserved in software */
5169 # define ENC_TVDAC_SLEW_FAST            (1 << 6)
5170 # define DAC_A_1_3_V                    (0 << 4)
5171 # define DAC_A_1_1_V                    (1 << 4)
5172 # define DAC_A_0_7_V                    (2 << 4)
5173 # define DAC_A_MASK                     (3 << 4)
5174 # define DAC_B_1_3_V                    (0 << 2)
5175 # define DAC_B_1_1_V                    (1 << 2)
5176 # define DAC_B_0_7_V                    (2 << 2)
5177 # define DAC_B_MASK                     (3 << 2)
5178 # define DAC_C_1_3_V                    (0 << 0)
5179 # define DAC_C_1_1_V                    (1 << 0)
5180 # define DAC_C_0_7_V                    (2 << 0)
5181 # define DAC_C_MASK                     (3 << 0)
5182
5183 /*
5184  * CSC coefficients are stored in a floating point format with 9 bits of
5185  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
5186  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
5187  * -1 (0x3) being the only legal negative value.
5188  */
5189 #define TV_CSC_Y                _MMIO(0x68010)
5190 # define TV_RY_MASK                     0x07ff0000
5191 # define TV_RY_SHIFT                    16
5192 # define TV_GY_MASK                     0x00000fff
5193 # define TV_GY_SHIFT                    0
5194
5195 #define TV_CSC_Y2               _MMIO(0x68014)
5196 # define TV_BY_MASK                     0x07ff0000
5197 # define TV_BY_SHIFT                    16
5198 /*
5199  * Y attenuation for component video.
5200  *
5201  * Stored in 1.9 fixed point.
5202  */
5203 # define TV_AY_MASK                     0x000003ff
5204 # define TV_AY_SHIFT                    0
5205
5206 #define TV_CSC_U                _MMIO(0x68018)
5207 # define TV_RU_MASK                     0x07ff0000
5208 # define TV_RU_SHIFT                    16
5209 # define TV_GU_MASK                     0x000007ff
5210 # define TV_GU_SHIFT                    0
5211
5212 #define TV_CSC_U2               _MMIO(0x6801c)
5213 # define TV_BU_MASK                     0x07ff0000
5214 # define TV_BU_SHIFT                    16
5215 /*
5216  * U attenuation for component video.
5217  *
5218  * Stored in 1.9 fixed point.
5219  */
5220 # define TV_AU_MASK                     0x000003ff
5221 # define TV_AU_SHIFT                    0
5222
5223 #define TV_CSC_V                _MMIO(0x68020)
5224 # define TV_RV_MASK                     0x0fff0000
5225 # define TV_RV_SHIFT                    16
5226 # define TV_GV_MASK                     0x000007ff
5227 # define TV_GV_SHIFT                    0
5228
5229 #define TV_CSC_V2               _MMIO(0x68024)
5230 # define TV_BV_MASK                     0x07ff0000
5231 # define TV_BV_SHIFT                    16
5232 /*
5233  * V attenuation for component video.
5234  *
5235  * Stored in 1.9 fixed point.
5236  */
5237 # define TV_AV_MASK                     0x000007ff
5238 # define TV_AV_SHIFT                    0
5239
5240 #define TV_CLR_KNOBS            _MMIO(0x68028)
5241 /* 2s-complement brightness adjustment */
5242 # define TV_BRIGHTNESS_MASK             0xff000000
5243 # define TV_BRIGHTNESS_SHIFT            24
5244 /* Contrast adjustment, as a 2.6 unsigned floating point number */
5245 # define TV_CONTRAST_MASK               0x00ff0000
5246 # define TV_CONTRAST_SHIFT              16
5247 /* Saturation adjustment, as a 2.6 unsigned floating point number */
5248 # define TV_SATURATION_MASK             0x0000ff00
5249 # define TV_SATURATION_SHIFT            8
5250 /* Hue adjustment, as an integer phase angle in degrees */
5251 # define TV_HUE_MASK                    0x000000ff
5252 # define TV_HUE_SHIFT                   0
5253
5254 #define TV_CLR_LEVEL            _MMIO(0x6802c)
5255 /* Controls the DAC level for black */
5256 # define TV_BLACK_LEVEL_MASK            0x01ff0000
5257 # define TV_BLACK_LEVEL_SHIFT           16
5258 /* Controls the DAC level for blanking */
5259 # define TV_BLANK_LEVEL_MASK            0x000001ff
5260 # define TV_BLANK_LEVEL_SHIFT           0
5261
5262 #define TV_H_CTL_1              _MMIO(0x68030)
5263 /* Number of pixels in the hsync. */
5264 # define TV_HSYNC_END_MASK              0x1fff0000
5265 # define TV_HSYNC_END_SHIFT             16
5266 /* Total number of pixels minus one in the line (display and blanking). */
5267 # define TV_HTOTAL_MASK                 0x00001fff
5268 # define TV_HTOTAL_SHIFT                0
5269
5270 #define TV_H_CTL_2              _MMIO(0x68034)
5271 /* Enables the colorburst (needed for non-component color) */
5272 # define TV_BURST_ENA                   (1 << 31)
5273 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
5274 # define TV_HBURST_START_SHIFT          16
5275 # define TV_HBURST_START_MASK           0x1fff0000
5276 /* Length of the colorburst */
5277 # define TV_HBURST_LEN_SHIFT            0
5278 # define TV_HBURST_LEN_MASK             0x0001fff
5279
5280 #define TV_H_CTL_3              _MMIO(0x68038)
5281 /* End of hblank, measured in pixels minus one from start of hsync */
5282 # define TV_HBLANK_END_SHIFT            16
5283 # define TV_HBLANK_END_MASK             0x1fff0000
5284 /* Start of hblank, measured in pixels minus one from start of hsync */
5285 # define TV_HBLANK_START_SHIFT          0
5286 # define TV_HBLANK_START_MASK           0x0001fff
5287
5288 #define TV_V_CTL_1              _MMIO(0x6803c)
5289 /* XXX */
5290 # define TV_NBR_END_SHIFT               16
5291 # define TV_NBR_END_MASK                0x07ff0000
5292 /* XXX */
5293 # define TV_VI_END_F1_SHIFT             8
5294 # define TV_VI_END_F1_MASK              0x00003f00
5295 /* XXX */
5296 # define TV_VI_END_F2_SHIFT             0
5297 # define TV_VI_END_F2_MASK              0x0000003f
5298
5299 #define TV_V_CTL_2              _MMIO(0x68040)
5300 /* Length of vsync, in half lines */
5301 # define TV_VSYNC_LEN_MASK              0x07ff0000
5302 # define TV_VSYNC_LEN_SHIFT             16
5303 /* Offset of the start of vsync in field 1, measured in one less than the
5304  * number of half lines.
5305  */
5306 # define TV_VSYNC_START_F1_MASK         0x00007f00
5307 # define TV_VSYNC_START_F1_SHIFT        8
5308 /*
5309  * Offset of the start of vsync in field 2, measured in one less than the
5310  * number of half lines.
5311  */
5312 # define TV_VSYNC_START_F2_MASK         0x0000007f
5313 # define TV_VSYNC_START_F2_SHIFT        0
5314
5315 #define TV_V_CTL_3              _MMIO(0x68044)
5316 /* Enables generation of the equalization signal */
5317 # define TV_EQUAL_ENA                   (1 << 31)
5318 /* Length of vsync, in half lines */
5319 # define TV_VEQ_LEN_MASK                0x007f0000
5320 # define TV_VEQ_LEN_SHIFT               16
5321 /* Offset of the start of equalization in field 1, measured in one less than
5322  * the number of half lines.
5323  */
5324 # define TV_VEQ_START_F1_MASK           0x0007f00
5325 # define TV_VEQ_START_F1_SHIFT          8
5326 /*
5327  * Offset of the start of equalization in field 2, measured in one less than
5328  * the number of half lines.
5329  */
5330 # define TV_VEQ_START_F2_MASK           0x000007f
5331 # define TV_VEQ_START_F2_SHIFT          0
5332
5333 #define TV_V_CTL_4              _MMIO(0x68048)
5334 /*
5335  * Offset to start of vertical colorburst, measured in one less than the
5336  * number of lines from vertical start.
5337  */
5338 # define TV_VBURST_START_F1_MASK        0x003f0000
5339 # define TV_VBURST_START_F1_SHIFT       16
5340 /*
5341  * Offset to the end of vertical colorburst, measured in one less than the
5342  * number of lines from the start of NBR.
5343  */
5344 # define TV_VBURST_END_F1_MASK          0x000000ff
5345 # define TV_VBURST_END_F1_SHIFT         0
5346
5347 #define TV_V_CTL_5              _MMIO(0x6804c)
5348 /*
5349  * Offset to start of vertical colorburst, measured in one less than the
5350  * number of lines from vertical start.
5351  */
5352 # define TV_VBURST_START_F2_MASK        0x003f0000
5353 # define TV_VBURST_START_F2_SHIFT       16
5354 /*
5355  * Offset to the end of vertical colorburst, measured in one less than the
5356  * number of lines from the start of NBR.
5357  */
5358 # define TV_VBURST_END_F2_MASK          0x000000ff
5359 # define TV_VBURST_END_F2_SHIFT         0
5360
5361 #define TV_V_CTL_6              _MMIO(0x68050)
5362 /*
5363  * Offset to start of vertical colorburst, measured in one less than the
5364  * number of lines from vertical start.
5365  */
5366 # define TV_VBURST_START_F3_MASK        0x003f0000
5367 # define TV_VBURST_START_F3_SHIFT       16
5368 /*
5369  * Offset to the end of vertical colorburst, measured in one less than the
5370  * number of lines from the start of NBR.
5371  */
5372 # define TV_VBURST_END_F3_MASK          0x000000ff
5373 # define TV_VBURST_END_F3_SHIFT         0
5374
5375 #define TV_V_CTL_7              _MMIO(0x68054)
5376 /*
5377  * Offset to start of vertical colorburst, measured in one less than the
5378  * number of lines from vertical start.
5379  */
5380 # define TV_VBURST_START_F4_MASK        0x003f0000
5381 # define TV_VBURST_START_F4_SHIFT       16
5382 /*
5383  * Offset to the end of vertical colorburst, measured in one less than the
5384  * number of lines from the start of NBR.
5385  */
5386 # define TV_VBURST_END_F4_MASK          0x000000ff
5387 # define TV_VBURST_END_F4_SHIFT         0
5388
5389 #define TV_SC_CTL_1             _MMIO(0x68060)
5390 /* Turns on the first subcarrier phase generation DDA */
5391 # define TV_SC_DDA1_EN                  (1 << 31)
5392 /* Turns on the first subcarrier phase generation DDA */
5393 # define TV_SC_DDA2_EN                  (1 << 30)
5394 /* Turns on the first subcarrier phase generation DDA */
5395 # define TV_SC_DDA3_EN                  (1 << 29)
5396 /* Sets the subcarrier DDA to reset frequency every other field */
5397 # define TV_SC_RESET_EVERY_2            (0 << 24)
5398 /* Sets the subcarrier DDA to reset frequency every fourth field */
5399 # define TV_SC_RESET_EVERY_4            (1 << 24)
5400 /* Sets the subcarrier DDA to reset frequency every eighth field */
5401 # define TV_SC_RESET_EVERY_8            (2 << 24)
5402 /* Sets the subcarrier DDA to never reset the frequency */
5403 # define TV_SC_RESET_NEVER              (3 << 24)
5404 /* Sets the peak amplitude of the colorburst.*/
5405 # define TV_BURST_LEVEL_MASK            0x00ff0000
5406 # define TV_BURST_LEVEL_SHIFT           16
5407 /* Sets the increment of the first subcarrier phase generation DDA */
5408 # define TV_SCDDA1_INC_MASK             0x00000fff
5409 # define TV_SCDDA1_INC_SHIFT            0
5410
5411 #define TV_SC_CTL_2             _MMIO(0x68064)
5412 /* Sets the rollover for the second subcarrier phase generation DDA */
5413 # define TV_SCDDA2_SIZE_MASK            0x7fff0000
5414 # define TV_SCDDA2_SIZE_SHIFT           16
5415 /* Sets the increent of the second subcarrier phase generation DDA */
5416 # define TV_SCDDA2_INC_MASK             0x00007fff
5417 # define TV_SCDDA2_INC_SHIFT            0
5418
5419 #define TV_SC_CTL_3             _MMIO(0x68068)
5420 /* Sets the rollover for the third subcarrier phase generation DDA */
5421 # define TV_SCDDA3_SIZE_MASK            0x7fff0000
5422 # define TV_SCDDA3_SIZE_SHIFT           16
5423 /* Sets the increent of the third subcarrier phase generation DDA */
5424 # define TV_SCDDA3_INC_MASK             0x00007fff
5425 # define TV_SCDDA3_INC_SHIFT            0
5426
5427 #define TV_WIN_POS              _MMIO(0x68070)
5428 /* X coordinate of the display from the start of horizontal active */
5429 # define TV_XPOS_MASK                   0x1fff0000
5430 # define TV_XPOS_SHIFT                  16
5431 /* Y coordinate of the display from the start of vertical active (NBR) */
5432 # define TV_YPOS_MASK                   0x00000fff
5433 # define TV_YPOS_SHIFT                  0
5434
5435 #define TV_WIN_SIZE             _MMIO(0x68074)
5436 /* Horizontal size of the display window, measured in pixels*/
5437 # define TV_XSIZE_MASK                  0x1fff0000
5438 # define TV_XSIZE_SHIFT                 16
5439 /*
5440  * Vertical size of the display window, measured in pixels.
5441  *
5442  * Must be even for interlaced modes.
5443  */
5444 # define TV_YSIZE_MASK                  0x00000fff
5445 # define TV_YSIZE_SHIFT                 0
5446
5447 #define TV_FILTER_CTL_1         _MMIO(0x68080)
5448 /*
5449  * Enables automatic scaling calculation.
5450  *
5451  * If set, the rest of the registers are ignored, and the calculated values can
5452  * be read back from the register.
5453  */
5454 # define TV_AUTO_SCALE                  (1 << 31)
5455 /*
5456  * Disables the vertical filter.
5457  *
5458  * This is required on modes more than 1024 pixels wide */
5459 # define TV_V_FILTER_BYPASS             (1 << 29)
5460 /* Enables adaptive vertical filtering */
5461 # define TV_VADAPT                      (1 << 28)
5462 # define TV_VADAPT_MODE_MASK            (3 << 26)
5463 /* Selects the least adaptive vertical filtering mode */
5464 # define TV_VADAPT_MODE_LEAST           (0 << 26)
5465 /* Selects the moderately adaptive vertical filtering mode */
5466 # define TV_VADAPT_MODE_MODERATE        (1 << 26)
5467 /* Selects the most adaptive vertical filtering mode */
5468 # define TV_VADAPT_MODE_MOST            (3 << 26)
5469 /*
5470  * Sets the horizontal scaling factor.
5471  *
5472  * This should be the fractional part of the horizontal scaling factor divided
5473  * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
5474  *
5475  * (src width - 1) / ((oversample * dest width) - 1)
5476  */
5477 # define TV_HSCALE_FRAC_MASK            0x00003fff
5478 # define TV_HSCALE_FRAC_SHIFT           0
5479
5480 #define TV_FILTER_CTL_2         _MMIO(0x68084)
5481 /*
5482  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5483  *
5484  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5485  */
5486 # define TV_VSCALE_INT_MASK             0x00038000
5487 # define TV_VSCALE_INT_SHIFT            15
5488 /*
5489  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5490  *
5491  * \sa TV_VSCALE_INT_MASK
5492  */
5493 # define TV_VSCALE_FRAC_MASK            0x00007fff
5494 # define TV_VSCALE_FRAC_SHIFT           0
5495
5496 #define TV_FILTER_CTL_3         _MMIO(0x68088)
5497 /*
5498  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5499  *
5500  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5501  *
5502  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5503  */
5504 # define TV_VSCALE_IP_INT_MASK          0x00038000
5505 # define TV_VSCALE_IP_INT_SHIFT         15
5506 /*
5507  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5508  *
5509  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5510  *
5511  * \sa TV_VSCALE_IP_INT_MASK
5512  */
5513 # define TV_VSCALE_IP_FRAC_MASK         0x00007fff
5514 # define TV_VSCALE_IP_FRAC_SHIFT                0
5515
5516 #define TV_CC_CONTROL           _MMIO(0x68090)
5517 # define TV_CC_ENABLE                   (1 << 31)
5518 /*
5519  * Specifies which field to send the CC data in.
5520  *
5521  * CC data is usually sent in field 0.
5522  */
5523 # define TV_CC_FID_MASK                 (1 << 27)
5524 # define TV_CC_FID_SHIFT                27
5525 /* Sets the horizontal position of the CC data.  Usually 135. */
5526 # define TV_CC_HOFF_MASK                0x03ff0000
5527 # define TV_CC_HOFF_SHIFT               16
5528 /* Sets the vertical position of the CC data.  Usually 21 */
5529 # define TV_CC_LINE_MASK                0x0000003f
5530 # define TV_CC_LINE_SHIFT               0
5531
5532 #define TV_CC_DATA              _MMIO(0x68094)
5533 # define TV_CC_RDY                      (1 << 31)
5534 /* Second word of CC data to be transmitted. */
5535 # define TV_CC_DATA_2_MASK              0x007f0000
5536 # define TV_CC_DATA_2_SHIFT             16
5537 /* First word of CC data to be transmitted. */
5538 # define TV_CC_DATA_1_MASK              0x0000007f
5539 # define TV_CC_DATA_1_SHIFT             0
5540
5541 #define TV_H_LUMA(i)            _MMIO(0x68100 + (i) * 4) /* 60 registers */
5542 #define TV_H_CHROMA(i)          _MMIO(0x68200 + (i) * 4) /* 60 registers */
5543 #define TV_V_LUMA(i)            _MMIO(0x68300 + (i) * 4) /* 43 registers */
5544 #define TV_V_CHROMA(i)          _MMIO(0x68400 + (i) * 4) /* 43 registers */
5545
5546 /* Display Port */
5547 #define DP_A                    _MMIO(0x64000) /* eDP */
5548 #define DP_B                    _MMIO(0x64100)
5549 #define DP_C                    _MMIO(0x64200)
5550 #define DP_D                    _MMIO(0x64300)
5551
5552 #define VLV_DP_B                _MMIO(VLV_DISPLAY_BASE + 0x64100)
5553 #define VLV_DP_C                _MMIO(VLV_DISPLAY_BASE + 0x64200)
5554 #define CHV_DP_D                _MMIO(VLV_DISPLAY_BASE + 0x64300)
5555
5556 #define   DP_PORT_EN                    (1 << 31)
5557 #define   DP_PIPE_SEL_SHIFT             30
5558 #define   DP_PIPE_SEL_MASK              (1 << 30)
5559 #define   DP_PIPE_SEL(pipe)             ((pipe) << 30)
5560 #define   DP_PIPE_SEL_SHIFT_IVB         29
5561 #define   DP_PIPE_SEL_MASK_IVB          (3 << 29)
5562 #define   DP_PIPE_SEL_IVB(pipe)         ((pipe) << 29)
5563 #define   DP_PIPE_SEL_SHIFT_CHV         16
5564 #define   DP_PIPE_SEL_MASK_CHV          (3 << 16)
5565 #define   DP_PIPE_SEL_CHV(pipe)         ((pipe) << 16)
5566
5567 /* Link training mode - select a suitable mode for each stage */
5568 #define   DP_LINK_TRAIN_PAT_1           (0 << 28)
5569 #define   DP_LINK_TRAIN_PAT_2           (1 << 28)
5570 #define   DP_LINK_TRAIN_PAT_IDLE        (2 << 28)
5571 #define   DP_LINK_TRAIN_OFF             (3 << 28)
5572 #define   DP_LINK_TRAIN_MASK            (3 << 28)
5573 #define   DP_LINK_TRAIN_SHIFT           28
5574
5575 /* CPT Link training mode */
5576 #define   DP_LINK_TRAIN_PAT_1_CPT       (0 << 8)
5577 #define   DP_LINK_TRAIN_PAT_2_CPT       (1 << 8)
5578 #define   DP_LINK_TRAIN_PAT_IDLE_CPT    (2 << 8)
5579 #define   DP_LINK_TRAIN_OFF_CPT         (3 << 8)
5580 #define   DP_LINK_TRAIN_MASK_CPT        (7 << 8)
5581 #define   DP_LINK_TRAIN_SHIFT_CPT       8
5582
5583 /* Signal voltages. These are mostly controlled by the other end */
5584 #define   DP_VOLTAGE_0_4                (0 << 25)
5585 #define   DP_VOLTAGE_0_6                (1 << 25)
5586 #define   DP_VOLTAGE_0_8                (2 << 25)
5587 #define   DP_VOLTAGE_1_2                (3 << 25)
5588 #define   DP_VOLTAGE_MASK               (7 << 25)
5589 #define   DP_VOLTAGE_SHIFT              25
5590
5591 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5592  * they want
5593  */
5594 #define   DP_PRE_EMPHASIS_0             (0 << 22)
5595 #define   DP_PRE_EMPHASIS_3_5           (1 << 22)
5596 #define   DP_PRE_EMPHASIS_6             (2 << 22)
5597 #define   DP_PRE_EMPHASIS_9_5           (3 << 22)
5598 #define   DP_PRE_EMPHASIS_MASK          (7 << 22)
5599 #define   DP_PRE_EMPHASIS_SHIFT         22
5600
5601 /* How many wires to use. I guess 3 was too hard */
5602 #define   DP_PORT_WIDTH(width)          (((width) - 1) << 19)
5603 #define   DP_PORT_WIDTH_MASK            (7 << 19)
5604 #define   DP_PORT_WIDTH_SHIFT           19
5605
5606 /* Mystic DPCD version 1.1 special mode */
5607 #define   DP_ENHANCED_FRAMING           (1 << 18)
5608
5609 /* eDP */
5610 #define   DP_PLL_FREQ_270MHZ            (0 << 16)
5611 #define   DP_PLL_FREQ_162MHZ            (1 << 16)
5612 #define   DP_PLL_FREQ_MASK              (3 << 16)
5613
5614 /* locked once port is enabled */
5615 #define   DP_PORT_REVERSAL              (1 << 15)
5616
5617 /* eDP */
5618 #define   DP_PLL_ENABLE                 (1 << 14)
5619
5620 /* sends the clock on lane 15 of the PEG for debug */
5621 #define   DP_CLOCK_OUTPUT_ENABLE        (1 << 13)
5622
5623 #define   DP_SCRAMBLING_DISABLE         (1 << 12)
5624 #define   DP_SCRAMBLING_DISABLE_IRONLAKE        (1 << 7)
5625
5626 /* limit RGB values to avoid confusing TVs */
5627 #define   DP_COLOR_RANGE_16_235         (1 << 8)
5628
5629 /* Turn on the audio link */
5630 #define   DP_AUDIO_OUTPUT_ENABLE        (1 << 6)
5631
5632 /* vs and hs sync polarity */
5633 #define   DP_SYNC_VS_HIGH               (1 << 4)
5634 #define   DP_SYNC_HS_HIGH               (1 << 3)
5635
5636 /* A fantasy */
5637 #define   DP_DETECTED                   (1 << 2)
5638
5639 /* The aux channel provides a way to talk to the
5640  * signal sink for DDC etc. Max packet size supported
5641  * is 20 bytes in each direction, hence the 5 fixed
5642  * data registers
5643  */
5644 #define _DPA_AUX_CH_CTL         (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
5645 #define _DPA_AUX_CH_DATA1       (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
5646
5647 #define _DPB_AUX_CH_CTL         (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
5648 #define _DPB_AUX_CH_DATA1       (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
5649
5650 #define DP_AUX_CH_CTL(aux_ch)   _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5651 #define DP_AUX_CH_DATA(aux_ch, i)       _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5652
5653 #define   DP_AUX_CH_CTL_SEND_BUSY           (1 << 31)
5654 #define   DP_AUX_CH_CTL_DONE                (1 << 30)
5655 #define   DP_AUX_CH_CTL_INTERRUPT           (1 << 29)
5656 #define   DP_AUX_CH_CTL_TIME_OUT_ERROR      (1 << 28)
5657 #define   DP_AUX_CH_CTL_TIME_OUT_400us      (0 << 26)
5658 #define   DP_AUX_CH_CTL_TIME_OUT_600us      (1 << 26)
5659 #define   DP_AUX_CH_CTL_TIME_OUT_800us      (2 << 26)
5660 #define   DP_AUX_CH_CTL_TIME_OUT_MAX        (3 << 26) /* Varies per platform */
5661 #define   DP_AUX_CH_CTL_TIME_OUT_MASK       (3 << 26)
5662 #define   DP_AUX_CH_CTL_RECEIVE_ERROR       (1 << 25)
5663 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
5664 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
5665 #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
5666 #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
5667 #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT     (1 << 15)
5668 #define   DP_AUX_CH_CTL_MANCHESTER_TEST     (1 << 14)
5669 #define   DP_AUX_CH_CTL_SYNC_TEST           (1 << 13)
5670 #define   DP_AUX_CH_CTL_DEGLITCH_TEST       (1 << 12)
5671 #define   DP_AUX_CH_CTL_PRECHARGE_TEST      (1 << 11)
5672 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
5673 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
5674 #define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL    (1 << 14)
5675 #define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL     (1 << 13)
5676 #define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL    (1 << 12)
5677 #define   DP_AUX_CH_CTL_TBT_IO                  (1 << 11)
5678 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5679 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5680 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)
5681
5682 /*
5683  * Computing GMCH M and N values for the Display Port link
5684  *
5685  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5686  *
5687  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5688  *
5689  * The GMCH value is used internally
5690  *
5691  * bytes_per_pixel is the number of bytes coming out of the plane,
5692  * which is after the LUTs, so we want the bytes for our color format.
5693  * For our current usage, this is always 3, one byte for R, G and B.
5694  */
5695 #define _PIPEA_DATA_M_G4X       0x70050
5696 #define _PIPEB_DATA_M_G4X       0x71050
5697
5698 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5699 #define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */
5700 #define  TU_SIZE_SHIFT          25
5701 #define  TU_SIZE_MASK           (0x3f << 25)
5702
5703 #define  DATA_LINK_M_N_MASK     (0xffffff)
5704 #define  DATA_LINK_N_MAX        (0x800000)
5705
5706 #define _PIPEA_DATA_N_G4X       0x70054
5707 #define _PIPEB_DATA_N_G4X       0x71054
5708 #define   PIPE_GMCH_DATA_N_MASK                 (0xffffff)
5709
5710 /*
5711  * Computing Link M and N values for the Display Port link
5712  *
5713  * Link M / N = pixel_clock / ls_clk
5714  *
5715  * (the DP spec calls pixel_clock the 'strm_clk')
5716  *
5717  * The Link value is transmitted in the Main Stream
5718  * Attributes and VB-ID.
5719  */
5720
5721 #define _PIPEA_LINK_M_G4X       0x70060
5722 #define _PIPEB_LINK_M_G4X       0x71060
5723 #define   PIPEA_DP_LINK_M_MASK                  (0xffffff)
5724
5725 #define _PIPEA_LINK_N_G4X       0x70064
5726 #define _PIPEB_LINK_N_G4X       0x71064
5727 #define   PIPEA_DP_LINK_N_MASK                  (0xffffff)
5728
5729 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5730 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5731 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5732 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5733
5734 /* Display & cursor control */
5735
5736 /* Pipe A */
5737 #define _PIPEADSL               0x70000
5738 #define   DSL_LINEMASK_GEN2     0x00000fff
5739 #define   DSL_LINEMASK_GEN3     0x00001fff
5740 #define _PIPEACONF              0x70008
5741 #define   PIPECONF_ENABLE       (1 << 31)
5742 #define   PIPECONF_DISABLE      0
5743 #define   PIPECONF_DOUBLE_WIDE  (1 << 30)
5744 #define   I965_PIPECONF_ACTIVE  (1 << 30)
5745 #define   PIPECONF_DSI_PLL_LOCKED       (1 << 29) /* vlv & pipe A only */
5746 #define   PIPECONF_FRAME_START_DELAY_MASK       (3 << 27) /* pre-hsw */
5747 #define   PIPECONF_FRAME_START_DELAY(x)         ((x) << 27) /* pre-hsw: 0-3 */
5748 #define   PIPECONF_SINGLE_WIDE  0
5749 #define   PIPECONF_PIPE_UNLOCKED 0
5750 #define   PIPECONF_PIPE_LOCKED  (1 << 25)
5751 #define   PIPECONF_FORCE_BORDER (1 << 25)
5752 #define   PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */
5753 #define   PIPECONF_GAMMA_MODE_MASK_ILK  (3 << 24) /* ilk-ivb */
5754 #define   PIPECONF_GAMMA_MODE_8BIT      (0 << 24) /* gmch,ilk-ivb */
5755 #define   PIPECONF_GAMMA_MODE_10BIT     (1 << 24) /* gmch,ilk-ivb */
5756 #define   PIPECONF_GAMMA_MODE_12BIT     (2 << 24) /* ilk-ivb */
5757 #define   PIPECONF_GAMMA_MODE_SPLIT     (3 << 24) /* ivb */
5758 #define   PIPECONF_GAMMA_MODE(x)        ((x) << 24) /* pass in GAMMA_MODE_MODE_* */
5759 #define   PIPECONF_GAMMA_MODE_SHIFT     24
5760 #define   PIPECONF_INTERLACE_MASK       (7 << 21)
5761 #define   PIPECONF_INTERLACE_MASK_HSW   (3 << 21)
5762 /* Note that pre-gen3 does not support interlaced display directly. Panel
5763  * fitting must be disabled on pre-ilk for interlaced. */
5764 #define   PIPECONF_PROGRESSIVE                  (0 << 21)
5765 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
5766 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT       (5 << 21) /* gen4 only */
5767 #define   PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
5768 #define   PIPECONF_INTERLACE_FIELD_0_ONLY       (7 << 21) /* gen3 only */
5769 /* Ironlake and later have a complete new set of values for interlaced. PFIT
5770  * means panel fitter required, PF means progressive fetch, DBL means power
5771  * saving pixel doubling. */
5772 #define   PIPECONF_PFIT_PF_INTERLACED_ILK       (1 << 21)
5773 #define   PIPECONF_INTERLACED_ILK               (3 << 21)
5774 #define   PIPECONF_INTERLACED_DBL_ILK           (4 << 21) /* ilk/snb only */
5775 #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK   (5 << 21) /* ilk/snb only */
5776 #define   PIPECONF_INTERLACE_MODE_MASK          (7 << 21)
5777 #define   PIPECONF_EDP_RR_MODE_SWITCH           (1 << 20)
5778 #define   PIPECONF_CXSR_DOWNCLOCK       (1 << 16)
5779 #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV       (1 << 14)
5780 #define   PIPECONF_COLOR_RANGE_SELECT   (1 << 13)
5781 #define   PIPECONF_OUTPUT_COLORSPACE_MASK       (3 << 11) /* ilk-ivb */
5782 #define   PIPECONF_OUTPUT_COLORSPACE_RGB        (0 << 11) /* ilk-ivb */
5783 #define   PIPECONF_OUTPUT_COLORSPACE_YUV601     (1 << 11) /* ilk-ivb */
5784 #define   PIPECONF_OUTPUT_COLORSPACE_YUV709     (2 << 11) /* ilk-ivb */
5785 #define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW    (1 << 11) /* hsw only */
5786 #define   PIPECONF_BPC_MASK     (0x7 << 5)
5787 #define   PIPECONF_8BPC         (0 << 5)
5788 #define   PIPECONF_10BPC        (1 << 5)
5789 #define   PIPECONF_6BPC         (2 << 5)
5790 #define   PIPECONF_12BPC        (3 << 5)
5791 #define   PIPECONF_DITHER_EN    (1 << 4)
5792 #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5793 #define   PIPECONF_DITHER_TYPE_SP (0 << 2)
5794 #define   PIPECONF_DITHER_TYPE_ST1 (1 << 2)
5795 #define   PIPECONF_DITHER_TYPE_ST2 (2 << 2)
5796 #define   PIPECONF_DITHER_TYPE_TEMP (3 << 2)
5797 #define _PIPEASTAT              0x70024
5798 #define   PIPE_FIFO_UNDERRUN_STATUS             (1UL << 31)
5799 #define   SPRITE1_FLIP_DONE_INT_EN_VLV          (1UL << 30)
5800 #define   PIPE_CRC_ERROR_ENABLE                 (1UL << 29)
5801 #define   PIPE_CRC_DONE_ENABLE                  (1UL << 28)
5802 #define   PERF_COUNTER2_INTERRUPT_EN            (1UL << 27)
5803 #define   PIPE_GMBUS_EVENT_ENABLE               (1UL << 27)
5804 #define   PLANE_FLIP_DONE_INT_EN_VLV            (1UL << 26)
5805 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE         (1UL << 26)
5806 #define   PIPE_VSYNC_INTERRUPT_ENABLE           (1UL << 25)
5807 #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE      (1UL << 24)
5808 #define   PIPE_DPST_EVENT_ENABLE                (1UL << 23)
5809 #define   SPRITE0_FLIP_DONE_INT_EN_VLV          (1UL << 22)
5810 #define   PIPE_LEGACY_BLC_EVENT_ENABLE          (1UL << 22)
5811 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE       (1UL << 21)
5812 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE      (1UL << 20)
5813 #define   PIPE_B_PSR_INTERRUPT_ENABLE_VLV       (1UL << 19)
5814 #define   PERF_COUNTER_INTERRUPT_EN             (1UL << 19)
5815 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE      (1UL << 18) /* pre-965 */
5816 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE    (1UL << 18) /* 965 or later */
5817 #define   PIPE_FRAMESTART_INTERRUPT_ENABLE      (1UL << 17)
5818 #define   PIPE_VBLANK_INTERRUPT_ENABLE          (1UL << 17)
5819 #define   PIPEA_HBLANK_INT_EN_VLV               (1UL << 16)
5820 #define   PIPE_OVERLAY_UPDATED_ENABLE           (1UL << 16)
5821 #define   SPRITE1_FLIP_DONE_INT_STATUS_VLV      (1UL << 15)
5822 #define   SPRITE0_FLIP_DONE_INT_STATUS_VLV      (1UL << 14)
5823 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS       (1UL << 13)
5824 #define   PIPE_CRC_DONE_INTERRUPT_STATUS        (1UL << 12)
5825 #define   PERF_COUNTER2_INTERRUPT_STATUS        (1UL << 11)
5826 #define   PIPE_GMBUS_INTERRUPT_STATUS           (1UL << 11)
5827 #define   PLANE_FLIP_DONE_INT_STATUS_VLV        (1UL << 10)
5828 #define   PIPE_HOTPLUG_INTERRUPT_STATUS         (1UL << 10)
5829 #define   PIPE_VSYNC_INTERRUPT_STATUS           (1UL << 9)
5830 #define   PIPE_DISPLAY_LINE_COMPARE_STATUS      (1UL << 8)
5831 #define   PIPE_DPST_EVENT_STATUS                (1UL << 7)
5832 #define   PIPE_A_PSR_STATUS_VLV                 (1UL << 6)
5833 #define   PIPE_LEGACY_BLC_EVENT_STATUS          (1UL << 6)
5834 #define   PIPE_ODD_FIELD_INTERRUPT_STATUS       (1UL << 5)
5835 #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS      (1UL << 4)
5836 #define   PIPE_B_PSR_STATUS_VLV                 (1UL << 3)
5837 #define   PERF_COUNTER_INTERRUPT_STATUS         (1UL << 3)
5838 #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS      (1UL << 2) /* pre-965 */
5839 #define   PIPE_START_VBLANK_INTERRUPT_STATUS    (1UL << 2) /* 965 or later */
5840 #define   PIPE_FRAMESTART_INTERRUPT_STATUS      (1UL << 1)
5841 #define   PIPE_VBLANK_INTERRUPT_STATUS          (1UL << 1)
5842 #define   PIPE_HBLANK_INT_STATUS                (1UL << 0)
5843 #define   PIPE_OVERLAY_UPDATED_STATUS           (1UL << 0)
5844
5845 #define PIPESTAT_INT_ENABLE_MASK                0x7fff0000
5846 #define PIPESTAT_INT_STATUS_MASK                0x0000ffff
5847
5848 #define PIPE_A_OFFSET           0x70000
5849 #define PIPE_B_OFFSET           0x71000
5850 #define PIPE_C_OFFSET           0x72000
5851 #define PIPE_D_OFFSET           0x73000
5852 #define CHV_PIPE_C_OFFSET       0x74000
5853 /*
5854  * There's actually no pipe EDP. Some pipe registers have
5855  * simply shifted from the pipe to the transcoder, while
5856  * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5857  * to access such registers in transcoder EDP.
5858  */
5859 #define PIPE_EDP_OFFSET 0x7f000
5860
5861 /* ICL DSI 0 and 1 */
5862 #define PIPE_DSI0_OFFSET        0x7b000
5863 #define PIPE_DSI1_OFFSET        0x7b800
5864
5865 #define PIPECONF(pipe)          _MMIO_PIPE2(pipe, _PIPEACONF)
5866 #define PIPEDSL(pipe)           _MMIO_PIPE2(pipe, _PIPEADSL)
5867 #define PIPEFRAME(pipe)         _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5868 #define PIPEFRAMEPIXEL(pipe)    _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5869 #define PIPESTAT(pipe)          _MMIO_PIPE2(pipe, _PIPEASTAT)
5870
5871 #define  _PIPEAGCMAX           0x70010
5872 #define  _PIPEBGCMAX           0x71010
5873 #define PIPEGCMAX_RGB_MASK     REG_GENMASK(15, 0)
5874 #define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
5875
5876 #define _PIPE_MISC_A                    0x70030
5877 #define _PIPE_MISC_B                    0x71030
5878 #define   PIPEMISC_YUV420_ENABLE        (1 << 27) /* glk+ */
5879 #define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
5880 #define   PIPEMISC_HDR_MODE_PRECISION   (1 << 23) /* icl+ */
5881 #define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
5882 #define   PIPEMISC_DITHER_BPC_MASK      (7 << 5)
5883 #define   PIPEMISC_DITHER_8_BPC         (0 << 5)
5884 #define   PIPEMISC_DITHER_10_BPC        (1 << 5)
5885 #define   PIPEMISC_DITHER_6_BPC         (2 << 5)
5886 #define   PIPEMISC_DITHER_12_BPC        (3 << 5)
5887 #define   PIPEMISC_DITHER_ENABLE        (1 << 4)
5888 #define   PIPEMISC_DITHER_TYPE_MASK     (3 << 2)
5889 #define   PIPEMISC_DITHER_TYPE_SP       (0 << 2)
5890 #define PIPEMISC(pipe)                  _MMIO_PIPE2(pipe, _PIPE_MISC_A)
5891
5892 /* Skylake+ pipe bottom (background) color */
5893 #define _SKL_BOTTOM_COLOR_A             0x70034
5894 #define   SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
5895 #define   SKL_BOTTOM_COLOR_CSC_ENABLE   (1 << 30)
5896 #define SKL_BOTTOM_COLOR(pipe)          _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
5897
5898 #define VLV_DPFLIPSTAT                          _MMIO(VLV_DISPLAY_BASE + 0x70028)
5899 #define   PIPEB_LINE_COMPARE_INT_EN             (1 << 29)
5900 #define   PIPEB_HLINE_INT_EN                    (1 << 28)
5901 #define   PIPEB_VBLANK_INT_EN                   (1 << 27)
5902 #define   SPRITED_FLIP_DONE_INT_EN              (1 << 26)
5903 #define   SPRITEC_FLIP_DONE_INT_EN              (1 << 25)
5904 #define   PLANEB_FLIP_DONE_INT_EN               (1 << 24)
5905 #define   PIPE_PSR_INT_EN                       (1 << 22)
5906 #define   PIPEA_LINE_COMPARE_INT_EN             (1 << 21)
5907 #define   PIPEA_HLINE_INT_EN                    (1 << 20)
5908 #define   PIPEA_VBLANK_INT_EN                   (1 << 19)
5909 #define   SPRITEB_FLIP_DONE_INT_EN              (1 << 18)
5910 #define   SPRITEA_FLIP_DONE_INT_EN              (1 << 17)
5911 #define   PLANEA_FLIPDONE_INT_EN                (1 << 16)
5912 #define   PIPEC_LINE_COMPARE_INT_EN             (1 << 13)
5913 #define   PIPEC_HLINE_INT_EN                    (1 << 12)
5914 #define   PIPEC_VBLANK_INT_EN                   (1 << 11)
5915 #define   SPRITEF_FLIPDONE_INT_EN               (1 << 10)
5916 #define   SPRITEE_FLIPDONE_INT_EN               (1 << 9)
5917 #define   PLANEC_FLIPDONE_INT_EN                (1 << 8)
5918
5919 #define DPINVGTT                                _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5920 #define   SPRITEF_INVALID_GTT_INT_EN            (1 << 27)
5921 #define   SPRITEE_INVALID_GTT_INT_EN            (1 << 26)
5922 #define   PLANEC_INVALID_GTT_INT_EN             (1 << 25)
5923 #define   CURSORC_INVALID_GTT_INT_EN            (1 << 24)
5924 #define   CURSORB_INVALID_GTT_INT_EN            (1 << 23)
5925 #define   CURSORA_INVALID_GTT_INT_EN            (1 << 22)
5926 #define   SPRITED_INVALID_GTT_INT_EN            (1 << 21)
5927 #define   SPRITEC_INVALID_GTT_INT_EN            (1 << 20)
5928 #define   PLANEB_INVALID_GTT_INT_EN             (1 << 19)
5929 #define   SPRITEB_INVALID_GTT_INT_EN            (1 << 18)
5930 #define   SPRITEA_INVALID_GTT_INT_EN            (1 << 17)
5931 #define   PLANEA_INVALID_GTT_INT_EN             (1 << 16)
5932 #define   DPINVGTT_EN_MASK                      0xff0000
5933 #define   DPINVGTT_EN_MASK_CHV                  0xfff0000
5934 #define   SPRITEF_INVALID_GTT_STATUS            (1 << 11)
5935 #define   SPRITEE_INVALID_GTT_STATUS            (1 << 10)
5936 #define   PLANEC_INVALID_GTT_STATUS             (1 << 9)
5937 #define   CURSORC_INVALID_GTT_STATUS            (1 << 8)
5938 #define   CURSORB_INVALID_GTT_STATUS            (1 << 7)
5939 #define   CURSORA_INVALID_GTT_STATUS            (1 << 6)
5940 #define   SPRITED_INVALID_GTT_STATUS            (1 << 5)
5941 #define   SPRITEC_INVALID_GTT_STATUS            (1 << 4)
5942 #define   PLANEB_INVALID_GTT_STATUS             (1 << 3)
5943 #define   SPRITEB_INVALID_GTT_STATUS            (1 << 2)
5944 #define   SPRITEA_INVALID_GTT_STATUS            (1 << 1)
5945 #define   PLANEA_INVALID_GTT_STATUS             (1 << 0)
5946 #define   DPINVGTT_STATUS_MASK                  0xff
5947 #define   DPINVGTT_STATUS_MASK_CHV              0xfff
5948
5949 #define DSPARB                  _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
5950 #define   DSPARB_CSTART_MASK    (0x7f << 7)
5951 #define   DSPARB_CSTART_SHIFT   7
5952 #define   DSPARB_BSTART_MASK    (0x7f)
5953 #define   DSPARB_BSTART_SHIFT   0
5954 #define   DSPARB_BEND_SHIFT     9 /* on 855 */
5955 #define   DSPARB_AEND_SHIFT     0
5956 #define   DSPARB_SPRITEA_SHIFT_VLV      0
5957 #define   DSPARB_SPRITEA_MASK_VLV       (0xff << 0)
5958 #define   DSPARB_SPRITEB_SHIFT_VLV      8
5959 #define   DSPARB_SPRITEB_MASK_VLV       (0xff << 8)
5960 #define   DSPARB_SPRITEC_SHIFT_VLV      16
5961 #define   DSPARB_SPRITEC_MASK_VLV       (0xff << 16)
5962 #define   DSPARB_SPRITED_SHIFT_VLV      24
5963 #define   DSPARB_SPRITED_MASK_VLV       (0xff << 24)
5964 #define DSPARB2                         _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5965 #define   DSPARB_SPRITEA_HI_SHIFT_VLV   0
5966 #define   DSPARB_SPRITEA_HI_MASK_VLV    (0x1 << 0)
5967 #define   DSPARB_SPRITEB_HI_SHIFT_VLV   4
5968 #define   DSPARB_SPRITEB_HI_MASK_VLV    (0x1 << 4)
5969 #define   DSPARB_SPRITEC_HI_SHIFT_VLV   8
5970 #define   DSPARB_SPRITEC_HI_MASK_VLV    (0x1 << 8)
5971 #define   DSPARB_SPRITED_HI_SHIFT_VLV   12
5972 #define   DSPARB_SPRITED_HI_MASK_VLV    (0x1 << 12)
5973 #define   DSPARB_SPRITEE_HI_SHIFT_VLV   16
5974 #define   DSPARB_SPRITEE_HI_MASK_VLV    (0x1 << 16)
5975 #define   DSPARB_SPRITEF_HI_SHIFT_VLV   20
5976 #define   DSPARB_SPRITEF_HI_MASK_VLV    (0x1 << 20)
5977 #define DSPARB3                         _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5978 #define   DSPARB_SPRITEE_SHIFT_VLV      0
5979 #define   DSPARB_SPRITEE_MASK_VLV       (0xff << 0)
5980 #define   DSPARB_SPRITEF_SHIFT_VLV      8
5981 #define   DSPARB_SPRITEF_MASK_VLV       (0xff << 8)
5982
5983 /* pnv/gen4/g4x/vlv/chv */
5984 #define DSPFW1          _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
5985 #define   DSPFW_SR_SHIFT                23
5986 #define   DSPFW_SR_MASK                 (0x1ff << 23)
5987 #define   DSPFW_CURSORB_SHIFT           16
5988 #define   DSPFW_CURSORB_MASK            (0x3f << 16)
5989 #define   DSPFW_PLANEB_SHIFT            8
5990 #define   DSPFW_PLANEB_MASK             (0x7f << 8)
5991 #define   DSPFW_PLANEB_MASK_VLV         (0xff << 8) /* vlv/chv */
5992 #define   DSPFW_PLANEA_SHIFT            0
5993 #define   DSPFW_PLANEA_MASK             (0x7f << 0)
5994 #define   DSPFW_PLANEA_MASK_VLV         (0xff << 0) /* vlv/chv */
5995 #define DSPFW2          _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
5996 #define   DSPFW_FBC_SR_EN               (1 << 31)         /* g4x */
5997 #define   DSPFW_FBC_SR_SHIFT            28
5998 #define   DSPFW_FBC_SR_MASK             (0x7 << 28) /* g4x */
5999 #define   DSPFW_FBC_HPLL_SR_SHIFT       24
6000 #define   DSPFW_FBC_HPLL_SR_MASK        (0xf << 24) /* g4x */
6001 #define   DSPFW_SPRITEB_SHIFT           (16)
6002 #define   DSPFW_SPRITEB_MASK            (0x7f << 16) /* g4x */
6003 #define   DSPFW_SPRITEB_MASK_VLV        (0xff << 16) /* vlv/chv */
6004 #define   DSPFW_CURSORA_SHIFT           8
6005 #define   DSPFW_CURSORA_MASK            (0x3f << 8)
6006 #define   DSPFW_PLANEC_OLD_SHIFT        0
6007 #define   DSPFW_PLANEC_OLD_MASK         (0x7f << 0) /* pre-gen4 sprite C */
6008 #define   DSPFW_SPRITEA_SHIFT           0
6009 #define   DSPFW_SPRITEA_MASK            (0x7f << 0) /* g4x */
6010 #define   DSPFW_SPRITEA_MASK_VLV        (0xff << 0) /* vlv/chv */
6011 #define DSPFW3          _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
6012 #define   DSPFW_HPLL_SR_EN              (1 << 31)
6013 #define   PINEVIEW_SELF_REFRESH_EN      (1 << 30)
6014 #define   DSPFW_CURSOR_SR_SHIFT         24
6015 #define   DSPFW_CURSOR_SR_MASK          (0x3f << 24)
6016 #define   DSPFW_HPLL_CURSOR_SHIFT       16
6017 #define   DSPFW_HPLL_CURSOR_MASK        (0x3f << 16)
6018 #define   DSPFW_HPLL_SR_SHIFT           0
6019 #define   DSPFW_HPLL_SR_MASK            (0x1ff << 0)
6020
6021 /* vlv/chv */
6022 #define DSPFW4          _MMIO(VLV_DISPLAY_BASE + 0x70070)
6023 #define   DSPFW_SPRITEB_WM1_SHIFT       16
6024 #define   DSPFW_SPRITEB_WM1_MASK        (0xff << 16)
6025 #define   DSPFW_CURSORA_WM1_SHIFT       8
6026 #define   DSPFW_CURSORA_WM1_MASK        (0x3f << 8)
6027 #define   DSPFW_SPRITEA_WM1_SHIFT       0
6028 #define   DSPFW_SPRITEA_WM1_MASK        (0xff << 0)
6029 #define DSPFW5          _MMIO(VLV_DISPLAY_BASE + 0x70074)
6030 #define   DSPFW_PLANEB_WM1_SHIFT        24
6031 #define   DSPFW_PLANEB_WM1_MASK         (0xff << 24)
6032 #define   DSPFW_PLANEA_WM1_SHIFT        16
6033 #define   DSPFW_PLANEA_WM1_MASK         (0xff << 16)
6034 #define   DSPFW_CURSORB_WM1_SHIFT       8
6035 #define   DSPFW_CURSORB_WM1_MASK        (0x3f << 8)
6036 #define   DSPFW_CURSOR_SR_WM1_SHIFT     0
6037 #define   DSPFW_CURSOR_SR_WM1_MASK      (0x3f << 0)
6038 #define DSPFW6          _MMIO(VLV_DISPLAY_BASE + 0x70078)
6039 #define   DSPFW_SR_WM1_SHIFT            0
6040 #define   DSPFW_SR_WM1_MASK             (0x1ff << 0)
6041 #define DSPFW7          _MMIO(VLV_DISPLAY_BASE + 0x7007c)
6042 #define DSPFW7_CHV      _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
6043 #define   DSPFW_SPRITED_WM1_SHIFT       24
6044 #define   DSPFW_SPRITED_WM1_MASK        (0xff << 24)
6045 #define   DSPFW_SPRITED_SHIFT           16
6046 #define   DSPFW_SPRITED_MASK_VLV        (0xff << 16)
6047 #define   DSPFW_SPRITEC_WM1_SHIFT       8
6048 #define   DSPFW_SPRITEC_WM1_MASK        (0xff << 8)
6049 #define   DSPFW_SPRITEC_SHIFT           0
6050 #define   DSPFW_SPRITEC_MASK_VLV        (0xff << 0)
6051 #define DSPFW8_CHV      _MMIO(VLV_DISPLAY_BASE + 0x700b8)
6052 #define   DSPFW_SPRITEF_WM1_SHIFT       24
6053 #define   DSPFW_SPRITEF_WM1_MASK        (0xff << 24)
6054 #define   DSPFW_SPRITEF_SHIFT           16
6055 #define   DSPFW_SPRITEF_MASK_VLV        (0xff << 16)
6056 #define   DSPFW_SPRITEE_WM1_SHIFT       8
6057 #define   DSPFW_SPRITEE_WM1_MASK        (0xff << 8)
6058 #define   DSPFW_SPRITEE_SHIFT           0
6059 #define   DSPFW_SPRITEE_MASK_VLV        (0xff << 0)
6060 #define DSPFW9_CHV      _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
6061 #define   DSPFW_PLANEC_WM1_SHIFT        24
6062 #define   DSPFW_PLANEC_WM1_MASK         (0xff << 24)
6063 #define   DSPFW_PLANEC_SHIFT            16
6064 #define   DSPFW_PLANEC_MASK_VLV         (0xff << 16)
6065 #define   DSPFW_CURSORC_WM1_SHIFT       8
6066 #define   DSPFW_CURSORC_WM1_MASK        (0x3f << 16)
6067 #define   DSPFW_CURSORC_SHIFT           0
6068 #define   DSPFW_CURSORC_MASK            (0x3f << 0)
6069
6070 /* vlv/chv high order bits */
6071 #define DSPHOWM         _MMIO(VLV_DISPLAY_BASE + 0x70064)
6072 #define   DSPFW_SR_HI_SHIFT             24
6073 #define   DSPFW_SR_HI_MASK              (3 << 24) /* 2 bits for chv, 1 for vlv */
6074 #define   DSPFW_SPRITEF_HI_SHIFT        23
6075 #define   DSPFW_SPRITEF_HI_MASK         (1 << 23)
6076 #define   DSPFW_SPRITEE_HI_SHIFT        22
6077 #define   DSPFW_SPRITEE_HI_MASK         (1 << 22)
6078 #define   DSPFW_PLANEC_HI_SHIFT         21
6079 #define   DSPFW_PLANEC_HI_MASK          (1 << 21)
6080 #define   DSPFW_SPRITED_HI_SHIFT        20
6081 #define   DSPFW_SPRITED_HI_MASK         (1 << 20)
6082 #define   DSPFW_SPRITEC_HI_SHIFT        16
6083 #define   DSPFW_SPRITEC_HI_MASK         (1 << 16)
6084 #define   DSPFW_PLANEB_HI_SHIFT         12
6085 #define   DSPFW_PLANEB_HI_MASK          (1 << 12)
6086 #define   DSPFW_SPRITEB_HI_SHIFT        8
6087 #define   DSPFW_SPRITEB_HI_MASK         (1 << 8)
6088 #define   DSPFW_SPRITEA_HI_SHIFT        4
6089 #define   DSPFW_SPRITEA_HI_MASK         (1 << 4)
6090 #define   DSPFW_PLANEA_HI_SHIFT         0
6091 #define   DSPFW_PLANEA_HI_MASK          (1 << 0)
6092 #define DSPHOWM1        _MMIO(VLV_DISPLAY_BASE + 0x70068)
6093 #define   DSPFW_SR_WM1_HI_SHIFT         24
6094 #define   DSPFW_SR_WM1_HI_MASK          (3 << 24) /* 2 bits for chv, 1 for vlv */
6095 #define   DSPFW_SPRITEF_WM1_HI_SHIFT    23
6096 #define   DSPFW_SPRITEF_WM1_HI_MASK     (1 << 23)
6097 #define   DSPFW_SPRITEE_WM1_HI_SHIFT    22
6098 #define   DSPFW_SPRITEE_WM1_HI_MASK     (1 << 22)
6099 #define   DSPFW_PLANEC_WM1_HI_SHIFT     21
6100 #define   DSPFW_PLANEC_WM1_HI_MASK      (1 << 21)
6101 #define   DSPFW_SPRITED_WM1_HI_SHIFT    20
6102 #define   DSPFW_SPRITED_WM1_HI_MASK     (1 << 20)
6103 #define   DSPFW_SPRITEC_WM1_HI_SHIFT    16
6104 #define   DSPFW_SPRITEC_WM1_HI_MASK     (1 << 16)
6105 #define   DSPFW_PLANEB_WM1_HI_SHIFT     12
6106 #define   DSPFW_PLANEB_WM1_HI_MASK      (1 << 12)
6107 #define   DSPFW_SPRITEB_WM1_HI_SHIFT    8
6108 #define   DSPFW_SPRITEB_WM1_HI_MASK     (1 << 8)
6109 #define   DSPFW_SPRITEA_WM1_HI_SHIFT    4
6110 #define   DSPFW_SPRITEA_WM1_HI_MASK     (1 << 4)
6111 #define   DSPFW_PLANEA_WM1_HI_SHIFT     0
6112 #define   DSPFW_PLANEA_WM1_HI_MASK      (1 << 0)
6113
6114 /* drain latency register values*/
6115 #define VLV_DDL(pipe)                   _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
6116 #define DDL_CURSOR_SHIFT                24
6117 #define DDL_SPRITE_SHIFT(sprite)        (8 + 8 * (sprite))
6118 #define DDL_PLANE_SHIFT                 0
6119 #define DDL_PRECISION_HIGH              (1 << 7)
6120 #define DDL_PRECISION_LOW               (0 << 7)
6121 #define DRAIN_LATENCY_MASK              0x7f
6122
6123 #define CBR1_VLV                        _MMIO(VLV_DISPLAY_BASE + 0x70400)
6124 #define  CBR_PND_DEADLINE_DISABLE       (1 << 31)
6125 #define  CBR_PWM_CLOCK_MUX_SELECT       (1 << 30)
6126
6127 #define CBR4_VLV                        _MMIO(VLV_DISPLAY_BASE + 0x70450)
6128 #define  CBR_DPLLBMD_PIPE(pipe)         (1 << (7 + (pipe) * 11)) /* pipes B and C */
6129
6130 /* FIFO watermark sizes etc */
6131 #define G4X_FIFO_LINE_SIZE      64
6132 #define I915_FIFO_LINE_SIZE     64
6133 #define I830_FIFO_LINE_SIZE     32
6134
6135 #define VALLEYVIEW_FIFO_SIZE    255
6136 #define G4X_FIFO_SIZE           127
6137 #define I965_FIFO_SIZE          512
6138 #define I945_FIFO_SIZE          127
6139 #define I915_FIFO_SIZE          95
6140 #define I855GM_FIFO_SIZE        127 /* In cachelines */
6141 #define I830_FIFO_SIZE          95
6142
6143 #define VALLEYVIEW_MAX_WM       0xff
6144 #define G4X_MAX_WM              0x3f
6145 #define I915_MAX_WM             0x3f
6146
6147 #define PINEVIEW_DISPLAY_FIFO   512 /* in 64byte unit */
6148 #define PINEVIEW_FIFO_LINE_SIZE 64
6149 #define PINEVIEW_MAX_WM         0x1ff
6150 #define PINEVIEW_DFT_WM         0x3f
6151 #define PINEVIEW_DFT_HPLLOFF_WM 0
6152 #define PINEVIEW_GUARD_WM               10
6153 #define PINEVIEW_CURSOR_FIFO            64
6154 #define PINEVIEW_CURSOR_MAX_WM  0x3f
6155 #define PINEVIEW_CURSOR_DFT_WM  0
6156 #define PINEVIEW_CURSOR_GUARD_WM        5
6157
6158 #define VALLEYVIEW_CURSOR_MAX_WM 64
6159 #define I965_CURSOR_FIFO        64
6160 #define I965_CURSOR_MAX_WM      32
6161 #define I965_CURSOR_DFT_WM      8
6162
6163 /* Watermark register definitions for SKL */
6164 #define _CUR_WM_A_0             0x70140
6165 #define _CUR_WM_B_0             0x71140
6166 #define _PLANE_WM_1_A_0         0x70240
6167 #define _PLANE_WM_1_B_0         0x71240
6168 #define _PLANE_WM_2_A_0         0x70340
6169 #define _PLANE_WM_2_B_0         0x71340
6170 #define _PLANE_WM_TRANS_1_A_0   0x70268
6171 #define _PLANE_WM_TRANS_1_B_0   0x71268
6172 #define _PLANE_WM_TRANS_2_A_0   0x70368
6173 #define _PLANE_WM_TRANS_2_B_0   0x71368
6174 #define _CUR_WM_TRANS_A_0       0x70168
6175 #define _CUR_WM_TRANS_B_0       0x71168
6176 #define   PLANE_WM_EN           (1 << 31)
6177 #define   PLANE_WM_IGNORE_LINES (1 << 30)
6178 #define   PLANE_WM_LINES_SHIFT  14
6179 #define   PLANE_WM_LINES_MASK   0x1f
6180 #define   PLANE_WM_BLOCKS_MASK  0x7ff /* skl+: 10 bits, icl+ 11 bits */
6181
6182 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
6183 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
6184 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
6185
6186 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
6187 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
6188 #define _PLANE_WM_BASE(pipe, plane)     \
6189                         _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
6190 #define PLANE_WM(pipe, plane, level)    \
6191                         _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
6192 #define _PLANE_WM_TRANS_1(pipe) \
6193                         _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
6194 #define _PLANE_WM_TRANS_2(pipe) \
6195                         _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
6196 #define PLANE_WM_TRANS(pipe, plane)     \
6197         _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
6198
6199 /* define the Watermark register on Ironlake */
6200 #define WM0_PIPEA_ILK           _MMIO(0x45100)
6201 #define  WM0_PIPE_PLANE_MASK    (0xffff << 16)
6202 #define  WM0_PIPE_PLANE_SHIFT   16
6203 #define  WM0_PIPE_SPRITE_MASK   (0xff << 8)
6204 #define  WM0_PIPE_SPRITE_SHIFT  8
6205 #define  WM0_PIPE_CURSOR_MASK   (0xff)
6206
6207 #define WM0_PIPEB_ILK           _MMIO(0x45104)
6208 #define WM0_PIPEC_IVB           _MMIO(0x45200)
6209 #define WM1_LP_ILK              _MMIO(0x45108)
6210 #define  WM1_LP_SR_EN           (1 << 31)
6211 #define  WM1_LP_LATENCY_SHIFT   24
6212 #define  WM1_LP_LATENCY_MASK    (0x7f << 24)
6213 #define  WM1_LP_FBC_MASK        (0xf << 20)
6214 #define  WM1_LP_FBC_SHIFT       20
6215 #define  WM1_LP_FBC_SHIFT_BDW   19
6216 #define  WM1_LP_SR_MASK         (0x7ff << 8)
6217 #define  WM1_LP_SR_SHIFT        8
6218 #define  WM1_LP_CURSOR_MASK     (0xff)
6219 #define WM2_LP_ILK              _MMIO(0x4510c)
6220 #define  WM2_LP_EN              (1 << 31)
6221 #define WM3_LP_ILK              _MMIO(0x45110)
6222 #define  WM3_LP_EN              (1 << 31)
6223 #define WM1S_LP_ILK             _MMIO(0x45120)
6224 #define WM2S_LP_IVB             _MMIO(0x45124)
6225 #define WM3S_LP_IVB             _MMIO(0x45128)
6226 #define  WM1S_LP_EN             (1 << 31)
6227
6228 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
6229         (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
6230          ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
6231
6232 /* Memory latency timer register */
6233 #define MLTR_ILK                _MMIO(0x11222)
6234 #define  MLTR_WM1_SHIFT         0
6235 #define  MLTR_WM2_SHIFT         8
6236 /* the unit of memory self-refresh latency time is 0.5us */
6237 #define  ILK_SRLT_MASK          0x3f
6238
6239
6240 /* the address where we get all kinds of latency value */
6241 #define SSKPD                   _MMIO(0x5d10)
6242 #define SSKPD_WM_MASK           0x3f
6243 #define SSKPD_WM0_SHIFT         0
6244 #define SSKPD_WM1_SHIFT         8
6245 #define SSKPD_WM2_SHIFT         16
6246 #define SSKPD_WM3_SHIFT         24
6247
6248 /*
6249  * The two pipe frame counter registers are not synchronized, so
6250  * reading a stable value is somewhat tricky. The following code
6251  * should work:
6252  *
6253  *  do {
6254  *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6255  *             PIPE_FRAME_HIGH_SHIFT;
6256  *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
6257  *             PIPE_FRAME_LOW_SHIFT);
6258  *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6259  *             PIPE_FRAME_HIGH_SHIFT);
6260  *  } while (high1 != high2);
6261  *  frame = (high1 << 8) | low1;
6262  */
6263 #define _PIPEAFRAMEHIGH          0x70040
6264 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
6265 #define   PIPE_FRAME_HIGH_SHIFT   0
6266 #define _PIPEAFRAMEPIXEL         0x70044
6267 #define   PIPE_FRAME_LOW_MASK     0xff000000
6268 #define   PIPE_FRAME_LOW_SHIFT    24
6269 #define   PIPE_PIXEL_MASK         0x00ffffff
6270 #define   PIPE_PIXEL_SHIFT        0
6271 /* GM45+ just has to be different */
6272 #define _PIPEA_FRMCOUNT_G4X     0x70040
6273 #define _PIPEA_FLIPCOUNT_G4X    0x70044
6274 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6275 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
6276
6277 /* Cursor A & B regs */
6278 #define _CURACNTR               0x70080
6279 /* Old style CUR*CNTR flags (desktop 8xx) */
6280 #define   CURSOR_ENABLE         0x80000000
6281 #define   CURSOR_GAMMA_ENABLE   0x40000000
6282 #define   CURSOR_STRIDE_SHIFT   28
6283 #define   CURSOR_STRIDE(x)      ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6284 #define   CURSOR_FORMAT_SHIFT   24
6285 #define   CURSOR_FORMAT_MASK    (0x07 << CURSOR_FORMAT_SHIFT)
6286 #define   CURSOR_FORMAT_2C      (0x00 << CURSOR_FORMAT_SHIFT)
6287 #define   CURSOR_FORMAT_3C      (0x01 << CURSOR_FORMAT_SHIFT)
6288 #define   CURSOR_FORMAT_4C      (0x02 << CURSOR_FORMAT_SHIFT)
6289 #define   CURSOR_FORMAT_ARGB    (0x04 << CURSOR_FORMAT_SHIFT)
6290 #define   CURSOR_FORMAT_XRGB    (0x05 << CURSOR_FORMAT_SHIFT)
6291 /* New style CUR*CNTR flags */
6292 #define   MCURSOR_MODE          0x27
6293 #define   MCURSOR_MODE_DISABLE   0x00
6294 #define   MCURSOR_MODE_128_32B_AX 0x02
6295 #define   MCURSOR_MODE_256_32B_AX 0x03
6296 #define   MCURSOR_MODE_64_32B_AX 0x07
6297 #define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6298 #define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6299 #define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
6300 #define   MCURSOR_PIPE_SELECT_MASK      (0x3 << 28)
6301 #define   MCURSOR_PIPE_SELECT_SHIFT     28
6302 #define   MCURSOR_PIPE_SELECT(pipe)     ((pipe) << 28)
6303 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
6304 #define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6305 #define   MCURSOR_ROTATE_180    (1 << 15)
6306 #define   MCURSOR_TRICKLE_FEED_DISABLE  (1 << 14)
6307 #define _CURABASE               0x70084
6308 #define _CURAPOS                0x70088
6309 #define   CURSOR_POS_MASK       0x007FF
6310 #define   CURSOR_POS_SIGN       0x8000
6311 #define   CURSOR_X_SHIFT        0
6312 #define   CURSOR_Y_SHIFT        16
6313 #define CURSIZE                 _MMIO(0x700a0) /* 845/865 */
6314 #define _CUR_FBC_CTL_A          0x700a0 /* ivb+ */
6315 #define   CUR_FBC_CTL_EN        (1 << 31)
6316 #define _CURASURFLIVE           0x700ac /* g4x+ */
6317 #define _CURBCNTR               0x700c0
6318 #define _CURBBASE               0x700c4
6319 #define _CURBPOS                0x700c8
6320
6321 #define _CURBCNTR_IVB           0x71080
6322 #define _CURBBASE_IVB           0x71084
6323 #define _CURBPOS_IVB            0x71088
6324
6325 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6326 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6327 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6328 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6329 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
6330
6331 #define CURSOR_A_OFFSET 0x70080
6332 #define CURSOR_B_OFFSET 0x700c0
6333 #define CHV_CURSOR_C_OFFSET 0x700e0
6334 #define IVB_CURSOR_B_OFFSET 0x71080
6335 #define IVB_CURSOR_C_OFFSET 0x72080
6336 #define TGL_CURSOR_D_OFFSET 0x73080
6337
6338 /* Display A control */
6339 #define _DSPACNTR                               0x70180
6340 #define   DISPLAY_PLANE_ENABLE                  (1 << 31)
6341 #define   DISPLAY_PLANE_DISABLE                 0
6342 #define   DISPPLANE_GAMMA_ENABLE                (1 << 30)
6343 #define   DISPPLANE_GAMMA_DISABLE               0
6344 #define   DISPPLANE_PIXFORMAT_MASK              (0xf << 26)
6345 #define   DISPPLANE_YUV422                      (0x0 << 26)
6346 #define   DISPPLANE_8BPP                        (0x2 << 26)
6347 #define   DISPPLANE_BGRA555                     (0x3 << 26)
6348 #define   DISPPLANE_BGRX555                     (0x4 << 26)
6349 #define   DISPPLANE_BGRX565                     (0x5 << 26)
6350 #define   DISPPLANE_BGRX888                     (0x6 << 26)
6351 #define   DISPPLANE_BGRA888                     (0x7 << 26)
6352 #define   DISPPLANE_RGBX101010                  (0x8 << 26)
6353 #define   DISPPLANE_RGBA101010                  (0x9 << 26)
6354 #define   DISPPLANE_BGRX101010                  (0xa << 26)
6355 #define   DISPPLANE_BGRA101010                  (0xb << 26)
6356 #define   DISPPLANE_RGBX161616                  (0xc << 26)
6357 #define   DISPPLANE_RGBX888                     (0xe << 26)
6358 #define   DISPPLANE_RGBA888                     (0xf << 26)
6359 #define   DISPPLANE_STEREO_ENABLE               (1 << 25)
6360 #define   DISPPLANE_STEREO_DISABLE              0
6361 #define   DISPPLANE_PIPE_CSC_ENABLE             (1 << 24) /* ilk+ */
6362 #define   DISPPLANE_SEL_PIPE_SHIFT              24
6363 #define   DISPPLANE_SEL_PIPE_MASK               (3 << DISPPLANE_SEL_PIPE_SHIFT)
6364 #define   DISPPLANE_SEL_PIPE(pipe)              ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6365 #define   DISPPLANE_SRC_KEY_ENABLE              (1 << 22)
6366 #define   DISPPLANE_SRC_KEY_DISABLE             0
6367 #define   DISPPLANE_LINE_DOUBLE                 (1 << 20)
6368 #define   DISPPLANE_NO_LINE_DOUBLE              0
6369 #define   DISPPLANE_STEREO_POLARITY_FIRST       0
6370 #define   DISPPLANE_STEREO_POLARITY_SECOND      (1 << 18)
6371 #define   DISPPLANE_ALPHA_PREMULTIPLY           (1 << 16) /* CHV pipe B */
6372 #define   DISPPLANE_ROTATE_180                  (1 << 15)
6373 #define   DISPPLANE_TRICKLE_FEED_DISABLE        (1 << 14) /* Ironlake */
6374 #define   DISPPLANE_TILED                       (1 << 10)
6375 #define   DISPPLANE_MIRROR                      (1 << 8) /* CHV pipe B */
6376 #define _DSPAADDR                               0x70184
6377 #define _DSPASTRIDE                             0x70188
6378 #define _DSPAPOS                                0x7018C /* reserved */
6379 #define _DSPASIZE                               0x70190
6380 #define _DSPASURF                               0x7019C /* 965+ only */
6381 #define _DSPATILEOFF                            0x701A4 /* 965+ only */
6382 #define _DSPAOFFSET                             0x701A4 /* HSW */
6383 #define _DSPASURFLIVE                           0x701AC
6384 #define _DSPAGAMC                               0x701E0
6385
6386 #define DSPCNTR(plane)          _MMIO_PIPE2(plane, _DSPACNTR)
6387 #define DSPADDR(plane)          _MMIO_PIPE2(plane, _DSPAADDR)
6388 #define DSPSTRIDE(plane)        _MMIO_PIPE2(plane, _DSPASTRIDE)
6389 #define DSPPOS(plane)           _MMIO_PIPE2(plane, _DSPAPOS)
6390 #define DSPSIZE(plane)          _MMIO_PIPE2(plane, _DSPASIZE)
6391 #define DSPSURF(plane)          _MMIO_PIPE2(plane, _DSPASURF)
6392 #define DSPTILEOFF(plane)       _MMIO_PIPE2(plane, _DSPATILEOFF)
6393 #define DSPLINOFF(plane)        DSPADDR(plane)
6394 #define DSPOFFSET(plane)        _MMIO_PIPE2(plane, _DSPAOFFSET)
6395 #define DSPSURFLIVE(plane)      _MMIO_PIPE2(plane, _DSPASURFLIVE)
6396 #define DSPGAMC(plane, i)       _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
6397
6398 /* CHV pipe B blender and primary plane */
6399 #define _CHV_BLEND_A            0x60a00
6400 #define   CHV_BLEND_LEGACY              (0 << 30)
6401 #define   CHV_BLEND_ANDROID             (1 << 30)
6402 #define   CHV_BLEND_MPO                 (2 << 30)
6403 #define   CHV_BLEND_MASK                (3 << 30)
6404 #define _CHV_CANVAS_A           0x60a04
6405 #define _PRIMPOS_A              0x60a08
6406 #define _PRIMSIZE_A             0x60a0c
6407 #define _PRIMCNSTALPHA_A        0x60a10
6408 #define   PRIM_CONST_ALPHA_ENABLE       (1 << 31)
6409
6410 #define CHV_BLEND(pipe)         _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6411 #define CHV_CANVAS(pipe)        _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6412 #define PRIMPOS(plane)          _MMIO_TRANS2(plane, _PRIMPOS_A)
6413 #define PRIMSIZE(plane)         _MMIO_TRANS2(plane, _PRIMSIZE_A)
6414 #define PRIMCNSTALPHA(plane)    _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6415
6416 /* Display/Sprite base address macros */
6417 #define DISP_BASEADDR_MASK      (0xfffff000)
6418 #define I915_LO_DISPBASE(val)   ((val) & ~DISP_BASEADDR_MASK)
6419 #define I915_HI_DISPBASE(val)   ((val) & DISP_BASEADDR_MASK)
6420
6421 /*
6422  * VBIOS flags
6423  * gen2:
6424  * [00:06] alm,mgm
6425  * [10:16] all
6426  * [30:32] alm,mgm
6427  * gen3+:
6428  * [00:0f] all
6429  * [10:1f] all
6430  * [30:32] all
6431  */
6432 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
6433 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
6434 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
6435 #define SWF_ILK(i)      _MMIO(0x4F000 + (i) * 4)
6436
6437 /* Pipe B */
6438 #define _PIPEBDSL               (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
6439 #define _PIPEBCONF              (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
6440 #define _PIPEBSTAT              (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
6441 #define _PIPEBFRAMEHIGH         0x71040
6442 #define _PIPEBFRAMEPIXEL        0x71044
6443 #define _PIPEB_FRMCOUNT_G4X     (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
6444 #define _PIPEB_FLIPCOUNT_G4X    (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
6445
6446
6447 /* Display B control */
6448 #define _DSPBCNTR               (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6449 #define   DISPPLANE_ALPHA_TRANS_ENABLE          (1 << 15)
6450 #define   DISPPLANE_ALPHA_TRANS_DISABLE         0
6451 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY        0
6452 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY        (1)
6453 #define _DSPBADDR               (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
6454 #define _DSPBSTRIDE             (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
6455 #define _DSPBPOS                (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
6456 #define _DSPBSIZE               (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
6457 #define _DSPBSURF               (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
6458 #define _DSPBTILEOFF            (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6459 #define _DSPBOFFSET             (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6460 #define _DSPBSURFLIVE           (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
6461
6462 /* ICL DSI 0 and 1 */
6463 #define _PIPEDSI0CONF           0x7b008
6464 #define _PIPEDSI1CONF           0x7b808
6465
6466 /* Sprite A control */
6467 #define _DVSACNTR               0x72180
6468 #define   DVS_ENABLE            (1 << 31)
6469 #define   DVS_GAMMA_ENABLE      (1 << 30)
6470 #define   DVS_YUV_RANGE_CORRECTION_DISABLE      (1 << 27)
6471 #define   DVS_PIXFORMAT_MASK    (3 << 25)
6472 #define   DVS_FORMAT_YUV422     (0 << 25)
6473 #define   DVS_FORMAT_RGBX101010 (1 << 25)
6474 #define   DVS_FORMAT_RGBX888    (2 << 25)
6475 #define   DVS_FORMAT_RGBX161616 (3 << 25)
6476 #define   DVS_PIPE_CSC_ENABLE   (1 << 24)
6477 #define   DVS_SOURCE_KEY        (1 << 22)
6478 #define   DVS_RGB_ORDER_XBGR    (1 << 20)
6479 #define   DVS_YUV_FORMAT_BT709  (1 << 18)
6480 #define   DVS_YUV_BYTE_ORDER_MASK (3 << 16)
6481 #define   DVS_YUV_ORDER_YUYV    (0 << 16)
6482 #define   DVS_YUV_ORDER_UYVY    (1 << 16)
6483 #define   DVS_YUV_ORDER_YVYU    (2 << 16)
6484 #define   DVS_YUV_ORDER_VYUY    (3 << 16)
6485 #define   DVS_ROTATE_180        (1 << 15)
6486 #define   DVS_DEST_KEY          (1 << 2)
6487 #define   DVS_TRICKLE_FEED_DISABLE (1 << 14)
6488 #define   DVS_TILED             (1 << 10)
6489 #define _DVSALINOFF             0x72184
6490 #define _DVSASTRIDE             0x72188
6491 #define _DVSAPOS                0x7218c
6492 #define _DVSASIZE               0x72190
6493 #define _DVSAKEYVAL             0x72194
6494 #define _DVSAKEYMSK             0x72198
6495 #define _DVSASURF               0x7219c
6496 #define _DVSAKEYMAXVAL          0x721a0
6497 #define _DVSATILEOFF            0x721a4
6498 #define _DVSASURFLIVE           0x721ac
6499 #define _DVSAGAMC_G4X           0x721e0 /* g4x */
6500 #define _DVSASCALE              0x72204
6501 #define   DVS_SCALE_ENABLE      (1 << 31)
6502 #define   DVS_FILTER_MASK       (3 << 29)
6503 #define   DVS_FILTER_MEDIUM     (0 << 29)
6504 #define   DVS_FILTER_ENHANCING  (1 << 29)
6505 #define   DVS_FILTER_SOFTENING  (2 << 29)
6506 #define   DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6507 #define   DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
6508 #define _DVSAGAMC_ILK           0x72300 /* ilk/snb */
6509 #define _DVSAGAMCMAX_ILK        0x72340 /* ilk/snb */
6510
6511 #define _DVSBCNTR               0x73180
6512 #define _DVSBLINOFF             0x73184
6513 #define _DVSBSTRIDE             0x73188
6514 #define _DVSBPOS                0x7318c
6515 #define _DVSBSIZE               0x73190
6516 #define _DVSBKEYVAL             0x73194
6517 #define _DVSBKEYMSK             0x73198
6518 #define _DVSBSURF               0x7319c
6519 #define _DVSBKEYMAXVAL          0x731a0
6520 #define _DVSBTILEOFF            0x731a4
6521 #define _DVSBSURFLIVE           0x731ac
6522 #define _DVSBGAMC_G4X           0x731e0 /* g4x */
6523 #define _DVSBSCALE              0x73204
6524 #define _DVSBGAMC_ILK           0x73300 /* ilk/snb */
6525 #define _DVSBGAMCMAX_ILK        0x73340 /* ilk/snb */
6526
6527 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6528 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6529 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6530 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6531 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6532 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6533 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6534 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6535 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6536 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6537 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6538 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6539 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
6540 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
6541 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
6542
6543 #define _SPRA_CTL               0x70280
6544 #define   SPRITE_ENABLE                 (1 << 31)
6545 #define   SPRITE_GAMMA_ENABLE           (1 << 30)
6546 #define   SPRITE_YUV_RANGE_CORRECTION_DISABLE   (1 << 28)
6547 #define   SPRITE_PIXFORMAT_MASK         (7 << 25)
6548 #define   SPRITE_FORMAT_YUV422          (0 << 25)
6549 #define   SPRITE_FORMAT_RGBX101010      (1 << 25)
6550 #define   SPRITE_FORMAT_RGBX888         (2 << 25)
6551 #define   SPRITE_FORMAT_RGBX161616      (3 << 25)
6552 #define   SPRITE_FORMAT_YUV444          (4 << 25)
6553 #define   SPRITE_FORMAT_XR_BGR101010    (5 << 25) /* Extended range */
6554 #define   SPRITE_PIPE_CSC_ENABLE        (1 << 24)
6555 #define   SPRITE_SOURCE_KEY             (1 << 22)
6556 #define   SPRITE_RGB_ORDER_RGBX         (1 << 20) /* only for 888 and 161616 */
6557 #define   SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
6558 #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709    (1 << 18) /* 0 is BT601 */
6559 #define   SPRITE_YUV_BYTE_ORDER_MASK    (3 << 16)
6560 #define   SPRITE_YUV_ORDER_YUYV         (0 << 16)
6561 #define   SPRITE_YUV_ORDER_UYVY         (1 << 16)
6562 #define   SPRITE_YUV_ORDER_YVYU         (2 << 16)
6563 #define   SPRITE_YUV_ORDER_VYUY         (3 << 16)
6564 #define   SPRITE_ROTATE_180             (1 << 15)
6565 #define   SPRITE_TRICKLE_FEED_DISABLE   (1 << 14)
6566 #define   SPRITE_INT_GAMMA_DISABLE      (1 << 13)
6567 #define   SPRITE_TILED                  (1 << 10)
6568 #define   SPRITE_DEST_KEY               (1 << 2)
6569 #define _SPRA_LINOFF            0x70284
6570 #define _SPRA_STRIDE            0x70288
6571 #define _SPRA_POS               0x7028c
6572 #define _SPRA_SIZE              0x70290
6573 #define _SPRA_KEYVAL            0x70294
6574 #define _SPRA_KEYMSK            0x70298
6575 #define _SPRA_SURF              0x7029c
6576 #define _SPRA_KEYMAX            0x702a0
6577 #define _SPRA_TILEOFF           0x702a4
6578 #define _SPRA_OFFSET            0x702a4
6579 #define _SPRA_SURFLIVE          0x702ac
6580 #define _SPRA_SCALE             0x70304
6581 #define   SPRITE_SCALE_ENABLE   (1 << 31)
6582 #define   SPRITE_FILTER_MASK    (3 << 29)
6583 #define   SPRITE_FILTER_MEDIUM  (0 << 29)
6584 #define   SPRITE_FILTER_ENHANCING       (1 << 29)
6585 #define   SPRITE_FILTER_SOFTENING       (2 << 29)
6586 #define   SPRITE_VERTICAL_OFFSET_HALF   (1 << 28) /* must be enabled below */
6587 #define   SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
6588 #define _SPRA_GAMC              0x70400
6589 #define _SPRA_GAMC16            0x70440
6590 #define _SPRA_GAMC17            0x7044c
6591
6592 #define _SPRB_CTL               0x71280
6593 #define _SPRB_LINOFF            0x71284
6594 #define _SPRB_STRIDE            0x71288
6595 #define _SPRB_POS               0x7128c
6596 #define _SPRB_SIZE              0x71290
6597 #define _SPRB_KEYVAL            0x71294
6598 #define _SPRB_KEYMSK            0x71298
6599 #define _SPRB_SURF              0x7129c
6600 #define _SPRB_KEYMAX            0x712a0
6601 #define _SPRB_TILEOFF           0x712a4
6602 #define _SPRB_OFFSET            0x712a4
6603 #define _SPRB_SURFLIVE          0x712ac
6604 #define _SPRB_SCALE             0x71304
6605 #define _SPRB_GAMC              0x71400
6606 #define _SPRB_GAMC16            0x71440
6607 #define _SPRB_GAMC17            0x7144c
6608
6609 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6610 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6611 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6612 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6613 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6614 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6615 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6616 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6617 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6618 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6619 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6620 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6621 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
6622 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
6623 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
6624 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6625
6626 #define _SPACNTR                (VLV_DISPLAY_BASE + 0x72180)
6627 #define   SP_ENABLE                     (1 << 31)
6628 #define   SP_GAMMA_ENABLE               (1 << 30)
6629 #define   SP_PIXFORMAT_MASK             (0xf << 26)
6630 #define   SP_FORMAT_YUV422              (0x0 << 26)
6631 #define   SP_FORMAT_8BPP                (0x2 << 26)
6632 #define   SP_FORMAT_BGR565              (0x5 << 26)
6633 #define   SP_FORMAT_BGRX8888            (0x6 << 26)
6634 #define   SP_FORMAT_BGRA8888            (0x7 << 26)
6635 #define   SP_FORMAT_RGBX1010102         (0x8 << 26)
6636 #define   SP_FORMAT_RGBA1010102         (0x9 << 26)
6637 #define   SP_FORMAT_BGRX1010102         (0xa << 26) /* CHV pipe B */
6638 #define   SP_FORMAT_BGRA1010102         (0xb << 26) /* CHV pipe B */
6639 #define   SP_FORMAT_RGBX8888            (0xe << 26)
6640 #define   SP_FORMAT_RGBA8888            (0xf << 26)
6641 #define   SP_ALPHA_PREMULTIPLY          (1 << 23) /* CHV pipe B */
6642 #define   SP_SOURCE_KEY                 (1 << 22)
6643 #define   SP_YUV_FORMAT_BT709           (1 << 18)
6644 #define   SP_YUV_BYTE_ORDER_MASK        (3 << 16)
6645 #define   SP_YUV_ORDER_YUYV             (0 << 16)
6646 #define   SP_YUV_ORDER_UYVY             (1 << 16)
6647 #define   SP_YUV_ORDER_YVYU             (2 << 16)
6648 #define   SP_YUV_ORDER_VYUY             (3 << 16)
6649 #define   SP_ROTATE_180                 (1 << 15)
6650 #define   SP_TILED                      (1 << 10)
6651 #define   SP_MIRROR                     (1 << 8) /* CHV pipe B */
6652 #define _SPALINOFF              (VLV_DISPLAY_BASE + 0x72184)
6653 #define _SPASTRIDE              (VLV_DISPLAY_BASE + 0x72188)
6654 #define _SPAPOS                 (VLV_DISPLAY_BASE + 0x7218c)
6655 #define _SPASIZE                (VLV_DISPLAY_BASE + 0x72190)
6656 #define _SPAKEYMINVAL           (VLV_DISPLAY_BASE + 0x72194)
6657 #define _SPAKEYMSK              (VLV_DISPLAY_BASE + 0x72198)
6658 #define _SPASURF                (VLV_DISPLAY_BASE + 0x7219c)
6659 #define _SPAKEYMAXVAL           (VLV_DISPLAY_BASE + 0x721a0)
6660 #define _SPATILEOFF             (VLV_DISPLAY_BASE + 0x721a4)
6661 #define _SPACONSTALPHA          (VLV_DISPLAY_BASE + 0x721a8)
6662 #define   SP_CONST_ALPHA_ENABLE         (1 << 31)
6663 #define _SPACLRC0               (VLV_DISPLAY_BASE + 0x721d0)
6664 #define   SP_CONTRAST(x)                ((x) << 18) /* u3.6 */
6665 #define   SP_BRIGHTNESS(x)              ((x) & 0xff) /* s8 */
6666 #define _SPACLRC1               (VLV_DISPLAY_BASE + 0x721d4)
6667 #define   SP_SH_SIN(x)                  (((x) & 0x7ff) << 16) /* s4.7 */
6668 #define   SP_SH_COS(x)                  (x) /* u3.7 */
6669 #define _SPAGAMC                (VLV_DISPLAY_BASE + 0x721e0)
6670
6671 #define _SPBCNTR                (VLV_DISPLAY_BASE + 0x72280)
6672 #define _SPBLINOFF              (VLV_DISPLAY_BASE + 0x72284)
6673 #define _SPBSTRIDE              (VLV_DISPLAY_BASE + 0x72288)
6674 #define _SPBPOS                 (VLV_DISPLAY_BASE + 0x7228c)
6675 #define _SPBSIZE                (VLV_DISPLAY_BASE + 0x72290)
6676 #define _SPBKEYMINVAL           (VLV_DISPLAY_BASE + 0x72294)
6677 #define _SPBKEYMSK              (VLV_DISPLAY_BASE + 0x72298)
6678 #define _SPBSURF                (VLV_DISPLAY_BASE + 0x7229c)
6679 #define _SPBKEYMAXVAL           (VLV_DISPLAY_BASE + 0x722a0)
6680 #define _SPBTILEOFF             (VLV_DISPLAY_BASE + 0x722a4)
6681 #define _SPBCONSTALPHA          (VLV_DISPLAY_BASE + 0x722a8)
6682 #define _SPBCLRC0               (VLV_DISPLAY_BASE + 0x722d0)
6683 #define _SPBCLRC1               (VLV_DISPLAY_BASE + 0x722d4)
6684 #define _SPBGAMC                (VLV_DISPLAY_BASE + 0x722e0)
6685
6686 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6687         _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6688 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6689         _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
6690
6691 #define SPCNTR(pipe, plane_id)          _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6692 #define SPLINOFF(pipe, plane_id)        _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6693 #define SPSTRIDE(pipe, plane_id)        _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6694 #define SPPOS(pipe, plane_id)           _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6695 #define SPSIZE(pipe, plane_id)          _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6696 #define SPKEYMINVAL(pipe, plane_id)     _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6697 #define SPKEYMSK(pipe, plane_id)        _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6698 #define SPSURF(pipe, plane_id)          _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6699 #define SPKEYMAXVAL(pipe, plane_id)     _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6700 #define SPTILEOFF(pipe, plane_id)       _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6701 #define SPCONSTALPHA(pipe, plane_id)    _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6702 #define SPCLRC0(pipe, plane_id)         _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
6703 #define SPCLRC1(pipe, plane_id)         _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
6704 #define SPGAMC(pipe, plane_id, i)       _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
6705
6706 /*
6707  * CHV pipe B sprite CSC
6708  *
6709  * |cr|   |c0 c1 c2|   |cr + cr_ioff|   |cr_ooff|
6710  * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6711  * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
6712  */
6713 #define _MMIO_CHV_SPCSC(plane_id, reg) \
6714         _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6715
6716 #define SPCSCYGOFF(plane_id)    _MMIO_CHV_SPCSC(plane_id, 0x6d900)
6717 #define SPCSCCBOFF(plane_id)    _MMIO_CHV_SPCSC(plane_id, 0x6d904)
6718 #define SPCSCCROFF(plane_id)    _MMIO_CHV_SPCSC(plane_id, 0x6d908)
6719 #define  SPCSC_OOFF(x)          (((x) & 0x7ff) << 16) /* s11 */
6720 #define  SPCSC_IOFF(x)          (((x) & 0x7ff) << 0) /* s11 */
6721
6722 #define SPCSCC01(plane_id)      _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6723 #define SPCSCC23(plane_id)      _MMIO_CHV_SPCSC(plane_id, 0x6d910)
6724 #define SPCSCC45(plane_id)      _MMIO_CHV_SPCSC(plane_id, 0x6d914)
6725 #define SPCSCC67(plane_id)      _MMIO_CHV_SPCSC(plane_id, 0x6d918)
6726 #define SPCSCC8(plane_id)       _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6727 #define  SPCSC_C1(x)            (((x) & 0x7fff) << 16) /* s3.12 */
6728 #define  SPCSC_C0(x)            (((x) & 0x7fff) << 0) /* s3.12 */
6729
6730 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
6731 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
6732 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
6733 #define  SPCSC_IMAX(x)          (((x) & 0x7ff) << 16) /* s11 */
6734 #define  SPCSC_IMIN(x)          (((x) & 0x7ff) << 0) /* s11 */
6735
6736 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6737 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
6738 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
6739 #define  SPCSC_OMAX(x)          ((x) << 16) /* u10 */
6740 #define  SPCSC_OMIN(x)          ((x) << 0) /* u10 */
6741
6742 /* Skylake plane registers */
6743
6744 #define _PLANE_CTL_1_A                          0x70180
6745 #define _PLANE_CTL_2_A                          0x70280
6746 #define _PLANE_CTL_3_A                          0x70380
6747 #define   PLANE_CTL_ENABLE                      (1 << 31)
6748 #define   PLANE_CTL_PIPE_GAMMA_ENABLE           (1 << 30)   /* Pre-GLK */
6749 #define   PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE        (1 << 28)
6750 /*
6751  * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6752  * expanded to include bit 23 as well. However, the shift-24 based values
6753  * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6754  */
6755 #define   PLANE_CTL_FORMAT_MASK                 (0xf << 24)
6756 #define   PLANE_CTL_FORMAT_YUV422               (0 << 24)
6757 #define   PLANE_CTL_FORMAT_NV12                 (1 << 24)
6758 #define   PLANE_CTL_FORMAT_XRGB_2101010         (2 << 24)
6759 #define   PLANE_CTL_FORMAT_P010                 (3 << 24)
6760 #define   PLANE_CTL_FORMAT_XRGB_8888            (4 << 24)
6761 #define   PLANE_CTL_FORMAT_P012                 (5 << 24)
6762 #define   PLANE_CTL_FORMAT_XRGB_16161616F       (6 << 24)
6763 #define   PLANE_CTL_FORMAT_P016                 (7 << 24)
6764 #define   PLANE_CTL_FORMAT_AYUV                 (8 << 24)
6765 #define   PLANE_CTL_FORMAT_INDEXED              (12 << 24)
6766 #define   PLANE_CTL_FORMAT_RGB_565              (14 << 24)
6767 #define   ICL_PLANE_CTL_FORMAT_MASK             (0x1f << 23)
6768 #define   PLANE_CTL_PIPE_CSC_ENABLE             (1 << 23) /* Pre-GLK */
6769 #define   PLANE_CTL_FORMAT_Y210                 (1 << 23)
6770 #define   PLANE_CTL_FORMAT_Y212                 (3 << 23)
6771 #define   PLANE_CTL_FORMAT_Y216                 (5 << 23)
6772 #define   PLANE_CTL_FORMAT_Y410                 (7 << 23)
6773 #define   PLANE_CTL_FORMAT_Y412                 (9 << 23)
6774 #define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)
6775 #define   PLANE_CTL_KEY_ENABLE_MASK             (0x3 << 21)
6776 #define   PLANE_CTL_KEY_ENABLE_SOURCE           (1 << 21)
6777 #define   PLANE_CTL_KEY_ENABLE_DESTINATION      (2 << 21)
6778 #define   PLANE_CTL_ORDER_BGRX                  (0 << 20)
6779 #define   PLANE_CTL_ORDER_RGBX                  (1 << 20)
6780 #define   PLANE_CTL_YUV420_Y_PLANE              (1 << 19)
6781 #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
6782 #define   PLANE_CTL_YUV422_ORDER_MASK           (0x3 << 16)
6783 #define   PLANE_CTL_YUV422_YUYV                 (0 << 16)
6784 #define   PLANE_CTL_YUV422_UYVY                 (1 << 16)
6785 #define   PLANE_CTL_YUV422_YVYU                 (2 << 16)
6786 #define   PLANE_CTL_YUV422_VYUY                 (3 << 16)
6787 #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
6788 #define   PLANE_CTL_TRICKLE_FEED_DISABLE        (1 << 14)
6789 #define   PLANE_CTL_CLEAR_COLOR_DISABLE         (1 << 13) /* TGL+ */
6790 #define   PLANE_CTL_PLANE_GAMMA_DISABLE         (1 << 13) /* Pre-GLK */
6791 #define   PLANE_CTL_TILED_MASK                  (0x7 << 10)
6792 #define   PLANE_CTL_TILED_LINEAR                (0 << 10)
6793 #define   PLANE_CTL_TILED_X                     (1 << 10)
6794 #define   PLANE_CTL_TILED_Y                     (4 << 10)
6795 #define   PLANE_CTL_TILED_YF                    (5 << 10)
6796 #define   PLANE_CTL_FLIP_HORIZONTAL             (1 << 8)
6797 #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE  (1 << 4) /* TGL+ */
6798 #define   PLANE_CTL_ALPHA_MASK                  (0x3 << 4) /* Pre-GLK */
6799 #define   PLANE_CTL_ALPHA_DISABLE               (0 << 4)
6800 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY        (2 << 4)
6801 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY        (3 << 4)
6802 #define   PLANE_CTL_ROTATE_MASK                 0x3
6803 #define   PLANE_CTL_ROTATE_0                    0x0
6804 #define   PLANE_CTL_ROTATE_90                   0x1
6805 #define   PLANE_CTL_ROTATE_180                  0x2
6806 #define   PLANE_CTL_ROTATE_270                  0x3
6807 #define _PLANE_STRIDE_1_A                       0x70188
6808 #define _PLANE_STRIDE_2_A                       0x70288
6809 #define _PLANE_STRIDE_3_A                       0x70388
6810 #define _PLANE_POS_1_A                          0x7018c
6811 #define _PLANE_POS_2_A                          0x7028c
6812 #define _PLANE_POS_3_A                          0x7038c
6813 #define _PLANE_SIZE_1_A                         0x70190
6814 #define _PLANE_SIZE_2_A                         0x70290
6815 #define _PLANE_SIZE_3_A                         0x70390
6816 #define _PLANE_SURF_1_A                         0x7019c
6817 #define _PLANE_SURF_2_A                         0x7029c
6818 #define _PLANE_SURF_3_A                         0x7039c
6819 #define _PLANE_OFFSET_1_A                       0x701a4
6820 #define _PLANE_OFFSET_2_A                       0x702a4
6821 #define _PLANE_OFFSET_3_A                       0x703a4
6822 #define _PLANE_KEYVAL_1_A                       0x70194
6823 #define _PLANE_KEYVAL_2_A                       0x70294
6824 #define _PLANE_KEYMSK_1_A                       0x70198
6825 #define _PLANE_KEYMSK_2_A                       0x70298
6826 #define  PLANE_KEYMSK_ALPHA_ENABLE              (1 << 31)
6827 #define _PLANE_KEYMAX_1_A                       0x701a0
6828 #define _PLANE_KEYMAX_2_A                       0x702a0
6829 #define  PLANE_KEYMAX_ALPHA(a)                  ((a) << 24)
6830 #define _PLANE_AUX_DIST_1_A                     0x701c0
6831 #define _PLANE_AUX_DIST_2_A                     0x702c0
6832 #define _PLANE_AUX_OFFSET_1_A                   0x701c4
6833 #define _PLANE_AUX_OFFSET_2_A                   0x702c4
6834 #define _PLANE_CUS_CTL_1_A                      0x701c8
6835 #define _PLANE_CUS_CTL_2_A                      0x702c8
6836 #define  PLANE_CUS_ENABLE                       (1 << 31)
6837 #define  PLANE_CUS_PLANE_6                      (0 << 30)
6838 #define  PLANE_CUS_PLANE_7                      (1 << 30)
6839 #define  PLANE_CUS_HPHASE_SIGN_NEGATIVE         (1 << 19)
6840 #define  PLANE_CUS_HPHASE_0                     (0 << 16)
6841 #define  PLANE_CUS_HPHASE_0_25                  (1 << 16)
6842 #define  PLANE_CUS_HPHASE_0_5                   (2 << 16)
6843 #define  PLANE_CUS_VPHASE_SIGN_NEGATIVE         (1 << 15)
6844 #define  PLANE_CUS_VPHASE_0                     (0 << 12)
6845 #define  PLANE_CUS_VPHASE_0_25                  (1 << 12)
6846 #define  PLANE_CUS_VPHASE_0_5                   (2 << 12)
6847 #define _PLANE_COLOR_CTL_1_A                    0x701CC /* GLK+ */
6848 #define _PLANE_COLOR_CTL_2_A                    0x702CC /* GLK+ */
6849 #define _PLANE_COLOR_CTL_3_A                    0x703CC /* GLK+ */
6850 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE         (1 << 30) /* Pre-ICL */
6851 #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE      (1 << 28)
6852 #define   PLANE_COLOR_INPUT_CSC_ENABLE          (1 << 20) /* ICL+ */
6853 #define   PLANE_COLOR_PIPE_CSC_ENABLE           (1 << 23) /* Pre-ICL */
6854 #define   PLANE_COLOR_CSC_MODE_BYPASS                   (0 << 17)
6855 #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709         (1 << 17)
6856 #define   PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709         (2 << 17)
6857 #define   PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020       (3 << 17)
6858 #define   PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020        (4 << 17)
6859 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE       (1 << 13)
6860 #define   PLANE_COLOR_ALPHA_MASK                (0x3 << 4)
6861 #define   PLANE_COLOR_ALPHA_DISABLE             (0 << 4)
6862 #define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY      (2 << 4)
6863 #define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY      (3 << 4)
6864 #define _PLANE_BUF_CFG_1_A                      0x7027c
6865 #define _PLANE_BUF_CFG_2_A                      0x7037c
6866 #define _PLANE_NV12_BUF_CFG_1_A         0x70278
6867 #define _PLANE_NV12_BUF_CFG_2_A         0x70378
6868
6869 /* Input CSC Register Definitions */
6870 #define _PLANE_INPUT_CSC_RY_GY_1_A      0x701E0
6871 #define _PLANE_INPUT_CSC_RY_GY_2_A      0x702E0
6872
6873 #define _PLANE_INPUT_CSC_RY_GY_1_B      0x711E0
6874 #define _PLANE_INPUT_CSC_RY_GY_2_B      0x712E0
6875
6876 #define _PLANE_INPUT_CSC_RY_GY_1(pipe)  \
6877         _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
6878              _PLANE_INPUT_CSC_RY_GY_1_B)
6879 #define _PLANE_INPUT_CSC_RY_GY_2(pipe)  \
6880         _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
6881              _PLANE_INPUT_CSC_RY_GY_2_B)
6882
6883 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index)       \
6884         _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
6885                     _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
6886
6887 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A          0x701F8
6888 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A          0x702F8
6889
6890 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B          0x711F8
6891 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B          0x712F8
6892
6893 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe)      \
6894         _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
6895              _PLANE_INPUT_CSC_PREOFF_HI_1_B)
6896 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe)      \
6897         _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
6898              _PLANE_INPUT_CSC_PREOFF_HI_2_B)
6899 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index)      \
6900         _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
6901                     _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
6902
6903 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A         0x70204
6904 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A         0x70304
6905
6906 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B         0x71204
6907 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B         0x71304
6908
6909 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)     \
6910         _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
6911              _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
6912 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)     \
6913         _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
6914              _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
6915 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)     \
6916         _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
6917                     _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
6918
6919 #define _PLANE_CTL_1_B                          0x71180
6920 #define _PLANE_CTL_2_B                          0x71280
6921 #define _PLANE_CTL_3_B                          0x71380
6922 #define _PLANE_CTL_1(pipe)      _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6923 #define _PLANE_CTL_2(pipe)      _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6924 #define _PLANE_CTL_3(pipe)      _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6925 #define PLANE_CTL(pipe, plane)  \
6926         _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
6927
6928 #define _PLANE_STRIDE_1_B                       0x71188
6929 #define _PLANE_STRIDE_2_B                       0x71288
6930 #define _PLANE_STRIDE_3_B                       0x71388
6931 #define _PLANE_STRIDE_1(pipe)   \
6932         _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6933 #define _PLANE_STRIDE_2(pipe)   \
6934         _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6935 #define _PLANE_STRIDE_3(pipe)   \
6936         _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6937 #define PLANE_STRIDE(pipe, plane)       \
6938         _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
6939
6940 #define _PLANE_POS_1_B                          0x7118c
6941 #define _PLANE_POS_2_B                          0x7128c
6942 #define _PLANE_POS_3_B                          0x7138c
6943 #define _PLANE_POS_1(pipe)      _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6944 #define _PLANE_POS_2(pipe)      _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6945 #define _PLANE_POS_3(pipe)      _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6946 #define PLANE_POS(pipe, plane)  \
6947         _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
6948
6949 #define _PLANE_SIZE_1_B                         0x71190
6950 #define _PLANE_SIZE_2_B                         0x71290
6951 #define _PLANE_SIZE_3_B                         0x71390
6952 #define _PLANE_SIZE_1(pipe)     _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6953 #define _PLANE_SIZE_2(pipe)     _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6954 #define _PLANE_SIZE_3(pipe)     _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6955 #define PLANE_SIZE(pipe, plane) \
6956         _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
6957
6958 #define _PLANE_SURF_1_B                         0x7119c
6959 #define _PLANE_SURF_2_B                         0x7129c
6960 #define _PLANE_SURF_3_B                         0x7139c
6961 #define _PLANE_SURF_1(pipe)     _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6962 #define _PLANE_SURF_2(pipe)     _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6963 #define _PLANE_SURF_3(pipe)     _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6964 #define PLANE_SURF(pipe, plane) \
6965         _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
6966
6967 #define _PLANE_OFFSET_1_B                       0x711a4
6968 #define _PLANE_OFFSET_2_B                       0x712a4
6969 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6970 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6971 #define PLANE_OFFSET(pipe, plane)       \
6972         _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
6973
6974 #define _PLANE_KEYVAL_1_B                       0x71194
6975 #define _PLANE_KEYVAL_2_B                       0x71294
6976 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6977 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6978 #define PLANE_KEYVAL(pipe, plane)       \
6979         _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
6980
6981 #define _PLANE_KEYMSK_1_B                       0x71198
6982 #define _PLANE_KEYMSK_2_B                       0x71298
6983 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6984 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6985 #define PLANE_KEYMSK(pipe, plane)       \
6986         _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
6987
6988 #define _PLANE_KEYMAX_1_B                       0x711a0
6989 #define _PLANE_KEYMAX_2_B                       0x712a0
6990 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6991 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6992 #define PLANE_KEYMAX(pipe, plane)       \
6993         _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
6994
6995 #define _PLANE_BUF_CFG_1_B                      0x7127c
6996 #define _PLANE_BUF_CFG_2_B                      0x7137c
6997 #define  DDB_ENTRY_MASK                         0x7FF /* skl+: 10 bits, icl+ 11 bits */
6998 #define  DDB_ENTRY_END_SHIFT                    16
6999 #define _PLANE_BUF_CFG_1(pipe)  \
7000         _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
7001 #define _PLANE_BUF_CFG_2(pipe)  \
7002         _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
7003 #define PLANE_BUF_CFG(pipe, plane)      \
7004         _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
7005
7006 #define _PLANE_NV12_BUF_CFG_1_B         0x71278
7007 #define _PLANE_NV12_BUF_CFG_2_B         0x71378
7008 #define _PLANE_NV12_BUF_CFG_1(pipe)     \
7009         _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
7010 #define _PLANE_NV12_BUF_CFG_2(pipe)     \
7011         _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
7012 #define PLANE_NV12_BUF_CFG(pipe, plane) \
7013         _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
7014
7015 #define _PLANE_AUX_DIST_1_B             0x711c0
7016 #define _PLANE_AUX_DIST_2_B             0x712c0
7017 #define _PLANE_AUX_DIST_1(pipe) \
7018                         _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
7019 #define _PLANE_AUX_DIST_2(pipe) \
7020                         _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
7021 #define PLANE_AUX_DIST(pipe, plane)     \
7022         _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
7023
7024 #define _PLANE_AUX_OFFSET_1_B           0x711c4
7025 #define _PLANE_AUX_OFFSET_2_B           0x712c4
7026 #define _PLANE_AUX_OFFSET_1(pipe)       \
7027                 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
7028 #define _PLANE_AUX_OFFSET_2(pipe)       \
7029                 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
7030 #define PLANE_AUX_OFFSET(pipe, plane)   \
7031         _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
7032
7033 #define _PLANE_CUS_CTL_1_B              0x711c8
7034 #define _PLANE_CUS_CTL_2_B              0x712c8
7035 #define _PLANE_CUS_CTL_1(pipe)       \
7036                 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
7037 #define _PLANE_CUS_CTL_2(pipe)       \
7038                 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
7039 #define PLANE_CUS_CTL(pipe, plane)   \
7040         _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
7041
7042 #define _PLANE_COLOR_CTL_1_B                    0x711CC
7043 #define _PLANE_COLOR_CTL_2_B                    0x712CC
7044 #define _PLANE_COLOR_CTL_3_B                    0x713CC
7045 #define _PLANE_COLOR_CTL_1(pipe)        \
7046         _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
7047 #define _PLANE_COLOR_CTL_2(pipe)        \
7048         _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
7049 #define PLANE_COLOR_CTL(pipe, plane)    \
7050         _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
7051
7052 #/* SKL new cursor registers */
7053 #define _CUR_BUF_CFG_A                          0x7017c
7054 #define _CUR_BUF_CFG_B                          0x7117c
7055 #define CUR_BUF_CFG(pipe)       _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
7056
7057 /* VBIOS regs */
7058 #define VGACNTRL                _MMIO(0x71400)
7059 # define VGA_DISP_DISABLE                       (1 << 31)
7060 # define VGA_2X_MODE                            (1 << 30)
7061 # define VGA_PIPE_B_SELECT                      (1 << 29)
7062
7063 #define VLV_VGACNTRL            _MMIO(VLV_DISPLAY_BASE + 0x71400)
7064
7065 /* Ironlake */
7066
7067 #define CPU_VGACNTRL    _MMIO(0x41000)
7068
7069 #define DIGITAL_PORT_HOTPLUG_CNTRL      _MMIO(0x44030)
7070 #define  DIGITAL_PORTA_HOTPLUG_ENABLE           (1 << 4)
7071 #define  DIGITAL_PORTA_PULSE_DURATION_2ms       (0 << 2) /* pre-HSW */
7072 #define  DIGITAL_PORTA_PULSE_DURATION_4_5ms     (1 << 2) /* pre-HSW */
7073 #define  DIGITAL_PORTA_PULSE_DURATION_6ms       (2 << 2) /* pre-HSW */
7074 #define  DIGITAL_PORTA_PULSE_DURATION_100ms     (3 << 2) /* pre-HSW */
7075 #define  DIGITAL_PORTA_PULSE_DURATION_MASK      (3 << 2) /* pre-HSW */
7076 #define  DIGITAL_PORTA_HOTPLUG_STATUS_MASK      (3 << 0)
7077 #define  DIGITAL_PORTA_HOTPLUG_NO_DETECT        (0 << 0)
7078 #define  DIGITAL_PORTA_HOTPLUG_SHORT_DETECT     (1 << 0)
7079 #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT      (2 << 0)
7080
7081 /* refresh rate hardware control */
7082 #define RR_HW_CTL       _MMIO(0x45300)
7083 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
7084 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
7085
7086 #define FDI_PLL_BIOS_0  _MMIO(0x46000)
7087 #define  FDI_PLL_FB_CLOCK_MASK  0xff
7088 #define FDI_PLL_BIOS_1  _MMIO(0x46004)
7089 #define FDI_PLL_BIOS_2  _MMIO(0x46008)
7090 #define DISPLAY_PORT_PLL_BIOS_0         _MMIO(0x4600c)
7091 #define DISPLAY_PORT_PLL_BIOS_1         _MMIO(0x46010)
7092 #define DISPLAY_PORT_PLL_BIOS_2         _MMIO(0x46014)
7093
7094 #define PCH_3DCGDIS0            _MMIO(0x46020)
7095 # define MARIUNIT_CLOCK_GATE_DISABLE            (1 << 18)
7096 # define SVSMUNIT_CLOCK_GATE_DISABLE            (1 << 1)
7097
7098 #define PCH_3DCGDIS1            _MMIO(0x46024)
7099 # define VFMUNIT_CLOCK_GATE_DISABLE             (1 << 11)
7100
7101 #define FDI_PLL_FREQ_CTL        _MMIO(0x46030)
7102 #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1 << 24)
7103 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
7104 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
7105
7106
7107 #define _PIPEA_DATA_M1          0x60030
7108 #define  PIPE_DATA_M1_OFFSET    0
7109 #define _PIPEA_DATA_N1          0x60034
7110 #define  PIPE_DATA_N1_OFFSET    0
7111
7112 #define _PIPEA_DATA_M2          0x60038
7113 #define  PIPE_DATA_M2_OFFSET    0
7114 #define _PIPEA_DATA_N2          0x6003c
7115 #define  PIPE_DATA_N2_OFFSET    0
7116
7117 #define _PIPEA_LINK_M1          0x60040
7118 #define  PIPE_LINK_M1_OFFSET    0
7119 #define _PIPEA_LINK_N1          0x60044
7120 #define  PIPE_LINK_N1_OFFSET    0
7121
7122 #define _PIPEA_LINK_M2          0x60048
7123 #define  PIPE_LINK_M2_OFFSET    0
7124 #define _PIPEA_LINK_N2          0x6004c
7125 #define  PIPE_LINK_N2_OFFSET    0
7126
7127 /* PIPEB timing regs are same start from 0x61000 */
7128
7129 #define _PIPEB_DATA_M1          0x61030
7130 #define _PIPEB_DATA_N1          0x61034
7131 #define _PIPEB_DATA_M2          0x61038
7132 #define _PIPEB_DATA_N2          0x6103c
7133 #define _PIPEB_LINK_M1          0x61040
7134 #define _PIPEB_LINK_N1          0x61044
7135 #define _PIPEB_LINK_M2          0x61048
7136 #define _PIPEB_LINK_N2          0x6104c
7137
7138 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
7139 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
7140 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
7141 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
7142 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
7143 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
7144 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
7145 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
7146
7147 /* CPU panel fitter */
7148 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
7149 #define _PFA_CTL_1               0x68080
7150 #define _PFB_CTL_1               0x68880
7151 #define  PF_ENABLE              (1 << 31)
7152 #define  PF_PIPE_SEL_MASK_IVB   (3 << 29)
7153 #define  PF_PIPE_SEL_IVB(pipe)  ((pipe) << 29)
7154 #define  PF_FILTER_MASK         (3 << 23)
7155 #define  PF_FILTER_PROGRAMMED   (0 << 23)
7156 #define  PF_FILTER_MED_3x3      (1 << 23)
7157 #define  PF_FILTER_EDGE_ENHANCE (2 << 23)
7158 #define  PF_FILTER_EDGE_SOFTEN  (3 << 23)
7159 #define _PFA_WIN_SZ             0x68074
7160 #define _PFB_WIN_SZ             0x68874
7161 #define _PFA_WIN_POS            0x68070
7162 #define _PFB_WIN_POS            0x68870
7163 #define _PFA_VSCALE             0x68084
7164 #define _PFB_VSCALE             0x68884
7165 #define _PFA_HSCALE             0x68090
7166 #define _PFB_HSCALE             0x68890
7167
7168 #define PF_CTL(pipe)            _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
7169 #define PF_WIN_SZ(pipe)         _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
7170 #define PF_WIN_POS(pipe)        _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
7171 #define PF_VSCALE(pipe)         _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
7172 #define PF_HSCALE(pipe)         _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
7173
7174 #define _PSA_CTL                0x68180
7175 #define _PSB_CTL                0x68980
7176 #define PS_ENABLE               (1 << 31)
7177 #define _PSA_WIN_SZ             0x68174
7178 #define _PSB_WIN_SZ             0x68974
7179 #define _PSA_WIN_POS            0x68170
7180 #define _PSB_WIN_POS            0x68970
7181
7182 #define PS_CTL(pipe)            _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
7183 #define PS_WIN_SZ(pipe)         _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
7184 #define PS_WIN_POS(pipe)        _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
7185
7186 /*
7187  * Skylake scalers
7188  */
7189 #define _PS_1A_CTRL      0x68180
7190 #define _PS_2A_CTRL      0x68280
7191 #define _PS_1B_CTRL      0x68980
7192 #define _PS_2B_CTRL      0x68A80
7193 #define _PS_1C_CTRL      0x69180
7194 #define PS_SCALER_EN        (1 << 31)
7195 #define SKL_PS_SCALER_MODE_MASK (3 << 28)
7196 #define SKL_PS_SCALER_MODE_DYN  (0 << 28)
7197 #define SKL_PS_SCALER_MODE_HQ  (1 << 28)
7198 #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
7199 #define PS_SCALER_MODE_PLANAR (1 << 29)
7200 #define PS_SCALER_MODE_NORMAL (0 << 29)
7201 #define PS_PLANE_SEL_MASK  (7 << 25)
7202 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
7203 #define PS_FILTER_MASK         (3 << 23)
7204 #define PS_FILTER_MEDIUM       (0 << 23)
7205 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
7206 #define PS_FILTER_BILINEAR     (3 << 23)
7207 #define PS_VERT3TAP            (1 << 21)
7208 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
7209 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
7210 #define PS_PWRUP_PROGRESS         (1 << 17)
7211 #define PS_V_FILTER_BYPASS        (1 << 8)
7212 #define PS_VADAPT_EN              (1 << 7)
7213 #define PS_VADAPT_MODE_MASK        (3 << 5)
7214 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
7215 #define PS_VADAPT_MODE_MOD_ADAPT   (1 << 5)
7216 #define PS_VADAPT_MODE_MOST_ADAPT  (3 << 5)
7217 #define PS_PLANE_Y_SEL_MASK  (7 << 5)
7218 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
7219
7220 #define _PS_PWR_GATE_1A     0x68160
7221 #define _PS_PWR_GATE_2A     0x68260
7222 #define _PS_PWR_GATE_1B     0x68960
7223 #define _PS_PWR_GATE_2B     0x68A60
7224 #define _PS_PWR_GATE_1C     0x69160
7225 #define PS_PWR_GATE_DIS_OVERRIDE       (1 << 31)
7226 #define PS_PWR_GATE_SETTLING_TIME_32   (0 << 3)
7227 #define PS_PWR_GATE_SETTLING_TIME_64   (1 << 3)
7228 #define PS_PWR_GATE_SETTLING_TIME_96   (2 << 3)
7229 #define PS_PWR_GATE_SETTLING_TIME_128  (3 << 3)
7230 #define PS_PWR_GATE_SLPEN_8             0
7231 #define PS_PWR_GATE_SLPEN_16            1
7232 #define PS_PWR_GATE_SLPEN_24            2
7233 #define PS_PWR_GATE_SLPEN_32            3
7234
7235 #define _PS_WIN_POS_1A      0x68170
7236 #define _PS_WIN_POS_2A      0x68270
7237 #define _PS_WIN_POS_1B      0x68970
7238 #define _PS_WIN_POS_2B      0x68A70
7239 #define _PS_WIN_POS_1C      0x69170
7240
7241 #define _PS_WIN_SZ_1A       0x68174
7242 #define _PS_WIN_SZ_2A       0x68274
7243 #define _PS_WIN_SZ_1B       0x68974
7244 #define _PS_WIN_SZ_2B       0x68A74
7245 #define _PS_WIN_SZ_1C       0x69174
7246
7247 #define _PS_VSCALE_1A       0x68184
7248 #define _PS_VSCALE_2A       0x68284
7249 #define _PS_VSCALE_1B       0x68984
7250 #define _PS_VSCALE_2B       0x68A84
7251 #define _PS_VSCALE_1C       0x69184
7252
7253 #define _PS_HSCALE_1A       0x68190
7254 #define _PS_HSCALE_2A       0x68290
7255 #define _PS_HSCALE_1B       0x68990
7256 #define _PS_HSCALE_2B       0x68A90
7257 #define _PS_HSCALE_1C       0x69190
7258
7259 #define _PS_VPHASE_1A       0x68188
7260 #define _PS_VPHASE_2A       0x68288
7261 #define _PS_VPHASE_1B       0x68988
7262 #define _PS_VPHASE_2B       0x68A88
7263 #define _PS_VPHASE_1C       0x69188
7264 #define  PS_Y_PHASE(x)          ((x) << 16)
7265 #define  PS_UV_RGB_PHASE(x)     ((x) << 0)
7266 #define   PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
7267 #define   PS_PHASE_TRIP (1 << 0)
7268
7269 #define _PS_HPHASE_1A       0x68194
7270 #define _PS_HPHASE_2A       0x68294
7271 #define _PS_HPHASE_1B       0x68994
7272 #define _PS_HPHASE_2B       0x68A94
7273 #define _PS_HPHASE_1C       0x69194
7274
7275 #define _PS_ECC_STAT_1A     0x681D0
7276 #define _PS_ECC_STAT_2A     0x682D0
7277 #define _PS_ECC_STAT_1B     0x689D0
7278 #define _PS_ECC_STAT_2B     0x68AD0
7279 #define _PS_ECC_STAT_1C     0x691D0
7280
7281 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
7282 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe,        \
7283                         _ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
7284                         _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
7285 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe,    \
7286                         _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
7287                         _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
7288 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe,     \
7289                         _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
7290                         _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
7291 #define SKL_PS_WIN_SZ(pipe, id)  _MMIO_PIPE(pipe,     \
7292                         _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A),   \
7293                         _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
7294 #define SKL_PS_VSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
7295                         _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A),   \
7296                         _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
7297 #define SKL_PS_HSCALE(pipe, id)  _MMIO_PIPE(pipe,     \
7298                         _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A),   \
7299                         _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
7300 #define SKL_PS_VPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
7301                         _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A),   \
7302                         _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
7303 #define SKL_PS_HPHASE(pipe, id)  _MMIO_PIPE(pipe,     \
7304                         _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A),   \
7305                         _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
7306 #define SKL_PS_ECC_STAT(pipe, id)  _MMIO_PIPE(pipe,     \
7307                         _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
7308                         _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
7309
7310 /* legacy palette */
7311 #define _LGC_PALETTE_A           0x4a000
7312 #define _LGC_PALETTE_B           0x4a800
7313 #define LGC_PALETTE_RED_MASK     REG_GENMASK(23, 16)
7314 #define LGC_PALETTE_GREEN_MASK   REG_GENMASK(15, 8)
7315 #define LGC_PALETTE_BLUE_MASK    REG_GENMASK(7, 0)
7316 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
7317
7318 /* ilk/snb precision palette */
7319 #define _PREC_PALETTE_A           0x4b000
7320 #define _PREC_PALETTE_B           0x4c000
7321 #define   PREC_PALETTE_RED_MASK   REG_GENMASK(29, 20)
7322 #define   PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10)
7323 #define   PREC_PALETTE_BLUE_MASK  REG_GENMASK(9, 0)
7324 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
7325
7326 #define  _PREC_PIPEAGCMAX              0x4d000
7327 #define  _PREC_PIPEBGCMAX              0x4d010
7328 #define PREC_PIPEGCMAX(pipe, i)        _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
7329
7330 #define _GAMMA_MODE_A           0x4a480
7331 #define _GAMMA_MODE_B           0x4ac80
7332 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
7333 #define  PRE_CSC_GAMMA_ENABLE   (1 << 31)
7334 #define  POST_CSC_GAMMA_ENABLE  (1 << 30)
7335 #define  GAMMA_MODE_MODE_MASK   (3 << 0)
7336 #define  GAMMA_MODE_MODE_8BIT   (0 << 0)
7337 #define  GAMMA_MODE_MODE_10BIT  (1 << 0)
7338 #define  GAMMA_MODE_MODE_12BIT  (2 << 0)
7339 #define  GAMMA_MODE_MODE_SPLIT  (3 << 0) /* ivb-bdw */
7340 #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED  (3 << 0) /* icl + */
7341
7342 /* DMC/CSR */
7343 #define CSR_PROGRAM(i)          _MMIO(0x80000 + (i) * 4)
7344 #define CSR_SSP_BASE_ADDR_GEN9  0x00002FC0
7345 #define CSR_HTP_ADDR_SKL        0x00500034
7346 #define CSR_SSP_BASE            _MMIO(0x8F074)
7347 #define CSR_HTP_SKL             _MMIO(0x8F004)
7348 #define CSR_LAST_WRITE          _MMIO(0x8F034)
7349 #define CSR_LAST_WRITE_VALUE    0xc003b400
7350 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
7351 #define CSR_MMIO_START_RANGE    0x80000
7352 #define CSR_MMIO_END_RANGE      0x8FFFF
7353 #define SKL_CSR_DC3_DC5_COUNT   _MMIO(0x80030)
7354 #define SKL_CSR_DC5_DC6_COUNT   _MMIO(0x8002C)
7355 #define BXT_CSR_DC3_DC5_COUNT   _MMIO(0x80038)
7356 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
7357 #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
7358
7359 #define DMC_DEBUG3              _MMIO(0x101090)
7360
7361 /* Display Internal Timeout Register */
7362 #define RM_TIMEOUT              _MMIO(0x42060)
7363 #define  MMIO_TIMEOUT_US(us)    ((us) << 0)
7364
7365 /* interrupts */
7366 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
7367 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
7368 #define DE_SPRITEA_FLIP_DONE    (1 << 28)
7369 #define DE_PLANEB_FLIP_DONE     (1 << 27)
7370 #define DE_PLANEA_FLIP_DONE     (1 << 26)
7371 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
7372 #define DE_PCU_EVENT            (1 << 25)
7373 #define DE_GTT_FAULT            (1 << 24)
7374 #define DE_POISON               (1 << 23)
7375 #define DE_PERFORM_COUNTER      (1 << 22)
7376 #define DE_PCH_EVENT            (1 << 21)
7377 #define DE_AUX_CHANNEL_A        (1 << 20)
7378 #define DE_DP_A_HOTPLUG         (1 << 19)
7379 #define DE_GSE                  (1 << 18)
7380 #define DE_PIPEB_VBLANK         (1 << 15)
7381 #define DE_PIPEB_EVEN_FIELD     (1 << 14)
7382 #define DE_PIPEB_ODD_FIELD      (1 << 13)
7383 #define DE_PIPEB_LINE_COMPARE   (1 << 12)
7384 #define DE_PIPEB_VSYNC          (1 << 11)
7385 #define DE_PIPEB_CRC_DONE       (1 << 10)
7386 #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
7387 #define DE_PIPEA_VBLANK         (1 << 7)
7388 #define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
7389 #define DE_PIPEA_EVEN_FIELD     (1 << 6)
7390 #define DE_PIPEA_ODD_FIELD      (1 << 5)
7391 #define DE_PIPEA_LINE_COMPARE   (1 << 4)
7392 #define DE_PIPEA_VSYNC          (1 << 3)
7393 #define DE_PIPEA_CRC_DONE       (1 << 2)
7394 #define DE_PIPE_CRC_DONE(pipe)  (1 << (2 + 8 * (pipe)))
7395 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
7396 #define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
7397
7398 /* More Ivybridge lolz */
7399 #define DE_ERR_INT_IVB                  (1 << 30)
7400 #define DE_GSE_IVB                      (1 << 29)
7401 #define DE_PCH_EVENT_IVB                (1 << 28)
7402 #define DE_DP_A_HOTPLUG_IVB             (1 << 27)
7403 #define DE_AUX_CHANNEL_A_IVB            (1 << 26)
7404 #define DE_EDP_PSR_INT_HSW              (1 << 19)
7405 #define DE_SPRITEC_FLIP_DONE_IVB        (1 << 14)
7406 #define DE_PLANEC_FLIP_DONE_IVB         (1 << 13)
7407 #define DE_PIPEC_VBLANK_IVB             (1 << 10)
7408 #define DE_SPRITEB_FLIP_DONE_IVB        (1 << 9)
7409 #define DE_PLANEB_FLIP_DONE_IVB         (1 << 8)
7410 #define DE_PIPEB_VBLANK_IVB             (1 << 5)
7411 #define DE_SPRITEA_FLIP_DONE_IVB        (1 << 4)
7412 #define DE_PLANEA_FLIP_DONE_IVB         (1 << 3)
7413 #define DE_PLANE_FLIP_DONE_IVB(plane)   (1 << (3 + 5 * (plane)))
7414 #define DE_PIPEA_VBLANK_IVB             (1 << 0)
7415 #define DE_PIPE_VBLANK_IVB(pipe)        (1 << ((pipe) * 5))
7416
7417 #define VLV_MASTER_IER                  _MMIO(0x4400c) /* Gunit master IER */
7418 #define   MASTER_INTERRUPT_ENABLE       (1 << 31)
7419
7420 #define DEISR   _MMIO(0x44000)
7421 #define DEIMR   _MMIO(0x44004)
7422 #define DEIIR   _MMIO(0x44008)
7423 #define DEIER   _MMIO(0x4400c)
7424
7425 #define GTISR   _MMIO(0x44010)
7426 #define GTIMR   _MMIO(0x44014)
7427 #define GTIIR   _MMIO(0x44018)
7428 #define GTIER   _MMIO(0x4401c)
7429
7430 #define GEN8_MASTER_IRQ                 _MMIO(0x44200)
7431 #define  GEN8_MASTER_IRQ_CONTROL        (1 << 31)
7432 #define  GEN8_PCU_IRQ                   (1 << 30)
7433 #define  GEN8_DE_PCH_IRQ                (1 << 23)
7434 #define  GEN8_DE_MISC_IRQ               (1 << 22)
7435 #define  GEN8_DE_PORT_IRQ               (1 << 20)
7436 #define  GEN8_DE_PIPE_C_IRQ             (1 << 18)
7437 #define  GEN8_DE_PIPE_B_IRQ             (1 << 17)
7438 #define  GEN8_DE_PIPE_A_IRQ             (1 << 16)
7439 #define  GEN8_DE_PIPE_IRQ(pipe)         (1 << (16 + (pipe)))
7440 #define  GEN8_GT_VECS_IRQ               (1 << 6)
7441 #define  GEN8_GT_GUC_IRQ                (1 << 5)
7442 #define  GEN8_GT_PM_IRQ                 (1 << 4)
7443 #define  GEN8_GT_VCS1_IRQ               (1 << 3) /* NB: VCS2 in bspec! */
7444 #define  GEN8_GT_VCS0_IRQ               (1 << 2) /* NB: VCS1 in bpsec! */
7445 #define  GEN8_GT_BCS_IRQ                (1 << 1)
7446 #define  GEN8_GT_RCS_IRQ                (1 << 0)
7447
7448 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7449 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7450 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7451 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7452
7453 #define GEN8_RCS_IRQ_SHIFT 0
7454 #define GEN8_BCS_IRQ_SHIFT 16
7455 #define GEN8_VCS0_IRQ_SHIFT 0  /* NB: VCS1 in bspec! */
7456 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
7457 #define GEN8_VECS_IRQ_SHIFT 0
7458 #define GEN8_WD_IRQ_SHIFT 16
7459
7460 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7461 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7462 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7463 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7464 #define  GEN8_PIPE_FIFO_UNDERRUN        (1 << 31)
7465 #define  GEN8_PIPE_CDCLK_CRC_ERROR      (1 << 29)
7466 #define  GEN8_PIPE_CDCLK_CRC_DONE       (1 << 28)
7467 #define  GEN8_PIPE_CURSOR_FAULT         (1 << 10)
7468 #define  GEN8_PIPE_SPRITE_FAULT         (1 << 9)
7469 #define  GEN8_PIPE_PRIMARY_FAULT        (1 << 8)
7470 #define  GEN8_PIPE_SPRITE_FLIP_DONE     (1 << 5)
7471 #define  GEN8_PIPE_PRIMARY_FLIP_DONE    (1 << 4)
7472 #define  GEN8_PIPE_SCAN_LINE_EVENT      (1 << 2)
7473 #define  GEN8_PIPE_VSYNC                (1 << 1)
7474 #define  GEN8_PIPE_VBLANK               (1 << 0)
7475 #define  GEN9_PIPE_CURSOR_FAULT         (1 << 11)
7476 #define  GEN11_PIPE_PLANE7_FAULT        (1 << 22)
7477 #define  GEN11_PIPE_PLANE6_FAULT        (1 << 21)
7478 #define  GEN11_PIPE_PLANE5_FAULT        (1 << 20)
7479 #define  GEN9_PIPE_PLANE4_FAULT         (1 << 10)
7480 #define  GEN9_PIPE_PLANE3_FAULT         (1 << 9)
7481 #define  GEN9_PIPE_PLANE2_FAULT         (1 << 8)
7482 #define  GEN9_PIPE_PLANE1_FAULT         (1 << 7)
7483 #define  GEN9_PIPE_PLANE4_FLIP_DONE     (1 << 6)
7484 #define  GEN9_PIPE_PLANE3_FLIP_DONE     (1 << 5)
7485 #define  GEN9_PIPE_PLANE2_FLIP_DONE     (1 << 4)
7486 #define  GEN9_PIPE_PLANE1_FLIP_DONE     (1 << 3)
7487 #define  GEN9_PIPE_PLANE_FLIP_DONE(p)   (1 << (3 + (p)))
7488 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7489         (GEN8_PIPE_CURSOR_FAULT | \
7490          GEN8_PIPE_SPRITE_FAULT | \
7491          GEN8_PIPE_PRIMARY_FAULT)
7492 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7493         (GEN9_PIPE_CURSOR_FAULT | \
7494          GEN9_PIPE_PLANE4_FAULT | \
7495          GEN9_PIPE_PLANE3_FAULT | \
7496          GEN9_PIPE_PLANE2_FAULT | \
7497          GEN9_PIPE_PLANE1_FAULT)
7498 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
7499         (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
7500          GEN11_PIPE_PLANE7_FAULT | \
7501          GEN11_PIPE_PLANE6_FAULT | \
7502          GEN11_PIPE_PLANE5_FAULT)
7503
7504 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
7505 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
7506 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
7507 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
7508 #define  DSI1_NON_TE                    (1 << 31)
7509 #define  DSI0_NON_TE                    (1 << 30)
7510 #define  ICL_AUX_CHANNEL_E              (1 << 29)
7511 #define  CNL_AUX_CHANNEL_F              (1 << 28)
7512 #define  GEN9_AUX_CHANNEL_D             (1 << 27)
7513 #define  GEN9_AUX_CHANNEL_C             (1 << 26)
7514 #define  GEN9_AUX_CHANNEL_B             (1 << 25)
7515 #define  DSI1_TE                        (1 << 24)
7516 #define  DSI0_TE                        (1 << 23)
7517 #define  BXT_DE_PORT_HP_DDIC            (1 << 5)
7518 #define  BXT_DE_PORT_HP_DDIB            (1 << 4)
7519 #define  BXT_DE_PORT_HP_DDIA            (1 << 3)
7520 #define  BXT_DE_PORT_HOTPLUG_MASK       (BXT_DE_PORT_HP_DDIA | \
7521                                          BXT_DE_PORT_HP_DDIB | \
7522                                          BXT_DE_PORT_HP_DDIC)
7523 #define  GEN8_PORT_DP_A_HOTPLUG         (1 << 3)
7524 #define  BXT_DE_PORT_GMBUS              (1 << 1)
7525 #define  GEN8_AUX_CHANNEL_A             (1 << 0)
7526 #define  TGL_DE_PORT_AUX_USBC6          (1 << 13)
7527 #define  TGL_DE_PORT_AUX_USBC5          (1 << 12)
7528 #define  TGL_DE_PORT_AUX_USBC4          (1 << 11)
7529 #define  TGL_DE_PORT_AUX_USBC3          (1 << 10)
7530 #define  TGL_DE_PORT_AUX_USBC2          (1 << 9)
7531 #define  TGL_DE_PORT_AUX_USBC1          (1 << 8)
7532 #define  TGL_DE_PORT_AUX_DDIC           (1 << 2)
7533 #define  TGL_DE_PORT_AUX_DDIB           (1 << 1)
7534 #define  TGL_DE_PORT_AUX_DDIA           (1 << 0)
7535
7536 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
7537 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
7538 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
7539 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
7540 #define  GEN8_DE_MISC_GSE               (1 << 27)
7541 #define  GEN8_DE_EDP_PSR                (1 << 19)
7542
7543 #define GEN8_PCU_ISR _MMIO(0x444e0)
7544 #define GEN8_PCU_IMR _MMIO(0x444e4)
7545 #define GEN8_PCU_IIR _MMIO(0x444e8)
7546 #define GEN8_PCU_IER _MMIO(0x444ec)
7547
7548 #define GEN11_GU_MISC_ISR       _MMIO(0x444f0)
7549 #define GEN11_GU_MISC_IMR       _MMIO(0x444f4)
7550 #define GEN11_GU_MISC_IIR       _MMIO(0x444f8)
7551 #define GEN11_GU_MISC_IER       _MMIO(0x444fc)
7552 #define  GEN11_GU_MISC_GSE      (1 << 27)
7553
7554 #define GEN11_GFX_MSTR_IRQ              _MMIO(0x190010)
7555 #define  GEN11_MASTER_IRQ               (1 << 31)
7556 #define  GEN11_PCU_IRQ                  (1 << 30)
7557 #define  GEN11_GU_MISC_IRQ              (1 << 29)
7558 #define  GEN11_DISPLAY_IRQ              (1 << 16)
7559 #define  GEN11_GT_DW_IRQ(x)             (1 << (x))
7560 #define  GEN11_GT_DW1_IRQ               (1 << 1)
7561 #define  GEN11_GT_DW0_IRQ               (1 << 0)
7562
7563 #define GEN11_DISPLAY_INT_CTL           _MMIO(0x44200)
7564 #define  GEN11_DISPLAY_IRQ_ENABLE       (1 << 31)
7565 #define  GEN11_AUDIO_CODEC_IRQ          (1 << 24)
7566 #define  GEN11_DE_PCH_IRQ               (1 << 23)
7567 #define  GEN11_DE_MISC_IRQ              (1 << 22)
7568 #define  GEN11_DE_HPD_IRQ               (1 << 21)
7569 #define  GEN11_DE_PORT_IRQ              (1 << 20)
7570 #define  GEN11_DE_PIPE_C                (1 << 18)
7571 #define  GEN11_DE_PIPE_B                (1 << 17)
7572 #define  GEN11_DE_PIPE_A                (1 << 16)
7573
7574 #define GEN11_DE_HPD_ISR                _MMIO(0x44470)
7575 #define GEN11_DE_HPD_IMR                _MMIO(0x44474)
7576 #define GEN11_DE_HPD_IIR                _MMIO(0x44478)
7577 #define GEN11_DE_HPD_IER                _MMIO(0x4447c)
7578 #define  GEN12_TC6_HOTPLUG                      (1 << 21)
7579 #define  GEN12_TC5_HOTPLUG                      (1 << 20)
7580 #define  GEN11_TC4_HOTPLUG                      (1 << 19)
7581 #define  GEN11_TC3_HOTPLUG                      (1 << 18)
7582 #define  GEN11_TC2_HOTPLUG                      (1 << 17)
7583 #define  GEN11_TC1_HOTPLUG                      (1 << 16)
7584 #define  GEN11_TC_HOTPLUG(tc_port)              (1 << ((tc_port) + 16))
7585 #define  GEN11_DE_TC_HOTPLUG_MASK               (GEN12_TC6_HOTPLUG | \
7586                                                  GEN12_TC5_HOTPLUG | \
7587                                                  GEN11_TC4_HOTPLUG | \
7588                                                  GEN11_TC3_HOTPLUG | \
7589                                                  GEN11_TC2_HOTPLUG | \
7590                                                  GEN11_TC1_HOTPLUG)
7591 #define  GEN12_TBT6_HOTPLUG                     (1 << 5)
7592 #define  GEN12_TBT5_HOTPLUG                     (1 << 4)
7593 #define  GEN11_TBT4_HOTPLUG                     (1 << 3)
7594 #define  GEN11_TBT3_HOTPLUG                     (1 << 2)
7595 #define  GEN11_TBT2_HOTPLUG                     (1 << 1)
7596 #define  GEN11_TBT1_HOTPLUG                     (1 << 0)
7597 #define  GEN11_TBT_HOTPLUG(tc_port)             (1 << (tc_port))
7598 #define  GEN11_DE_TBT_HOTPLUG_MASK              (GEN12_TBT6_HOTPLUG | \
7599                                                  GEN12_TBT5_HOTPLUG | \
7600                                                  GEN11_TBT4_HOTPLUG | \
7601                                                  GEN11_TBT3_HOTPLUG | \
7602                                                  GEN11_TBT2_HOTPLUG | \
7603                                                  GEN11_TBT1_HOTPLUG)
7604
7605 #define GEN11_TBT_HOTPLUG_CTL                           _MMIO(0x44030)
7606 #define GEN11_TC_HOTPLUG_CTL                            _MMIO(0x44038)
7607 #define  GEN11_HOTPLUG_CTL_ENABLE(tc_port)              (8 << (tc_port) * 4)
7608 #define  GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)         (2 << (tc_port) * 4)
7609 #define  GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)        (1 << (tc_port) * 4)
7610 #define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)           (0 << (tc_port) * 4)
7611
7612 #define GEN11_GT_INTR_DW0               _MMIO(0x190018)
7613 #define  GEN11_CSME                     (31)
7614 #define  GEN11_GUNIT                    (28)
7615 #define  GEN11_GUC                      (25)
7616 #define  GEN11_WDPERF                   (20)
7617 #define  GEN11_KCR                      (19)
7618 #define  GEN11_GTPM                     (16)
7619 #define  GEN11_BCS                      (15)
7620 #define  GEN11_RCS0                     (0)
7621
7622 #define GEN11_GT_INTR_DW1               _MMIO(0x19001c)
7623 #define  GEN11_VECS(x)                  (31 - (x))
7624 #define  GEN11_VCS(x)                   (x)
7625
7626 #define GEN11_GT_INTR_DW(x)             _MMIO(0x190018 + ((x) * 4))
7627
7628 #define GEN11_INTR_IDENTITY_REG0        _MMIO(0x190060)
7629 #define GEN11_INTR_IDENTITY_REG1        _MMIO(0x190064)
7630 #define  GEN11_INTR_DATA_VALID          (1 << 31)
7631 #define  GEN11_INTR_ENGINE_CLASS(x)     (((x) & GENMASK(18, 16)) >> 16)
7632 #define  GEN11_INTR_ENGINE_INSTANCE(x)  (((x) & GENMASK(25, 20)) >> 20)
7633 #define  GEN11_INTR_ENGINE_INTR(x)      ((x) & 0xffff)
7634 /* irq instances for OTHER_CLASS */
7635 #define OTHER_GUC_INSTANCE      0
7636 #define OTHER_GTPM_INSTANCE     1
7637
7638 #define GEN11_INTR_IDENTITY_REG(x)      _MMIO(0x190060 + ((x) * 4))
7639
7640 #define GEN11_IIR_REG0_SELECTOR         _MMIO(0x190070)
7641 #define GEN11_IIR_REG1_SELECTOR         _MMIO(0x190074)
7642
7643 #define GEN11_IIR_REG_SELECTOR(x)       _MMIO(0x190070 + ((x) * 4))
7644
7645 #define GEN11_RENDER_COPY_INTR_ENABLE   _MMIO(0x190030)
7646 #define GEN11_VCS_VECS_INTR_ENABLE      _MMIO(0x190034)
7647 #define GEN11_GUC_SG_INTR_ENABLE        _MMIO(0x190038)
7648 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
7649 #define GEN11_CRYPTO_RSVD_INTR_ENABLE   _MMIO(0x190040)
7650 #define GEN11_GUNIT_CSME_INTR_ENABLE    _MMIO(0x190044)
7651
7652 #define GEN11_RCS0_RSVD_INTR_MASK       _MMIO(0x190090)
7653 #define GEN11_BCS_RSVD_INTR_MASK        _MMIO(0x1900a0)
7654 #define GEN11_VCS0_VCS1_INTR_MASK       _MMIO(0x1900a8)
7655 #define GEN11_VCS2_VCS3_INTR_MASK       _MMIO(0x1900ac)
7656 #define GEN11_VECS0_VECS1_INTR_MASK     _MMIO(0x1900d0)
7657 #define GEN11_GUC_SG_INTR_MASK          _MMIO(0x1900e8)
7658 #define GEN11_GPM_WGBOXPERF_INTR_MASK   _MMIO(0x1900ec)
7659 #define GEN11_CRYPTO_RSVD_INTR_MASK     _MMIO(0x1900f0)
7660 #define GEN11_GUNIT_CSME_INTR_MASK      _MMIO(0x1900f4)
7661
7662 #define   ENGINE1_MASK                  REG_GENMASK(31, 16)
7663 #define   ENGINE0_MASK                  REG_GENMASK(15, 0)
7664
7665 #define ILK_DISPLAY_CHICKEN2    _MMIO(0x42004)
7666 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
7667 #define  ILK_ELPIN_409_SELECT   (1 << 25)
7668 #define  ILK_DPARB_GATE (1 << 22)
7669 #define  ILK_VSDPFD_FULL        (1 << 21)
7670 #define FUSE_STRAP                      _MMIO(0x42014)
7671 #define  ILK_INTERNAL_GRAPHICS_DISABLE  (1 << 31)
7672 #define  ILK_INTERNAL_DISPLAY_DISABLE   (1 << 30)
7673 #define  ILK_DISPLAY_DEBUG_DISABLE      (1 << 29)
7674 #define  IVB_PIPE_C_DISABLE             (1 << 28)
7675 #define  ILK_HDCP_DISABLE               (1 << 25)
7676 #define  ILK_eDP_A_DISABLE              (1 << 24)
7677 #define  HSW_CDCLK_LIMIT                (1 << 24)
7678 #define  ILK_DESKTOP                    (1 << 23)
7679 #define  HSW_CPU_SSC_ENABLE             (1 << 21)
7680
7681 #define FUSE_STRAP3                     _MMIO(0x42020)
7682 #define  HSW_REF_CLK_SELECT             (1 << 1)
7683
7684 #define ILK_DSPCLK_GATE_D                       _MMIO(0x42020)
7685 #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE        (1 << 28)
7686 #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE       (1 << 9)
7687 #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE      (1 << 8)
7688 #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE        (1 << 7)
7689 #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE       (1 << 5)
7690
7691 #define IVB_CHICKEN3    _MMIO(0x4200c)
7692 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE      (1 << 5)
7693 # define CHICKEN3_DGMG_DONE_FIX_DISABLE         (1 << 2)
7694
7695 #define CHICKEN_PAR1_1          _MMIO(0x42080)
7696 #define  SKL_DE_COMPRESSED_HASH_MODE    (1 << 15)
7697 #define  DPA_MASK_VBLANK_SRD    (1 << 15)
7698 #define  FORCE_ARB_IDLE_PLANES  (1 << 14)
7699 #define  SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
7700
7701 #define CHICKEN_PAR2_1          _MMIO(0x42090)
7702 #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT  (1 << 14)
7703
7704 #define CHICKEN_MISC_2          _MMIO(0x42084)
7705 #define  CNL_COMP_PWR_DOWN      (1 << 23)
7706 #define  GLK_CL2_PWR_DOWN       (1 << 12)
7707 #define  GLK_CL1_PWR_DOWN       (1 << 11)
7708 #define  GLK_CL0_PWR_DOWN       (1 << 10)
7709
7710 #define CHICKEN_MISC_4          _MMIO(0x4208c)
7711 #define   FBC_STRIDE_OVERRIDE   (1 << 13)
7712 #define   FBC_STRIDE_MASK       0x1FFF
7713
7714 #define _CHICKEN_PIPESL_1_A     0x420b0
7715 #define _CHICKEN_PIPESL_1_B     0x420b4
7716 #define  HSW_FBCQ_DIS                   (1 << 22)
7717 #define  BDW_DPRS_MASK_VBLANK_SRD       (1 << 0)
7718 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7719
7720 #define _CHICKEN_TRANS_A        0x420c0
7721 #define _CHICKEN_TRANS_B        0x420c4
7722 #define _CHICKEN_TRANS_C        0x420c8
7723 #define _CHICKEN_TRANS_EDP      0x420cc
7724 #define _CHICKEN_TRANS_D        0x420d8
7725 #define CHICKEN_TRANS(trans)    _MMIO(_PICK((trans), \
7726                                             [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
7727                                             [TRANSCODER_A] = _CHICKEN_TRANS_A, \
7728                                             [TRANSCODER_B] = _CHICKEN_TRANS_B, \
7729                                             [TRANSCODER_C] = _CHICKEN_TRANS_C, \
7730                                             [TRANSCODER_D] = _CHICKEN_TRANS_D))
7731 #define  HSW_FRAME_START_DELAY_MASK     (3 << 27)
7732 #define  HSW_FRAME_START_DELAY(x)       ((x) << 27) /* 0-3 */
7733 #define  VSC_DATA_SEL_SOFTWARE_CONTROL  (1 << 25) /* GLK and CNL+ */
7734 #define  DDI_TRAINING_OVERRIDE_ENABLE   (1 << 19)
7735 #define  DDI_TRAINING_OVERRIDE_VALUE    (1 << 18)
7736 #define  DDIE_TRAINING_OVERRIDE_ENABLE  (1 << 17) /* CHICKEN_TRANS_A only */
7737 #define  DDIE_TRAINING_OVERRIDE_VALUE   (1 << 16) /* CHICKEN_TRANS_A only */
7738 #define  PSR2_ADD_VERTICAL_LINE_COUNT   (1 << 15)
7739 #define  PSR2_VSC_ENABLE_PROG_HEADER    (1 << 12)
7740
7741 #define DISP_ARB_CTL    _MMIO(0x45000)
7742 #define  DISP_FBC_MEMORY_WAKE           (1 << 31)
7743 #define  DISP_TILE_SURFACE_SWIZZLING    (1 << 13)
7744 #define  DISP_FBC_WM_DIS                (1 << 15)
7745 #define DISP_ARB_CTL2   _MMIO(0x45004)
7746 #define  DISP_DATA_PARTITION_5_6        (1 << 6)
7747 #define  DISP_IPC_ENABLE                (1 << 3)
7748 #define DBUF_CTL        _MMIO(0x45008)
7749 #define DBUF_CTL_S1     _MMIO(0x45008)
7750 #define DBUF_CTL_S2     _MMIO(0x44FE8)
7751 #define  DBUF_POWER_REQUEST             (1 << 31)
7752 #define  DBUF_POWER_STATE               (1 << 30)
7753 #define GEN7_MSG_CTL    _MMIO(0x45010)
7754 #define  WAIT_FOR_PCH_RESET_ACK         (1 << 1)
7755 #define  WAIT_FOR_PCH_FLR_ACK           (1 << 0)
7756
7757 #define BW_BUDDY1_CTL                   _MMIO(0x45140)
7758 #define BW_BUDDY2_CTL                   _MMIO(0x45150)
7759 #define   BW_BUDDY_DISABLE              REG_BIT(31)
7760
7761 #define BW_BUDDY1_PAGE_MASK             _MMIO(0x45144)
7762 #define BW_BUDDY2_PAGE_MASK             _MMIO(0x45154)
7763
7764 #define HSW_NDE_RSTWRN_OPT      _MMIO(0x46408)
7765 #define  RESET_PCH_HANDSHAKE_ENABLE     (1 << 4)
7766
7767 #define GEN8_CHICKEN_DCPR_1             _MMIO(0x46430)
7768 #define   SKL_SELECT_ALTERNATE_DC_EXIT  (1 << 30)
7769 #define   MASK_WAKEMEM                  (1 << 13)
7770 #define   CNL_DDI_CLOCK_REG_ACCESS_ON   (1 << 7)
7771
7772 #define SKL_DFSM                        _MMIO(0x51000)
7773 #define   SKL_DFSM_DISPLAY_PM_DISABLE   (1 << 27)
7774 #define   SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
7775 #define   SKL_DFSM_CDCLK_LIMIT_MASK     (3 << 23)
7776 #define   SKL_DFSM_CDCLK_LIMIT_675      (0 << 23)
7777 #define   SKL_DFSM_CDCLK_LIMIT_540      (1 << 23)
7778 #define   SKL_DFSM_CDCLK_LIMIT_450      (2 << 23)
7779 #define   SKL_DFSM_CDCLK_LIMIT_337_5    (3 << 23)
7780 #define   ICL_DFSM_DMC_DISABLE          (1 << 23)
7781 #define   SKL_DFSM_PIPE_A_DISABLE       (1 << 30)
7782 #define   SKL_DFSM_PIPE_B_DISABLE       (1 << 21)
7783 #define   SKL_DFSM_PIPE_C_DISABLE       (1 << 28)
7784 #define   TGL_DFSM_PIPE_D_DISABLE       (1 << 22)
7785 #define   CNL_DFSM_DISPLAY_DSC_DISABLE  (1 << 7)
7786
7787 #define SKL_DSSM                                _MMIO(0x51004)
7788 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz         (1 << 31)
7789 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK          (7 << 29)
7790 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz         (0 << 29)
7791 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz       (1 << 29)
7792 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz       (2 << 29)
7793
7794 #define GEN7_FF_SLICE_CS_CHICKEN1       _MMIO(0x20e0)
7795 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
7796
7797 #define FF_SLICE_CS_CHICKEN2                    _MMIO(0x20e4)
7798 #define  GEN9_TSG_BARRIER_ACK_DISABLE           (1 << 8)
7799 #define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1 << 10)
7800
7801 #define GEN9_CS_DEBUG_MODE1             _MMIO(0x20ec)
7802 #define   FF_DOP_CLOCK_GATE_DISABLE     REG_BIT(1)
7803 #define GEN9_CTX_PREEMPT_REG            _MMIO(0x2248)
7804 #define   GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
7805
7806 #define GEN8_CS_CHICKEN1                _MMIO(0x2580)
7807 #define GEN9_PREEMPT_3D_OBJECT_LEVEL            (1 << 0)
7808 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo)        (((hi) << 2) | ((lo) << 1))
7809 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL     GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7810 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL   GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7811 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL        GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7812 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK           GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
7813
7814 /* GEN7 chicken */
7815 #define GEN7_COMMON_SLICE_CHICKEN1              _MMIO(0x7010)
7816   #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC     ((1 << 10) | (1 << 26))
7817   #define GEN9_RHWO_OPTIMIZATION_DISABLE        (1 << 14)
7818
7819 #define COMMON_SLICE_CHICKEN2                                   _MMIO(0x7014)
7820   #define GEN9_PBE_COMPRESSED_HASH_SELECTION                    (1 << 13)
7821   #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE        (1 << 12)
7822   #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION              (1 << 8)
7823   #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE                  (1 << 0)
7824
7825 #define GEN8_L3CNTLREG  _MMIO(0x7034)
7826   #define GEN8_ERRDETBCTRL (1 << 9)
7827
7828 #define GEN11_COMMON_SLICE_CHICKEN3             _MMIO(0x7304)
7829   #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC    (1 << 11)
7830   #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE    (1 << 9)
7831
7832 #define HIZ_CHICKEN                                     _MMIO(0x7018)
7833 # define CHV_HZ_8X8_MODE_IN_1X                          (1 << 15)
7834 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE    (1 << 3)
7835
7836 #define GEN9_SLICE_COMMON_ECO_CHICKEN0          _MMIO(0x7308)
7837 #define  DISABLE_PIXEL_MASK_CAMMING             (1 << 14)
7838
7839 #define GEN9_SLICE_COMMON_ECO_CHICKEN1          _MMIO(0x731c)
7840 #define   GEN11_STATE_CACHE_REDIRECT_TO_CS      (1 << 11)
7841
7842 #define GEN7_SARCHKMD                           _MMIO(0xB000)
7843 #define GEN7_DISABLE_DEMAND_PREFETCH            (1 << 31)
7844 #define GEN7_DISABLE_SAMPLER_PREFETCH           (1 << 30)
7845
7846 #define GEN7_L3SQCREG1                          _MMIO(0xB010)
7847 #define  VLV_B0_WA_L3SQCREG1_VALUE              0x00D30000
7848
7849 #define GEN8_L3SQCREG1                          _MMIO(0xB100)
7850 /*
7851  * Note that on CHV the following has an off-by-one error wrt. to BSpec.
7852  * Using the formula in BSpec leads to a hang, while the formula here works
7853  * fine and matches the formulas for all other platforms. A BSpec change
7854  * request has been filed to clarify this.
7855  */
7856 #define  L3_GENERAL_PRIO_CREDITS(x)             (((x) >> 1) << 19)
7857 #define  L3_HIGH_PRIO_CREDITS(x)                (((x) >> 1) << 14)
7858 #define  L3_PRIO_CREDITS_MASK                   ((0x1f << 19) | (0x1f << 14))
7859
7860 #define GEN7_L3CNTLREG1                         _MMIO(0xB01C)
7861 #define  GEN7_WA_FOR_GEN7_L3_CONTROL                    0x3C47FF8C
7862 #define  GEN7_L3AGDIS                           (1 << 19)
7863 #define GEN7_L3CNTLREG2                         _MMIO(0xB020)
7864 #define GEN7_L3CNTLREG3                         _MMIO(0xB024)
7865
7866 #define GEN7_L3_CHICKEN_MODE_REGISTER           _MMIO(0xB030)
7867 #define   GEN7_WA_L3_CHICKEN_MODE               0x20000000
7868 #define GEN10_L3_CHICKEN_MODE_REGISTER          _MMIO(0xB114)
7869 #define   GEN11_I2M_WRITE_DISABLE               (1 << 28)
7870
7871 #define GEN7_L3SQCREG4                          _MMIO(0xb034)
7872 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE        (1 << 27)
7873
7874 #define GEN11_SCRATCH2                                  _MMIO(0xb140)
7875 #define  GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE      (1 << 19)
7876
7877 #define GEN8_L3SQCREG4                          _MMIO(0xb118)
7878 #define  GEN11_LQSC_CLEAN_EVICT_DISABLE         (1 << 6)
7879 #define  GEN8_LQSC_RO_PERF_DIS                  (1 << 27)
7880 #define  GEN8_LQSC_FLUSH_COHERENT_LINES         (1 << 21)
7881
7882 /* GEN8 chicken */
7883 #define HDC_CHICKEN0                            _MMIO(0x7300)
7884 #define CNL_HDC_CHICKEN0                        _MMIO(0xE5F0)
7885 #define ICL_HDC_MODE                            _MMIO(0xE5F4)
7886 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
7887 #define  HDC_FENCE_DEST_SLM_DISABLE             (1 << 14)
7888 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED        (1 << 11)
7889 #define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT    (1 << 5)
7890 #define  HDC_FORCE_NON_COHERENT                 (1 << 4)
7891 #define  HDC_BARRIER_PERFORMANCE_DISABLE        (1 << 10)
7892
7893 #define GEN8_HDC_CHICKEN1                       _MMIO(0x7304)
7894
7895 /* GEN9 chicken */
7896 #define SLICE_ECO_CHICKEN0                      _MMIO(0x7308)
7897 #define   PIXEL_MASK_CAMMING_DISABLE            (1 << 14)
7898
7899 #define GEN9_WM_CHICKEN3                        _MMIO(0x5588)
7900 #define   GEN9_FACTOR_IN_CLR_VAL_HIZ            (1 << 9)
7901
7902 /* WaCatErrorRejectionIssue */
7903 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG          _MMIO(0x9030)
7904 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB       (1 << 11)
7905
7906 #define HSW_SCRATCH1                            _MMIO(0xb038)
7907 #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE   (1 << 27)
7908
7909 #define BDW_SCRATCH1                                    _MMIO(0xb11c)
7910 #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE      (1 << 2)
7911
7912 /*GEN11 chicken */
7913 #define _PIPEA_CHICKEN                          0x70038
7914 #define _PIPEB_CHICKEN                          0x71038
7915 #define _PIPEC_CHICKEN                          0x72038
7916 #define PIPE_CHICKEN(pipe)                      _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
7917                                                            _PIPEB_CHICKEN)
7918 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU      (1 << 15)
7919 #define   PER_PIXEL_ALPHA_BYPASS_EN             (1 << 7)
7920
7921 #define FF_MODE2                        _MMIO(0x6604)
7922 #define   FF_MODE2_TDS_TIMER_MASK       REG_GENMASK(23, 16)
7923 #define   FF_MODE2_TDS_TIMER_128        REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
7924
7925 /* PCH */
7926
7927 #define PCH_DISPLAY_BASE        0xc0000u
7928
7929 /* south display engine interrupt: IBX */
7930 #define SDE_AUDIO_POWER_D       (1 << 27)
7931 #define SDE_AUDIO_POWER_C       (1 << 26)
7932 #define SDE_AUDIO_POWER_B       (1 << 25)
7933 #define SDE_AUDIO_POWER_SHIFT   (25)
7934 #define SDE_AUDIO_POWER_MASK    (7 << SDE_AUDIO_POWER_SHIFT)
7935 #define SDE_GMBUS               (1 << 24)
7936 #define SDE_AUDIO_HDCP_TRANSB   (1 << 23)
7937 #define SDE_AUDIO_HDCP_TRANSA   (1 << 22)
7938 #define SDE_AUDIO_HDCP_MASK     (3 << 22)
7939 #define SDE_AUDIO_TRANSB        (1 << 21)
7940 #define SDE_AUDIO_TRANSA        (1 << 20)
7941 #define SDE_AUDIO_TRANS_MASK    (3 << 20)
7942 #define SDE_POISON              (1 << 19)
7943 /* 18 reserved */
7944 #define SDE_FDI_RXB             (1 << 17)
7945 #define SDE_FDI_RXA             (1 << 16)
7946 #define SDE_FDI_MASK            (3 << 16)
7947 #define SDE_AUXD                (1 << 15)
7948 #define SDE_AUXC                (1 << 14)
7949 #define SDE_AUXB                (1 << 13)
7950 #define SDE_AUX_MASK            (7 << 13)
7951 /* 12 reserved */
7952 #define SDE_CRT_HOTPLUG         (1 << 11)
7953 #define SDE_PORTD_HOTPLUG       (1 << 10)
7954 #define SDE_PORTC_HOTPLUG       (1 << 9)
7955 #define SDE_PORTB_HOTPLUG       (1 << 8)
7956 #define SDE_SDVOB_HOTPLUG       (1 << 6)
7957 #define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
7958                                  SDE_SDVOB_HOTPLUG |    \
7959                                  SDE_PORTB_HOTPLUG |    \
7960                                  SDE_PORTC_HOTPLUG |    \
7961                                  SDE_PORTD_HOTPLUG)
7962 #define SDE_TRANSB_CRC_DONE     (1 << 5)
7963 #define SDE_TRANSB_CRC_ERR      (1 << 4)
7964 #define SDE_TRANSB_FIFO_UNDER   (1 << 3)
7965 #define SDE_TRANSA_CRC_DONE     (1 << 2)
7966 #define SDE_TRANSA_CRC_ERR      (1 << 1)
7967 #define SDE_TRANSA_FIFO_UNDER   (1 << 0)
7968 #define SDE_TRANS_MASK          (0x3f)
7969
7970 /* south display engine interrupt: CPT - CNP */
7971 #define SDE_AUDIO_POWER_D_CPT   (1 << 31)
7972 #define SDE_AUDIO_POWER_C_CPT   (1 << 30)
7973 #define SDE_AUDIO_POWER_B_CPT   (1 << 29)
7974 #define SDE_AUDIO_POWER_SHIFT_CPT   29
7975 #define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
7976 #define SDE_AUXD_CPT            (1 << 27)
7977 #define SDE_AUXC_CPT            (1 << 26)
7978 #define SDE_AUXB_CPT            (1 << 25)
7979 #define SDE_AUX_MASK_CPT        (7 << 25)
7980 #define SDE_PORTE_HOTPLUG_SPT   (1 << 25)
7981 #define SDE_PORTA_HOTPLUG_SPT   (1 << 24)
7982 #define SDE_PORTD_HOTPLUG_CPT   (1 << 23)
7983 #define SDE_PORTC_HOTPLUG_CPT   (1 << 22)
7984 #define SDE_PORTB_HOTPLUG_CPT   (1 << 21)
7985 #define SDE_CRT_HOTPLUG_CPT     (1 << 19)
7986 #define SDE_SDVOB_HOTPLUG_CPT   (1 << 18)
7987 #define SDE_HOTPLUG_MASK_CPT    (SDE_CRT_HOTPLUG_CPT |          \
7988                                  SDE_SDVOB_HOTPLUG_CPT |        \
7989                                  SDE_PORTD_HOTPLUG_CPT |        \
7990                                  SDE_PORTC_HOTPLUG_CPT |        \
7991                                  SDE_PORTB_HOTPLUG_CPT)
7992 #define SDE_HOTPLUG_MASK_SPT    (SDE_PORTE_HOTPLUG_SPT |        \
7993                                  SDE_PORTD_HOTPLUG_CPT |        \
7994                                  SDE_PORTC_HOTPLUG_CPT |        \
7995                                  SDE_PORTB_HOTPLUG_CPT |        \
7996                                  SDE_PORTA_HOTPLUG_SPT)
7997 #define SDE_GMBUS_CPT           (1 << 17)
7998 #define SDE_ERROR_CPT           (1 << 16)
7999 #define SDE_AUDIO_CP_REQ_C_CPT  (1 << 10)
8000 #define SDE_AUDIO_CP_CHG_C_CPT  (1 << 9)
8001 #define SDE_FDI_RXC_CPT         (1 << 8)
8002 #define SDE_AUDIO_CP_REQ_B_CPT  (1 << 6)
8003 #define SDE_AUDIO_CP_CHG_B_CPT  (1 << 5)
8004 #define SDE_FDI_RXB_CPT         (1 << 4)
8005 #define SDE_AUDIO_CP_REQ_A_CPT  (1 << 2)
8006 #define SDE_AUDIO_CP_CHG_A_CPT  (1 << 1)
8007 #define SDE_FDI_RXA_CPT         (1 << 0)
8008 #define SDE_AUDIO_CP_REQ_CPT    (SDE_AUDIO_CP_REQ_C_CPT | \
8009                                  SDE_AUDIO_CP_REQ_B_CPT | \
8010                                  SDE_AUDIO_CP_REQ_A_CPT)
8011 #define SDE_AUDIO_CP_CHG_CPT    (SDE_AUDIO_CP_CHG_C_CPT | \
8012                                  SDE_AUDIO_CP_CHG_B_CPT | \
8013                                  SDE_AUDIO_CP_CHG_A_CPT)
8014 #define SDE_FDI_MASK_CPT        (SDE_FDI_RXC_CPT | \
8015                                  SDE_FDI_RXB_CPT | \
8016                                  SDE_FDI_RXA_CPT)
8017
8018 /* south display engine interrupt: ICP/TGP */
8019 #define SDE_GMBUS_ICP                   (1 << 23)
8020 #define SDE_TC_HOTPLUG_ICP(tc_port)     (1 << ((tc_port) + 24))
8021 #define SDE_DDI_HOTPLUG_ICP(port)       (1 << ((port) + 16))
8022 #define SDE_DDI_MASK_ICP                (SDE_DDI_HOTPLUG_ICP(PORT_B) | \
8023                                          SDE_DDI_HOTPLUG_ICP(PORT_A))
8024 #define SDE_TC_MASK_ICP                 (SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
8025                                          SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
8026                                          SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
8027                                          SDE_TC_HOTPLUG_ICP(PORT_TC1))
8028 #define SDE_DDI_MASK_TGP                (SDE_DDI_HOTPLUG_ICP(PORT_C) | \
8029                                          SDE_DDI_HOTPLUG_ICP(PORT_B) | \
8030                                          SDE_DDI_HOTPLUG_ICP(PORT_A))
8031 #define SDE_TC_MASK_TGP                 (SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
8032                                          SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
8033                                          SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
8034                                          SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
8035                                          SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
8036                                          SDE_TC_HOTPLUG_ICP(PORT_TC1))
8037
8038 #define SDEISR  _MMIO(0xc4000)
8039 #define SDEIMR  _MMIO(0xc4004)
8040 #define SDEIIR  _MMIO(0xc4008)
8041 #define SDEIER  _MMIO(0xc400c)
8042
8043 #define SERR_INT                        _MMIO(0xc4040)
8044 #define  SERR_INT_POISON                (1 << 31)
8045 #define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)     (1 << ((pipe) * 3))
8046
8047 /* digital port hotplug */
8048 #define PCH_PORT_HOTPLUG                _MMIO(0xc4030)  /* SHOTPLUG_CTL */
8049 #define  PORTA_HOTPLUG_ENABLE           (1 << 28) /* LPT:LP+ & BXT */
8050 #define  BXT_DDIA_HPD_INVERT            (1 << 27)
8051 #define  PORTA_HOTPLUG_STATUS_MASK      (3 << 24) /* SPT+ & BXT */
8052 #define  PORTA_HOTPLUG_NO_DETECT        (0 << 24) /* SPT+ & BXT */
8053 #define  PORTA_HOTPLUG_SHORT_DETECT     (1 << 24) /* SPT+ & BXT */
8054 #define  PORTA_HOTPLUG_LONG_DETECT      (2 << 24) /* SPT+ & BXT */
8055 #define  PORTD_HOTPLUG_ENABLE           (1 << 20)
8056 #define  PORTD_PULSE_DURATION_2ms       (0 << 18) /* pre-LPT */
8057 #define  PORTD_PULSE_DURATION_4_5ms     (1 << 18) /* pre-LPT */
8058 #define  PORTD_PULSE_DURATION_6ms       (2 << 18) /* pre-LPT */
8059 #define  PORTD_PULSE_DURATION_100ms     (3 << 18) /* pre-LPT */
8060 #define  PORTD_PULSE_DURATION_MASK      (3 << 18) /* pre-LPT */
8061 #define  PORTD_HOTPLUG_STATUS_MASK      (3 << 16)
8062 #define  PORTD_HOTPLUG_NO_DETECT        (0 << 16)
8063 #define  PORTD_HOTPLUG_SHORT_DETECT     (1 << 16)
8064 #define  PORTD_HOTPLUG_LONG_DETECT      (2 << 16)
8065 #define  PORTC_HOTPLUG_ENABLE           (1 << 12)
8066 #define  BXT_DDIC_HPD_INVERT            (1 << 11)
8067 #define  PORTC_PULSE_DURATION_2ms       (0 << 10) /* pre-LPT */
8068 #define  PORTC_PULSE_DURATION_4_5ms     (1 << 10) /* pre-LPT */
8069 #define  PORTC_PULSE_DURATION_6ms       (2 << 10) /* pre-LPT */
8070 #define  PORTC_PULSE_DURATION_100ms     (3 << 10) /* pre-LPT */
8071 #define  PORTC_PULSE_DURATION_MASK      (3 << 10) /* pre-LPT */
8072 #define  PORTC_HOTPLUG_STATUS_MASK      (3 << 8)
8073 #define  PORTC_HOTPLUG_NO_DETECT        (0 << 8)
8074 #define  PORTC_HOTPLUG_SHORT_DETECT     (1 << 8)
8075 #define  PORTC_HOTPLUG_LONG_DETECT      (2 << 8)
8076 #define  PORTB_HOTPLUG_ENABLE           (1 << 4)
8077 #define  BXT_DDIB_HPD_INVERT            (1 << 3)
8078 #define  PORTB_PULSE_DURATION_2ms       (0 << 2) /* pre-LPT */
8079 #define  PORTB_PULSE_DURATION_4_5ms     (1 << 2) /* pre-LPT */
8080 #define  PORTB_PULSE_DURATION_6ms       (2 << 2) /* pre-LPT */
8081 #define  PORTB_PULSE_DURATION_100ms     (3 << 2) /* pre-LPT */
8082 #define  PORTB_PULSE_DURATION_MASK      (3 << 2) /* pre-LPT */
8083 #define  PORTB_HOTPLUG_STATUS_MASK      (3 << 0)
8084 #define  PORTB_HOTPLUG_NO_DETECT        (0 << 0)
8085 #define  PORTB_HOTPLUG_SHORT_DETECT     (1 << 0)
8086 #define  PORTB_HOTPLUG_LONG_DETECT      (2 << 0)
8087 #define  BXT_DDI_HPD_INVERT_MASK        (BXT_DDIA_HPD_INVERT | \
8088                                         BXT_DDIB_HPD_INVERT | \
8089                                         BXT_DDIC_HPD_INVERT)
8090
8091 #define PCH_PORT_HOTPLUG2               _MMIO(0xc403C)  /* SHOTPLUG_CTL2 SPT+ */
8092 #define  PORTE_HOTPLUG_ENABLE           (1 << 4)
8093 #define  PORTE_HOTPLUG_STATUS_MASK      (3 << 0)
8094 #define  PORTE_HOTPLUG_NO_DETECT        (0 << 0)
8095 #define  PORTE_HOTPLUG_SHORT_DETECT     (1 << 0)
8096 #define  PORTE_HOTPLUG_LONG_DETECT      (2 << 0)
8097
8098 /* This register is a reuse of PCH_PORT_HOTPLUG register. The
8099  * functionality covered in PCH_PORT_HOTPLUG is split into
8100  * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
8101  */
8102
8103 #define SHOTPLUG_CTL_DDI                                _MMIO(0xc4030)
8104 #define   SHOTPLUG_CTL_DDI_HPD_ENABLE(port)             (0x8 << (4 * (port)))
8105 #define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port)        (0x3 << (4 * (port)))
8106 #define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port)          (0x0 << (4 * (port)))
8107 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port)       (0x1 << (4 * (port)))
8108 #define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port)        (0x2 << (4 * (port)))
8109 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port)  (0x3 << (4 * (port)))
8110
8111 #define SHOTPLUG_CTL_TC                         _MMIO(0xc4034)
8112 #define   ICP_TC_HPD_ENABLE(tc_port)            (8 << (tc_port) * 4)
8113
8114 #define SHPD_FILTER_CNT                         _MMIO(0xc4038)
8115 #define   SHPD_FILTER_CNT_500_ADJ               0x001D9
8116
8117 /* Icelake DSC Rate Control Range Parameter Registers */
8118 #define DSCA_RC_RANGE_PARAMETERS_0              _MMIO(0x6B240)
8119 #define DSCA_RC_RANGE_PARAMETERS_0_UDW          _MMIO(0x6B240 + 4)
8120 #define DSCC_RC_RANGE_PARAMETERS_0              _MMIO(0x6BA40)
8121 #define DSCC_RC_RANGE_PARAMETERS_0_UDW          _MMIO(0x6BA40 + 4)
8122 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB      (0x78208)
8123 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB  (0x78208 + 4)
8124 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB      (0x78308)
8125 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB  (0x78308 + 4)
8126 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC      (0x78408)
8127 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC  (0x78408 + 4)
8128 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC      (0x78508)
8129 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC  (0x78508 + 4)
8130 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8131                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
8132                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
8133 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8134                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
8135                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
8136 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8137                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
8138                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
8139 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8140                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
8141                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
8142 #define RC_BPG_OFFSET_SHIFT                     10
8143 #define RC_MAX_QP_SHIFT                         5
8144 #define RC_MIN_QP_SHIFT                         0
8145
8146 #define DSCA_RC_RANGE_PARAMETERS_1              _MMIO(0x6B248)
8147 #define DSCA_RC_RANGE_PARAMETERS_1_UDW          _MMIO(0x6B248 + 4)
8148 #define DSCC_RC_RANGE_PARAMETERS_1              _MMIO(0x6BA48)
8149 #define DSCC_RC_RANGE_PARAMETERS_1_UDW          _MMIO(0x6BA48 + 4)
8150 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB      (0x78210)
8151 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB  (0x78210 + 4)
8152 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB      (0x78310)
8153 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB  (0x78310 + 4)
8154 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC      (0x78410)
8155 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC  (0x78410 + 4)
8156 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC      (0x78510)
8157 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC  (0x78510 + 4)
8158 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8159                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
8160                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
8161 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8162                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
8163                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
8164 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8165                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
8166                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
8167 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8168                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
8169                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
8170
8171 #define DSCA_RC_RANGE_PARAMETERS_2              _MMIO(0x6B250)
8172 #define DSCA_RC_RANGE_PARAMETERS_2_UDW          _MMIO(0x6B250 + 4)
8173 #define DSCC_RC_RANGE_PARAMETERS_2              _MMIO(0x6BA50)
8174 #define DSCC_RC_RANGE_PARAMETERS_2_UDW          _MMIO(0x6BA50 + 4)
8175 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB      (0x78218)
8176 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB  (0x78218 + 4)
8177 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB      (0x78318)
8178 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB  (0x78318 + 4)
8179 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC      (0x78418)
8180 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC  (0x78418 + 4)
8181 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC      (0x78518)
8182 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC  (0x78518 + 4)
8183 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8184                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
8185                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
8186 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8187                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
8188                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
8189 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8190                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
8191                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
8192 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8193                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
8194                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
8195
8196 #define DSCA_RC_RANGE_PARAMETERS_3              _MMIO(0x6B258)
8197 #define DSCA_RC_RANGE_PARAMETERS_3_UDW          _MMIO(0x6B258 + 4)
8198 #define DSCC_RC_RANGE_PARAMETERS_3              _MMIO(0x6BA58)
8199 #define DSCC_RC_RANGE_PARAMETERS_3_UDW          _MMIO(0x6BA58 + 4)
8200 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB      (0x78220)
8201 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB  (0x78220 + 4)
8202 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB      (0x78320)
8203 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB  (0x78320 + 4)
8204 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC      (0x78420)
8205 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC  (0x78420 + 4)
8206 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC      (0x78520)
8207 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC  (0x78520 + 4)
8208 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8209                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
8210                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
8211 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8212                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
8213                                                         _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
8214 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)            _MMIO_PIPE((pipe) - PIPE_B, \
8215                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
8216                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
8217 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
8218                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
8219                                                         _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
8220
8221 #define   ICP_TC_HPD_LONG_DETECT(tc_port)       (2 << (tc_port) * 4)
8222 #define   ICP_TC_HPD_SHORT_DETECT(tc_port)      (1 << (tc_port) * 4)
8223
8224 #define ICP_DDI_HPD_ENABLE_MASK         (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
8225                                          SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
8226 #define ICP_TC_HPD_ENABLE_MASK          (ICP_TC_HPD_ENABLE(PORT_TC4) | \
8227                                          ICP_TC_HPD_ENABLE(PORT_TC3) | \
8228                                          ICP_TC_HPD_ENABLE(PORT_TC2) | \
8229                                          ICP_TC_HPD_ENABLE(PORT_TC1))
8230 #define TGP_DDI_HPD_ENABLE_MASK         (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
8231                                          SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
8232                                          SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
8233 #define TGP_TC_HPD_ENABLE_MASK          (ICP_TC_HPD_ENABLE(PORT_TC6) | \
8234                                          ICP_TC_HPD_ENABLE(PORT_TC5) | \
8235                                          ICP_TC_HPD_ENABLE_MASK)
8236
8237 #define _PCH_DPLL_A              0xc6014
8238 #define _PCH_DPLL_B              0xc6018
8239 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
8240
8241 #define _PCH_FPA0                0xc6040
8242 #define  FP_CB_TUNE             (0x3 << 22)
8243 #define _PCH_FPA1                0xc6044
8244 #define _PCH_FPB0                0xc6048
8245 #define _PCH_FPB1                0xc604c
8246 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
8247 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
8248
8249 #define PCH_DPLL_TEST           _MMIO(0xc606c)
8250
8251 #define PCH_DREF_CONTROL        _MMIO(0xC6200)
8252 #define  DREF_CONTROL_MASK      0x7fc3
8253 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0 << 13)
8254 #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2 << 13)
8255 #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3 << 13)
8256 #define  DREF_CPU_SOURCE_OUTPUT_MASK            (3 << 13)
8257 #define  DREF_SSC_SOURCE_DISABLE                (0 << 11)
8258 #define  DREF_SSC_SOURCE_ENABLE                 (2 << 11)
8259 #define  DREF_SSC_SOURCE_MASK                   (3 << 11)
8260 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0 << 9)
8261 #define  DREF_NONSPREAD_CK505_ENABLE            (1 << 9)
8262 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2 << 9)
8263 #define  DREF_NONSPREAD_SOURCE_MASK             (3 << 9)
8264 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0 << 7)
8265 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2 << 7)
8266 #define  DREF_SUPERSPREAD_SOURCE_MASK           (3 << 7)
8267 #define  DREF_SSC4_DOWNSPREAD                   (0 << 6)
8268 #define  DREF_SSC4_CENTERSPREAD                 (1 << 6)
8269 #define  DREF_SSC1_DISABLE                      (0 << 1)
8270 #define  DREF_SSC1_ENABLE                       (1 << 1)
8271 #define  DREF_SSC4_DISABLE                      (0)
8272 #define  DREF_SSC4_ENABLE                       (1)
8273
8274 #define PCH_RAWCLK_FREQ         _MMIO(0xc6204)
8275 #define  FDL_TP1_TIMER_SHIFT    12
8276 #define  FDL_TP1_TIMER_MASK     (3 << 12)
8277 #define  FDL_TP2_TIMER_SHIFT    10
8278 #define  FDL_TP2_TIMER_MASK     (3 << 10)
8279 #define  RAWCLK_FREQ_MASK       0x3ff
8280 #define  CNP_RAWCLK_DIV_MASK    (0x3ff << 16)
8281 #define  CNP_RAWCLK_DIV(div)    ((div) << 16)
8282 #define  CNP_RAWCLK_FRAC_MASK   (0xf << 26)
8283 #define  CNP_RAWCLK_DEN(den)    ((den) << 26)
8284 #define  ICP_RAWCLK_NUM(num)    ((num) << 11)
8285
8286 #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
8287
8288 #define PCH_SSC4_PARMS          _MMIO(0xc6210)
8289 #define PCH_SSC4_AUX_PARMS      _MMIO(0xc6214)
8290
8291 #define PCH_DPLL_SEL            _MMIO(0xc7000)
8292 #define  TRANS_DPLLB_SEL(pipe)          (1 << ((pipe) * 4))
8293 #define  TRANS_DPLLA_SEL(pipe)          0
8294 #define  TRANS_DPLL_ENABLE(pipe)        (1 << ((pipe) * 4 + 3))
8295
8296 /* transcoder */
8297
8298 #define _PCH_TRANS_HTOTAL_A             0xe0000
8299 #define  TRANS_HTOTAL_SHIFT             16
8300 #define  TRANS_HACTIVE_SHIFT            0
8301 #define _PCH_TRANS_HBLANK_A             0xe0004
8302 #define  TRANS_HBLANK_END_SHIFT         16
8303 #define  TRANS_HBLANK_START_SHIFT       0
8304 #define _PCH_TRANS_HSYNC_A              0xe0008
8305 #define  TRANS_HSYNC_END_SHIFT          16
8306 #define  TRANS_HSYNC_START_SHIFT        0
8307 #define _PCH_TRANS_VTOTAL_A             0xe000c
8308 #define  TRANS_VTOTAL_SHIFT             16
8309 #define  TRANS_VACTIVE_SHIFT            0
8310 #define _PCH_TRANS_VBLANK_A             0xe0010
8311 #define  TRANS_VBLANK_END_SHIFT         16
8312 #define  TRANS_VBLANK_START_SHIFT       0
8313 #define _PCH_TRANS_VSYNC_A              0xe0014
8314 #define  TRANS_VSYNC_END_SHIFT          16
8315 #define  TRANS_VSYNC_START_SHIFT        0
8316 #define _PCH_TRANS_VSYNCSHIFT_A         0xe0028
8317
8318 #define _PCH_TRANSA_DATA_M1     0xe0030
8319 #define _PCH_TRANSA_DATA_N1     0xe0034
8320 #define _PCH_TRANSA_DATA_M2     0xe0038
8321 #define _PCH_TRANSA_DATA_N2     0xe003c
8322 #define _PCH_TRANSA_LINK_M1     0xe0040
8323 #define _PCH_TRANSA_LINK_N1     0xe0044
8324 #define _PCH_TRANSA_LINK_M2     0xe0048
8325 #define _PCH_TRANSA_LINK_N2     0xe004c
8326
8327 /* Per-transcoder DIP controls (PCH) */
8328 #define _VIDEO_DIP_CTL_A         0xe0200
8329 #define _VIDEO_DIP_DATA_A        0xe0208
8330 #define _VIDEO_DIP_GCP_A         0xe0210
8331 #define  GCP_COLOR_INDICATION           (1 << 2)
8332 #define  GCP_DEFAULT_PHASE_ENABLE       (1 << 1)
8333 #define  GCP_AV_MUTE                    (1 << 0)
8334
8335 #define _VIDEO_DIP_CTL_B         0xe1200
8336 #define _VIDEO_DIP_DATA_B        0xe1208
8337 #define _VIDEO_DIP_GCP_B         0xe1210
8338
8339 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
8340 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
8341 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
8342
8343 /* Per-transcoder DIP controls (VLV) */
8344 #define _VLV_VIDEO_DIP_CTL_A            (VLV_DISPLAY_BASE + 0x60200)
8345 #define _VLV_VIDEO_DIP_DATA_A           (VLV_DISPLAY_BASE + 0x60208)
8346 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A   (VLV_DISPLAY_BASE + 0x60210)
8347
8348 #define _VLV_VIDEO_DIP_CTL_B            (VLV_DISPLAY_BASE + 0x61170)
8349 #define _VLV_VIDEO_DIP_DATA_B           (VLV_DISPLAY_BASE + 0x61174)
8350 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B   (VLV_DISPLAY_BASE + 0x61178)
8351
8352 #define _CHV_VIDEO_DIP_CTL_C            (VLV_DISPLAY_BASE + 0x611f0)
8353 #define _CHV_VIDEO_DIP_DATA_C           (VLV_DISPLAY_BASE + 0x611f4)
8354 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C   (VLV_DISPLAY_BASE + 0x611f8)
8355
8356 #define VLV_TVIDEO_DIP_CTL(pipe) \
8357         _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
8358                _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
8359 #define VLV_TVIDEO_DIP_DATA(pipe) \
8360         _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
8361                _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
8362 #define VLV_TVIDEO_DIP_GCP(pipe) \
8363         _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
8364                 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
8365
8366 /* Haswell DIP controls */
8367
8368 #define _HSW_VIDEO_DIP_CTL_A            0x60200
8369 #define _HSW_VIDEO_DIP_AVI_DATA_A       0x60220
8370 #define _HSW_VIDEO_DIP_VS_DATA_A        0x60260
8371 #define _HSW_VIDEO_DIP_SPD_DATA_A       0x602A0
8372 #define _HSW_VIDEO_DIP_GMP_DATA_A       0x602E0
8373 #define _HSW_VIDEO_DIP_VSC_DATA_A       0x60320
8374 #define _GLK_VIDEO_DIP_DRM_DATA_A       0x60440
8375 #define _HSW_VIDEO_DIP_AVI_ECC_A        0x60240
8376 #define _HSW_VIDEO_DIP_VS_ECC_A         0x60280
8377 #define _HSW_VIDEO_DIP_SPD_ECC_A        0x602C0
8378 #define _HSW_VIDEO_DIP_GMP_ECC_A        0x60300
8379 #define _HSW_VIDEO_DIP_VSC_ECC_A        0x60344
8380 #define _HSW_VIDEO_DIP_GCP_A            0x60210
8381
8382 #define _HSW_VIDEO_DIP_CTL_B            0x61200
8383 #define _HSW_VIDEO_DIP_AVI_DATA_B       0x61220
8384 #define _HSW_VIDEO_DIP_VS_DATA_B        0x61260
8385 #define _HSW_VIDEO_DIP_SPD_DATA_B       0x612A0
8386 #define _HSW_VIDEO_DIP_GMP_DATA_B       0x612E0
8387 #define _HSW_VIDEO_DIP_VSC_DATA_B       0x61320
8388 #define _GLK_VIDEO_DIP_DRM_DATA_B       0x61440
8389 #define _HSW_VIDEO_DIP_BVI_ECC_B        0x61240
8390 #define _HSW_VIDEO_DIP_VS_ECC_B         0x61280
8391 #define _HSW_VIDEO_DIP_SPD_ECC_B        0x612C0
8392 #define _HSW_VIDEO_DIP_GMP_ECC_B        0x61300
8393 #define _HSW_VIDEO_DIP_VSC_ECC_B        0x61344
8394 #define _HSW_VIDEO_DIP_GCP_B            0x61210
8395
8396 /* Icelake PPS_DATA and _ECC DIP Registers.
8397  * These are available for transcoders B,C and eDP.
8398  * Adding the _A so as to reuse the _MMIO_TRANS2
8399  * definition, with which it offsets to the right location.
8400  */
8401
8402 #define _ICL_VIDEO_DIP_PPS_DATA_A       0x60350
8403 #define _ICL_VIDEO_DIP_PPS_DATA_B       0x61350
8404 #define _ICL_VIDEO_DIP_PPS_ECC_A        0x603D4
8405 #define _ICL_VIDEO_DIP_PPS_ECC_B        0x613D4
8406
8407 #define HSW_TVIDEO_DIP_CTL(trans)               _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
8408 #define HSW_TVIDEO_DIP_GCP(trans)               _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
8409 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i)       _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
8410 #define HSW_TVIDEO_DIP_VS_DATA(trans, i)        _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
8411 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i)       _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
8412 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i)       _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
8413 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i)       _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
8414 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i)       _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
8415 #define ICL_VIDEO_DIP_PPS_DATA(trans, i)        _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
8416 #define ICL_VIDEO_DIP_PPS_ECC(trans, i)         _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
8417
8418 #define _HSW_STEREO_3D_CTL_A            0x70020
8419 #define   S3D_ENABLE                    (1 << 31)
8420 #define _HSW_STEREO_3D_CTL_B            0x71020
8421
8422 #define HSW_STEREO_3D_CTL(trans)        _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
8423
8424 #define _PCH_TRANS_HTOTAL_B          0xe1000
8425 #define _PCH_TRANS_HBLANK_B          0xe1004
8426 #define _PCH_TRANS_HSYNC_B           0xe1008
8427 #define _PCH_TRANS_VTOTAL_B          0xe100c
8428 #define _PCH_TRANS_VBLANK_B          0xe1010
8429 #define _PCH_TRANS_VSYNC_B           0xe1014
8430 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
8431
8432 #define PCH_TRANS_HTOTAL(pipe)          _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
8433 #define PCH_TRANS_HBLANK(pipe)          _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
8434 #define PCH_TRANS_HSYNC(pipe)           _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
8435 #define PCH_TRANS_VTOTAL(pipe)          _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
8436 #define PCH_TRANS_VBLANK(pipe)          _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
8437 #define PCH_TRANS_VSYNC(pipe)           _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
8438 #define PCH_TRANS_VSYNCSHIFT(pipe)      _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
8439
8440 #define _PCH_TRANSB_DATA_M1     0xe1030
8441 #define _PCH_TRANSB_DATA_N1     0xe1034
8442 #define _PCH_TRANSB_DATA_M2     0xe1038
8443 #define _PCH_TRANSB_DATA_N2     0xe103c
8444 #define _PCH_TRANSB_LINK_M1     0xe1040
8445 #define _PCH_TRANSB_LINK_N1     0xe1044
8446 #define _PCH_TRANSB_LINK_M2     0xe1048
8447 #define _PCH_TRANSB_LINK_N2     0xe104c
8448
8449 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
8450 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
8451 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
8452 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
8453 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
8454 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
8455 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
8456 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
8457
8458 #define _PCH_TRANSACONF              0xf0008
8459 #define _PCH_TRANSBCONF              0xf1008
8460 #define PCH_TRANSCONF(pipe)     _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
8461 #define LPT_TRANSCONF           PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
8462 #define  TRANS_DISABLE          (0 << 31)
8463 #define  TRANS_ENABLE           (1 << 31)
8464 #define  TRANS_STATE_MASK       (1 << 30)
8465 #define  TRANS_STATE_DISABLE    (0 << 30)
8466 #define  TRANS_STATE_ENABLE     (1 << 30)
8467 #define  TRANS_FRAME_START_DELAY_MASK   (3 << 27) /* ibx */
8468 #define  TRANS_FRAME_START_DELAY(x)     ((x) << 27) /* ibx: 0-3 */
8469 #define  TRANS_INTERLACE_MASK   (7 << 21)
8470 #define  TRANS_PROGRESSIVE      (0 << 21)
8471 #define  TRANS_INTERLACED       (3 << 21)
8472 #define  TRANS_LEGACY_INTERLACED_ILK (2 << 21)
8473 #define  TRANS_8BPC             (0 << 5)
8474 #define  TRANS_10BPC            (1 << 5)
8475 #define  TRANS_6BPC             (2 << 5)
8476 #define  TRANS_12BPC            (3 << 5)
8477
8478 #define _TRANSA_CHICKEN1         0xf0060
8479 #define _TRANSB_CHICKEN1         0xf1060
8480 #define TRANS_CHICKEN1(pipe)    _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
8481 #define  TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE     (1 << 10)
8482 #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE      (1 << 4)
8483 #define _TRANSA_CHICKEN2         0xf0064
8484 #define _TRANSB_CHICKEN2         0xf1064
8485 #define TRANS_CHICKEN2(pipe)    _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
8486 #define  TRANS_CHICKEN2_TIMING_OVERRIDE                 (1 << 31)
8487 #define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED           (1 << 29)
8488 #define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK          (3 << 27)
8489 #define  TRANS_CHICKEN2_FRAME_START_DELAY(x)            ((x) << 27) /* 0-3 */
8490 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER      (1 << 26)
8491 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH   (1 << 25)
8492
8493 #define SOUTH_CHICKEN1          _MMIO(0xc2000)
8494 #define  FDIA_PHASE_SYNC_SHIFT_OVR      19
8495 #define  FDIA_PHASE_SYNC_SHIFT_EN       18
8496 #define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8497 #define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8498 #define  FDI_BC_BIFURCATION_SELECT      (1 << 12)
8499 #define  CHASSIS_CLK_REQ_DURATION_MASK  (0xf << 8)
8500 #define  CHASSIS_CLK_REQ_DURATION(x)    ((x) << 8)
8501 #define  SPT_PWM_GRANULARITY            (1 << 0)
8502 #define SOUTH_CHICKEN2          _MMIO(0xc2004)
8503 #define  FDI_MPHY_IOSFSB_RESET_STATUS   (1 << 13)
8504 #define  FDI_MPHY_IOSFSB_RESET_CTL      (1 << 12)
8505 #define  LPT_PWM_GRANULARITY            (1 << 5)
8506 #define  DPLS_EDP_PPS_FIX_DIS           (1 << 0)
8507
8508 #define _FDI_RXA_CHICKEN        0xc200c
8509 #define _FDI_RXB_CHICKEN        0xc2010
8510 #define  FDI_RX_PHASE_SYNC_POINTER_OVR  (1 << 1)
8511 #define  FDI_RX_PHASE_SYNC_POINTER_EN   (1 << 0)
8512 #define FDI_RX_CHICKEN(pipe)    _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
8513
8514 #define SOUTH_DSPCLK_GATE_D     _MMIO(0xc2020)
8515 #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
8516 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
8517 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
8518 #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
8519 #define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
8520 #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
8521
8522 /* CPU: FDI_TX */
8523 #define _FDI_TXA_CTL            0x60100
8524 #define _FDI_TXB_CTL            0x61100
8525 #define FDI_TX_CTL(pipe)        _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
8526 #define  FDI_TX_DISABLE         (0 << 31)
8527 #define  FDI_TX_ENABLE          (1 << 31)
8528 #define  FDI_LINK_TRAIN_PATTERN_1       (0 << 28)
8529 #define  FDI_LINK_TRAIN_PATTERN_2       (1 << 28)
8530 #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2 << 28)
8531 #define  FDI_LINK_TRAIN_NONE            (3 << 28)
8532 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0 << 25)
8533 #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1 << 25)
8534 #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2 << 25)
8535 #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3 << 25)
8536 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8537 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
8538 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2 << 22)
8539 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3 << 22)
8540 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8541    SNB has different settings. */
8542 /* SNB A-stepping */
8543 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A         (0x38 << 22)
8544 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A         (0x02 << 22)
8545 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A       (0x01 << 22)
8546 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A         (0x0 << 22)
8547 /* SNB B-stepping */
8548 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B         (0x0 << 22)
8549 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B         (0x3a << 22)
8550 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B       (0x39 << 22)
8551 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B         (0x38 << 22)
8552 #define  FDI_LINK_TRAIN_VOL_EMP_MASK            (0x3f << 22)
8553 #define  FDI_DP_PORT_WIDTH_SHIFT                19
8554 #define  FDI_DP_PORT_WIDTH_MASK                 (7 << FDI_DP_PORT_WIDTH_SHIFT)
8555 #define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8556 #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1 << 18)
8557 /* Ironlake: hardwired to 1 */
8558 #define  FDI_TX_PLL_ENABLE              (1 << 14)
8559
8560 /* Ivybridge has different bits for lolz */
8561 #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0 << 8)
8562 #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1 << 8)
8563 #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2 << 8)
8564 #define  FDI_LINK_TRAIN_NONE_IVB            (3 << 8)
8565
8566 /* both Tx and Rx */
8567 #define  FDI_COMPOSITE_SYNC             (1 << 11)
8568 #define  FDI_LINK_TRAIN_AUTO            (1 << 10)
8569 #define  FDI_SCRAMBLING_ENABLE          (0 << 7)
8570 #define  FDI_SCRAMBLING_DISABLE         (1 << 7)
8571
8572 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8573 #define _FDI_RXA_CTL             0xf000c
8574 #define _FDI_RXB_CTL             0xf100c
8575 #define FDI_RX_CTL(pipe)        _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
8576 #define  FDI_RX_ENABLE          (1 << 31)
8577 /* train, dp width same as FDI_TX */
8578 #define  FDI_FS_ERRC_ENABLE             (1 << 27)
8579 #define  FDI_FE_ERRC_ENABLE             (1 << 26)
8580 #define  FDI_RX_POLARITY_REVERSED_LPT   (1 << 16)
8581 #define  FDI_8BPC                       (0 << 16)
8582 #define  FDI_10BPC                      (1 << 16)
8583 #define  FDI_6BPC                       (2 << 16)
8584 #define  FDI_12BPC                      (3 << 16)
8585 #define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1 << 15)
8586 #define  FDI_DMI_LINK_REVERSE_MASK      (1 << 14)
8587 #define  FDI_RX_PLL_ENABLE              (1 << 13)
8588 #define  FDI_FS_ERR_CORRECT_ENABLE      (1 << 11)
8589 #define  FDI_FE_ERR_CORRECT_ENABLE      (1 << 10)
8590 #define  FDI_FS_ERR_REPORT_ENABLE       (1 << 9)
8591 #define  FDI_FE_ERR_REPORT_ENABLE       (1 << 8)
8592 #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1 << 6)
8593 #define  FDI_PCDCLK                     (1 << 4)
8594 /* CPT */
8595 #define  FDI_AUTO_TRAINING                      (1 << 10)
8596 #define  FDI_LINK_TRAIN_PATTERN_1_CPT           (0 << 8)
8597 #define  FDI_LINK_TRAIN_PATTERN_2_CPT           (1 << 8)
8598 #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT        (2 << 8)
8599 #define  FDI_LINK_TRAIN_NORMAL_CPT              (3 << 8)
8600 #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT        (3 << 8)
8601
8602 #define _FDI_RXA_MISC                   0xf0010
8603 #define _FDI_RXB_MISC                   0xf1010
8604 #define  FDI_RX_PWRDN_LANE1_MASK        (3 << 26)
8605 #define  FDI_RX_PWRDN_LANE1_VAL(x)      ((x) << 26)
8606 #define  FDI_RX_PWRDN_LANE0_MASK        (3 << 24)
8607 #define  FDI_RX_PWRDN_LANE0_VAL(x)      ((x) << 24)
8608 #define  FDI_RX_TP1_TO_TP2_48           (2 << 20)
8609 #define  FDI_RX_TP1_TO_TP2_64           (3 << 20)
8610 #define  FDI_RX_FDI_DELAY_90            (0x90 << 0)
8611 #define FDI_RX_MISC(pipe)       _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
8612
8613 #define _FDI_RXA_TUSIZE1        0xf0030
8614 #define _FDI_RXA_TUSIZE2        0xf0038
8615 #define _FDI_RXB_TUSIZE1        0xf1030
8616 #define _FDI_RXB_TUSIZE2        0xf1038
8617 #define FDI_RX_TUSIZE1(pipe)    _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
8618 #define FDI_RX_TUSIZE2(pipe)    _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
8619
8620 /* FDI_RX interrupt register format */
8621 #define FDI_RX_INTER_LANE_ALIGN         (1 << 10)
8622 #define FDI_RX_SYMBOL_LOCK              (1 << 9) /* train 2 */
8623 #define FDI_RX_BIT_LOCK                 (1 << 8) /* train 1 */
8624 #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1 << 7)
8625 #define FDI_RX_FS_CODE_ERR              (1 << 6)
8626 #define FDI_RX_FE_CODE_ERR              (1 << 5)
8627 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1 << 4)
8628 #define FDI_RX_HDCP_LINK_FAIL           (1 << 3)
8629 #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1 << 2)
8630 #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1 << 1)
8631 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
8632
8633 #define _FDI_RXA_IIR            0xf0014
8634 #define _FDI_RXA_IMR            0xf0018
8635 #define _FDI_RXB_IIR            0xf1014
8636 #define _FDI_RXB_IMR            0xf1018
8637 #define FDI_RX_IIR(pipe)        _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
8638 #define FDI_RX_IMR(pipe)        _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
8639
8640 #define FDI_PLL_CTL_1           _MMIO(0xfe000)
8641 #define FDI_PLL_CTL_2           _MMIO(0xfe004)
8642
8643 #define PCH_LVDS        _MMIO(0xe1180)
8644 #define  LVDS_DETECTED  (1 << 1)
8645
8646 #define _PCH_DP_B               0xe4100
8647 #define PCH_DP_B                _MMIO(_PCH_DP_B)
8648 #define _PCH_DPB_AUX_CH_CTL     0xe4110
8649 #define _PCH_DPB_AUX_CH_DATA1   0xe4114
8650 #define _PCH_DPB_AUX_CH_DATA2   0xe4118
8651 #define _PCH_DPB_AUX_CH_DATA3   0xe411c
8652 #define _PCH_DPB_AUX_CH_DATA4   0xe4120
8653 #define _PCH_DPB_AUX_CH_DATA5   0xe4124
8654
8655 #define _PCH_DP_C               0xe4200
8656 #define PCH_DP_C                _MMIO(_PCH_DP_C)
8657 #define _PCH_DPC_AUX_CH_CTL     0xe4210
8658 #define _PCH_DPC_AUX_CH_DATA1   0xe4214
8659 #define _PCH_DPC_AUX_CH_DATA2   0xe4218
8660 #define _PCH_DPC_AUX_CH_DATA3   0xe421c
8661 #define _PCH_DPC_AUX_CH_DATA4   0xe4220
8662 #define _PCH_DPC_AUX_CH_DATA5   0xe4224
8663
8664 #define _PCH_DP_D               0xe4300
8665 #define PCH_DP_D                _MMIO(_PCH_DP_D)
8666 #define _PCH_DPD_AUX_CH_CTL     0xe4310
8667 #define _PCH_DPD_AUX_CH_DATA1   0xe4314
8668 #define _PCH_DPD_AUX_CH_DATA2   0xe4318
8669 #define _PCH_DPD_AUX_CH_DATA3   0xe431c
8670 #define _PCH_DPD_AUX_CH_DATA4   0xe4320
8671 #define _PCH_DPD_AUX_CH_DATA5   0xe4324
8672
8673 #define PCH_DP_AUX_CH_CTL(aux_ch)               _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
8674 #define PCH_DP_AUX_CH_DATA(aux_ch, i)   _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
8675
8676 /* CPT */
8677 #define _TRANS_DP_CTL_A         0xe0300
8678 #define _TRANS_DP_CTL_B         0xe1300
8679 #define _TRANS_DP_CTL_C         0xe2300
8680 #define TRANS_DP_CTL(pipe)      _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
8681 #define  TRANS_DP_OUTPUT_ENABLE (1 << 31)
8682 #define  TRANS_DP_PORT_SEL_MASK         (3 << 29)
8683 #define  TRANS_DP_PORT_SEL_NONE         (3 << 29)
8684 #define  TRANS_DP_PORT_SEL(port)        (((port) - PORT_B) << 29)
8685 #define  TRANS_DP_AUDIO_ONLY    (1 << 26)
8686 #define  TRANS_DP_ENH_FRAMING   (1 << 18)
8687 #define  TRANS_DP_8BPC          (0 << 9)
8688 #define  TRANS_DP_10BPC         (1 << 9)
8689 #define  TRANS_DP_6BPC          (2 << 9)
8690 #define  TRANS_DP_12BPC         (3 << 9)
8691 #define  TRANS_DP_BPC_MASK      (3 << 9)
8692 #define  TRANS_DP_VSYNC_ACTIVE_HIGH     (1 << 4)
8693 #define  TRANS_DP_VSYNC_ACTIVE_LOW      0
8694 #define  TRANS_DP_HSYNC_ACTIVE_HIGH     (1 << 3)
8695 #define  TRANS_DP_HSYNC_ACTIVE_LOW      0
8696 #define  TRANS_DP_SYNC_MASK     (3 << 3)
8697
8698 /* SNB eDP training params */
8699 /* SNB A-stepping */
8700 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A         (0x38 << 22)
8701 #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A         (0x02 << 22)
8702 #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A       (0x01 << 22)
8703 #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A         (0x0 << 22)
8704 /* SNB B-stepping */
8705 #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B     (0x0 << 22)
8706 #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B       (0x1 << 22)
8707 #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B     (0x3a << 22)
8708 #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B   (0x39 << 22)
8709 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B    (0x38 << 22)
8710 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB        (0x3f << 22)
8711
8712 /* IVB */
8713 #define EDP_LINK_TRAIN_400MV_0DB_IVB            (0x24 << 22)
8714 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB          (0x2a << 22)
8715 #define EDP_LINK_TRAIN_400MV_6DB_IVB            (0x2f << 22)
8716 #define EDP_LINK_TRAIN_600MV_0DB_IVB            (0x30 << 22)
8717 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB          (0x36 << 22)
8718 #define EDP_LINK_TRAIN_800MV_0DB_IVB            (0x38 << 22)
8719 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB          (0x3e << 22)
8720
8721 /* legacy values */
8722 #define EDP_LINK_TRAIN_500MV_0DB_IVB            (0x00 << 22)
8723 #define EDP_LINK_TRAIN_1000MV_0DB_IVB           (0x20 << 22)
8724 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB          (0x02 << 22)
8725 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB         (0x22 << 22)
8726 #define EDP_LINK_TRAIN_1000MV_6DB_IVB           (0x23 << 22)
8727
8728 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB        (0x3f << 22)
8729
8730 #define  VLV_PMWGICZ                            _MMIO(0x1300a4)
8731
8732 #define  RC6_LOCATION                           _MMIO(0xD40)
8733 #define    RC6_CTX_IN_DRAM                      (1 << 0)
8734 #define  RC6_CTX_BASE                           _MMIO(0xD48)
8735 #define    RC6_CTX_BASE_MASK                    0xFFFFFFF0
8736 #define  PWRCTX_MAXCNT_RCSUNIT                  _MMIO(0x2054)
8737 #define  PWRCTX_MAXCNT_VCSUNIT0                 _MMIO(0x12054)
8738 #define  PWRCTX_MAXCNT_BCSUNIT                  _MMIO(0x22054)
8739 #define  PWRCTX_MAXCNT_VECSUNIT                 _MMIO(0x1A054)
8740 #define  PWRCTX_MAXCNT_VCSUNIT1                 _MMIO(0x1C054)
8741 #define    IDLE_TIME_MASK                       0xFFFFF
8742 #define  FORCEWAKE                              _MMIO(0xA18C)
8743 #define  FORCEWAKE_VLV                          _MMIO(0x1300b0)
8744 #define  FORCEWAKE_ACK_VLV                      _MMIO(0x1300b4)
8745 #define  FORCEWAKE_MEDIA_VLV                    _MMIO(0x1300b8)
8746 #define  FORCEWAKE_ACK_MEDIA_VLV                _MMIO(0x1300bc)
8747 #define  FORCEWAKE_ACK_HSW                      _MMIO(0x130044)
8748 #define  FORCEWAKE_ACK                          _MMIO(0x130090)
8749 #define  VLV_GTLC_WAKE_CTRL                     _MMIO(0x130090)
8750 #define   VLV_GTLC_RENDER_CTX_EXISTS            (1 << 25)
8751 #define   VLV_GTLC_MEDIA_CTX_EXISTS             (1 << 24)
8752 #define   VLV_GTLC_ALLOWWAKEREQ                 (1 << 0)
8753
8754 #define  VLV_GTLC_PW_STATUS                     _MMIO(0x130094)
8755 #define   VLV_GTLC_ALLOWWAKEACK                 (1 << 0)
8756 #define   VLV_GTLC_ALLOWWAKEERR                 (1 << 1)
8757 #define   VLV_GTLC_PW_MEDIA_STATUS_MASK         (1 << 5)
8758 #define   VLV_GTLC_PW_RENDER_STATUS_MASK        (1 << 7)
8759 #define  FORCEWAKE_MT                           _MMIO(0xa188) /* multi-threaded */
8760 #define  FORCEWAKE_MEDIA_GEN9                   _MMIO(0xa270)
8761 #define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)         _MMIO(0xa540 + (n) * 4)
8762 #define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)         _MMIO(0xa560 + (n) * 4)
8763 #define  FORCEWAKE_RENDER_GEN9                  _MMIO(0xa278)
8764 #define  FORCEWAKE_BLITTER_GEN9                 _MMIO(0xa188)
8765 #define  FORCEWAKE_ACK_MEDIA_GEN9               _MMIO(0x0D88)
8766 #define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)     _MMIO(0x0D50 + (n) * 4)
8767 #define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)     _MMIO(0x0D70 + (n) * 4)
8768 #define  FORCEWAKE_ACK_RENDER_GEN9              _MMIO(0x0D84)
8769 #define  FORCEWAKE_ACK_BLITTER_GEN9             _MMIO(0x130044)
8770 #define   FORCEWAKE_KERNEL                      BIT(0)
8771 #define   FORCEWAKE_USER                        BIT(1)
8772 #define   FORCEWAKE_KERNEL_FALLBACK             BIT(15)
8773 #define  FORCEWAKE_MT_ACK                       _MMIO(0x130040)
8774 #define  ECOBUS                                 _MMIO(0xa180)
8775 #define    FORCEWAKE_MT_ENABLE                  (1 << 5)
8776 #define  VLV_SPAREG2H                           _MMIO(0xA194)
8777 #define  GEN9_PWRGT_DOMAIN_STATUS               _MMIO(0xA2A0)
8778 #define   GEN9_PWRGT_MEDIA_STATUS_MASK          (1 << 0)
8779 #define   GEN9_PWRGT_RENDER_STATUS_MASK         (1 << 1)
8780
8781 #define POWERGATE_ENABLE                        _MMIO(0xa210)
8782 #define    VDN_HCP_POWERGATE_ENABLE(n)          BIT(((n) * 2) + 3)
8783 #define    VDN_MFX_POWERGATE_ENABLE(n)          BIT(((n) * 2) + 4)
8784
8785 #define  GTFIFODBG                              _MMIO(0x120000)
8786 #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV    (0x1f << 20)
8787 #define    GT_FIFO_FREE_ENTRIES_CHV             (0x7f << 13)
8788 #define    GT_FIFO_SBDROPERR                    (1 << 6)
8789 #define    GT_FIFO_BLOBDROPERR                  (1 << 5)
8790 #define    GT_FIFO_SB_READ_ABORTERR             (1 << 4)
8791 #define    GT_FIFO_DROPERR                      (1 << 3)
8792 #define    GT_FIFO_OVFERR                       (1 << 2)
8793 #define    GT_FIFO_IAWRERR                      (1 << 1)
8794 #define    GT_FIFO_IARDERR                      (1 << 0)
8795
8796 #define  GTFIFOCTL                              _MMIO(0x120008)
8797 #define    GT_FIFO_FREE_ENTRIES_MASK            0x7f
8798 #define    GT_FIFO_NUM_RESERVED_ENTRIES         20
8799 #define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL   (1 << 12)
8800 #define    GT_FIFO_CTL_RC6_POLICY_STALL         (1 << 11)
8801
8802 #define  HSW_IDICR                              _MMIO(0x9008)
8803 #define    IDIHASHMSK(x)                        (((x) & 0x3f) << 16)
8804 #define  HSW_EDRAM_CAP                          _MMIO(0x120010)
8805 #define    EDRAM_ENABLED                        0x1
8806 #define    EDRAM_NUM_BANKS(cap)                 (((cap) >> 1) & 0xf)
8807 #define    EDRAM_WAYS_IDX(cap)                  (((cap) >> 5) & 0x7)
8808 #define    EDRAM_SETS_IDX(cap)                  (((cap) >> 8) & 0x3)
8809
8810 #define GEN6_UCGCTL1                            _MMIO(0x9400)
8811 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE                (1 << 22)
8812 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE              (1 << 16)
8813 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE                (1 << 5)
8814 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE                 (1 << 7)
8815
8816 #define GEN6_UCGCTL2                            _MMIO(0x9404)
8817 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE                 (1 << 31)
8818 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE                (1 << 30)
8819 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE                (1 << 22)
8820 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE                (1 << 13)
8821 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE               (1 << 12)
8822 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE                (1 << 11)
8823
8824 #define GEN6_UCGCTL3                            _MMIO(0x9408)
8825 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE               (1 << 20)
8826
8827 #define GEN7_UCGCTL4                            _MMIO(0x940c)
8828 #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE       (1 << 25)
8829 #define  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE      (1 << 14)
8830
8831 #define GEN6_RCGCTL1                            _MMIO(0x9410)
8832 #define GEN6_RCGCTL2                            _MMIO(0x9414)
8833 #define GEN6_RSTCTL                             _MMIO(0x9420)
8834
8835 #define GEN8_UCGCTL6                            _MMIO(0x9430)
8836 #define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE      (1 << 24)
8837 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE       (1 << 14)
8838 #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
8839
8840 #define GEN6_GFXPAUSE                           _MMIO(0xA000)
8841 #define GEN6_RPNSWREQ                           _MMIO(0xA008)
8842 #define   GEN6_TURBO_DISABLE                    (1 << 31)
8843 #define   GEN6_FREQUENCY(x)                     ((x) << 25)
8844 #define   HSW_FREQUENCY(x)                      ((x) << 24)
8845 #define   GEN9_FREQUENCY(x)                     ((x) << 23)
8846 #define   GEN6_OFFSET(x)                        ((x) << 19)
8847 #define   GEN6_AGGRESSIVE_TURBO                 (0 << 15)
8848 #define GEN6_RC_VIDEO_FREQ                      _MMIO(0xA00C)
8849 #define GEN6_RC_CONTROL                         _MMIO(0xA090)
8850 #define   GEN6_RC_CTL_RC6pp_ENABLE              (1 << 16)
8851 #define   GEN6_RC_CTL_RC6p_ENABLE               (1 << 17)
8852 #define   GEN6_RC_CTL_RC6_ENABLE                (1 << 18)
8853 #define   GEN6_RC_CTL_RC1e_ENABLE               (1 << 20)
8854 #define   GEN6_RC_CTL_RC7_ENABLE                (1 << 22)
8855 #define   VLV_RC_CTL_CTX_RST_PARALLEL           (1 << 24)
8856 #define   GEN7_RC_CTL_TO_MODE                   (1 << 28)
8857 #define   GEN6_RC_CTL_EI_MODE(x)                ((x) << 27)
8858 #define   GEN6_RC_CTL_HW_ENABLE                 (1 << 31)
8859 #define GEN6_RP_DOWN_TIMEOUT                    _MMIO(0xA010)
8860 #define GEN6_RP_INTERRUPT_LIMITS                _MMIO(0xA014)
8861 #define GEN6_RPSTAT1                            _MMIO(0xA01C)
8862 #define   GEN6_CAGF_SHIFT                       8
8863 #define   HSW_CAGF_SHIFT                        7
8864 #define   GEN9_CAGF_SHIFT                       23
8865 #define   GEN6_CAGF_MASK                        (0x7f << GEN6_CAGF_SHIFT)
8866 #define   HSW_CAGF_MASK                         (0x7f << HSW_CAGF_SHIFT)
8867 #define   GEN9_CAGF_MASK                        (0x1ff << GEN9_CAGF_SHIFT)
8868 #define GEN6_RP_CONTROL                         _MMIO(0xA024)
8869 #define   GEN6_RP_MEDIA_TURBO                   (1 << 11)
8870 #define   GEN6_RP_MEDIA_MODE_MASK               (3 << 9)
8871 #define   GEN6_RP_MEDIA_HW_TURBO_MODE           (3 << 9)
8872 #define   GEN6_RP_MEDIA_HW_NORMAL_MODE          (2 << 9)
8873 #define   GEN6_RP_MEDIA_HW_MODE                 (1 << 9)
8874 #define   GEN6_RP_MEDIA_SW_MODE                 (0 << 9)
8875 #define   GEN6_RP_MEDIA_IS_GFX                  (1 << 8)
8876 #define   GEN6_RP_ENABLE                        (1 << 7)
8877 #define   GEN6_RP_UP_IDLE_MIN                   (0x1 << 3)
8878 #define   GEN6_RP_UP_BUSY_AVG                   (0x2 << 3)
8879 #define   GEN6_RP_UP_BUSY_CONT                  (0x4 << 3)
8880 #define   GEN6_RP_DOWN_IDLE_AVG                 (0x2 << 0)
8881 #define   GEN6_RP_DOWN_IDLE_CONT                (0x1 << 0)
8882 #define GEN6_RP_UP_THRESHOLD                    _MMIO(0xA02C)
8883 #define GEN6_RP_DOWN_THRESHOLD                  _MMIO(0xA030)
8884 #define GEN6_RP_CUR_UP_EI                       _MMIO(0xA050)
8885 #define   GEN6_RP_EI_MASK                       0xffffff
8886 #define   GEN6_CURICONT_MASK                    GEN6_RP_EI_MASK
8887 #define GEN6_RP_CUR_UP                          _MMIO(0xA054)
8888 #define   GEN6_CURBSYTAVG_MASK                  GEN6_RP_EI_MASK
8889 #define GEN6_RP_PREV_UP                         _MMIO(0xA058)
8890 #define GEN6_RP_CUR_DOWN_EI                     _MMIO(0xA05C)
8891 #define   GEN6_CURIAVG_MASK                     GEN6_RP_EI_MASK
8892 #define GEN6_RP_CUR_DOWN                        _MMIO(0xA060)
8893 #define GEN6_RP_PREV_DOWN                       _MMIO(0xA064)
8894 #define GEN6_RP_UP_EI                           _MMIO(0xA068)
8895 #define GEN6_RP_DOWN_EI                         _MMIO(0xA06C)
8896 #define GEN6_RP_IDLE_HYSTERSIS                  _MMIO(0xA070)
8897 #define GEN6_RPDEUHWTC                          _MMIO(0xA080)
8898 #define GEN6_RPDEUC                             _MMIO(0xA084)
8899 #define GEN6_RPDEUCSW                           _MMIO(0xA088)
8900 #define GEN6_RC_STATE                           _MMIO(0xA094)
8901 #define   RC_SW_TARGET_STATE_SHIFT              16
8902 #define   RC_SW_TARGET_STATE_MASK               (7 << RC_SW_TARGET_STATE_SHIFT)
8903 #define GEN6_RC1_WAKE_RATE_LIMIT                _MMIO(0xA098)
8904 #define GEN6_RC6_WAKE_RATE_LIMIT                _MMIO(0xA09C)
8905 #define GEN6_RC6pp_WAKE_RATE_LIMIT              _MMIO(0xA0A0)
8906 #define GEN10_MEDIA_WAKE_RATE_LIMIT             _MMIO(0xA0A0)
8907 #define GEN6_RC_EVALUATION_INTERVAL             _MMIO(0xA0A8)
8908 #define GEN6_RC_IDLE_HYSTERSIS                  _MMIO(0xA0AC)
8909 #define GEN6_RC_SLEEP                           _MMIO(0xA0B0)
8910 #define GEN6_RCUBMABDTMR                        _MMIO(0xA0B0)
8911 #define GEN6_RC1e_THRESHOLD                     _MMIO(0xA0B4)
8912 #define GEN6_RC6_THRESHOLD                      _MMIO(0xA0B8)
8913 #define GEN6_RC6p_THRESHOLD                     _MMIO(0xA0BC)
8914 #define VLV_RCEDATA                             _MMIO(0xA0BC)
8915 #define GEN6_RC6pp_THRESHOLD                    _MMIO(0xA0C0)
8916 #define GEN6_PMINTRMSK                          _MMIO(0xA168)
8917 #define   GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC   (1 << 31)
8918 #define   ARAT_EXPIRED_INTRMSK                  (1 << 9)
8919 #define GEN8_MISC_CTRL0                         _MMIO(0xA180)
8920 #define VLV_PWRDWNUPCTL                         _MMIO(0xA294)
8921 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS           _MMIO(0xA0C4)
8922 #define GEN9_RENDER_PG_IDLE_HYSTERESIS          _MMIO(0xA0C8)
8923 #define GEN9_PG_ENABLE                          _MMIO(0xA210)
8924 #define GEN9_RENDER_PG_ENABLE                   REG_BIT(0)
8925 #define GEN9_MEDIA_PG_ENABLE                    REG_BIT(1)
8926 #define GEN11_MEDIA_SAMPLER_PG_ENABLE           REG_BIT(2)
8927 #define GEN8_PUSHBUS_CONTROL                    _MMIO(0xA248)
8928 #define GEN8_PUSHBUS_ENABLE                     _MMIO(0xA250)
8929 #define GEN8_PUSHBUS_SHIFT                      _MMIO(0xA25C)
8930
8931 #define VLV_CHICKEN_3                           _MMIO(VLV_DISPLAY_BASE + 0x7040C)
8932 #define  PIXEL_OVERLAP_CNT_MASK                 (3 << 30)
8933 #define  PIXEL_OVERLAP_CNT_SHIFT                30
8934
8935 #define GEN6_PMISR                              _MMIO(0x44020)
8936 #define GEN6_PMIMR                              _MMIO(0x44024) /* rps_lock */
8937 #define GEN6_PMIIR                              _MMIO(0x44028)
8938 #define GEN6_PMIER                              _MMIO(0x4402C)
8939 #define  GEN6_PM_MBOX_EVENT                     (1 << 25)
8940 #define  GEN6_PM_THERMAL_EVENT                  (1 << 24)
8941
8942 /*
8943  * For Gen11 these are in the upper word of the GPM_WGBOXPERF
8944  * registers. Shifting is handled on accessing the imr and ier.
8945  */
8946 #define  GEN6_PM_RP_DOWN_TIMEOUT                (1 << 6)
8947 #define  GEN6_PM_RP_UP_THRESHOLD                (1 << 5)
8948 #define  GEN6_PM_RP_DOWN_THRESHOLD              (1 << 4)
8949 #define  GEN6_PM_RP_UP_EI_EXPIRED               (1 << 2)
8950 #define  GEN6_PM_RP_DOWN_EI_EXPIRED             (1 << 1)
8951 #define  GEN6_PM_RPS_EVENTS                     (GEN6_PM_RP_UP_EI_EXPIRED   | \
8952                                                  GEN6_PM_RP_UP_THRESHOLD    | \
8953                                                  GEN6_PM_RP_DOWN_EI_EXPIRED | \
8954                                                  GEN6_PM_RP_DOWN_THRESHOLD  | \
8955                                                  GEN6_PM_RP_DOWN_TIMEOUT)
8956
8957 #define GEN7_GT_SCRATCH(i)                      _MMIO(0x4F100 + (i) * 4)
8958 #define GEN7_GT_SCRATCH_REG_NUM                 8
8959
8960 #define VLV_GTLC_SURVIVABILITY_REG              _MMIO(0x130098)
8961 #define VLV_GFX_CLK_STATUS_BIT                  (1 << 3)
8962 #define VLV_GFX_CLK_FORCE_ON_BIT                (1 << 2)
8963
8964 #define GEN6_GT_GFX_RC6_LOCKED                  _MMIO(0x138104)
8965 #define VLV_COUNTER_CONTROL                     _MMIO(0x138104)
8966 #define   VLV_COUNT_RANGE_HIGH                  (1 << 15)
8967 #define   VLV_MEDIA_RC0_COUNT_EN                (1 << 5)
8968 #define   VLV_RENDER_RC0_COUNT_EN               (1 << 4)
8969 #define   VLV_MEDIA_RC6_COUNT_EN                (1 << 1)
8970 #define   VLV_RENDER_RC6_COUNT_EN               (1 << 0)
8971 #define GEN6_GT_GFX_RC6                         _MMIO(0x138108)
8972 #define VLV_GT_RENDER_RC6                       _MMIO(0x138108)
8973 #define VLV_GT_MEDIA_RC6                        _MMIO(0x13810C)
8974
8975 #define GEN6_GT_GFX_RC6p                        _MMIO(0x13810C)
8976 #define GEN6_GT_GFX_RC6pp                       _MMIO(0x138110)
8977 #define VLV_RENDER_C0_COUNT                     _MMIO(0x138118)
8978 #define VLV_MEDIA_C0_COUNT                      _MMIO(0x13811C)
8979
8980 #define GEN6_PCODE_MAILBOX                      _MMIO(0x138124)
8981 #define   GEN6_PCODE_READY                      (1 << 31)
8982 #define   GEN6_PCODE_ERROR_MASK                 0xFF
8983 #define     GEN6_PCODE_SUCCESS                  0x0
8984 #define     GEN6_PCODE_ILLEGAL_CMD              0x1
8985 #define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8986 #define     GEN6_PCODE_TIMEOUT                  0x3
8987 #define     GEN6_PCODE_UNIMPLEMENTED_CMD        0xFF
8988 #define     GEN7_PCODE_TIMEOUT                  0x2
8989 #define     GEN7_PCODE_ILLEGAL_DATA             0x3
8990 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8991 #define   GEN6_PCODE_WRITE_RC6VIDS              0x4
8992 #define   GEN6_PCODE_READ_RC6VIDS               0x5
8993 #define     GEN6_ENCODE_RC6_VID(mv)             (((mv) - 245) / 5)
8994 #define     GEN6_DECODE_RC6_VID(vids)           (((vids) * 5) + 245)
8995 #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ     0x18
8996 #define   GEN9_PCODE_READ_MEM_LATENCY           0x6
8997 #define     GEN9_MEM_LATENCY_LEVEL_MASK         0xFF
8998 #define     GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT    8
8999 #define     GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT    16
9000 #define     GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT    24
9001 #define   SKL_PCODE_LOAD_HDCP_KEYS              0x5
9002 #define   SKL_PCODE_CDCLK_CONTROL               0x7
9003 #define     SKL_CDCLK_PREPARE_FOR_CHANGE        0x3
9004 #define     SKL_CDCLK_READY_FOR_CHANGE          0x1
9005 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE       0x8
9006 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE        0x9
9007 #define   GEN6_READ_OC_PARAMS                   0xc
9008 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO        0xd
9009 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO   (0x0 << 8)
9010 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
9011 #define   GEN6_PCODE_READ_D_COMP                0x10
9012 #define   GEN6_PCODE_WRITE_D_COMP               0x11
9013 #define   HSW_PCODE_DE_WRITE_FREQ_REQ           0x17
9014 #define   DISPLAY_IPS_CONTROL                   0x19
9015             /* See also IPS_CTL */
9016 #define     IPS_PCODE_CONTROL                   (1 << 30)
9017 #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL  0x1A
9018 #define   GEN9_PCODE_SAGV_CONTROL               0x21
9019 #define     GEN9_SAGV_DISABLE                   0x0
9020 #define     GEN9_SAGV_IS_DISABLED               0x1
9021 #define     GEN9_SAGV_ENABLE                    0x3
9022 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US     0x23
9023 #define GEN6_PCODE_DATA                         _MMIO(0x138128)
9024 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT        8
9025 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT      16
9026 #define GEN6_PCODE_DATA1                        _MMIO(0x13812C)
9027
9028 #define GEN6_GT_CORE_STATUS             _MMIO(0x138060)
9029 #define   GEN6_CORE_CPD_STATE_MASK      (7 << 4)
9030 #define   GEN6_RCn_MASK                 7
9031 #define   GEN6_RC0                      0
9032 #define   GEN6_RC3                      2
9033 #define   GEN6_RC6                      3
9034 #define   GEN6_RC7                      4
9035
9036 #define GEN8_GT_SLICE_INFO              _MMIO(0x138064)
9037 #define   GEN8_LSLICESTAT_MASK          0x7
9038
9039 #define CHV_POWER_SS0_SIG1              _MMIO(0xa720)
9040 #define CHV_POWER_SS1_SIG1              _MMIO(0xa728)
9041 #define   CHV_SS_PG_ENABLE              (1 << 1)
9042 #define   CHV_EU08_PG_ENABLE            (1 << 9)
9043 #define   CHV_EU19_PG_ENABLE            (1 << 17)
9044 #define   CHV_EU210_PG_ENABLE           (1 << 25)
9045
9046 #define CHV_POWER_SS0_SIG2              _MMIO(0xa724)
9047 #define CHV_POWER_SS1_SIG2              _MMIO(0xa72c)
9048 #define   CHV_EU311_PG_ENABLE           (1 << 1)
9049
9050 #define GEN9_SLICE_PGCTL_ACK(slice)     _MMIO(0x804c + (slice) * 0x4)
9051 #define GEN10_SLICE_PGCTL_ACK(slice)    _MMIO(0x804c + ((slice) / 3) * 0x34 + \
9052                                               ((slice) % 3) * 0x4)
9053 #define   GEN9_PGCTL_SLICE_ACK          (1 << 0)
9054 #define   GEN9_PGCTL_SS_ACK(subslice)   (1 << (2 + (subslice) * 2))
9055 #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
9056
9057 #define GEN9_SS01_EU_PGCTL_ACK(slice)   _MMIO(0x805c + (slice) * 0x8)
9058 #define GEN10_SS01_EU_PGCTL_ACK(slice)  _MMIO(0x805c + ((slice) / 3) * 0x30 + \
9059                                               ((slice) % 3) * 0x8)
9060 #define GEN9_SS23_EU_PGCTL_ACK(slice)   _MMIO(0x8060 + (slice) * 0x8)
9061 #define GEN10_SS23_EU_PGCTL_ACK(slice)  _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
9062                                               ((slice) % 3) * 0x8)
9063 #define   GEN9_PGCTL_SSA_EU08_ACK       (1 << 0)
9064 #define   GEN9_PGCTL_SSA_EU19_ACK       (1 << 2)
9065 #define   GEN9_PGCTL_SSA_EU210_ACK      (1 << 4)
9066 #define   GEN9_PGCTL_SSA_EU311_ACK      (1 << 6)
9067 #define   GEN9_PGCTL_SSB_EU08_ACK       (1 << 8)
9068 #define   GEN9_PGCTL_SSB_EU19_ACK       (1 << 10)
9069 #define   GEN9_PGCTL_SSB_EU210_ACK      (1 << 12)
9070 #define   GEN9_PGCTL_SSB_EU311_ACK      (1 << 14)
9071
9072 #define GEN7_MISCCPCTL                          _MMIO(0x9424)
9073 #define   GEN7_DOP_CLOCK_GATE_ENABLE            (1 << 0)
9074 #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE      (1 << 2)
9075 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE        (1 << 4)
9076 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1 << 6)
9077
9078 #define GEN8_GARBCNTL                           _MMIO(0xB004)
9079 #define   GEN9_GAPS_TSV_CREDIT_DISABLE          (1 << 7)
9080 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK     (0x3f << 22)
9081 #define   GEN11_HASH_CTRL_EXCL_MASK             (0x7f << 0)
9082 #define   GEN11_HASH_CTRL_EXCL_BIT0             (1 << 0)
9083
9084 #define GEN11_GLBLINVL                          _MMIO(0xB404)
9085 #define   GEN11_BANK_HASH_ADDR_EXCL_MASK        (0x7f << 5)
9086 #define   GEN11_BANK_HASH_ADDR_EXCL_BIT0        (1 << 5)
9087
9088 #define GEN10_DFR_RATIO_EN_AND_CHICKEN  _MMIO(0x9550)
9089 #define   DFR_DISABLE                   (1 << 9)
9090
9091 #define GEN11_GACB_PERF_CTRL                    _MMIO(0x4B80)
9092 #define   GEN11_HASH_CTRL_MASK                  (0x3 << 12 | 0xf << 0)
9093 #define   GEN11_HASH_CTRL_BIT0                  (1 << 0)
9094 #define   GEN11_HASH_CTRL_BIT4                  (1 << 12)
9095
9096 #define GEN11_LSN_UNSLCVC                               _MMIO(0xB43C)
9097 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC      (1 << 9)
9098 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC       (1 << 7)
9099
9100 #define GEN10_SAMPLER_MODE              _MMIO(0xE18C)
9101 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG     REG_BIT(5)
9102
9103 /* IVYBRIDGE DPF */
9104 #define GEN7_L3CDERRST1(slice)          _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
9105 #define   GEN7_L3CDERRST1_ROW_MASK      (0x7ff << 14)
9106 #define   GEN7_PARITY_ERROR_VALID       (1 << 13)
9107 #define   GEN7_L3CDERRST1_BANK_MASK     (3 << 11)
9108 #define   GEN7_L3CDERRST1_SUBBANK_MASK  (7 << 8)
9109 #define GEN7_PARITY_ERROR_ROW(reg) \
9110                 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
9111 #define GEN7_PARITY_ERROR_BANK(reg) \
9112                 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
9113 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
9114                 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
9115 #define   GEN7_L3CDERRST1_ENABLE        (1 << 7)
9116
9117 #define GEN7_L3LOG(slice, i)            _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
9118 #define GEN7_L3LOG_SIZE                 0x80
9119
9120 #define GEN7_HALF_SLICE_CHICKEN1        _MMIO(0xe100) /* IVB GT1 + VLV */
9121 #define GEN7_HALF_SLICE_CHICKEN1_GT2    _MMIO(0xf100)
9122 #define   GEN7_MAX_PS_THREAD_DEP                (8 << 12)
9123 #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE   (1 << 10)
9124 #define   GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE       (1 << 4)
9125 #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE  (1 << 3)
9126
9127 #define GEN9_HALF_SLICE_CHICKEN5        _MMIO(0xe188)
9128 #define   GEN9_DG_MIRROR_FIX_ENABLE     (1 << 5)
9129 #define   GEN9_CCS_TLB_PREFETCH_ENABLE  (1 << 3)
9130
9131 #define GEN8_ROW_CHICKEN                _MMIO(0xe4f0)
9132 #define   FLOW_CONTROL_ENABLE           (1 << 15)
9133 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
9134 #define   STALL_DOP_GATING_DISABLE              (1 << 5)
9135 #define   THROTTLE_12_5                         (7 << 2)
9136 #define   DISABLE_EARLY_EOT                     (1 << 1)
9137
9138 #define GEN7_ROW_CHICKEN2               _MMIO(0xe4f4)
9139 #define GEN7_ROW_CHICKEN2_GT2           _MMIO(0xf4f4)
9140 #define   DOP_CLOCK_GATING_DISABLE      (1 << 0)
9141 #define   PUSH_CONSTANT_DEREF_DISABLE   (1 << 8)
9142 #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE    (1 << 1)
9143
9144 #define HSW_ROW_CHICKEN3                _MMIO(0xe49c)
9145 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
9146
9147 #define HALF_SLICE_CHICKEN2             _MMIO(0xe180)
9148 #define   GEN8_ST_PO_DISABLE            (1 << 13)
9149
9150 #define HALF_SLICE_CHICKEN3             _MMIO(0xe184)
9151 #define   HSW_SAMPLE_C_PERFORMANCE      (1 << 9)
9152 #define   GEN8_CENTROID_PIXEL_OPT_DIS   (1 << 8)
9153 #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC   (1 << 5)
9154 #define   CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4)
9155 #define   GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
9156
9157 #define GEN9_HALF_SLICE_CHICKEN7        _MMIO(0xe194)
9158 #define   GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR        (1 << 8)
9159 #define   GEN9_ENABLE_YV12_BUGFIX       (1 << 4)
9160 #define   GEN9_ENABLE_GPGPU_PREEMPTION  (1 << 2)
9161
9162 /* Audio */
9163 #define G4X_AUD_VID_DID                 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
9164 #define   INTEL_AUDIO_DEVCL             0x808629FB
9165 #define   INTEL_AUDIO_DEVBLC            0x80862801
9166 #define   INTEL_AUDIO_DEVCTG            0x80862802
9167
9168 #define G4X_AUD_CNTL_ST                 _MMIO(0x620B4)
9169 #define   G4X_ELDV_DEVCL_DEVBLC         (1 << 13)
9170 #define   G4X_ELDV_DEVCTG               (1 << 14)
9171 #define   G4X_ELD_ADDR_MASK             (0xf << 5)
9172 #define   G4X_ELD_ACK                   (1 << 4)
9173 #define G4X_HDMIW_HDMIEDID              _MMIO(0x6210C)
9174
9175 #define _IBX_HDMIW_HDMIEDID_A           0xE2050
9176 #define _IBX_HDMIW_HDMIEDID_B           0xE2150
9177 #define IBX_HDMIW_HDMIEDID(pipe)        _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
9178                                                   _IBX_HDMIW_HDMIEDID_B)
9179 #define _IBX_AUD_CNTL_ST_A              0xE20B4
9180 #define _IBX_AUD_CNTL_ST_B              0xE21B4
9181 #define IBX_AUD_CNTL_ST(pipe)           _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
9182                                                   _IBX_AUD_CNTL_ST_B)
9183 #define   IBX_ELD_BUFFER_SIZE_MASK      (0x1f << 10)
9184 #define   IBX_ELD_ADDRESS_MASK          (0x1f << 5)
9185 #define   IBX_ELD_ACK                   (1 << 4)
9186 #define IBX_AUD_CNTL_ST2                _MMIO(0xE20C0)
9187 #define   IBX_CP_READY(port)            ((1 << 1) << (((port) - 1) * 4))
9188 #define   IBX_ELD_VALID(port)           ((1 << 0) << (((port) - 1) * 4))
9189
9190 #define _CPT_HDMIW_HDMIEDID_A           0xE5050
9191 #define _CPT_HDMIW_HDMIEDID_B           0xE5150
9192 #define CPT_HDMIW_HDMIEDID(pipe)        _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
9193 #define _CPT_AUD_CNTL_ST_A              0xE50B4
9194 #define _CPT_AUD_CNTL_ST_B              0xE51B4
9195 #define CPT_AUD_CNTL_ST(pipe)           _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
9196 #define CPT_AUD_CNTRL_ST2               _MMIO(0xE50C0)
9197
9198 #define _VLV_HDMIW_HDMIEDID_A           (VLV_DISPLAY_BASE + 0x62050)
9199 #define _VLV_HDMIW_HDMIEDID_B           (VLV_DISPLAY_BASE + 0x62150)
9200 #define VLV_HDMIW_HDMIEDID(pipe)        _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
9201 #define _VLV_AUD_CNTL_ST_A              (VLV_DISPLAY_BASE + 0x620B4)
9202 #define _VLV_AUD_CNTL_ST_B              (VLV_DISPLAY_BASE + 0x621B4)
9203 #define VLV_AUD_CNTL_ST(pipe)           _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
9204 #define VLV_AUD_CNTL_ST2                _MMIO(VLV_DISPLAY_BASE + 0x620C0)
9205
9206 /* These are the 4 32-bit write offset registers for each stream
9207  * output buffer.  It determines the offset from the
9208  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
9209  */
9210 #define GEN7_SO_WRITE_OFFSET(n)         _MMIO(0x5280 + (n) * 4)
9211
9212 #define _IBX_AUD_CONFIG_A               0xe2000
9213 #define _IBX_AUD_CONFIG_B               0xe2100
9214 #define IBX_AUD_CFG(pipe)               _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
9215 #define _CPT_AUD_CONFIG_A               0xe5000
9216 #define _CPT_AUD_CONFIG_B               0xe5100
9217 #define CPT_AUD_CFG(pipe)               _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
9218 #define _VLV_AUD_CONFIG_A               (VLV_DISPLAY_BASE + 0x62000)
9219 #define _VLV_AUD_CONFIG_B               (VLV_DISPLAY_BASE + 0x62100)
9220 #define VLV_AUD_CFG(pipe)               _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
9221
9222 #define   AUD_CONFIG_N_VALUE_INDEX              (1 << 29)
9223 #define   AUD_CONFIG_N_PROG_ENABLE              (1 << 28)
9224 #define   AUD_CONFIG_UPPER_N_SHIFT              20
9225 #define   AUD_CONFIG_UPPER_N_MASK               (0xff << 20)
9226 #define   AUD_CONFIG_LOWER_N_SHIFT              4
9227 #define   AUD_CONFIG_LOWER_N_MASK               (0xfff << 4)
9228 #define   AUD_CONFIG_N_MASK                     (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
9229 #define   AUD_CONFIG_N(n) \
9230         (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) |   \
9231          (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
9232 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT     16
9233 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK      (0xf << 16)
9234 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175     (0 << 16)
9235 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200     (1 << 16)
9236 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000     (2 << 16)
9237 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027     (3 << 16)
9238 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000     (4 << 16)
9239 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054     (5 << 16)
9240 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176     (6 << 16)
9241 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250     (7 << 16)
9242 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352    (8 << 16)
9243 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500    (9 << 16)
9244 #define   AUD_CONFIG_DISABLE_NCTS               (1 << 3)
9245
9246 /* HSW Audio */
9247 #define _HSW_AUD_CONFIG_A               0x65000
9248 #define _HSW_AUD_CONFIG_B               0x65100
9249 #define HSW_AUD_CFG(trans)              _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
9250
9251 #define _HSW_AUD_MISC_CTRL_A            0x65010
9252 #define _HSW_AUD_MISC_CTRL_B            0x65110
9253 #define HSW_AUD_MISC_CTRL(trans)        _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
9254
9255 #define _HSW_AUD_M_CTS_ENABLE_A         0x65028
9256 #define _HSW_AUD_M_CTS_ENABLE_B         0x65128
9257 #define HSW_AUD_M_CTS_ENABLE(trans)     _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
9258 #define   AUD_M_CTS_M_VALUE_INDEX       (1 << 21)
9259 #define   AUD_M_CTS_M_PROG_ENABLE       (1 << 20)
9260 #define   AUD_CONFIG_M_MASK             0xfffff
9261
9262 #define _HSW_AUD_DIP_ELD_CTRL_ST_A      0x650b4
9263 #define _HSW_AUD_DIP_ELD_CTRL_ST_B      0x651b4
9264 #define HSW_AUD_DIP_ELD_CTRL(trans)     _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
9265
9266 /* Audio Digital Converter */
9267 #define _HSW_AUD_DIG_CNVT_1             0x65080
9268 #define _HSW_AUD_DIG_CNVT_2             0x65180
9269 #define AUD_DIG_CNVT(trans)             _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
9270 #define DIP_PORT_SEL_MASK               0x3
9271
9272 #define _HSW_AUD_EDID_DATA_A            0x65050
9273 #define _HSW_AUD_EDID_DATA_B            0x65150
9274 #define HSW_AUD_EDID_DATA(trans)        _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
9275
9276 #define HSW_AUD_PIPE_CONV_CFG           _MMIO(0x6507c)
9277 #define HSW_AUD_PIN_ELD_CP_VLD          _MMIO(0x650c0)
9278 #define   AUDIO_INACTIVE(trans)         ((1 << 3) << ((trans) * 4))
9279 #define   AUDIO_OUTPUT_ENABLE(trans)    ((1 << 2) << ((trans) * 4))
9280 #define   AUDIO_CP_READY(trans)         ((1 << 1) << ((trans) * 4))
9281 #define   AUDIO_ELD_VALID(trans)        ((1 << 0) << ((trans) * 4))
9282
9283 #define HSW_AUD_CHICKENBIT                      _MMIO(0x65f10)
9284 #define   SKL_AUD_CODEC_WAKE_SIGNAL             (1 << 15)
9285
9286 #define AUD_FREQ_CNTRL                  _MMIO(0x65900)
9287 #define AUD_PIN_BUF_CTL         _MMIO(0x48414)
9288 #define   AUD_PIN_BUF_ENABLE            REG_BIT(31)
9289
9290 /*
9291  * HSW - ICL power wells
9292  *
9293  * Platforms have up to 3 power well control register sets, each set
9294  * controlling up to 16 power wells via a request/status HW flag tuple:
9295  * - main (HSW_PWR_WELL_CTL[1-4])
9296  * - AUX  (ICL_PWR_WELL_CTL_AUX[1-4])
9297  * - DDI  (ICL_PWR_WELL_CTL_DDI[1-4])
9298  * Each control register set consists of up to 4 registers used by different
9299  * sources that can request a power well to be enabled:
9300  * - BIOS   (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
9301  * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
9302  * - KVMR   (HSW_PWR_WELL_CTL3)   (only in the main register set)
9303  * - DEBUG  (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
9304  */
9305 #define HSW_PWR_WELL_CTL1                       _MMIO(0x45400)
9306 #define HSW_PWR_WELL_CTL2                       _MMIO(0x45404)
9307 #define HSW_PWR_WELL_CTL3                       _MMIO(0x45408)
9308 #define HSW_PWR_WELL_CTL4                       _MMIO(0x4540C)
9309 #define   HSW_PWR_WELL_CTL_REQ(pw_idx)          (0x2 << ((pw_idx) * 2))
9310 #define   HSW_PWR_WELL_CTL_STATE(pw_idx)        (0x1 << ((pw_idx) * 2))
9311
9312 /* HSW/BDW power well */
9313 #define   HSW_PW_CTL_IDX_GLOBAL                 15
9314
9315 /* SKL/BXT/GLK/CNL power wells */
9316 #define   SKL_PW_CTL_IDX_PW_2                   15
9317 #define   SKL_PW_CTL_IDX_PW_1                   14
9318 #define   CNL_PW_CTL_IDX_AUX_F                  12
9319 #define   CNL_PW_CTL_IDX_AUX_D                  11
9320 #define   GLK_PW_CTL_IDX_AUX_C                  10
9321 #define   GLK_PW_CTL_IDX_AUX_B                  9
9322 #define   GLK_PW_CTL_IDX_AUX_A                  8
9323 #define   CNL_PW_CTL_IDX_DDI_F                  6
9324 #define   SKL_PW_CTL_IDX_DDI_D                  4
9325 #define   SKL_PW_CTL_IDX_DDI_C                  3
9326 #define   SKL_PW_CTL_IDX_DDI_B                  2
9327 #define   SKL_PW_CTL_IDX_DDI_A_E                1
9328 #define   GLK_PW_CTL_IDX_DDI_A                  1
9329 #define   SKL_PW_CTL_IDX_MISC_IO                0
9330
9331 /* ICL/TGL - power wells */
9332 #define   TGL_PW_CTL_IDX_PW_5                   4
9333 #define   ICL_PW_CTL_IDX_PW_4                   3
9334 #define   ICL_PW_CTL_IDX_PW_3                   2
9335 #define   ICL_PW_CTL_IDX_PW_2                   1
9336 #define   ICL_PW_CTL_IDX_PW_1                   0
9337
9338 #define ICL_PWR_WELL_CTL_AUX1                   _MMIO(0x45440)
9339 #define ICL_PWR_WELL_CTL_AUX2                   _MMIO(0x45444)
9340 #define ICL_PWR_WELL_CTL_AUX4                   _MMIO(0x4544C)
9341 #define   TGL_PW_CTL_IDX_AUX_TBT6               14
9342 #define   TGL_PW_CTL_IDX_AUX_TBT5               13
9343 #define   TGL_PW_CTL_IDX_AUX_TBT4               12
9344 #define   ICL_PW_CTL_IDX_AUX_TBT4               11
9345 #define   TGL_PW_CTL_IDX_AUX_TBT3               11
9346 #define   ICL_PW_CTL_IDX_AUX_TBT3               10
9347 #define   TGL_PW_CTL_IDX_AUX_TBT2               10
9348 #define   ICL_PW_CTL_IDX_AUX_TBT2               9
9349 #define   TGL_PW_CTL_IDX_AUX_TBT1               9
9350 #define   ICL_PW_CTL_IDX_AUX_TBT1               8
9351 #define   TGL_PW_CTL_IDX_AUX_TC6                8
9352 #define   TGL_PW_CTL_IDX_AUX_TC5                7
9353 #define   TGL_PW_CTL_IDX_AUX_TC4                6
9354 #define   ICL_PW_CTL_IDX_AUX_F                  5
9355 #define   TGL_PW_CTL_IDX_AUX_TC3                5
9356 #define   ICL_PW_CTL_IDX_AUX_E                  4
9357 #define   TGL_PW_CTL_IDX_AUX_TC2                4
9358 #define   ICL_PW_CTL_IDX_AUX_D                  3
9359 #define   TGL_PW_CTL_IDX_AUX_TC1                3
9360 #define   ICL_PW_CTL_IDX_AUX_C                  2
9361 #define   ICL_PW_CTL_IDX_AUX_B                  1
9362 #define   ICL_PW_CTL_IDX_AUX_A                  0
9363
9364 #define ICL_PWR_WELL_CTL_DDI1                   _MMIO(0x45450)
9365 #define ICL_PWR_WELL_CTL_DDI2                   _MMIO(0x45454)
9366 #define ICL_PWR_WELL_CTL_DDI4                   _MMIO(0x4545C)
9367 #define   TGL_PW_CTL_IDX_DDI_TC6                8
9368 #define   TGL_PW_CTL_IDX_DDI_TC5                7
9369 #define   TGL_PW_CTL_IDX_DDI_TC4                6
9370 #define   ICL_PW_CTL_IDX_DDI_F                  5
9371 #define   TGL_PW_CTL_IDX_DDI_TC3                5
9372 #define   ICL_PW_CTL_IDX_DDI_E                  4
9373 #define   TGL_PW_CTL_IDX_DDI_TC2                4
9374 #define   ICL_PW_CTL_IDX_DDI_D                  3
9375 #define   TGL_PW_CTL_IDX_DDI_TC1                3
9376 #define   ICL_PW_CTL_IDX_DDI_C                  2
9377 #define   ICL_PW_CTL_IDX_DDI_B                  1
9378 #define   ICL_PW_CTL_IDX_DDI_A                  0
9379
9380 /* HSW - power well misc debug registers */
9381 #define HSW_PWR_WELL_CTL5                       _MMIO(0x45410)
9382 #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP       (1 << 31)
9383 #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE        (1 << 20)
9384 #define   HSW_PWR_WELL_FORCE_ON                 (1 << 19)
9385 #define HSW_PWR_WELL_CTL6                       _MMIO(0x45414)
9386
9387 /* SKL Fuse Status */
9388 enum skl_power_gate {
9389         SKL_PG0,
9390         SKL_PG1,
9391         SKL_PG2,
9392         ICL_PG3,
9393         ICL_PG4,
9394 };
9395
9396 #define SKL_FUSE_STATUS                         _MMIO(0x42000)
9397 #define  SKL_FUSE_DOWNLOAD_STATUS               (1 << 31)
9398 /*
9399  * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9400  * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
9401  */
9402 #define  SKL_PW_CTL_IDX_TO_PG(pw_idx)           \
9403         ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
9404 /*
9405  * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9406  * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9407  */
9408 #define  ICL_PW_CTL_IDX_TO_PG(pw_idx)           \
9409         ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
9410 #define  SKL_FUSE_PG_DIST_STATUS(pg)            (1 << (27 - (pg)))
9411
9412 #define _CNL_AUX_REG_IDX(pw_idx)        ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
9413 #define _CNL_AUX_ANAOVRD1_B             0x162250
9414 #define _CNL_AUX_ANAOVRD1_C             0x162210
9415 #define _CNL_AUX_ANAOVRD1_D             0x1622D0
9416 #define _CNL_AUX_ANAOVRD1_F             0x162A90
9417 #define CNL_AUX_ANAOVRD1(pw_idx)        _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
9418                                                     _CNL_AUX_ANAOVRD1_B, \
9419                                                     _CNL_AUX_ANAOVRD1_C, \
9420                                                     _CNL_AUX_ANAOVRD1_D, \
9421                                                     _CNL_AUX_ANAOVRD1_F))
9422 #define   CNL_AUX_ANAOVRD1_ENABLE       (1 << 16)
9423 #define   CNL_AUX_ANAOVRD1_LDO_BYPASS   (1 << 23)
9424
9425 #define _ICL_AUX_REG_IDX(pw_idx)        ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
9426 #define _ICL_AUX_ANAOVRD1_A             0x162398
9427 #define _ICL_AUX_ANAOVRD1_B             0x6C398
9428 #define ICL_AUX_ANAOVRD1(pw_idx)        _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
9429                                                     _ICL_AUX_ANAOVRD1_A, \
9430                                                     _ICL_AUX_ANAOVRD1_B))
9431 #define   ICL_AUX_ANAOVRD1_LDO_BYPASS   (1 << 7)
9432 #define   ICL_AUX_ANAOVRD1_ENABLE       (1 << 0)
9433
9434 /* HDCP Key Registers */
9435 #define HDCP_KEY_CONF                   _MMIO(0x66c00)
9436 #define  HDCP_AKSV_SEND_TRIGGER         BIT(31)
9437 #define  HDCP_CLEAR_KEYS_TRIGGER        BIT(30)
9438 #define  HDCP_KEY_LOAD_TRIGGER          BIT(8)
9439 #define HDCP_KEY_STATUS                 _MMIO(0x66c04)
9440 #define  HDCP_FUSE_IN_PROGRESS          BIT(7)
9441 #define  HDCP_FUSE_ERROR                BIT(6)
9442 #define  HDCP_FUSE_DONE                 BIT(5)
9443 #define  HDCP_KEY_LOAD_STATUS           BIT(1)
9444 #define  HDCP_KEY_LOAD_DONE             BIT(0)
9445 #define HDCP_AKSV_LO                    _MMIO(0x66c10)
9446 #define HDCP_AKSV_HI                    _MMIO(0x66c14)
9447
9448 /* HDCP Repeater Registers */
9449 #define HDCP_REP_CTL                    _MMIO(0x66d00)
9450 #define  HDCP_TRANSA_REP_PRESENT        BIT(31)
9451 #define  HDCP_TRANSB_REP_PRESENT        BIT(30)
9452 #define  HDCP_TRANSC_REP_PRESENT        BIT(29)
9453 #define  HDCP_TRANSD_REP_PRESENT        BIT(28)
9454 #define  HDCP_DDIB_REP_PRESENT          BIT(30)
9455 #define  HDCP_DDIA_REP_PRESENT          BIT(29)
9456 #define  HDCP_DDIC_REP_PRESENT          BIT(28)
9457 #define  HDCP_DDID_REP_PRESENT          BIT(27)
9458 #define  HDCP_DDIF_REP_PRESENT          BIT(26)
9459 #define  HDCP_DDIE_REP_PRESENT          BIT(25)
9460 #define  HDCP_TRANSA_SHA1_M0            (1 << 20)
9461 #define  HDCP_TRANSB_SHA1_M0            (2 << 20)
9462 #define  HDCP_TRANSC_SHA1_M0            (3 << 20)
9463 #define  HDCP_TRANSD_SHA1_M0            (4 << 20)
9464 #define  HDCP_DDIB_SHA1_M0              (1 << 20)
9465 #define  HDCP_DDIA_SHA1_M0              (2 << 20)
9466 #define  HDCP_DDIC_SHA1_M0              (3 << 20)
9467 #define  HDCP_DDID_SHA1_M0              (4 << 20)
9468 #define  HDCP_DDIF_SHA1_M0              (5 << 20)
9469 #define  HDCP_DDIE_SHA1_M0              (6 << 20) /* Bspec says 5? */
9470 #define  HDCP_SHA1_BUSY                 BIT(16)
9471 #define  HDCP_SHA1_READY                BIT(17)
9472 #define  HDCP_SHA1_COMPLETE             BIT(18)
9473 #define  HDCP_SHA1_V_MATCH              BIT(19)
9474 #define  HDCP_SHA1_TEXT_32              (1 << 1)
9475 #define  HDCP_SHA1_COMPLETE_HASH        (2 << 1)
9476 #define  HDCP_SHA1_TEXT_24              (4 << 1)
9477 #define  HDCP_SHA1_TEXT_16              (5 << 1)
9478 #define  HDCP_SHA1_TEXT_8               (6 << 1)
9479 #define  HDCP_SHA1_TEXT_0               (7 << 1)
9480 #define HDCP_SHA_V_PRIME_H0             _MMIO(0x66d04)
9481 #define HDCP_SHA_V_PRIME_H1             _MMIO(0x66d08)
9482 #define HDCP_SHA_V_PRIME_H2             _MMIO(0x66d0C)
9483 #define HDCP_SHA_V_PRIME_H3             _MMIO(0x66d10)
9484 #define HDCP_SHA_V_PRIME_H4             _MMIO(0x66d14)
9485 #define HDCP_SHA_V_PRIME(h)             _MMIO((0x66d04 + (h) * 4))
9486 #define HDCP_SHA_TEXT                   _MMIO(0x66d18)
9487
9488 /* HDCP Auth Registers */
9489 #define _PORTA_HDCP_AUTHENC             0x66800
9490 #define _PORTB_HDCP_AUTHENC             0x66500
9491 #define _PORTC_HDCP_AUTHENC             0x66600
9492 #define _PORTD_HDCP_AUTHENC             0x66700
9493 #define _PORTE_HDCP_AUTHENC             0x66A00
9494 #define _PORTF_HDCP_AUTHENC             0x66900
9495 #define _PORT_HDCP_AUTHENC(port, x)     _MMIO(_PICK(port, \
9496                                           _PORTA_HDCP_AUTHENC, \
9497                                           _PORTB_HDCP_AUTHENC, \
9498                                           _PORTC_HDCP_AUTHENC, \
9499                                           _PORTD_HDCP_AUTHENC, \
9500                                           _PORTE_HDCP_AUTHENC, \
9501                                           _PORTF_HDCP_AUTHENC) + (x))
9502 #define PORT_HDCP_CONF(port)            _PORT_HDCP_AUTHENC(port, 0x0)
9503 #define _TRANSA_HDCP_CONF               0x66400
9504 #define _TRANSB_HDCP_CONF               0x66500
9505 #define TRANS_HDCP_CONF(trans)          _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
9506                                                     _TRANSB_HDCP_CONF)
9507 #define HDCP_CONF(dev_priv, trans, port) \
9508                                         (INTEL_GEN(dev_priv) >= 12 ? \
9509                                          TRANS_HDCP_CONF(trans) : \
9510                                          PORT_HDCP_CONF(port))
9511
9512 #define  HDCP_CONF_CAPTURE_AN           BIT(0)
9513 #define  HDCP_CONF_AUTH_AND_ENC         (BIT(1) | BIT(0))
9514 #define PORT_HDCP_ANINIT(port)          _PORT_HDCP_AUTHENC(port, 0x4)
9515 #define _TRANSA_HDCP_ANINIT             0x66404
9516 #define _TRANSB_HDCP_ANINIT             0x66504
9517 #define TRANS_HDCP_ANINIT(trans)        _MMIO_TRANS(trans, \
9518                                                     _TRANSA_HDCP_ANINIT, \
9519                                                     _TRANSB_HDCP_ANINIT)
9520 #define HDCP_ANINIT(dev_priv, trans, port) \
9521                                         (INTEL_GEN(dev_priv) >= 12 ? \
9522                                          TRANS_HDCP_ANINIT(trans) : \
9523                                          PORT_HDCP_ANINIT(port))
9524
9525 #define PORT_HDCP_ANLO(port)            _PORT_HDCP_AUTHENC(port, 0x8)
9526 #define _TRANSA_HDCP_ANLO               0x66408
9527 #define _TRANSB_HDCP_ANLO               0x66508
9528 #define TRANS_HDCP_ANLO(trans)          _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
9529                                                     _TRANSB_HDCP_ANLO)
9530 #define HDCP_ANLO(dev_priv, trans, port) \
9531                                         (INTEL_GEN(dev_priv) >= 12 ? \
9532                                          TRANS_HDCP_ANLO(trans) : \
9533                                          PORT_HDCP_ANLO(port))
9534
9535 #define PORT_HDCP_ANHI(port)            _PORT_HDCP_AUTHENC(port, 0xC)
9536 #define _TRANSA_HDCP_ANHI               0x6640C
9537 #define _TRANSB_HDCP_ANHI               0x6650C
9538 #define TRANS_HDCP_ANHI(trans)          _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
9539                                                     _TRANSB_HDCP_ANHI)
9540 #define HDCP_ANHI(dev_priv, trans, port) \
9541                                         (INTEL_GEN(dev_priv) >= 12 ? \
9542                                          TRANS_HDCP_ANHI(trans) : \
9543                                          PORT_HDCP_ANHI(port))
9544
9545 #define PORT_HDCP_BKSVLO(port)          _PORT_HDCP_AUTHENC(port, 0x10)
9546 #define _TRANSA_HDCP_BKSVLO             0x66410
9547 #define _TRANSB_HDCP_BKSVLO             0x66510
9548 #define TRANS_HDCP_BKSVLO(trans)        _MMIO_TRANS(trans, \
9549                                                     _TRANSA_HDCP_BKSVLO, \
9550                                                     _TRANSB_HDCP_BKSVLO)
9551 #define HDCP_BKSVLO(dev_priv, trans, port) \
9552                                         (INTEL_GEN(dev_priv) >= 12 ? \
9553                                          TRANS_HDCP_BKSVLO(trans) : \
9554                                          PORT_HDCP_BKSVLO(port))
9555
9556 #define PORT_HDCP_BKSVHI(port)          _PORT_HDCP_AUTHENC(port, 0x14)
9557 #define _TRANSA_HDCP_BKSVHI             0x66414
9558 #define _TRANSB_HDCP_BKSVHI             0x66514
9559 #define TRANS_HDCP_BKSVHI(trans)        _MMIO_TRANS(trans, \
9560                                                     _TRANSA_HDCP_BKSVHI, \
9561                                                     _TRANSB_HDCP_BKSVHI)
9562 #define HDCP_BKSVHI(dev_priv, trans, port) \
9563                                         (INTEL_GEN(dev_priv) >= 12 ? \
9564                                          TRANS_HDCP_BKSVHI(trans) : \
9565                                          PORT_HDCP_BKSVHI(port))
9566
9567 #define PORT_HDCP_RPRIME(port)          _PORT_HDCP_AUTHENC(port, 0x18)
9568 #define _TRANSA_HDCP_RPRIME             0x66418
9569 #define _TRANSB_HDCP_RPRIME             0x66518
9570 #define TRANS_HDCP_RPRIME(trans)        _MMIO_TRANS(trans, \
9571                                                     _TRANSA_HDCP_RPRIME, \
9572                                                     _TRANSB_HDCP_RPRIME)
9573 #define HDCP_RPRIME(dev_priv, trans, port) \
9574                                         (INTEL_GEN(dev_priv) >= 12 ? \
9575                                          TRANS_HDCP_RPRIME(trans) : \
9576                                          PORT_HDCP_RPRIME(port))
9577
9578 #define PORT_HDCP_STATUS(port)          _PORT_HDCP_AUTHENC(port, 0x1C)
9579 #define _TRANSA_HDCP_STATUS             0x6641C
9580 #define _TRANSB_HDCP_STATUS             0x6651C
9581 #define TRANS_HDCP_STATUS(trans)        _MMIO_TRANS(trans, \
9582                                                     _TRANSA_HDCP_STATUS, \
9583                                                     _TRANSB_HDCP_STATUS)
9584 #define HDCP_STATUS(dev_priv, trans, port) \
9585                                         (INTEL_GEN(dev_priv) >= 12 ? \
9586                                          TRANS_HDCP_STATUS(trans) : \
9587                                          PORT_HDCP_STATUS(port))
9588
9589 #define  HDCP_STATUS_STREAM_A_ENC       BIT(31)
9590 #define  HDCP_STATUS_STREAM_B_ENC       BIT(30)
9591 #define  HDCP_STATUS_STREAM_C_ENC       BIT(29)
9592 #define  HDCP_STATUS_STREAM_D_ENC       BIT(28)
9593 #define  HDCP_STATUS_AUTH               BIT(21)
9594 #define  HDCP_STATUS_ENC                BIT(20)
9595 #define  HDCP_STATUS_RI_MATCH           BIT(19)
9596 #define  HDCP_STATUS_R0_READY           BIT(18)
9597 #define  HDCP_STATUS_AN_READY           BIT(17)
9598 #define  HDCP_STATUS_CIPHER             BIT(16)
9599 #define  HDCP_STATUS_FRAME_CNT(x)       (((x) >> 8) & 0xff)
9600
9601 /* HDCP2.2 Registers */
9602 #define _PORTA_HDCP2_BASE               0x66800
9603 #define _PORTB_HDCP2_BASE               0x66500
9604 #define _PORTC_HDCP2_BASE               0x66600
9605 #define _PORTD_HDCP2_BASE               0x66700
9606 #define _PORTE_HDCP2_BASE               0x66A00
9607 #define _PORTF_HDCP2_BASE               0x66900
9608 #define _PORT_HDCP2_BASE(port, x)       _MMIO(_PICK((port), \
9609                                           _PORTA_HDCP2_BASE, \
9610                                           _PORTB_HDCP2_BASE, \
9611                                           _PORTC_HDCP2_BASE, \
9612                                           _PORTD_HDCP2_BASE, \
9613                                           _PORTE_HDCP2_BASE, \
9614                                           _PORTF_HDCP2_BASE) + (x))
9615 #define PORT_HDCP2_AUTH(port)           _PORT_HDCP2_BASE(port, 0x98)
9616 #define _TRANSA_HDCP2_AUTH              0x66498
9617 #define _TRANSB_HDCP2_AUTH              0x66598
9618 #define TRANS_HDCP2_AUTH(trans)         _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
9619                                                     _TRANSB_HDCP2_AUTH)
9620 #define   AUTH_LINK_AUTHENTICATED       BIT(31)
9621 #define   AUTH_LINK_TYPE                BIT(30)
9622 #define   AUTH_FORCE_CLR_INPUTCTR       BIT(19)
9623 #define   AUTH_CLR_KEYS                 BIT(18)
9624 #define HDCP2_AUTH(dev_priv, trans, port) \
9625                                         (INTEL_GEN(dev_priv) >= 12 ? \
9626                                          TRANS_HDCP2_AUTH(trans) : \
9627                                          PORT_HDCP2_AUTH(port))
9628
9629 #define PORT_HDCP2_CTL(port)            _PORT_HDCP2_BASE(port, 0xB0)
9630 #define _TRANSA_HDCP2_CTL               0x664B0
9631 #define _TRANSB_HDCP2_CTL               0x665B0
9632 #define TRANS_HDCP2_CTL(trans)          _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
9633                                                     _TRANSB_HDCP2_CTL)
9634 #define   CTL_LINK_ENCRYPTION_REQ       BIT(31)
9635 #define HDCP2_CTL(dev_priv, trans, port) \
9636                                         (INTEL_GEN(dev_priv) >= 12 ? \
9637                                          TRANS_HDCP2_CTL(trans) : \
9638                                          PORT_HDCP2_CTL(port))
9639
9640 #define PORT_HDCP2_STATUS(port)         _PORT_HDCP2_BASE(port, 0xB4)
9641 #define _TRANSA_HDCP2_STATUS            0x664B4
9642 #define _TRANSB_HDCP2_STATUS            0x665B4
9643 #define TRANS_HDCP2_STATUS(trans)       _MMIO_TRANS(trans, \
9644                                                     _TRANSA_HDCP2_STATUS, \
9645                                                     _TRANSB_HDCP2_STATUS)
9646 #define   LINK_TYPE_STATUS              BIT(22)
9647 #define   LINK_AUTH_STATUS              BIT(21)
9648 #define   LINK_ENCRYPTION_STATUS        BIT(20)
9649 #define HDCP2_STATUS(dev_priv, trans, port) \
9650                                         (INTEL_GEN(dev_priv) >= 12 ? \
9651                                          TRANS_HDCP2_STATUS(trans) : \
9652                                          PORT_HDCP2_STATUS(port))
9653
9654 /* Per-pipe DDI Function Control */
9655 #define _TRANS_DDI_FUNC_CTL_A           0x60400
9656 #define _TRANS_DDI_FUNC_CTL_B           0x61400
9657 #define _TRANS_DDI_FUNC_CTL_C           0x62400
9658 #define _TRANS_DDI_FUNC_CTL_D           0x63400
9659 #define _TRANS_DDI_FUNC_CTL_EDP         0x6F400
9660 #define _TRANS_DDI_FUNC_CTL_DSI0        0x6b400
9661 #define _TRANS_DDI_FUNC_CTL_DSI1        0x6bc00
9662 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
9663
9664 #define  TRANS_DDI_FUNC_ENABLE          (1 << 31)
9665 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
9666 #define  TRANS_DDI_PORT_SHIFT           28
9667 #define  TGL_TRANS_DDI_PORT_SHIFT       27
9668 #define  TRANS_DDI_PORT_MASK            (7 << TRANS_DDI_PORT_SHIFT)
9669 #define  TGL_TRANS_DDI_PORT_MASK        (0xf << TGL_TRANS_DDI_PORT_SHIFT)
9670 #define  TRANS_DDI_SELECT_PORT(x)       ((x) << TRANS_DDI_PORT_SHIFT)
9671 #define  TGL_TRANS_DDI_SELECT_PORT(x)   (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
9672 #define  TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val)     (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT)
9673 #define  TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
9674 #define  TRANS_DDI_MODE_SELECT_MASK     (7 << 24)
9675 #define  TRANS_DDI_MODE_SELECT_HDMI     (0 << 24)
9676 #define  TRANS_DDI_MODE_SELECT_DVI      (1 << 24)
9677 #define  TRANS_DDI_MODE_SELECT_DP_SST   (2 << 24)
9678 #define  TRANS_DDI_MODE_SELECT_DP_MST   (3 << 24)
9679 #define  TRANS_DDI_MODE_SELECT_FDI      (4 << 24)
9680 #define  TRANS_DDI_BPC_MASK             (7 << 20)
9681 #define  TRANS_DDI_BPC_8                (0 << 20)
9682 #define  TRANS_DDI_BPC_10               (1 << 20)
9683 #define  TRANS_DDI_BPC_6                (2 << 20)
9684 #define  TRANS_DDI_BPC_12               (3 << 20)
9685 #define  TRANS_DDI_PVSYNC               (1 << 17)
9686 #define  TRANS_DDI_PHSYNC               (1 << 16)
9687 #define  TRANS_DDI_EDP_INPUT_MASK       (7 << 12)
9688 #define  TRANS_DDI_EDP_INPUT_A_ON       (0 << 12)
9689 #define  TRANS_DDI_EDP_INPUT_A_ONOFF    (4 << 12)
9690 #define  TRANS_DDI_EDP_INPUT_B_ONOFF    (5 << 12)
9691 #define  TRANS_DDI_EDP_INPUT_C_ONOFF    (6 << 12)
9692 #define  TRANS_DDI_EDP_INPUT_D_ONOFF    (7 << 12)
9693 #define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK    REG_GENMASK(11, 10)
9694 #define  TRANS_DDI_MST_TRANSPORT_SELECT(trans)  \
9695         REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
9696 #define  TRANS_DDI_HDCP_SIGNALLING      (1 << 9)
9697 #define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC  (1 << 8)
9698 #define  TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
9699 #define  TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
9700 #define  TRANS_DDI_BFI_ENABLE           (1 << 4)
9701 #define  TRANS_DDI_HIGH_TMDS_CHAR_RATE  (1 << 4)
9702 #define  TRANS_DDI_HDMI_SCRAMBLING      (1 << 0)
9703 #define  TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
9704                                         | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
9705                                         | TRANS_DDI_HDMI_SCRAMBLING)
9706
9707 #define _TRANS_DDI_FUNC_CTL2_A          0x60404
9708 #define _TRANS_DDI_FUNC_CTL2_B          0x61404
9709 #define _TRANS_DDI_FUNC_CTL2_C          0x62404
9710 #define _TRANS_DDI_FUNC_CTL2_EDP        0x6f404
9711 #define _TRANS_DDI_FUNC_CTL2_DSI0       0x6b404
9712 #define _TRANS_DDI_FUNC_CTL2_DSI1       0x6bc04
9713 #define TRANS_DDI_FUNC_CTL2(tran)       _MMIO_TRANS2(tran, \
9714                                                      _TRANS_DDI_FUNC_CTL2_A)
9715 #define  PORT_SYNC_MODE_ENABLE                  (1 << 4)
9716 #define  PORT_SYNC_MODE_MASTER_SELECT(x)        ((x) << 0)
9717 #define  PORT_SYNC_MODE_MASTER_SELECT_MASK      (0x7 << 0)
9718 #define  PORT_SYNC_MODE_MASTER_SELECT_SHIFT     0
9719
9720 /* DisplayPort Transport Control */
9721 #define _DP_TP_CTL_A                    0x64040
9722 #define _DP_TP_CTL_B                    0x64140
9723 #define _TGL_DP_TP_CTL_A                0x60540
9724 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
9725 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
9726 #define  DP_TP_CTL_ENABLE                       (1 << 31)
9727 #define  DP_TP_CTL_FEC_ENABLE                   (1 << 30)
9728 #define  DP_TP_CTL_MODE_SST                     (0 << 27)
9729 #define  DP_TP_CTL_MODE_MST                     (1 << 27)
9730 #define  DP_TP_CTL_FORCE_ACT                    (1 << 25)
9731 #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE        (1 << 18)
9732 #define  DP_TP_CTL_FDI_AUTOTRAIN                (1 << 15)
9733 #define  DP_TP_CTL_LINK_TRAIN_MASK              (7 << 8)
9734 #define  DP_TP_CTL_LINK_TRAIN_PAT1              (0 << 8)
9735 #define  DP_TP_CTL_LINK_TRAIN_PAT2              (1 << 8)
9736 #define  DP_TP_CTL_LINK_TRAIN_PAT3              (4 << 8)
9737 #define  DP_TP_CTL_LINK_TRAIN_PAT4              (5 << 8)
9738 #define  DP_TP_CTL_LINK_TRAIN_IDLE              (2 << 8)
9739 #define  DP_TP_CTL_LINK_TRAIN_NORMAL            (3 << 8)
9740 #define  DP_TP_CTL_SCRAMBLE_DISABLE             (1 << 7)
9741
9742 /* DisplayPort Transport Status */
9743 #define _DP_TP_STATUS_A                 0x64044
9744 #define _DP_TP_STATUS_B                 0x64144
9745 #define _TGL_DP_TP_STATUS_A             0x60544
9746 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
9747 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
9748 #define  DP_TP_STATUS_FEC_ENABLE_LIVE           (1 << 28)
9749 #define  DP_TP_STATUS_IDLE_DONE                 (1 << 25)
9750 #define  DP_TP_STATUS_ACT_SENT                  (1 << 24)
9751 #define  DP_TP_STATUS_MODE_STATUS_MST           (1 << 23)
9752 #define  DP_TP_STATUS_AUTOTRAIN_DONE            (1 << 12)
9753 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC2       (3 << 8)
9754 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC1       (3 << 4)
9755 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0       (3 << 0)
9756
9757 /* DDI Buffer Control */
9758 #define _DDI_BUF_CTL_A                          0x64000
9759 #define _DDI_BUF_CTL_B                          0x64100
9760 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
9761 #define  DDI_BUF_CTL_ENABLE                     (1 << 31)
9762 #define  DDI_BUF_TRANS_SELECT(n)        ((n) << 24)
9763 #define  DDI_BUF_EMP_MASK                       (0xf << 24)
9764 #define  DDI_BUF_PORT_REVERSAL                  (1 << 16)
9765 #define  DDI_BUF_IS_IDLE                        (1 << 7)
9766 #define  DDI_A_4_LANES                          (1 << 4)
9767 #define  DDI_PORT_WIDTH(width)                  (((width) - 1) << 1)
9768 #define  DDI_PORT_WIDTH_MASK                    (7 << 1)
9769 #define  DDI_PORT_WIDTH_SHIFT                   1
9770 #define  DDI_INIT_DISPLAY_DETECTED              (1 << 0)
9771
9772 /* DDI Buffer Translations */
9773 #define _DDI_BUF_TRANS_A                0x64E00
9774 #define _DDI_BUF_TRANS_B                0x64E60
9775 #define DDI_BUF_TRANS_LO(port, i)       _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
9776 #define  DDI_BUF_BALANCE_LEG_ENABLE     (1 << 31)
9777 #define DDI_BUF_TRANS_HI(port, i)       _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
9778
9779 /* Sideband Interface (SBI) is programmed indirectly, via
9780  * SBI_ADDR, which contains the register offset; and SBI_DATA,
9781  * which contains the payload */
9782 #define SBI_ADDR                        _MMIO(0xC6000)
9783 #define SBI_DATA                        _MMIO(0xC6004)
9784 #define SBI_CTL_STAT                    _MMIO(0xC6008)
9785 #define  SBI_CTL_DEST_ICLK              (0x0 << 16)
9786 #define  SBI_CTL_DEST_MPHY              (0x1 << 16)
9787 #define  SBI_CTL_OP_IORD                (0x2 << 8)
9788 #define  SBI_CTL_OP_IOWR                (0x3 << 8)
9789 #define  SBI_CTL_OP_CRRD                (0x6 << 8)
9790 #define  SBI_CTL_OP_CRWR                (0x7 << 8)
9791 #define  SBI_RESPONSE_FAIL              (0x1 << 1)
9792 #define  SBI_RESPONSE_SUCCESS           (0x0 << 1)
9793 #define  SBI_BUSY                       (0x1 << 0)
9794 #define  SBI_READY                      (0x0 << 0)
9795
9796 /* SBI offsets */
9797 #define  SBI_SSCDIVINTPHASE                     0x0200
9798 #define  SBI_SSCDIVINTPHASE6                    0x0600
9799 #define   SBI_SSCDIVINTPHASE_DIVSEL_SHIFT       1
9800 #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK        (0x7f << 1)
9801 #define   SBI_SSCDIVINTPHASE_DIVSEL(x)          ((x) << 1)
9802 #define   SBI_SSCDIVINTPHASE_INCVAL_SHIFT       8
9803 #define   SBI_SSCDIVINTPHASE_INCVAL_MASK        (0x7f << 8)
9804 #define   SBI_SSCDIVINTPHASE_INCVAL(x)          ((x) << 8)
9805 #define   SBI_SSCDIVINTPHASE_DIR(x)             ((x) << 15)
9806 #define   SBI_SSCDIVINTPHASE_PROPAGATE          (1 << 0)
9807 #define  SBI_SSCDITHPHASE                       0x0204
9808 #define  SBI_SSCCTL                             0x020c
9809 #define  SBI_SSCCTL6                            0x060C
9810 #define   SBI_SSCCTL_PATHALT                    (1 << 3)
9811 #define   SBI_SSCCTL_DISABLE                    (1 << 0)
9812 #define  SBI_SSCAUXDIV6                         0x0610
9813 #define   SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT      4
9814 #define   SBI_SSCAUXDIV_FINALDIV2SEL_MASK       (1 << 4)
9815 #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)         ((x) << 4)
9816 #define  SBI_DBUFF0                             0x2a00
9817 #define  SBI_GEN0                               0x1f00
9818 #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE       (1 << 0)
9819
9820 /* LPT PIXCLK_GATE */
9821 #define PIXCLK_GATE                     _MMIO(0xC6020)
9822 #define  PIXCLK_GATE_UNGATE             (1 << 0)
9823 #define  PIXCLK_GATE_GATE               (0 << 0)
9824
9825 /* SPLL */
9826 #define SPLL_CTL                        _MMIO(0x46020)
9827 #define  SPLL_PLL_ENABLE                (1 << 31)
9828 #define  SPLL_REF_BCLK                  (0 << 28)
9829 #define  SPLL_REF_MUXED_SSC             (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
9830 #define  SPLL_REF_NON_SSC_HSW           (2 << 28)
9831 #define  SPLL_REF_PCH_SSC_BDW           (2 << 28)
9832 #define  SPLL_REF_LCPLL                 (3 << 28)
9833 #define  SPLL_REF_MASK                  (3 << 28)
9834 #define  SPLL_FREQ_810MHz               (0 << 26)
9835 #define  SPLL_FREQ_1350MHz              (1 << 26)
9836 #define  SPLL_FREQ_2700MHz              (2 << 26)
9837 #define  SPLL_FREQ_MASK                 (3 << 26)
9838
9839 /* WRPLL */
9840 #define _WRPLL_CTL1                     0x46040
9841 #define _WRPLL_CTL2                     0x46060
9842 #define WRPLL_CTL(pll)                  _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
9843 #define  WRPLL_PLL_ENABLE               (1 << 31)
9844 #define  WRPLL_REF_BCLK                 (0 << 28)
9845 #define  WRPLL_REF_PCH_SSC              (1 << 28)
9846 #define  WRPLL_REF_MUXED_SSC_BDW        (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
9847 #define  WRPLL_REF_SPECIAL_HSW          (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
9848 #define  WRPLL_REF_LCPLL                (3 << 28)
9849 #define  WRPLL_REF_MASK                 (3 << 28)
9850 /* WRPLL divider programming */
9851 #define  WRPLL_DIVIDER_REFERENCE(x)     ((x) << 0)
9852 #define  WRPLL_DIVIDER_REF_MASK         (0xff)
9853 #define  WRPLL_DIVIDER_POST(x)          ((x) << 8)
9854 #define  WRPLL_DIVIDER_POST_MASK        (0x3f << 8)
9855 #define  WRPLL_DIVIDER_POST_SHIFT       8
9856 #define  WRPLL_DIVIDER_FEEDBACK(x)      ((x) << 16)
9857 #define  WRPLL_DIVIDER_FB_SHIFT         16
9858 #define  WRPLL_DIVIDER_FB_MASK          (0xff << 16)
9859
9860 /* Port clock selection */
9861 #define _PORT_CLK_SEL_A                 0x46100
9862 #define _PORT_CLK_SEL_B                 0x46104
9863 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
9864 #define  PORT_CLK_SEL_LCPLL_2700        (0 << 29)
9865 #define  PORT_CLK_SEL_LCPLL_1350        (1 << 29)
9866 #define  PORT_CLK_SEL_LCPLL_810         (2 << 29)
9867 #define  PORT_CLK_SEL_SPLL              (3 << 29)
9868 #define  PORT_CLK_SEL_WRPLL(pll)        (((pll) + 4) << 29)
9869 #define  PORT_CLK_SEL_WRPLL1            (4 << 29)
9870 #define  PORT_CLK_SEL_WRPLL2            (5 << 29)
9871 #define  PORT_CLK_SEL_NONE              (7 << 29)
9872 #define  PORT_CLK_SEL_MASK              (7 << 29)
9873
9874 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
9875 #define DDI_CLK_SEL(port)               PORT_CLK_SEL(port)
9876 #define  DDI_CLK_SEL_NONE               (0x0 << 28)
9877 #define  DDI_CLK_SEL_MG                 (0x8 << 28)
9878 #define  DDI_CLK_SEL_TBT_162            (0xC << 28)
9879 #define  DDI_CLK_SEL_TBT_270            (0xD << 28)
9880 #define  DDI_CLK_SEL_TBT_540            (0xE << 28)
9881 #define  DDI_CLK_SEL_TBT_810            (0xF << 28)
9882 #define  DDI_CLK_SEL_MASK               (0xF << 28)
9883
9884 /* Transcoder clock selection */
9885 #define _TRANS_CLK_SEL_A                0x46140
9886 #define _TRANS_CLK_SEL_B                0x46144
9887 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
9888 /* For each transcoder, we need to select the corresponding port clock */
9889 #define  TRANS_CLK_SEL_DISABLED         (0x0 << 29)
9890 #define  TRANS_CLK_SEL_PORT(x)          (((x) + 1) << 29)
9891 #define  TGL_TRANS_CLK_SEL_DISABLED     (0x0 << 28)
9892 #define  TGL_TRANS_CLK_SEL_PORT(x)      (((x) + 1) << 28)
9893
9894
9895 #define CDCLK_FREQ                      _MMIO(0x46200)
9896
9897 #define _TRANSA_MSA_MISC                0x60410
9898 #define _TRANSB_MSA_MISC                0x61410
9899 #define _TRANSC_MSA_MISC                0x62410
9900 #define _TRANS_EDP_MSA_MISC             0x6f410
9901 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
9902 /* See DP_MSA_MISC_* for the bit definitions */
9903
9904 /* LCPLL Control */
9905 #define LCPLL_CTL                       _MMIO(0x130040)
9906 #define  LCPLL_PLL_DISABLE              (1 << 31)
9907 #define  LCPLL_PLL_LOCK                 (1 << 30)
9908 #define  LCPLL_REF_NON_SSC              (0 << 28)
9909 #define  LCPLL_REF_BCLK                 (2 << 28)
9910 #define  LCPLL_REF_PCH_SSC              (3 << 28)
9911 #define  LCPLL_REF_MASK                 (3 << 28)
9912 #define  LCPLL_CLK_FREQ_MASK            (3 << 26)
9913 #define  LCPLL_CLK_FREQ_450             (0 << 26)
9914 #define  LCPLL_CLK_FREQ_54O_BDW         (1 << 26)
9915 #define  LCPLL_CLK_FREQ_337_5_BDW       (2 << 26)
9916 #define  LCPLL_CLK_FREQ_675_BDW         (3 << 26)
9917 #define  LCPLL_CD_CLOCK_DISABLE         (1 << 25)
9918 #define  LCPLL_ROOT_CD_CLOCK_DISABLE    (1 << 24)
9919 #define  LCPLL_CD2X_CLOCK_DISABLE       (1 << 23)
9920 #define  LCPLL_POWER_DOWN_ALLOW         (1 << 22)
9921 #define  LCPLL_CD_SOURCE_FCLK           (1 << 21)
9922 #define  LCPLL_CD_SOURCE_FCLK_DONE      (1 << 19)
9923
9924 /*
9925  * SKL Clocks
9926  */
9927
9928 /* CDCLK_CTL */
9929 #define CDCLK_CTL                       _MMIO(0x46000)
9930 #define  CDCLK_FREQ_SEL_MASK            (3 << 26)
9931 #define  CDCLK_FREQ_450_432             (0 << 26)
9932 #define  CDCLK_FREQ_540                 (1 << 26)
9933 #define  CDCLK_FREQ_337_308             (2 << 26)
9934 #define  CDCLK_FREQ_675_617             (3 << 26)
9935 #define  BXT_CDCLK_CD2X_DIV_SEL_MASK    (3 << 22)
9936 #define  BXT_CDCLK_CD2X_DIV_SEL_1       (0 << 22)
9937 #define  BXT_CDCLK_CD2X_DIV_SEL_1_5     (1 << 22)
9938 #define  BXT_CDCLK_CD2X_DIV_SEL_2       (2 << 22)
9939 #define  BXT_CDCLK_CD2X_DIV_SEL_4       (3 << 22)
9940 #define  BXT_CDCLK_CD2X_PIPE(pipe)      ((pipe) << 20)
9941 #define  CDCLK_DIVMUX_CD_OVERRIDE       (1 << 19)
9942 #define  BXT_CDCLK_CD2X_PIPE_NONE       BXT_CDCLK_CD2X_PIPE(3)
9943 #define  ICL_CDCLK_CD2X_PIPE(pipe)      (_PICK(pipe, 0, 2, 6) << 19)
9944 #define  ICL_CDCLK_CD2X_PIPE_NONE       (7 << 19)
9945 #define  TGL_CDCLK_CD2X_PIPE(pipe)      BXT_CDCLK_CD2X_PIPE(pipe)
9946 #define  TGL_CDCLK_CD2X_PIPE_NONE       ICL_CDCLK_CD2X_PIPE_NONE
9947 #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
9948 #define  CDCLK_FREQ_DECIMAL_MASK        (0x7ff)
9949
9950 /* LCPLL_CTL */
9951 #define LCPLL1_CTL              _MMIO(0x46010)
9952 #define LCPLL2_CTL              _MMIO(0x46014)
9953 #define  LCPLL_PLL_ENABLE       (1 << 31)
9954
9955 /* DPLL control1 */
9956 #define DPLL_CTRL1              _MMIO(0x6C058)
9957 #define  DPLL_CTRL1_HDMI_MODE(id)               (1 << ((id) * 6 + 5))
9958 #define  DPLL_CTRL1_SSC(id)                     (1 << ((id) * 6 + 4))
9959 #define  DPLL_CTRL1_LINK_RATE_MASK(id)          (7 << ((id) * 6 + 1))
9960 #define  DPLL_CTRL1_LINK_RATE_SHIFT(id)         ((id) * 6 + 1)
9961 #define  DPLL_CTRL1_LINK_RATE(linkrate, id)     ((linkrate) << ((id) * 6 + 1))
9962 #define  DPLL_CTRL1_OVERRIDE(id)                (1 << ((id) * 6))
9963 #define  DPLL_CTRL1_LINK_RATE_2700              0
9964 #define  DPLL_CTRL1_LINK_RATE_1350              1
9965 #define  DPLL_CTRL1_LINK_RATE_810               2
9966 #define  DPLL_CTRL1_LINK_RATE_1620              3
9967 #define  DPLL_CTRL1_LINK_RATE_1080              4
9968 #define  DPLL_CTRL1_LINK_RATE_2160              5
9969
9970 /* DPLL control2 */
9971 #define DPLL_CTRL2                              _MMIO(0x6C05C)
9972 #define  DPLL_CTRL2_DDI_CLK_OFF(port)           (1 << ((port) + 15))
9973 #define  DPLL_CTRL2_DDI_CLK_SEL_MASK(port)      (3 << ((port) * 3 + 1))
9974 #define  DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)    ((port) * 3 + 1)
9975 #define  DPLL_CTRL2_DDI_CLK_SEL(clk, port)      ((clk) << ((port) * 3 + 1))
9976 #define  DPLL_CTRL2_DDI_SEL_OVERRIDE(port)     (1 << ((port) * 3))
9977
9978 /* DPLL Status */
9979 #define DPLL_STATUS     _MMIO(0x6C060)
9980 #define  DPLL_LOCK(id) (1 << ((id) * 8))
9981
9982 /* DPLL cfg */
9983 #define _DPLL1_CFGCR1   0x6C040
9984 #define _DPLL2_CFGCR1   0x6C048
9985 #define _DPLL3_CFGCR1   0x6C050
9986 #define  DPLL_CFGCR1_FREQ_ENABLE        (1 << 31)
9987 #define  DPLL_CFGCR1_DCO_FRACTION_MASK  (0x7fff << 9)
9988 #define  DPLL_CFGCR1_DCO_FRACTION(x)    ((x) << 9)
9989 #define  DPLL_CFGCR1_DCO_INTEGER_MASK   (0x1ff)
9990
9991 #define _DPLL1_CFGCR2   0x6C044
9992 #define _DPLL2_CFGCR2   0x6C04C
9993 #define _DPLL3_CFGCR2   0x6C054
9994 #define  DPLL_CFGCR2_QDIV_RATIO_MASK    (0xff << 8)
9995 #define  DPLL_CFGCR2_QDIV_RATIO(x)      ((x) << 8)
9996 #define  DPLL_CFGCR2_QDIV_MODE(x)       ((x) << 7)
9997 #define  DPLL_CFGCR2_KDIV_MASK          (3 << 5)
9998 #define  DPLL_CFGCR2_KDIV(x)            ((x) << 5)
9999 #define  DPLL_CFGCR2_KDIV_5 (0 << 5)
10000 #define  DPLL_CFGCR2_KDIV_2 (1 << 5)
10001 #define  DPLL_CFGCR2_KDIV_3 (2 << 5)
10002 #define  DPLL_CFGCR2_KDIV_1 (3 << 5)
10003 #define  DPLL_CFGCR2_PDIV_MASK          (7 << 2)
10004 #define  DPLL_CFGCR2_PDIV(x)            ((x) << 2)
10005 #define  DPLL_CFGCR2_PDIV_1 (0 << 2)
10006 #define  DPLL_CFGCR2_PDIV_2 (1 << 2)
10007 #define  DPLL_CFGCR2_PDIV_3 (2 << 2)
10008 #define  DPLL_CFGCR2_PDIV_7 (4 << 2)
10009 #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK  (3)
10010
10011 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
10012 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
10013
10014 /*
10015  * CNL Clocks
10016  */
10017 #define DPCLKA_CFGCR0                           _MMIO(0x6C200)
10018 #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)        (1 << ((port) ==  PORT_F ? 23 : \
10019                                                       (port) + 10))
10020 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)  ((port) == PORT_F ? 21 : \
10021                                                 (port) * 2)
10022 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)   (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
10023 #define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)   ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
10024
10025 #define ICL_DPCLKA_CFGCR0                       _MMIO(0x164280)
10026 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)     (1 << _PICK(phy, 10, 11, 24))
10027 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)  (1 << ((tc_port) < PORT_TC4 ? \
10028                                                        (tc_port) + 12 : \
10029                                                        (tc_port) - PORT_TC4 + 21))
10030 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)       ((phy) * 2)
10031 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)        (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10032 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)        ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10033
10034 /* CNL PLL */
10035 #define DPLL0_ENABLE            0x46010
10036 #define DPLL1_ENABLE            0x46014
10037 #define  PLL_ENABLE             (1 << 31)
10038 #define  PLL_LOCK               (1 << 30)
10039 #define  PLL_POWER_ENABLE       (1 << 27)
10040 #define  PLL_POWER_STATE        (1 << 26)
10041 #define CNL_DPLL_ENABLE(pll)    _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
10042
10043 #define TBT_PLL_ENABLE          _MMIO(0x46020)
10044
10045 #define _MG_PLL1_ENABLE         0x46030
10046 #define _MG_PLL2_ENABLE         0x46034
10047 #define _MG_PLL3_ENABLE         0x46038
10048 #define _MG_PLL4_ENABLE         0x4603C
10049 /* Bits are the same as DPLL0_ENABLE */
10050 #define MG_PLL_ENABLE(tc_port)  _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
10051                                            _MG_PLL2_ENABLE)
10052
10053 #define _MG_REFCLKIN_CTL_PORT1                          0x16892C
10054 #define _MG_REFCLKIN_CTL_PORT2                          0x16992C
10055 #define _MG_REFCLKIN_CTL_PORT3                          0x16A92C
10056 #define _MG_REFCLKIN_CTL_PORT4                          0x16B92C
10057 #define   MG_REFCLKIN_CTL_OD_2_MUX(x)                   ((x) << 8)
10058 #define   MG_REFCLKIN_CTL_OD_2_MUX_MASK                 (0x7 << 8)
10059 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
10060                                             _MG_REFCLKIN_CTL_PORT1, \
10061                                             _MG_REFCLKIN_CTL_PORT2)
10062
10063 #define _MG_CLKTOP2_CORECLKCTL1_PORT1                   0x1688D8
10064 #define _MG_CLKTOP2_CORECLKCTL1_PORT2                   0x1698D8
10065 #define _MG_CLKTOP2_CORECLKCTL1_PORT3                   0x16A8D8
10066 #define _MG_CLKTOP2_CORECLKCTL1_PORT4                   0x16B8D8
10067 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x)          ((x) << 16)
10068 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK        (0xff << 16)
10069 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)          ((x) << 8)
10070 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK        (0xff << 8)
10071 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
10072                                                    _MG_CLKTOP2_CORECLKCTL1_PORT1, \
10073                                                    _MG_CLKTOP2_CORECLKCTL1_PORT2)
10074
10075 #define _MG_CLKTOP2_HSCLKCTL_PORT1                      0x1688D4
10076 #define _MG_CLKTOP2_HSCLKCTL_PORT2                      0x1698D4
10077 #define _MG_CLKTOP2_HSCLKCTL_PORT3                      0x16A8D4
10078 #define _MG_CLKTOP2_HSCLKCTL_PORT4                      0x16B8D4
10079 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x)          ((x) << 16)
10080 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK        (0x1 << 16)
10081 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x)        ((x) << 14)
10082 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK      (0x3 << 14)
10083 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK          (0x3 << 12)
10084 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2             (0 << 12)
10085 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3             (1 << 12)
10086 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5             (2 << 12)
10087 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7             (3 << 12)
10088 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)            ((x) << 8)
10089 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT         8
10090 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK          (0xf << 8)
10091 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
10092                                                 _MG_CLKTOP2_HSCLKCTL_PORT1, \
10093                                                 _MG_CLKTOP2_HSCLKCTL_PORT2)
10094
10095 #define _MG_PLL_DIV0_PORT1                              0x168A00
10096 #define _MG_PLL_DIV0_PORT2                              0x169A00
10097 #define _MG_PLL_DIV0_PORT3                              0x16AA00
10098 #define _MG_PLL_DIV0_PORT4                              0x16BA00
10099 #define   MG_PLL_DIV0_FRACNEN_H                         (1 << 30)
10100 #define   MG_PLL_DIV0_FBDIV_FRAC_MASK                   (0x3fffff << 8)
10101 #define   MG_PLL_DIV0_FBDIV_FRAC_SHIFT                  8
10102 #define   MG_PLL_DIV0_FBDIV_FRAC(x)                     ((x) << 8)
10103 #define   MG_PLL_DIV0_FBDIV_INT_MASK                    (0xff << 0)
10104 #define   MG_PLL_DIV0_FBDIV_INT(x)                      ((x) << 0)
10105 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
10106                                         _MG_PLL_DIV0_PORT2)
10107
10108 #define _MG_PLL_DIV1_PORT1                              0x168A04
10109 #define _MG_PLL_DIV1_PORT2                              0x169A04
10110 #define _MG_PLL_DIV1_PORT3                              0x16AA04
10111 #define _MG_PLL_DIV1_PORT4                              0x16BA04
10112 #define   MG_PLL_DIV1_IREF_NDIVRATIO(x)                 ((x) << 16)
10113 #define   MG_PLL_DIV1_DITHER_DIV_1                      (0 << 12)
10114 #define   MG_PLL_DIV1_DITHER_DIV_2                      (1 << 12)
10115 #define   MG_PLL_DIV1_DITHER_DIV_4                      (2 << 12)
10116 #define   MG_PLL_DIV1_DITHER_DIV_8                      (3 << 12)
10117 #define   MG_PLL_DIV1_NDIVRATIO(x)                      ((x) << 4)
10118 #define   MG_PLL_DIV1_FBPREDIV_MASK                     (0xf << 0)
10119 #define   MG_PLL_DIV1_FBPREDIV(x)                       ((x) << 0)
10120 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
10121                                         _MG_PLL_DIV1_PORT2)
10122
10123 #define _MG_PLL_LF_PORT1                                0x168A08
10124 #define _MG_PLL_LF_PORT2                                0x169A08
10125 #define _MG_PLL_LF_PORT3                                0x16AA08
10126 #define _MG_PLL_LF_PORT4                                0x16BA08
10127 #define   MG_PLL_LF_TDCTARGETCNT(x)                     ((x) << 24)
10128 #define   MG_PLL_LF_AFCCNTSEL_256                       (0 << 20)
10129 #define   MG_PLL_LF_AFCCNTSEL_512                       (1 << 20)
10130 #define   MG_PLL_LF_GAINCTRL(x)                         ((x) << 16)
10131 #define   MG_PLL_LF_INT_COEFF(x)                        ((x) << 8)
10132 #define   MG_PLL_LF_PROP_COEFF(x)                       ((x) << 0)
10133 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
10134                                       _MG_PLL_LF_PORT2)
10135
10136 #define _MG_PLL_FRAC_LOCK_PORT1                         0x168A0C
10137 #define _MG_PLL_FRAC_LOCK_PORT2                         0x169A0C
10138 #define _MG_PLL_FRAC_LOCK_PORT3                         0x16AA0C
10139 #define _MG_PLL_FRAC_LOCK_PORT4                         0x16BA0C
10140 #define   MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32             (1 << 18)
10141 #define   MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32            (1 << 16)
10142 #define   MG_PLL_FRAC_LOCK_LOCKTHRESH(x)                ((x) << 11)
10143 #define   MG_PLL_FRAC_LOCK_DCODITHEREN                  (1 << 10)
10144 #define   MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN               (1 << 8)
10145 #define   MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x)              ((x) << 0)
10146 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
10147                                              _MG_PLL_FRAC_LOCK_PORT1, \
10148                                              _MG_PLL_FRAC_LOCK_PORT2)
10149
10150 #define _MG_PLL_SSC_PORT1                               0x168A10
10151 #define _MG_PLL_SSC_PORT2                               0x169A10
10152 #define _MG_PLL_SSC_PORT3                               0x16AA10
10153 #define _MG_PLL_SSC_PORT4                               0x16BA10
10154 #define   MG_PLL_SSC_EN                                 (1 << 28)
10155 #define   MG_PLL_SSC_TYPE(x)                            ((x) << 26)
10156 #define   MG_PLL_SSC_STEPLENGTH(x)                      ((x) << 16)
10157 #define   MG_PLL_SSC_STEPNUM(x)                         ((x) << 10)
10158 #define   MG_PLL_SSC_FLLEN                              (1 << 9)
10159 #define   MG_PLL_SSC_STEPSIZE(x)                        ((x) << 0)
10160 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
10161                                        _MG_PLL_SSC_PORT2)
10162
10163 #define _MG_PLL_BIAS_PORT1                              0x168A14
10164 #define _MG_PLL_BIAS_PORT2                              0x169A14
10165 #define _MG_PLL_BIAS_PORT3                              0x16AA14
10166 #define _MG_PLL_BIAS_PORT4                              0x16BA14
10167 #define   MG_PLL_BIAS_BIAS_GB_SEL(x)                    ((x) << 30)
10168 #define   MG_PLL_BIAS_BIAS_GB_SEL_MASK                  (0x3 << 30)
10169 #define   MG_PLL_BIAS_INIT_DCOAMP(x)                    ((x) << 24)
10170 #define   MG_PLL_BIAS_INIT_DCOAMP_MASK                  (0x3f << 24)
10171 #define   MG_PLL_BIAS_BIAS_BONUS(x)                     ((x) << 16)
10172 #define   MG_PLL_BIAS_BIAS_BONUS_MASK                   (0xff << 16)
10173 #define   MG_PLL_BIAS_BIASCAL_EN                        (1 << 15)
10174 #define   MG_PLL_BIAS_CTRIM(x)                          ((x) << 8)
10175 #define   MG_PLL_BIAS_CTRIM_MASK                        (0x1f << 8)
10176 #define   MG_PLL_BIAS_VREF_RDAC(x)                      ((x) << 5)
10177 #define   MG_PLL_BIAS_VREF_RDAC_MASK                    (0x7 << 5)
10178 #define   MG_PLL_BIAS_IREFTRIM(x)                       ((x) << 0)
10179 #define   MG_PLL_BIAS_IREFTRIM_MASK                     (0x1f << 0)
10180 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
10181                                         _MG_PLL_BIAS_PORT2)
10182
10183 #define _MG_PLL_TDC_COLDST_BIAS_PORT1                   0x168A18
10184 #define _MG_PLL_TDC_COLDST_BIAS_PORT2                   0x169A18
10185 #define _MG_PLL_TDC_COLDST_BIAS_PORT3                   0x16AA18
10186 #define _MG_PLL_TDC_COLDST_BIAS_PORT4                   0x16BA18
10187 #define   MG_PLL_TDC_COLDST_IREFINT_EN                  (1 << 27)
10188 #define   MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x)    ((x) << 17)
10189 #define   MG_PLL_TDC_COLDST_COLDSTART                   (1 << 16)
10190 #define   MG_PLL_TDC_TDCOVCCORR_EN                      (1 << 2)
10191 #define   MG_PLL_TDC_TDCSEL(x)                          ((x) << 0)
10192 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
10193                                                    _MG_PLL_TDC_COLDST_BIAS_PORT1, \
10194                                                    _MG_PLL_TDC_COLDST_BIAS_PORT2)
10195
10196 #define _CNL_DPLL0_CFGCR0               0x6C000
10197 #define _CNL_DPLL1_CFGCR0               0x6C080
10198 #define  DPLL_CFGCR0_HDMI_MODE          (1 << 30)
10199 #define  DPLL_CFGCR0_SSC_ENABLE         (1 << 29)
10200 #define  DPLL_CFGCR0_SSC_ENABLE_ICL     (1 << 25)
10201 #define  DPLL_CFGCR0_LINK_RATE_MASK     (0xf << 25)
10202 #define  DPLL_CFGCR0_LINK_RATE_2700     (0 << 25)
10203 #define  DPLL_CFGCR0_LINK_RATE_1350     (1 << 25)
10204 #define  DPLL_CFGCR0_LINK_RATE_810      (2 << 25)
10205 #define  DPLL_CFGCR0_LINK_RATE_1620     (3 << 25)
10206 #define  DPLL_CFGCR0_LINK_RATE_1080     (4 << 25)
10207 #define  DPLL_CFGCR0_LINK_RATE_2160     (5 << 25)
10208 #define  DPLL_CFGCR0_LINK_RATE_3240     (6 << 25)
10209 #define  DPLL_CFGCR0_LINK_RATE_4050     (7 << 25)
10210 #define  DPLL_CFGCR0_DCO_FRACTION_MASK  (0x7fff << 10)
10211 #define  DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
10212 #define  DPLL_CFGCR0_DCO_FRACTION(x)    ((x) << 10)
10213 #define  DPLL_CFGCR0_DCO_INTEGER_MASK   (0x3ff)
10214 #define CNL_DPLL_CFGCR0(pll)            _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
10215
10216 #define _CNL_DPLL0_CFGCR1               0x6C004
10217 #define _CNL_DPLL1_CFGCR1               0x6C084
10218 #define  DPLL_CFGCR1_QDIV_RATIO_MASK    (0xff << 10)
10219 #define  DPLL_CFGCR1_QDIV_RATIO_SHIFT   (10)
10220 #define  DPLL_CFGCR1_QDIV_RATIO(x)      ((x) << 10)
10221 #define  DPLL_CFGCR1_QDIV_MODE_SHIFT    (9)
10222 #define  DPLL_CFGCR1_QDIV_MODE(x)       ((x) << 9)
10223 #define  DPLL_CFGCR1_KDIV_MASK          (7 << 6)
10224 #define  DPLL_CFGCR1_KDIV_SHIFT         (6)
10225 #define  DPLL_CFGCR1_KDIV(x)            ((x) << 6)
10226 #define  DPLL_CFGCR1_KDIV_1             (1 << 6)
10227 #define  DPLL_CFGCR1_KDIV_2             (2 << 6)
10228 #define  DPLL_CFGCR1_KDIV_3             (4 << 6)
10229 #define  DPLL_CFGCR1_PDIV_MASK          (0xf << 2)
10230 #define  DPLL_CFGCR1_PDIV_SHIFT         (2)
10231 #define  DPLL_CFGCR1_PDIV(x)            ((x) << 2)
10232 #define  DPLL_CFGCR1_PDIV_2             (1 << 2)
10233 #define  DPLL_CFGCR1_PDIV_3             (2 << 2)
10234 #define  DPLL_CFGCR1_PDIV_5             (4 << 2)
10235 #define  DPLL_CFGCR1_PDIV_7             (8 << 2)
10236 #define  DPLL_CFGCR1_CENTRAL_FREQ       (3 << 0)
10237 #define  DPLL_CFGCR1_CENTRAL_FREQ_8400  (3 << 0)
10238 #define  TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL  (0 << 0)
10239 #define CNL_DPLL_CFGCR1(pll)            _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
10240
10241 #define _ICL_DPLL0_CFGCR0               0x164000
10242 #define _ICL_DPLL1_CFGCR0               0x164080
10243 #define ICL_DPLL_CFGCR0(pll)            _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
10244                                                   _ICL_DPLL1_CFGCR0)
10245
10246 #define _ICL_DPLL0_CFGCR1               0x164004
10247 #define _ICL_DPLL1_CFGCR1               0x164084
10248 #define ICL_DPLL_CFGCR1(pll)            _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
10249                                                   _ICL_DPLL1_CFGCR1)
10250
10251 #define _TGL_DPLL0_CFGCR0               0x164284
10252 #define _TGL_DPLL1_CFGCR0               0x16428C
10253 /* TODO: add DPLL4 */
10254 #define _TGL_TBTPLL_CFGCR0              0x16429C
10255 #define TGL_DPLL_CFGCR0(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
10256                                                   _TGL_DPLL1_CFGCR0, \
10257                                                   _TGL_TBTPLL_CFGCR0)
10258
10259 #define _TGL_DPLL0_CFGCR1               0x164288
10260 #define _TGL_DPLL1_CFGCR1               0x164290
10261 /* TODO: add DPLL4 */
10262 #define _TGL_TBTPLL_CFGCR1              0x1642A0
10263 #define TGL_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
10264                                                    _TGL_DPLL1_CFGCR1, \
10265                                                    _TGL_TBTPLL_CFGCR1)
10266
10267 #define _DKL_PHY1_BASE                  0x168000
10268 #define _DKL_PHY2_BASE                  0x169000
10269 #define _DKL_PHY3_BASE                  0x16A000
10270 #define _DKL_PHY4_BASE                  0x16B000
10271 #define _DKL_PHY5_BASE                  0x16C000
10272 #define _DKL_PHY6_BASE                  0x16D000
10273
10274 /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
10275 #define _DKL_PLL_DIV0                   0x200
10276 #define   DKL_PLL_DIV0_INTEG_COEFF(x)   ((x) << 16)
10277 #define   DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16)
10278 #define   DKL_PLL_DIV0_PROP_COEFF(x)    ((x) << 12)
10279 #define   DKL_PLL_DIV0_PROP_COEFF_MASK  (0xF << 12)
10280 #define   DKL_PLL_DIV0_FBPREDIV_SHIFT   (8)
10281 #define   DKL_PLL_DIV0_FBPREDIV(x)      ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
10282 #define   DKL_PLL_DIV0_FBPREDIV_MASK    (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
10283 #define   DKL_PLL_DIV0_FBDIV_INT(x)     ((x) << 0)
10284 #define   DKL_PLL_DIV0_FBDIV_INT_MASK   (0xFF << 0)
10285 #define DKL_PLL_DIV0(tc_port)           _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10286                                                     _DKL_PHY2_BASE) + \
10287                                                     _DKL_PLL_DIV0)
10288
10289 #define _DKL_PLL_DIV1                           0x204
10290 #define   DKL_PLL_DIV1_IREF_TRIM(x)             ((x) << 16)
10291 #define   DKL_PLL_DIV1_IREF_TRIM_MASK           (0x1F << 16)
10292 #define   DKL_PLL_DIV1_TDC_TARGET_CNT(x)        ((x) << 0)
10293 #define   DKL_PLL_DIV1_TDC_TARGET_CNT_MASK      (0xFF << 0)
10294 #define DKL_PLL_DIV1(tc_port)           _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10295                                                     _DKL_PHY2_BASE) + \
10296                                                     _DKL_PLL_DIV1)
10297
10298 #define _DKL_PLL_SSC                            0x210
10299 #define   DKL_PLL_SSC_IREF_NDIV_RATIO(x)        ((x) << 29)
10300 #define   DKL_PLL_SSC_IREF_NDIV_RATIO_MASK      (0x7 << 29)
10301 #define   DKL_PLL_SSC_STEP_LEN(x)               ((x) << 16)
10302 #define   DKL_PLL_SSC_STEP_LEN_MASK             (0xFF << 16)
10303 #define   DKL_PLL_SSC_STEP_NUM(x)               ((x) << 11)
10304 #define   DKL_PLL_SSC_STEP_NUM_MASK             (0x7 << 11)
10305 #define   DKL_PLL_SSC_EN                        (1 << 9)
10306 #define DKL_PLL_SSC(tc_port)            _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10307                                                     _DKL_PHY2_BASE) + \
10308                                                     _DKL_PLL_SSC)
10309
10310 #define _DKL_PLL_BIAS                   0x214
10311 #define   DKL_PLL_BIAS_FRAC_EN_H        (1 << 30)
10312 #define   DKL_PLL_BIAS_FBDIV_SHIFT      (8)
10313 #define   DKL_PLL_BIAS_FBDIV_FRAC(x)    ((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
10314 #define   DKL_PLL_BIAS_FBDIV_FRAC_MASK  (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
10315 #define DKL_PLL_BIAS(tc_port)           _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10316                                                     _DKL_PHY2_BASE) + \
10317                                                     _DKL_PLL_BIAS)
10318
10319 #define _DKL_PLL_TDC_COLDST_BIAS                0x218
10320 #define   DKL_PLL_TDC_SSC_STEP_SIZE(x)          ((x) << 8)
10321 #define   DKL_PLL_TDC_SSC_STEP_SIZE_MASK        (0xFF << 8)
10322 #define   DKL_PLL_TDC_FEED_FWD_GAIN(x)          ((x) << 0)
10323 #define   DKL_PLL_TDC_FEED_FWD_GAIN_MASK        (0xFF << 0)
10324 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
10325                                                      _DKL_PHY1_BASE, \
10326                                                      _DKL_PHY2_BASE) + \
10327                                                      _DKL_PLL_TDC_COLDST_BIAS)
10328
10329 #define _DKL_REFCLKIN_CTL               0x12C
10330 /* Bits are the same as MG_REFCLKIN_CTL */
10331 #define DKL_REFCLKIN_CTL(tc_port)       _MMIO(_PORT(tc_port, \
10332                                                     _DKL_PHY1_BASE, \
10333                                                     _DKL_PHY2_BASE) + \
10334                                               _DKL_REFCLKIN_CTL)
10335
10336 #define _DKL_CLKTOP2_HSCLKCTL           0xD4
10337 /* Bits are the same as MG_CLKTOP2_HSCLKCTL */
10338 #define DKL_CLKTOP2_HSCLKCTL(tc_port)   _MMIO(_PORT(tc_port, \
10339                                                     _DKL_PHY1_BASE, \
10340                                                     _DKL_PHY2_BASE) + \
10341                                               _DKL_CLKTOP2_HSCLKCTL)
10342
10343 #define _DKL_CLKTOP2_CORECLKCTL1                0xD8
10344 /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
10345 #define DKL_CLKTOP2_CORECLKCTL1(tc_port)        _MMIO(_PORT(tc_port, \
10346                                                             _DKL_PHY1_BASE, \
10347                                                             _DKL_PHY2_BASE) + \
10348                                                       _DKL_CLKTOP2_CORECLKCTL1)
10349
10350 #define _DKL_TX_DPCNTL0                         0x2C0
10351 #define  DKL_TX_PRESHOOT_COEFF(x)                       ((x) << 13)
10352 #define  DKL_TX_PRESHOOT_COEFF_MASK                     (0x1f << 13)
10353 #define  DKL_TX_DE_EMPHASIS_COEFF(x)            ((x) << 8)
10354 #define  DKL_TX_DE_EMPAHSIS_COEFF_MASK          (0x1f << 8)
10355 #define  DKL_TX_VSWING_CONTROL(x)                       ((x) << 0)
10356 #define  DKL_TX_VSWING_CONTROL_MASK                     (0x7 << 0)
10357 #define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \
10358                                                      _DKL_PHY1_BASE, \
10359                                                      _DKL_PHY2_BASE) + \
10360                                                      _DKL_TX_DPCNTL0)
10361
10362 #define _DKL_TX_DPCNTL1                         0x2C4
10363 /* Bits are the same as DKL_TX_DPCNTRL0 */
10364 #define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \
10365                                                      _DKL_PHY1_BASE, \
10366                                                      _DKL_PHY2_BASE) + \
10367                                                      _DKL_TX_DPCNTL1)
10368
10369 #define _DKL_TX_DPCNTL2                         0x2C8
10370 #define  DKL_TX_DP20BITMODE                             (1 << 2)
10371 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
10372                                                      _DKL_PHY1_BASE, \
10373                                                      _DKL_PHY2_BASE) + \
10374                                                      _DKL_TX_DPCNTL2)
10375
10376 #define _DKL_TX_FW_CALIB                                0x2F8
10377 #define  DKL_TX_CFG_DISABLE_WAIT_INIT                   (1 << 7)
10378 #define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \
10379                                                      _DKL_PHY1_BASE, \
10380                                                      _DKL_PHY2_BASE) + \
10381                                                      _DKL_TX_FW_CALIB)
10382
10383 #define _DKL_TX_PMD_LANE_SUS                            0xD00
10384 #define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
10385                                                           _DKL_PHY1_BASE, \
10386                                                           _DKL_PHY2_BASE) + \
10387                                                           _DKL_TX_PMD_LANE_SUS)
10388
10389 #define _DKL_TX_DW17                                    0xDC4
10390 #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
10391                                                      _DKL_PHY1_BASE, \
10392                                                      _DKL_PHY2_BASE) + \
10393                                                      _DKL_TX_DW17)
10394
10395 #define _DKL_TX_DW18                                    0xDC8
10396 #define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \
10397                                                      _DKL_PHY1_BASE, \
10398                                                      _DKL_PHY2_BASE) + \
10399                                                      _DKL_TX_DW18)
10400
10401 #define _DKL_DP_MODE                                    0xA0
10402 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
10403                                                      _DKL_PHY1_BASE, \
10404                                                      _DKL_PHY2_BASE) + \
10405                                                      _DKL_DP_MODE)
10406
10407 #define _DKL_CMN_UC_DW27                        0x36C
10408 #define  DKL_CMN_UC_DW27_UC_HEALTH              (0x1 << 15)
10409 #define DKL_CMN_UC_DW_27(tc_port)               _MMIO(_PORT(tc_port, \
10410                                                             _DKL_PHY1_BASE, \
10411                                                             _DKL_PHY2_BASE) + \
10412                                                             _DKL_CMN_UC_DW27)
10413
10414 /*
10415  * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
10416  * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
10417  * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
10418  * bits that point the 4KB window into the full PHY register space.
10419  */
10420 #define _HIP_INDEX_REG0                 0x1010A0
10421 #define _HIP_INDEX_REG1                 0x1010A4
10422 #define HIP_INDEX_REG(tc_port)          _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
10423                                               : _HIP_INDEX_REG1)
10424 #define _HIP_INDEX_SHIFT(tc_port)       (8 * ((tc_port) % 4))
10425 #define HIP_INDEX_VAL(tc_port, val)     ((val) << _HIP_INDEX_SHIFT(tc_port))
10426
10427 /* BXT display engine PLL */
10428 #define BXT_DE_PLL_CTL                  _MMIO(0x6d000)
10429 #define   BXT_DE_PLL_RATIO(x)           (x)     /* {60,65,100} * 19.2MHz */
10430 #define   BXT_DE_PLL_RATIO_MASK         0xff
10431
10432 #define BXT_DE_PLL_ENABLE               _MMIO(0x46070)
10433 #define   BXT_DE_PLL_PLL_ENABLE         (1 << 31)
10434 #define   BXT_DE_PLL_LOCK               (1 << 30)
10435 #define   CNL_CDCLK_PLL_RATIO(x)        (x)
10436 #define   CNL_CDCLK_PLL_RATIO_MASK      0xff
10437
10438 /* GEN9 DC */
10439 #define DC_STATE_EN                     _MMIO(0x45504)
10440 #define  DC_STATE_DISABLE               0
10441 #define  DC_STATE_EN_DC3CO              REG_BIT(30)
10442 #define  DC_STATE_DC3CO_STATUS          REG_BIT(29)
10443 #define  DC_STATE_EN_UPTO_DC5           (1 << 0)
10444 #define  DC_STATE_EN_DC9                (1 << 3)
10445 #define  DC_STATE_EN_UPTO_DC6           (2 << 0)
10446 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
10447
10448 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
10449 #define  DC_STATE_DEBUG_MASK_CORES      (1 << 0)
10450 #define  DC_STATE_DEBUG_MASK_MEMORY_UP  (1 << 1)
10451
10452 #define BXT_P_CR_MC_BIOS_REQ_0_0_0      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
10453 #define  BXT_REQ_DATA_MASK                      0x3F
10454 #define  BXT_DRAM_CHANNEL_ACTIVE_SHIFT          12
10455 #define  BXT_DRAM_CHANNEL_ACTIVE_MASK           (0xF << 12)
10456 #define  BXT_MEMORY_FREQ_MULTIPLIER_HZ          133333333
10457
10458 #define BXT_D_CR_DRP0_DUNIT8                    0x1000
10459 #define BXT_D_CR_DRP0_DUNIT9                    0x1200
10460 #define  BXT_D_CR_DRP0_DUNIT_START              8
10461 #define  BXT_D_CR_DRP0_DUNIT_END                11
10462 #define BXT_D_CR_DRP0_DUNIT(x)  _MMIO(MCHBAR_MIRROR_BASE_SNB + \
10463                                       _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
10464                                                  BXT_D_CR_DRP0_DUNIT9))
10465 #define  BXT_DRAM_RANK_MASK                     0x3
10466 #define  BXT_DRAM_RANK_SINGLE                   0x1
10467 #define  BXT_DRAM_RANK_DUAL                     0x3
10468 #define  BXT_DRAM_WIDTH_MASK                    (0x3 << 4)
10469 #define  BXT_DRAM_WIDTH_SHIFT                   4
10470 #define  BXT_DRAM_WIDTH_X8                      (0x0 << 4)
10471 #define  BXT_DRAM_WIDTH_X16                     (0x1 << 4)
10472 #define  BXT_DRAM_WIDTH_X32                     (0x2 << 4)
10473 #define  BXT_DRAM_WIDTH_X64                     (0x3 << 4)
10474 #define  BXT_DRAM_SIZE_MASK                     (0x7 << 6)
10475 #define  BXT_DRAM_SIZE_SHIFT                    6
10476 #define  BXT_DRAM_SIZE_4GBIT                    (0x0 << 6)
10477 #define  BXT_DRAM_SIZE_6GBIT                    (0x1 << 6)
10478 #define  BXT_DRAM_SIZE_8GBIT                    (0x2 << 6)
10479 #define  BXT_DRAM_SIZE_12GBIT                   (0x3 << 6)
10480 #define  BXT_DRAM_SIZE_16GBIT                   (0x4 << 6)
10481 #define  BXT_DRAM_TYPE_MASK                     (0x7 << 22)
10482 #define  BXT_DRAM_TYPE_SHIFT                    22
10483 #define  BXT_DRAM_TYPE_DDR3                     (0x0 << 22)
10484 #define  BXT_DRAM_TYPE_LPDDR3                   (0x1 << 22)
10485 #define  BXT_DRAM_TYPE_LPDDR4                   (0x2 << 22)
10486 #define  BXT_DRAM_TYPE_DDR4                     (0x4 << 22)
10487
10488 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ           266666666
10489 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU       _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
10490 #define  SKL_REQ_DATA_MASK                      (0xF << 0)
10491
10492 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
10493 #define  SKL_DRAM_DDR_TYPE_MASK                 (0x3 << 0)
10494 #define  SKL_DRAM_DDR_TYPE_DDR4                 (0 << 0)
10495 #define  SKL_DRAM_DDR_TYPE_DDR3                 (1 << 0)
10496 #define  SKL_DRAM_DDR_TYPE_LPDDR3               (2 << 0)
10497 #define  SKL_DRAM_DDR_TYPE_LPDDR4               (3 << 0)
10498
10499 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
10500 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
10501 #define  SKL_DRAM_S_SHIFT                       16
10502 #define  SKL_DRAM_SIZE_MASK                     0x3F
10503 #define  SKL_DRAM_WIDTH_MASK                    (0x3 << 8)
10504 #define  SKL_DRAM_WIDTH_SHIFT                   8
10505 #define  SKL_DRAM_WIDTH_X8                      (0x0 << 8)
10506 #define  SKL_DRAM_WIDTH_X16                     (0x1 << 8)
10507 #define  SKL_DRAM_WIDTH_X32                     (0x2 << 8)
10508 #define  SKL_DRAM_RANK_MASK                     (0x1 << 10)
10509 #define  SKL_DRAM_RANK_SHIFT                    10
10510 #define  SKL_DRAM_RANK_1                        (0x0 << 10)
10511 #define  SKL_DRAM_RANK_2                        (0x1 << 10)
10512 #define  SKL_DRAM_RANK_MASK                     (0x1 << 10)
10513 #define  CNL_DRAM_SIZE_MASK                     0x7F
10514 #define  CNL_DRAM_WIDTH_MASK                    (0x3 << 7)
10515 #define  CNL_DRAM_WIDTH_SHIFT                   7
10516 #define  CNL_DRAM_WIDTH_X8                      (0x0 << 7)
10517 #define  CNL_DRAM_WIDTH_X16                     (0x1 << 7)
10518 #define  CNL_DRAM_WIDTH_X32                     (0x2 << 7)
10519 #define  CNL_DRAM_RANK_MASK                     (0x3 << 9)
10520 #define  CNL_DRAM_RANK_SHIFT                    9
10521 #define  CNL_DRAM_RANK_1                        (0x0 << 9)
10522 #define  CNL_DRAM_RANK_2                        (0x1 << 9)
10523 #define  CNL_DRAM_RANK_3                        (0x2 << 9)
10524 #define  CNL_DRAM_RANK_4                        (0x3 << 9)
10525
10526 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
10527  * since on HSW we can't write to it using I915_WRITE. */
10528 #define D_COMP_HSW                      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
10529 #define D_COMP_BDW                      _MMIO(0x138144)
10530 #define  D_COMP_RCOMP_IN_PROGRESS       (1 << 9)
10531 #define  D_COMP_COMP_FORCE              (1 << 8)
10532 #define  D_COMP_COMP_DISABLE            (1 << 0)
10533
10534 /* Pipe WM_LINETIME - watermark line time */
10535 #define _PIPE_WM_LINETIME_A             0x45270
10536 #define _PIPE_WM_LINETIME_B             0x45274
10537 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
10538 #define   PIPE_WM_LINETIME_MASK                 (0x1ff)
10539 #define   PIPE_WM_LINETIME_TIME(x)              ((x))
10540 #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK    (0x1ff << 16)
10541 #define   PIPE_WM_LINETIME_IPS_LINETIME(x)      ((x) << 16)
10542
10543 /* SFUSE_STRAP */
10544 #define SFUSE_STRAP                     _MMIO(0xc2014)
10545 #define  SFUSE_STRAP_FUSE_LOCK          (1 << 13)
10546 #define  SFUSE_STRAP_RAW_FREQUENCY      (1 << 8)
10547 #define  SFUSE_STRAP_DISPLAY_DISABLED   (1 << 7)
10548 #define  SFUSE_STRAP_CRT_DISABLED       (1 << 6)
10549 #define  SFUSE_STRAP_DDIF_DETECTED      (1 << 3)
10550 #define  SFUSE_STRAP_DDIB_DETECTED      (1 << 2)
10551 #define  SFUSE_STRAP_DDIC_DETECTED      (1 << 1)
10552 #define  SFUSE_STRAP_DDID_DETECTED      (1 << 0)
10553
10554 #define WM_MISC                         _MMIO(0x45260)
10555 #define  WM_MISC_DATA_PARTITION_5_6     (1 << 0)
10556
10557 #define WM_DBG                          _MMIO(0x45280)
10558 #define  WM_DBG_DISALLOW_MULTIPLE_LP    (1 << 0)
10559 #define  WM_DBG_DISALLOW_MAXFIFO        (1 << 1)
10560 #define  WM_DBG_DISALLOW_SPRITE         (1 << 2)
10561
10562 /* pipe CSC */
10563 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
10564 #define _PIPE_A_CSC_COEFF_BY    0x49014
10565 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
10566 #define _PIPE_A_CSC_COEFF_BU    0x4901c
10567 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
10568 #define _PIPE_A_CSC_COEFF_BV    0x49024
10569
10570 #define _PIPE_A_CSC_MODE        0x49028
10571 #define  ICL_CSC_ENABLE                 (1 << 31) /* icl+ */
10572 #define  ICL_OUTPUT_CSC_ENABLE          (1 << 30) /* icl+ */
10573 #define  CSC_BLACK_SCREEN_OFFSET        (1 << 2) /* ilk/snb */
10574 #define  CSC_POSITION_BEFORE_GAMMA      (1 << 1) /* pre-glk */
10575 #define  CSC_MODE_YUV_TO_RGB            (1 << 0) /* ilk/snb */
10576
10577 #define _PIPE_A_CSC_PREOFF_HI   0x49030
10578 #define _PIPE_A_CSC_PREOFF_ME   0x49034
10579 #define _PIPE_A_CSC_PREOFF_LO   0x49038
10580 #define _PIPE_A_CSC_POSTOFF_HI  0x49040
10581 #define _PIPE_A_CSC_POSTOFF_ME  0x49044
10582 #define _PIPE_A_CSC_POSTOFF_LO  0x49048
10583
10584 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
10585 #define _PIPE_B_CSC_COEFF_BY    0x49114
10586 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
10587 #define _PIPE_B_CSC_COEFF_BU    0x4911c
10588 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
10589 #define _PIPE_B_CSC_COEFF_BV    0x49124
10590 #define _PIPE_B_CSC_MODE        0x49128
10591 #define _PIPE_B_CSC_PREOFF_HI   0x49130
10592 #define _PIPE_B_CSC_PREOFF_ME   0x49134
10593 #define _PIPE_B_CSC_PREOFF_LO   0x49138
10594 #define _PIPE_B_CSC_POSTOFF_HI  0x49140
10595 #define _PIPE_B_CSC_POSTOFF_ME  0x49144
10596 #define _PIPE_B_CSC_POSTOFF_LO  0x49148
10597
10598 #define PIPE_CSC_COEFF_RY_GY(pipe)      _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
10599 #define PIPE_CSC_COEFF_BY(pipe)         _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
10600 #define PIPE_CSC_COEFF_RU_GU(pipe)      _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
10601 #define PIPE_CSC_COEFF_BU(pipe)         _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
10602 #define PIPE_CSC_COEFF_RV_GV(pipe)      _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
10603 #define PIPE_CSC_COEFF_BV(pipe)         _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
10604 #define PIPE_CSC_MODE(pipe)             _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
10605 #define PIPE_CSC_PREOFF_HI(pipe)        _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
10606 #define PIPE_CSC_PREOFF_ME(pipe)        _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
10607 #define PIPE_CSC_PREOFF_LO(pipe)        _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
10608 #define PIPE_CSC_POSTOFF_HI(pipe)       _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
10609 #define PIPE_CSC_POSTOFF_ME(pipe)       _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
10610 #define PIPE_CSC_POSTOFF_LO(pipe)       _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
10611
10612 /* Pipe Output CSC */
10613 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY  0x49050
10614 #define _PIPE_A_OUTPUT_CSC_COEFF_BY     0x49054
10615 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU  0x49058
10616 #define _PIPE_A_OUTPUT_CSC_COEFF_BU     0x4905c
10617 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV  0x49060
10618 #define _PIPE_A_OUTPUT_CSC_COEFF_BV     0x49064
10619 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI    0x49068
10620 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME    0x4906c
10621 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO    0x49070
10622 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI   0x49074
10623 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME   0x49078
10624 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO   0x4907c
10625
10626 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY  0x49150
10627 #define _PIPE_B_OUTPUT_CSC_COEFF_BY     0x49154
10628 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU  0x49158
10629 #define _PIPE_B_OUTPUT_CSC_COEFF_BU     0x4915c
10630 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV  0x49160
10631 #define _PIPE_B_OUTPUT_CSC_COEFF_BV     0x49164
10632 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI    0x49168
10633 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME    0x4916c
10634 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO    0x49170
10635 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI   0x49174
10636 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME   0x49178
10637 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO   0x4917c
10638
10639 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe)       _MMIO_PIPE(pipe,\
10640                                                            _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
10641                                                            _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
10642 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe)          _MMIO_PIPE(pipe, \
10643                                                            _PIPE_A_OUTPUT_CSC_COEFF_BY, \
10644                                                            _PIPE_B_OUTPUT_CSC_COEFF_BY)
10645 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe)       _MMIO_PIPE(pipe, \
10646                                                            _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
10647                                                            _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
10648 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe)          _MMIO_PIPE(pipe, \
10649                                                            _PIPE_A_OUTPUT_CSC_COEFF_BU, \
10650                                                            _PIPE_B_OUTPUT_CSC_COEFF_BU)
10651 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe)       _MMIO_PIPE(pipe, \
10652                                                            _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
10653                                                            _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
10654 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe)          _MMIO_PIPE(pipe, \
10655                                                            _PIPE_A_OUTPUT_CSC_COEFF_BV, \
10656                                                            _PIPE_B_OUTPUT_CSC_COEFF_BV)
10657 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe)         _MMIO_PIPE(pipe, \
10658                                                            _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
10659                                                            _PIPE_B_OUTPUT_CSC_PREOFF_HI)
10660 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe)         _MMIO_PIPE(pipe, \
10661                                                            _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
10662                                                            _PIPE_B_OUTPUT_CSC_PREOFF_ME)
10663 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe)         _MMIO_PIPE(pipe, \
10664                                                            _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
10665                                                            _PIPE_B_OUTPUT_CSC_PREOFF_LO)
10666 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe)        _MMIO_PIPE(pipe, \
10667                                                            _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
10668                                                            _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
10669 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe)        _MMIO_PIPE(pipe, \
10670                                                            _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
10671                                                            _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
10672 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe)        _MMIO_PIPE(pipe, \
10673                                                            _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
10674                                                            _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
10675
10676 /* pipe degamma/gamma LUTs on IVB+ */
10677 #define _PAL_PREC_INDEX_A       0x4A400
10678 #define _PAL_PREC_INDEX_B       0x4AC00
10679 #define _PAL_PREC_INDEX_C       0x4B400
10680 #define   PAL_PREC_10_12_BIT            (0 << 31)
10681 #define   PAL_PREC_SPLIT_MODE           (1 << 31)
10682 #define   PAL_PREC_AUTO_INCREMENT       (1 << 15)
10683 #define   PAL_PREC_INDEX_VALUE_MASK     (0x3ff << 0)
10684 #define   PAL_PREC_INDEX_VALUE(x)       ((x) << 0)
10685 #define _PAL_PREC_DATA_A        0x4A404
10686 #define _PAL_PREC_DATA_B        0x4AC04
10687 #define _PAL_PREC_DATA_C        0x4B404
10688 #define _PAL_PREC_GC_MAX_A      0x4A410
10689 #define _PAL_PREC_GC_MAX_B      0x4AC10
10690 #define _PAL_PREC_GC_MAX_C      0x4B410
10691 #define   PREC_PAL_DATA_RED_MASK        REG_GENMASK(29, 20)
10692 #define   PREC_PAL_DATA_GREEN_MASK      REG_GENMASK(19, 10)
10693 #define   PREC_PAL_DATA_BLUE_MASK       REG_GENMASK(9, 0)
10694 #define _PAL_PREC_EXT_GC_MAX_A  0x4A420
10695 #define _PAL_PREC_EXT_GC_MAX_B  0x4AC20
10696 #define _PAL_PREC_EXT_GC_MAX_C  0x4B420
10697 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
10698 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
10699 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
10700
10701 #define PREC_PAL_INDEX(pipe)            _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
10702 #define PREC_PAL_DATA(pipe)             _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
10703 #define PREC_PAL_GC_MAX(pipe, i)        _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
10704 #define PREC_PAL_EXT_GC_MAX(pipe, i)    _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
10705 #define PREC_PAL_EXT2_GC_MAX(pipe, i)   _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
10706
10707 #define _PRE_CSC_GAMC_INDEX_A   0x4A484
10708 #define _PRE_CSC_GAMC_INDEX_B   0x4AC84
10709 #define _PRE_CSC_GAMC_INDEX_C   0x4B484
10710 #define   PRE_CSC_GAMC_AUTO_INCREMENT   (1 << 10)
10711 #define _PRE_CSC_GAMC_DATA_A    0x4A488
10712 #define _PRE_CSC_GAMC_DATA_B    0x4AC88
10713 #define _PRE_CSC_GAMC_DATA_C    0x4B488
10714
10715 #define PRE_CSC_GAMC_INDEX(pipe)        _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
10716 #define PRE_CSC_GAMC_DATA(pipe)         _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
10717
10718 /* ICL Multi segmented gamma */
10719 #define _PAL_PREC_MULTI_SEG_INDEX_A     0x4A408
10720 #define _PAL_PREC_MULTI_SEG_INDEX_B     0x4AC08
10721 #define  PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT          REG_BIT(15)
10722 #define  PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK        REG_GENMASK(4, 0)
10723
10724 #define _PAL_PREC_MULTI_SEG_DATA_A      0x4A40C
10725 #define _PAL_PREC_MULTI_SEG_DATA_B      0x4AC0C
10726
10727 #define PREC_PAL_MULTI_SEG_INDEX(pipe)  _MMIO_PIPE(pipe, \
10728                                         _PAL_PREC_MULTI_SEG_INDEX_A, \
10729                                         _PAL_PREC_MULTI_SEG_INDEX_B)
10730 #define PREC_PAL_MULTI_SEG_DATA(pipe)   _MMIO_PIPE(pipe, \
10731                                         _PAL_PREC_MULTI_SEG_DATA_A, \
10732                                         _PAL_PREC_MULTI_SEG_DATA_B)
10733
10734 /* pipe CSC & degamma/gamma LUTs on CHV */
10735 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
10736 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
10737 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
10738 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
10739 #define _CGM_PIPE_A_CSC_COEFF8  (VLV_DISPLAY_BASE + 0x67910)
10740 #define _CGM_PIPE_A_DEGAMMA     (VLV_DISPLAY_BASE + 0x66000)
10741 #define _CGM_PIPE_A_GAMMA       (VLV_DISPLAY_BASE + 0x67000)
10742 #define _CGM_PIPE_A_MODE        (VLV_DISPLAY_BASE + 0x67A00)
10743 #define   CGM_PIPE_MODE_GAMMA   (1 << 2)
10744 #define   CGM_PIPE_MODE_CSC     (1 << 1)
10745 #define   CGM_PIPE_MODE_DEGAMMA (1 << 0)
10746 #define   CGM_PIPE_GAMMA_RED_MASK   REG_GENMASK(9, 0)
10747 #define   CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)
10748 #define   CGM_PIPE_GAMMA_BLUE_MASK  REG_GENMASK(9, 0)
10749
10750 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
10751 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
10752 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
10753 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
10754 #define _CGM_PIPE_B_CSC_COEFF8  (VLV_DISPLAY_BASE + 0x69910)
10755 #define _CGM_PIPE_B_DEGAMMA     (VLV_DISPLAY_BASE + 0x68000)
10756 #define _CGM_PIPE_B_GAMMA       (VLV_DISPLAY_BASE + 0x69000)
10757 #define _CGM_PIPE_B_MODE        (VLV_DISPLAY_BASE + 0x69A00)
10758
10759 #define CGM_PIPE_CSC_COEFF01(pipe)      _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
10760 #define CGM_PIPE_CSC_COEFF23(pipe)      _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
10761 #define CGM_PIPE_CSC_COEFF45(pipe)      _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
10762 #define CGM_PIPE_CSC_COEFF67(pipe)      _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
10763 #define CGM_PIPE_CSC_COEFF8(pipe)       _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
10764 #define CGM_PIPE_DEGAMMA(pipe, i, w)    _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
10765 #define CGM_PIPE_GAMMA(pipe, i, w)      _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
10766 #define CGM_PIPE_MODE(pipe)             _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
10767
10768 /* MIPI DSI registers */
10769
10770 #define _MIPI_PORT(port, a, c)  (((port) == PORT_A) ? a : c)    /* ports A and C only */
10771 #define _MMIO_MIPI(port, a, c)  _MMIO(_MIPI_PORT(port, a, c))
10772
10773 /* Gen11 DSI */
10774 #define _MMIO_DSI(tc, dsi0, dsi1)       _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
10775                                                     dsi0, dsi1)
10776
10777 #define MIPIO_TXESC_CLK_DIV1                    _MMIO(0x160004)
10778 #define  GLK_TX_ESC_CLK_DIV1_MASK                       0x3FF
10779 #define MIPIO_TXESC_CLK_DIV2                    _MMIO(0x160008)
10780 #define  GLK_TX_ESC_CLK_DIV2_MASK                       0x3FF
10781
10782 #define _ICL_DSI_ESC_CLK_DIV0           0x6b090
10783 #define _ICL_DSI_ESC_CLK_DIV1           0x6b890
10784 #define ICL_DSI_ESC_CLK_DIV(port)       _MMIO_PORT((port),      \
10785                                                         _ICL_DSI_ESC_CLK_DIV0, \
10786                                                         _ICL_DSI_ESC_CLK_DIV1)
10787 #define _ICL_DPHY_ESC_CLK_DIV0          0x162190
10788 #define _ICL_DPHY_ESC_CLK_DIV1          0x6C190
10789 #define ICL_DPHY_ESC_CLK_DIV(port)      _MMIO_PORT((port),      \
10790                                                 _ICL_DPHY_ESC_CLK_DIV0, \
10791                                                 _ICL_DPHY_ESC_CLK_DIV1)
10792 #define  ICL_BYTE_CLK_PER_ESC_CLK_MASK          (0x1f << 16)
10793 #define  ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16
10794 #define  ICL_ESC_CLK_DIV_MASK                   0x1ff
10795 #define  ICL_ESC_CLK_DIV_SHIFT                  0
10796 #define DSI_MAX_ESC_CLK                 20000           /* in KHz */
10797
10798 #define _DSI_CMD_FRMCTL_0               0x6b034
10799 #define _DSI_CMD_FRMCTL_1               0x6b834
10800 #define DSI_CMD_FRMCTL(port)            _MMIO_PORT(port,        \
10801                                                    _DSI_CMD_FRMCTL_0,\
10802                                                    _DSI_CMD_FRMCTL_1)
10803 #define   DSI_FRAME_UPDATE_REQUEST              (1 << 31)
10804 #define   DSI_PERIODIC_FRAME_UPDATE_ENABLE      (1 << 29)
10805 #define   DSI_NULL_PACKET_ENABLE                (1 << 28)
10806 #define   DSI_FRAME_IN_PROGRESS                 (1 << 0)
10807
10808 #define _DSI_INTR_MASK_REG_0            0x6b070
10809 #define _DSI_INTR_MASK_REG_1            0x6b870
10810 #define DSI_INTR_MASK_REG(port)         _MMIO_PORT(port,        \
10811                                                    _DSI_INTR_MASK_REG_0,\
10812                                                    _DSI_INTR_MASK_REG_1)
10813
10814 #define _DSI_INTR_IDENT_REG_0           0x6b074
10815 #define _DSI_INTR_IDENT_REG_1           0x6b874
10816 #define DSI_INTR_IDENT_REG(port)        _MMIO_PORT(port,        \
10817                                                    _DSI_INTR_IDENT_REG_0,\
10818                                                    _DSI_INTR_IDENT_REG_1)
10819 #define   DSI_TE_EVENT                          (1 << 31)
10820 #define   DSI_RX_DATA_OR_BTA_TERMINATED         (1 << 30)
10821 #define   DSI_TX_DATA                           (1 << 29)
10822 #define   DSI_ULPS_ENTRY_DONE                   (1 << 28)
10823 #define   DSI_NON_TE_TRIGGER_RECEIVED           (1 << 27)
10824 #define   DSI_HOST_CHKSUM_ERROR                 (1 << 26)
10825 #define   DSI_HOST_MULTI_ECC_ERROR              (1 << 25)
10826 #define   DSI_HOST_SINGL_ECC_ERROR              (1 << 24)
10827 #define   DSI_HOST_CONTENTION_DETECTED          (1 << 23)
10828 #define   DSI_HOST_FALSE_CONTROL_ERROR          (1 << 22)
10829 #define   DSI_HOST_TIMEOUT_ERROR                (1 << 21)
10830 #define   DSI_HOST_LOW_POWER_TX_SYNC_ERROR      (1 << 20)
10831 #define   DSI_HOST_ESCAPE_MODE_ENTRY_ERROR      (1 << 19)
10832 #define   DSI_FRAME_UPDATE_DONE                 (1 << 16)
10833 #define   DSI_PROTOCOL_VIOLATION_REPORTED       (1 << 15)
10834 #define   DSI_INVALID_TX_LENGTH                 (1 << 13)
10835 #define   DSI_INVALID_VC                        (1 << 12)
10836 #define   DSI_INVALID_DATA_TYPE                 (1 << 11)
10837 #define   DSI_PERIPHERAL_CHKSUM_ERROR           (1 << 10)
10838 #define   DSI_PERIPHERAL_MULTI_ECC_ERROR        (1 << 9)
10839 #define   DSI_PERIPHERAL_SINGLE_ECC_ERROR       (1 << 8)
10840 #define   DSI_PERIPHERAL_CONTENTION_DETECTED    (1 << 7)
10841 #define   DSI_PERIPHERAL_FALSE_CTRL_ERROR       (1 << 6)
10842 #define   DSI_PERIPHERAL_TIMEOUT_ERROR          (1 << 5)
10843 #define   DSI_PERIPHERAL_LP_TX_SYNC_ERROR       (1 << 4)
10844 #define   DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR (1 << 3)
10845 #define   DSI_EOT_SYNC_ERROR                    (1 << 2)
10846 #define   DSI_SOT_SYNC_ERROR                    (1 << 1)
10847 #define   DSI_SOT_ERROR                         (1 << 0)
10848
10849 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
10850 #define GEN4_TIMESTAMP          _MMIO(0x2358)
10851 #define ILK_TIMESTAMP_HI        _MMIO(0x70070)
10852 #define IVB_TIMESTAMP_CTR       _MMIO(0x44070)
10853
10854 #define GEN9_TIMESTAMP_OVERRIDE                         _MMIO(0x44074)
10855 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT       0
10856 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK        0x3ff
10857 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT   12
10858 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK    (0xf << 12)
10859
10860 #define _PIPE_FRMTMSTMP_A               0x70048
10861 #define PIPE_FRMTMSTMP(pipe)            \
10862                         _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
10863
10864 /* BXT MIPI clock controls */
10865 #define BXT_MAX_VAR_OUTPUT_KHZ                  39500
10866
10867 #define BXT_MIPI_CLOCK_CTL                      _MMIO(0x46090)
10868 #define  BXT_MIPI1_DIV_SHIFT                    26
10869 #define  BXT_MIPI2_DIV_SHIFT                    10
10870 #define  BXT_MIPI_DIV_SHIFT(port)               \
10871                         _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
10872                                         BXT_MIPI2_DIV_SHIFT)
10873
10874 /* TX control divider to select actual TX clock output from (8x/var) */
10875 #define  BXT_MIPI1_TX_ESCLK_SHIFT               26
10876 #define  BXT_MIPI2_TX_ESCLK_SHIFT               10
10877 #define  BXT_MIPI_TX_ESCLK_SHIFT(port)          \
10878                         _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
10879                                         BXT_MIPI2_TX_ESCLK_SHIFT)
10880 #define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK         (0x3F << 26)
10881 #define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK         (0x3F << 10)
10882 #define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)    \
10883                         _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
10884                                         BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
10885 #define  BXT_MIPI_TX_ESCLK_DIVIDER(port, val)   \
10886                 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
10887 /* RX upper control divider to select actual RX clock output from 8x */
10888 #define  BXT_MIPI1_RX_ESCLK_UPPER_SHIFT         21
10889 #define  BXT_MIPI2_RX_ESCLK_UPPER_SHIFT         5
10890 #define  BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)            \
10891                         _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
10892                                         BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
10893 #define  BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK           (3 << 21)
10894 #define  BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK           (3 << 5)
10895 #define  BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)      \
10896                         _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
10897                                         BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
10898 #define  BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val)     \
10899                 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
10900 /* 8/3X divider to select the actual 8/3X clock output from 8x */
10901 #define  BXT_MIPI1_8X_BY3_SHIFT                19
10902 #define  BXT_MIPI2_8X_BY3_SHIFT                3
10903 #define  BXT_MIPI_8X_BY3_SHIFT(port)          \
10904                         _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
10905                                         BXT_MIPI2_8X_BY3_SHIFT)
10906 #define  BXT_MIPI1_8X_BY3_DIVIDER_MASK         (3 << 19)
10907 #define  BXT_MIPI2_8X_BY3_DIVIDER_MASK         (3 << 3)
10908 #define  BXT_MIPI_8X_BY3_DIVIDER_MASK(port)    \
10909                         _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
10910                                                 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
10911 #define  BXT_MIPI_8X_BY3_DIVIDER(port, val)    \
10912                         (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
10913 /* RX lower control divider to select actual RX clock output from 8x */
10914 #define  BXT_MIPI1_RX_ESCLK_LOWER_SHIFT         16
10915 #define  BXT_MIPI2_RX_ESCLK_LOWER_SHIFT         0
10916 #define  BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)            \
10917                         _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
10918                                         BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
10919 #define  BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK           (3 << 16)
10920 #define  BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK           (3 << 0)
10921 #define  BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)      \
10922                         _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
10923                                         BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
10924 #define  BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val)     \
10925                 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
10926
10927 #define RX_DIVIDER_BIT_1_2                     0x3
10928 #define RX_DIVIDER_BIT_3_4                     0xC
10929
10930 /* BXT MIPI mode configure */
10931 #define  _BXT_MIPIA_TRANS_HACTIVE                       0x6B0F8
10932 #define  _BXT_MIPIC_TRANS_HACTIVE                       0x6B8F8
10933 #define  BXT_MIPI_TRANS_HACTIVE(tc)     _MMIO_MIPI(tc, \
10934                 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
10935
10936 #define  _BXT_MIPIA_TRANS_VACTIVE                       0x6B0FC
10937 #define  _BXT_MIPIC_TRANS_VACTIVE                       0x6B8FC
10938 #define  BXT_MIPI_TRANS_VACTIVE(tc)     _MMIO_MIPI(tc, \
10939                 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
10940
10941 #define  _BXT_MIPIA_TRANS_VTOTAL                        0x6B100
10942 #define  _BXT_MIPIC_TRANS_VTOTAL                        0x6B900
10943 #define  BXT_MIPI_TRANS_VTOTAL(tc)      _MMIO_MIPI(tc, \
10944                 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
10945
10946 #define BXT_DSI_PLL_CTL                 _MMIO(0x161000)
10947 #define  BXT_DSI_PLL_PVD_RATIO_SHIFT    16
10948 #define  BXT_DSI_PLL_PVD_RATIO_MASK     (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10949 #define  BXT_DSI_PLL_PVD_RATIO_1        (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10950 #define  BXT_DSIC_16X_BY1               (0 << 10)
10951 #define  BXT_DSIC_16X_BY2               (1 << 10)
10952 #define  BXT_DSIC_16X_BY3               (2 << 10)
10953 #define  BXT_DSIC_16X_BY4               (3 << 10)
10954 #define  BXT_DSIC_16X_MASK              (3 << 10)
10955 #define  BXT_DSIA_16X_BY1               (0 << 8)
10956 #define  BXT_DSIA_16X_BY2               (1 << 8)
10957 #define  BXT_DSIA_16X_BY3               (2 << 8)
10958 #define  BXT_DSIA_16X_BY4               (3 << 8)
10959 #define  BXT_DSIA_16X_MASK              (3 << 8)
10960 #define  BXT_DSI_FREQ_SEL_SHIFT         8
10961 #define  BXT_DSI_FREQ_SEL_MASK          (0xF << BXT_DSI_FREQ_SEL_SHIFT)
10962
10963 #define BXT_DSI_PLL_RATIO_MAX           0x7D
10964 #define BXT_DSI_PLL_RATIO_MIN           0x22
10965 #define GLK_DSI_PLL_RATIO_MAX           0x6F
10966 #define GLK_DSI_PLL_RATIO_MIN           0x22
10967 #define BXT_DSI_PLL_RATIO_MASK          0xFF
10968 #define BXT_REF_CLOCK_KHZ               19200
10969
10970 #define BXT_DSI_PLL_ENABLE              _MMIO(0x46080)
10971 #define  BXT_DSI_PLL_DO_ENABLE          (1 << 31)
10972 #define  BXT_DSI_PLL_LOCKED             (1 << 30)
10973
10974 #define _MIPIA_PORT_CTRL                        (VLV_DISPLAY_BASE + 0x61190)
10975 #define _MIPIC_PORT_CTRL                        (VLV_DISPLAY_BASE + 0x61700)
10976 #define MIPI_PORT_CTRL(port)    _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
10977
10978  /* BXT port control */
10979 #define _BXT_MIPIA_PORT_CTRL                            0x6B0C0
10980 #define _BXT_MIPIC_PORT_CTRL                            0x6B8C0
10981 #define BXT_MIPI_PORT_CTRL(tc)  _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
10982
10983 /* ICL DSI MODE control */
10984 #define _ICL_DSI_IO_MODECTL_0                           0x6B094
10985 #define _ICL_DSI_IO_MODECTL_1                           0x6B894
10986 #define ICL_DSI_IO_MODECTL(port)        _MMIO_PORT(port,        \
10987                                                     _ICL_DSI_IO_MODECTL_0, \
10988                                                     _ICL_DSI_IO_MODECTL_1)
10989 #define  COMBO_PHY_MODE_DSI                             (1 << 0)
10990
10991 /* Display Stream Splitter Control */
10992 #define DSS_CTL1                                _MMIO(0x67400)
10993 #define  SPLITTER_ENABLE                        (1 << 31)
10994 #define  JOINER_ENABLE                          (1 << 30)
10995 #define  DUAL_LINK_MODE_INTERLEAVE              (1 << 24)
10996 #define  DUAL_LINK_MODE_FRONTBACK               (0 << 24)
10997 #define  OVERLAP_PIXELS_MASK                    (0xf << 16)
10998 #define  OVERLAP_PIXELS(pixels)                 ((pixels) << 16)
10999 #define  LEFT_DL_BUF_TARGET_DEPTH_MASK          (0xfff << 0)
11000 #define  LEFT_DL_BUF_TARGET_DEPTH(pixels)       ((pixels) << 0)
11001 #define  MAX_DL_BUFFER_TARGET_DEPTH             0x5a0
11002
11003 #define DSS_CTL2                                _MMIO(0x67404)
11004 #define  LEFT_BRANCH_VDSC_ENABLE                (1 << 31)
11005 #define  RIGHT_BRANCH_VDSC_ENABLE               (1 << 15)
11006 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK         (0xfff << 0)
11007 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)      ((pixels) << 0)
11008
11009 #define _ICL_PIPE_DSS_CTL1_PB                   0x78200
11010 #define _ICL_PIPE_DSS_CTL1_PC                   0x78400
11011 #define ICL_PIPE_DSS_CTL1(pipe)                 _MMIO_PIPE((pipe) - PIPE_B, \
11012                                                            _ICL_PIPE_DSS_CTL1_PB, \
11013                                                            _ICL_PIPE_DSS_CTL1_PC)
11014 #define  BIG_JOINER_ENABLE                      (1 << 29)
11015 #define  MASTER_BIG_JOINER_ENABLE               (1 << 28)
11016 #define  VGA_CENTERING_ENABLE                   (1 << 27)
11017
11018 #define _ICL_PIPE_DSS_CTL2_PB                   0x78204
11019 #define _ICL_PIPE_DSS_CTL2_PC                   0x78404
11020 #define ICL_PIPE_DSS_CTL2(pipe)                 _MMIO_PIPE((pipe) - PIPE_B, \
11021                                                            _ICL_PIPE_DSS_CTL2_PB, \
11022                                                            _ICL_PIPE_DSS_CTL2_PC)
11023
11024 #define BXT_P_DSI_REGULATOR_CFG                 _MMIO(0x160020)
11025 #define  STAP_SELECT                                    (1 << 0)
11026
11027 #define BXT_P_DSI_REGULATOR_TX_CTRL             _MMIO(0x160054)
11028 #define  HS_IO_CTRL_SELECT                              (1 << 0)
11029
11030 #define  DPI_ENABLE                                     (1 << 31) /* A + C */
11031 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT              27
11032 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK               (0xf << 27)
11033 #define  DUAL_LINK_MODE_SHIFT                           26
11034 #define  DUAL_LINK_MODE_MASK                            (1 << 26)
11035 #define  DUAL_LINK_MODE_FRONT_BACK                      (0 << 26)
11036 #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE               (1 << 26)
11037 #define  DITHERING_ENABLE                               (1 << 25) /* A + C */
11038 #define  FLOPPED_HSTX                                   (1 << 23)
11039 #define  DE_INVERT                                      (1 << 19) /* XXX */
11040 #define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT                18
11041 #define  MIPIA_FLISDSI_DELAY_COUNT_MASK                 (0xf << 18)
11042 #define  AFE_LATCHOUT                                   (1 << 17)
11043 #define  LP_OUTPUT_HOLD                                 (1 << 16)
11044 #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT           15
11045 #define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK            (1 << 15)
11046 #define  MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT              11
11047 #define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK               (0xf << 11)
11048 #define  CSB_SHIFT                                      9
11049 #define  CSB_MASK                                       (3 << 9)
11050 #define  CSB_20MHZ                                      (0 << 9)
11051 #define  CSB_10MHZ                                      (1 << 9)
11052 #define  CSB_40MHZ                                      (2 << 9)
11053 #define  BANDGAP_MASK                                   (1 << 8)
11054 #define  BANDGAP_PNW_CIRCUIT                            (0 << 8)
11055 #define  BANDGAP_LNC_CIRCUIT                            (1 << 8)
11056 #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT            5
11057 #define  MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK             (7 << 5)
11058 #define  TEARING_EFFECT_DELAY                           (1 << 4) /* A + C */
11059 #define  TEARING_EFFECT_SHIFT                           2 /* A + C */
11060 #define  TEARING_EFFECT_MASK                            (3 << 2)
11061 #define  TEARING_EFFECT_OFF                             (0 << 2)
11062 #define  TEARING_EFFECT_DSI                             (1 << 2)
11063 #define  TEARING_EFFECT_GPIO                            (2 << 2)
11064 #define  LANE_CONFIGURATION_SHIFT                       0
11065 #define  LANE_CONFIGURATION_MASK                        (3 << 0)
11066 #define  LANE_CONFIGURATION_4LANE                       (0 << 0)
11067 #define  LANE_CONFIGURATION_DUAL_LINK_A                 (1 << 0)
11068 #define  LANE_CONFIGURATION_DUAL_LINK_B                 (2 << 0)
11069
11070 #define _MIPIA_TEARING_CTRL                     (VLV_DISPLAY_BASE + 0x61194)
11071 #define _MIPIC_TEARING_CTRL                     (VLV_DISPLAY_BASE + 0x61704)
11072 #define MIPI_TEARING_CTRL(port)                 _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
11073 #define  TEARING_EFFECT_DELAY_SHIFT                     0
11074 #define  TEARING_EFFECT_DELAY_MASK                      (0xffff << 0)
11075
11076 /* XXX: all bits reserved */
11077 #define _MIPIA_AUTOPWG                  (VLV_DISPLAY_BASE + 0x611a0)
11078
11079 /* MIPI DSI Controller and D-PHY registers */
11080
11081 #define _MIPIA_DEVICE_READY             (dev_priv->mipi_mmio_base + 0xb000)
11082 #define _MIPIC_DEVICE_READY             (dev_priv->mipi_mmio_base + 0xb800)
11083 #define MIPI_DEVICE_READY(port)         _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
11084 #define  BUS_POSSESSION                                 (1 << 3) /* set to give bus to receiver */
11085 #define  ULPS_STATE_MASK                                (3 << 1)
11086 #define  ULPS_STATE_ENTER                               (2 << 1)
11087 #define  ULPS_STATE_EXIT                                (1 << 1)
11088 #define  ULPS_STATE_NORMAL_OPERATION                    (0 << 1)
11089 #define  DEVICE_READY                                   (1 << 0)
11090
11091 #define _MIPIA_INTR_STAT                (dev_priv->mipi_mmio_base + 0xb004)
11092 #define _MIPIC_INTR_STAT                (dev_priv->mipi_mmio_base + 0xb804)
11093 #define MIPI_INTR_STAT(port)            _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
11094 #define _MIPIA_INTR_EN                  (dev_priv->mipi_mmio_base + 0xb008)
11095 #define _MIPIC_INTR_EN                  (dev_priv->mipi_mmio_base + 0xb808)
11096 #define MIPI_INTR_EN(port)              _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
11097 #define  TEARING_EFFECT                                 (1 << 31)
11098 #define  SPL_PKT_SENT_INTERRUPT                         (1 << 30)
11099 #define  GEN_READ_DATA_AVAIL                            (1 << 29)
11100 #define  LP_GENERIC_WR_FIFO_FULL                        (1 << 28)
11101 #define  HS_GENERIC_WR_FIFO_FULL                        (1 << 27)
11102 #define  RX_PROT_VIOLATION                              (1 << 26)
11103 #define  RX_INVALID_TX_LENGTH                           (1 << 25)
11104 #define  ACK_WITH_NO_ERROR                              (1 << 24)
11105 #define  TURN_AROUND_ACK_TIMEOUT                        (1 << 23)
11106 #define  LP_RX_TIMEOUT                                  (1 << 22)
11107 #define  HS_TX_TIMEOUT                                  (1 << 21)
11108 #define  DPI_FIFO_UNDERRUN                              (1 << 20)
11109 #define  LOW_CONTENTION                                 (1 << 19)
11110 #define  HIGH_CONTENTION                                (1 << 18)
11111 #define  TXDSI_VC_ID_INVALID                            (1 << 17)
11112 #define  TXDSI_DATA_TYPE_NOT_RECOGNISED                 (1 << 16)
11113 #define  TXCHECKSUM_ERROR                               (1 << 15)
11114 #define  TXECC_MULTIBIT_ERROR                           (1 << 14)
11115 #define  TXECC_SINGLE_BIT_ERROR                         (1 << 13)
11116 #define  TXFALSE_CONTROL_ERROR                          (1 << 12)
11117 #define  RXDSI_VC_ID_INVALID                            (1 << 11)
11118 #define  RXDSI_DATA_TYPE_NOT_REGOGNISED                 (1 << 10)
11119 #define  RXCHECKSUM_ERROR                               (1 << 9)
11120 #define  RXECC_MULTIBIT_ERROR                           (1 << 8)
11121 #define  RXECC_SINGLE_BIT_ERROR                         (1 << 7)
11122 #define  RXFALSE_CONTROL_ERROR                          (1 << 6)
11123 #define  RXHS_RECEIVE_TIMEOUT_ERROR                     (1 << 5)
11124 #define  RX_LP_TX_SYNC_ERROR                            (1 << 4)
11125 #define  RXEXCAPE_MODE_ENTRY_ERROR                      (1 << 3)
11126 #define  RXEOT_SYNC_ERROR                               (1 << 2)
11127 #define  RXSOT_SYNC_ERROR                               (1 << 1)
11128 #define  RXSOT_ERROR                                    (1 << 0)
11129
11130 #define _MIPIA_DSI_FUNC_PRG             (dev_priv->mipi_mmio_base + 0xb00c)
11131 #define _MIPIC_DSI_FUNC_PRG             (dev_priv->mipi_mmio_base + 0xb80c)
11132 #define MIPI_DSI_FUNC_PRG(port)         _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
11133 #define  CMD_MODE_DATA_WIDTH_MASK                       (7 << 13)
11134 #define  CMD_MODE_NOT_SUPPORTED                         (0 << 13)
11135 #define  CMD_MODE_DATA_WIDTH_16_BIT                     (1 << 13)
11136 #define  CMD_MODE_DATA_WIDTH_9_BIT                      (2 << 13)
11137 #define  CMD_MODE_DATA_WIDTH_8_BIT                      (3 << 13)
11138 #define  CMD_MODE_DATA_WIDTH_OPTION1                    (4 << 13)
11139 #define  CMD_MODE_DATA_WIDTH_OPTION2                    (5 << 13)
11140 #define  VID_MODE_FORMAT_MASK                           (0xf << 7)
11141 #define  VID_MODE_NOT_SUPPORTED                         (0 << 7)
11142 #define  VID_MODE_FORMAT_RGB565                         (1 << 7)
11143 #define  VID_MODE_FORMAT_RGB666_PACKED                  (2 << 7)
11144 #define  VID_MODE_FORMAT_RGB666                         (3 << 7)
11145 #define  VID_MODE_FORMAT_RGB888                         (4 << 7)
11146 #define  CMD_MODE_CHANNEL_NUMBER_SHIFT                  5
11147 #define  CMD_MODE_CHANNEL_NUMBER_MASK                   (3 << 5)
11148 #define  VID_MODE_CHANNEL_NUMBER_SHIFT                  3
11149 #define  VID_MODE_CHANNEL_NUMBER_MASK                   (3 << 3)
11150 #define  DATA_LANES_PRG_REG_SHIFT                       0
11151 #define  DATA_LANES_PRG_REG_MASK                        (7 << 0)
11152
11153 #define _MIPIA_HS_TX_TIMEOUT            (dev_priv->mipi_mmio_base + 0xb010)
11154 #define _MIPIC_HS_TX_TIMEOUT            (dev_priv->mipi_mmio_base + 0xb810)
11155 #define MIPI_HS_TX_TIMEOUT(port)        _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
11156 #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK             0xffffff
11157
11158 #define _MIPIA_LP_RX_TIMEOUT            (dev_priv->mipi_mmio_base + 0xb014)
11159 #define _MIPIC_LP_RX_TIMEOUT            (dev_priv->mipi_mmio_base + 0xb814)
11160 #define MIPI_LP_RX_TIMEOUT(port)        _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
11161 #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK              0xffffff
11162
11163 #define _MIPIA_TURN_AROUND_TIMEOUT      (dev_priv->mipi_mmio_base + 0xb018)
11164 #define _MIPIC_TURN_AROUND_TIMEOUT      (dev_priv->mipi_mmio_base + 0xb818)
11165 #define MIPI_TURN_AROUND_TIMEOUT(port)  _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
11166 #define  TURN_AROUND_TIMEOUT_MASK                       0x3f
11167
11168 #define _MIPIA_DEVICE_RESET_TIMER       (dev_priv->mipi_mmio_base + 0xb01c)
11169 #define _MIPIC_DEVICE_RESET_TIMER       (dev_priv->mipi_mmio_base + 0xb81c)
11170 #define MIPI_DEVICE_RESET_TIMER(port)   _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
11171 #define  DEVICE_RESET_TIMER_MASK                        0xffff
11172
11173 #define _MIPIA_DPI_RESOLUTION           (dev_priv->mipi_mmio_base + 0xb020)
11174 #define _MIPIC_DPI_RESOLUTION           (dev_priv->mipi_mmio_base + 0xb820)
11175 #define MIPI_DPI_RESOLUTION(port)       _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
11176 #define  VERTICAL_ADDRESS_SHIFT                         16
11177 #define  VERTICAL_ADDRESS_MASK                          (0xffff << 16)
11178 #define  HORIZONTAL_ADDRESS_SHIFT                       0
11179 #define  HORIZONTAL_ADDRESS_MASK                        0xffff
11180
11181 #define _MIPIA_DBI_FIFO_THROTTLE        (dev_priv->mipi_mmio_base + 0xb024)
11182 #define _MIPIC_DBI_FIFO_THROTTLE        (dev_priv->mipi_mmio_base + 0xb824)
11183 #define MIPI_DBI_FIFO_THROTTLE(port)    _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
11184 #define  DBI_FIFO_EMPTY_HALF                            (0 << 0)
11185 #define  DBI_FIFO_EMPTY_QUARTER                         (1 << 0)
11186 #define  DBI_FIFO_EMPTY_7_LOCATIONS                     (2 << 0)
11187
11188 /* regs below are bits 15:0 */
11189 #define _MIPIA_HSYNC_PADDING_COUNT      (dev_priv->mipi_mmio_base + 0xb028)
11190 #define _MIPIC_HSYNC_PADDING_COUNT      (dev_priv->mipi_mmio_base + 0xb828)
11191 #define MIPI_HSYNC_PADDING_COUNT(port)  _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
11192
11193 #define _MIPIA_HBP_COUNT                (dev_priv->mipi_mmio_base + 0xb02c)
11194 #define _MIPIC_HBP_COUNT                (dev_priv->mipi_mmio_base + 0xb82c)
11195 #define MIPI_HBP_COUNT(port)            _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
11196
11197 #define _MIPIA_HFP_COUNT                (dev_priv->mipi_mmio_base + 0xb030)
11198 #define _MIPIC_HFP_COUNT                (dev_priv->mipi_mmio_base + 0xb830)
11199 #define MIPI_HFP_COUNT(port)            _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
11200
11201 #define _MIPIA_HACTIVE_AREA_COUNT       (dev_priv->mipi_mmio_base + 0xb034)
11202 #define _MIPIC_HACTIVE_AREA_COUNT       (dev_priv->mipi_mmio_base + 0xb834)
11203 #define MIPI_HACTIVE_AREA_COUNT(port)   _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
11204
11205 #define _MIPIA_VSYNC_PADDING_COUNT      (dev_priv->mipi_mmio_base + 0xb038)
11206 #define _MIPIC_VSYNC_PADDING_COUNT      (dev_priv->mipi_mmio_base + 0xb838)
11207 #define MIPI_VSYNC_PADDING_COUNT(port)  _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
11208
11209 #define _MIPIA_VBP_COUNT                (dev_priv->mipi_mmio_base + 0xb03c)
11210 #define _MIPIC_VBP_COUNT                (dev_priv->mipi_mmio_base + 0xb83c)
11211 #define MIPI_VBP_COUNT(port)            _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
11212
11213 #define _MIPIA_VFP_COUNT                (dev_priv->mipi_mmio_base + 0xb040)
11214 #define _MIPIC_VFP_COUNT                (dev_priv->mipi_mmio_base + 0xb840)
11215 #define MIPI_VFP_COUNT(port)            _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
11216
11217 #define _MIPIA_HIGH_LOW_SWITCH_COUNT    (dev_priv->mipi_mmio_base + 0xb044)
11218 #define _MIPIC_HIGH_LOW_SWITCH_COUNT    (dev_priv->mipi_mmio_base + 0xb844)
11219 #define MIPI_HIGH_LOW_SWITCH_COUNT(port)        _MMIO_MIPI(port,        _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
11220
11221 /* regs above are bits 15:0 */
11222
11223 #define _MIPIA_DPI_CONTROL              (dev_priv->mipi_mmio_base + 0xb048)
11224 #define _MIPIC_DPI_CONTROL              (dev_priv->mipi_mmio_base + 0xb848)
11225 #define MIPI_DPI_CONTROL(port)          _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
11226 #define  DPI_LP_MODE                                    (1 << 6)
11227 #define  BACKLIGHT_OFF                                  (1 << 5)
11228 #define  BACKLIGHT_ON                                   (1 << 4)
11229 #define  COLOR_MODE_OFF                                 (1 << 3)
11230 #define  COLOR_MODE_ON                                  (1 << 2)
11231 #define  TURN_ON                                        (1 << 1)
11232 #define  SHUTDOWN                                       (1 << 0)
11233
11234 #define _MIPIA_DPI_DATA                 (dev_priv->mipi_mmio_base + 0xb04c)
11235 #define _MIPIC_DPI_DATA                 (dev_priv->mipi_mmio_base + 0xb84c)
11236 #define MIPI_DPI_DATA(port)             _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
11237 #define  COMMAND_BYTE_SHIFT                             0
11238 #define  COMMAND_BYTE_MASK                              (0x3f << 0)
11239
11240 #define _MIPIA_INIT_COUNT               (dev_priv->mipi_mmio_base + 0xb050)
11241 #define _MIPIC_INIT_COUNT               (dev_priv->mipi_mmio_base + 0xb850)
11242 #define MIPI_INIT_COUNT(port)           _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
11243 #define  MASTER_INIT_TIMER_SHIFT                        0
11244 #define  MASTER_INIT_TIMER_MASK                         (0xffff << 0)
11245
11246 #define _MIPIA_MAX_RETURN_PKT_SIZE      (dev_priv->mipi_mmio_base + 0xb054)
11247 #define _MIPIC_MAX_RETURN_PKT_SIZE      (dev_priv->mipi_mmio_base + 0xb854)
11248 #define MIPI_MAX_RETURN_PKT_SIZE(port)  _MMIO_MIPI(port, \
11249                         _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
11250 #define  MAX_RETURN_PKT_SIZE_SHIFT                      0
11251 #define  MAX_RETURN_PKT_SIZE_MASK                       (0x3ff << 0)
11252
11253 #define _MIPIA_VIDEO_MODE_FORMAT        (dev_priv->mipi_mmio_base + 0xb058)
11254 #define _MIPIC_VIDEO_MODE_FORMAT        (dev_priv->mipi_mmio_base + 0xb858)
11255 #define MIPI_VIDEO_MODE_FORMAT(port)    _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
11256 #define  RANDOM_DPI_DISPLAY_RESOLUTION                  (1 << 4)
11257 #define  DISABLE_VIDEO_BTA                              (1 << 3)
11258 #define  IP_TG_CONFIG                                   (1 << 2)
11259 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE           (1 << 0)
11260 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS          (2 << 0)
11261 #define  VIDEO_MODE_BURST                               (3 << 0)
11262
11263 #define _MIPIA_EOT_DISABLE              (dev_priv->mipi_mmio_base + 0xb05c)
11264 #define _MIPIC_EOT_DISABLE              (dev_priv->mipi_mmio_base + 0xb85c)
11265 #define MIPI_EOT_DISABLE(port)          _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
11266 #define  BXT_DEFEATURE_DPI_FIFO_CTR                     (1 << 9)
11267 #define  BXT_DPHY_DEFEATURE_EN                          (1 << 8)
11268 #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE           (1 << 7)
11269 #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE           (1 << 6)
11270 #define  LOW_CONTENTION_RECOVERY_DISABLE                (1 << 5)
11271 #define  HIGH_CONTENTION_RECOVERY_DISABLE               (1 << 4)
11272 #define  TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
11273 #define  TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE          (1 << 2)
11274 #define  CLOCKSTOP                                      (1 << 1)
11275 #define  EOT_DISABLE                                    (1 << 0)
11276
11277 #define _MIPIA_LP_BYTECLK               (dev_priv->mipi_mmio_base + 0xb060)
11278 #define _MIPIC_LP_BYTECLK               (dev_priv->mipi_mmio_base + 0xb860)
11279 #define MIPI_LP_BYTECLK(port)           _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
11280 #define  LP_BYTECLK_SHIFT                               0
11281 #define  LP_BYTECLK_MASK                                (0xffff << 0)
11282
11283 #define _MIPIA_TLPX_TIME_COUNT          (dev_priv->mipi_mmio_base + 0xb0a4)
11284 #define _MIPIC_TLPX_TIME_COUNT          (dev_priv->mipi_mmio_base + 0xb8a4)
11285 #define MIPI_TLPX_TIME_COUNT(port)       _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
11286
11287 #define _MIPIA_CLK_LANE_TIMING          (dev_priv->mipi_mmio_base + 0xb098)
11288 #define _MIPIC_CLK_LANE_TIMING          (dev_priv->mipi_mmio_base + 0xb898)
11289 #define MIPI_CLK_LANE_TIMING(port)       _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
11290
11291 /* bits 31:0 */
11292 #define _MIPIA_LP_GEN_DATA              (dev_priv->mipi_mmio_base + 0xb064)
11293 #define _MIPIC_LP_GEN_DATA              (dev_priv->mipi_mmio_base + 0xb864)
11294 #define MIPI_LP_GEN_DATA(port)          _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
11295
11296 /* bits 31:0 */
11297 #define _MIPIA_HS_GEN_DATA              (dev_priv->mipi_mmio_base + 0xb068)
11298 #define _MIPIC_HS_GEN_DATA              (dev_priv->mipi_mmio_base + 0xb868)
11299 #define MIPI_HS_GEN_DATA(port)          _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
11300
11301 #define _MIPIA_LP_GEN_CTRL              (dev_priv->mipi_mmio_base + 0xb06c)
11302 #define _MIPIC_LP_GEN_CTRL              (dev_priv->mipi_mmio_base + 0xb86c)
11303 #define MIPI_LP_GEN_CTRL(port)          _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
11304 #define _MIPIA_HS_GEN_CTRL              (dev_priv->mipi_mmio_base + 0xb070)
11305 #define _MIPIC_HS_GEN_CTRL              (dev_priv->mipi_mmio_base + 0xb870)
11306 #define MIPI_HS_GEN_CTRL(port)          _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
11307 #define  LONG_PACKET_WORD_COUNT_SHIFT                   8
11308 #define  LONG_PACKET_WORD_COUNT_MASK                    (0xffff << 8)
11309 #define  SHORT_PACKET_PARAM_SHIFT                       8
11310 #define  SHORT_PACKET_PARAM_MASK                        (0xffff << 8)
11311 #define  VIRTUAL_CHANNEL_SHIFT                          6
11312 #define  VIRTUAL_CHANNEL_MASK                           (3 << 6)
11313 #define  DATA_TYPE_SHIFT                                0
11314 #define  DATA_TYPE_MASK                                 (0x3f << 0)
11315 /* data type values, see include/video/mipi_display.h */
11316
11317 #define _MIPIA_GEN_FIFO_STAT            (dev_priv->mipi_mmio_base + 0xb074)
11318 #define _MIPIC_GEN_FIFO_STAT            (dev_priv->mipi_mmio_base + 0xb874)
11319 #define MIPI_GEN_FIFO_STAT(port)        _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
11320 #define  DPI_FIFO_EMPTY                                 (1 << 28)
11321 #define  DBI_FIFO_EMPTY                                 (1 << 27)
11322 #define  LP_CTRL_FIFO_EMPTY                             (1 << 26)
11323 #define  LP_CTRL_FIFO_HALF_EMPTY                        (1 << 25)
11324 #define  LP_CTRL_FIFO_FULL                              (1 << 24)
11325 #define  HS_CTRL_FIFO_EMPTY                             (1 << 18)
11326 #define  HS_CTRL_FIFO_HALF_EMPTY                        (1 << 17)
11327 #define  HS_CTRL_FIFO_FULL                              (1 << 16)
11328 #define  LP_DATA_FIFO_EMPTY                             (1 << 10)
11329 #define  LP_DATA_FIFO_HALF_EMPTY                        (1 << 9)
11330 #define  LP_DATA_FIFO_FULL                              (1 << 8)
11331 #define  HS_DATA_FIFO_EMPTY                             (1 << 2)
11332 #define  HS_DATA_FIFO_HALF_EMPTY                        (1 << 1)
11333 #define  HS_DATA_FIFO_FULL                              (1 << 0)
11334
11335 #define _MIPIA_HS_LS_DBI_ENABLE         (dev_priv->mipi_mmio_base + 0xb078)
11336 #define _MIPIC_HS_LS_DBI_ENABLE         (dev_priv->mipi_mmio_base + 0xb878)
11337 #define MIPI_HS_LP_DBI_ENABLE(port)     _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
11338 #define  DBI_HS_LP_MODE_MASK                            (1 << 0)
11339 #define  DBI_LP_MODE                                    (1 << 0)
11340 #define  DBI_HS_MODE                                    (0 << 0)
11341
11342 #define _MIPIA_DPHY_PARAM               (dev_priv->mipi_mmio_base + 0xb080)
11343 #define _MIPIC_DPHY_PARAM               (dev_priv->mipi_mmio_base + 0xb880)
11344 #define MIPI_DPHY_PARAM(port)           _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
11345 #define  EXIT_ZERO_COUNT_SHIFT                          24
11346 #define  EXIT_ZERO_COUNT_MASK                           (0x3f << 24)
11347 #define  TRAIL_COUNT_SHIFT                              16
11348 #define  TRAIL_COUNT_MASK                               (0x1f << 16)
11349 #define  CLK_ZERO_COUNT_SHIFT                           8
11350 #define  CLK_ZERO_COUNT_MASK                            (0xff << 8)
11351 #define  PREPARE_COUNT_SHIFT                            0
11352 #define  PREPARE_COUNT_MASK                             (0x3f << 0)
11353
11354 #define _ICL_DSI_T_INIT_MASTER_0        0x6b088
11355 #define _ICL_DSI_T_INIT_MASTER_1        0x6b888
11356 #define ICL_DSI_T_INIT_MASTER(port)     _MMIO_PORT(port,        \
11357                                                    _ICL_DSI_T_INIT_MASTER_0,\
11358                                                    _ICL_DSI_T_INIT_MASTER_1)
11359
11360 #define _DPHY_CLK_TIMING_PARAM_0        0x162180
11361 #define _DPHY_CLK_TIMING_PARAM_1        0x6c180
11362 #define DPHY_CLK_TIMING_PARAM(port)     _MMIO_PORT(port,        \
11363                                                    _DPHY_CLK_TIMING_PARAM_0,\
11364                                                    _DPHY_CLK_TIMING_PARAM_1)
11365 #define _DSI_CLK_TIMING_PARAM_0         0x6b080
11366 #define _DSI_CLK_TIMING_PARAM_1         0x6b880
11367 #define DSI_CLK_TIMING_PARAM(port)      _MMIO_PORT(port,        \
11368                                                    _DSI_CLK_TIMING_PARAM_0,\
11369                                                    _DSI_CLK_TIMING_PARAM_1)
11370 #define  CLK_PREPARE_OVERRIDE           (1 << 31)
11371 #define  CLK_PREPARE(x)         ((x) << 28)
11372 #define  CLK_PREPARE_MASK               (0x7 << 28)
11373 #define  CLK_PREPARE_SHIFT              28
11374 #define  CLK_ZERO_OVERRIDE              (1 << 27)
11375 #define  CLK_ZERO(x)                    ((x) << 20)
11376 #define  CLK_ZERO_MASK                  (0xf << 20)
11377 #define  CLK_ZERO_SHIFT         20
11378 #define  CLK_PRE_OVERRIDE               (1 << 19)
11379 #define  CLK_PRE(x)                     ((x) << 16)
11380 #define  CLK_PRE_MASK                   (0x3 << 16)
11381 #define  CLK_PRE_SHIFT                  16
11382 #define  CLK_POST_OVERRIDE              (1 << 15)
11383 #define  CLK_POST(x)                    ((x) << 8)
11384 #define  CLK_POST_MASK                  (0x7 << 8)
11385 #define  CLK_POST_SHIFT         8
11386 #define  CLK_TRAIL_OVERRIDE             (1 << 7)
11387 #define  CLK_TRAIL(x)                   ((x) << 0)
11388 #define  CLK_TRAIL_MASK         (0xf << 0)
11389 #define  CLK_TRAIL_SHIFT                0
11390
11391 #define _DPHY_DATA_TIMING_PARAM_0       0x162184
11392 #define _DPHY_DATA_TIMING_PARAM_1       0x6c184
11393 #define DPHY_DATA_TIMING_PARAM(port)    _MMIO_PORT(port,        \
11394                                                    _DPHY_DATA_TIMING_PARAM_0,\
11395                                                    _DPHY_DATA_TIMING_PARAM_1)
11396 #define _DSI_DATA_TIMING_PARAM_0        0x6B084
11397 #define _DSI_DATA_TIMING_PARAM_1        0x6B884
11398 #define DSI_DATA_TIMING_PARAM(port)     _MMIO_PORT(port,        \
11399                                                    _DSI_DATA_TIMING_PARAM_0,\
11400                                                    _DSI_DATA_TIMING_PARAM_1)
11401 #define  HS_PREPARE_OVERRIDE            (1 << 31)
11402 #define  HS_PREPARE(x)                  ((x) << 24)
11403 #define  HS_PREPARE_MASK                (0x7 << 24)
11404 #define  HS_PREPARE_SHIFT               24
11405 #define  HS_ZERO_OVERRIDE               (1 << 23)
11406 #define  HS_ZERO(x)                     ((x) << 16)
11407 #define  HS_ZERO_MASK                   (0xf << 16)
11408 #define  HS_ZERO_SHIFT                  16
11409 #define  HS_TRAIL_OVERRIDE              (1 << 15)
11410 #define  HS_TRAIL(x)                    ((x) << 8)
11411 #define  HS_TRAIL_MASK                  (0x7 << 8)
11412 #define  HS_TRAIL_SHIFT         8
11413 #define  HS_EXIT_OVERRIDE               (1 << 7)
11414 #define  HS_EXIT(x)                     ((x) << 0)
11415 #define  HS_EXIT_MASK                   (0x7 << 0)
11416 #define  HS_EXIT_SHIFT                  0
11417
11418 #define _DPHY_TA_TIMING_PARAM_0         0x162188
11419 #define _DPHY_TA_TIMING_PARAM_1         0x6c188
11420 #define DPHY_TA_TIMING_PARAM(port)      _MMIO_PORT(port,        \
11421                                                    _DPHY_TA_TIMING_PARAM_0,\
11422                                                    _DPHY_TA_TIMING_PARAM_1)
11423 #define _DSI_TA_TIMING_PARAM_0          0x6b098
11424 #define _DSI_TA_TIMING_PARAM_1          0x6b898
11425 #define DSI_TA_TIMING_PARAM(port)       _MMIO_PORT(port,        \
11426                                                    _DSI_TA_TIMING_PARAM_0,\
11427                                                    _DSI_TA_TIMING_PARAM_1)
11428 #define  TA_SURE_OVERRIDE               (1 << 31)
11429 #define  TA_SURE(x)                     ((x) << 16)
11430 #define  TA_SURE_MASK                   (0x1f << 16)
11431 #define  TA_SURE_SHIFT                  16
11432 #define  TA_GO_OVERRIDE         (1 << 15)
11433 #define  TA_GO(x)                       ((x) << 8)
11434 #define  TA_GO_MASK                     (0xf << 8)
11435 #define  TA_GO_SHIFT                    8
11436 #define  TA_GET_OVERRIDE                (1 << 7)
11437 #define  TA_GET(x)                      ((x) << 0)
11438 #define  TA_GET_MASK                    (0xf << 0)
11439 #define  TA_GET_SHIFT                   0
11440
11441 /* DSI transcoder configuration */
11442 #define _DSI_TRANS_FUNC_CONF_0          0x6b030
11443 #define _DSI_TRANS_FUNC_CONF_1          0x6b830
11444 #define DSI_TRANS_FUNC_CONF(tc)         _MMIO_DSI(tc,   \
11445                                                   _DSI_TRANS_FUNC_CONF_0,\
11446                                                   _DSI_TRANS_FUNC_CONF_1)
11447 #define  OP_MODE_MASK                   (0x3 << 28)
11448 #define  OP_MODE_SHIFT                  28
11449 #define  CMD_MODE_NO_GATE               (0x0 << 28)
11450 #define  CMD_MODE_TE_GATE               (0x1 << 28)
11451 #define  VIDEO_MODE_SYNC_EVENT          (0x2 << 28)
11452 #define  VIDEO_MODE_SYNC_PULSE          (0x3 << 28)
11453 #define  TE_SOURCE_GPIO                 (1 << 27)
11454 #define  LINK_READY                     (1 << 20)
11455 #define  PIX_FMT_MASK                   (0x3 << 16)
11456 #define  PIX_FMT_SHIFT                  16
11457 #define  PIX_FMT_RGB565                 (0x0 << 16)
11458 #define  PIX_FMT_RGB666_PACKED          (0x1 << 16)
11459 #define  PIX_FMT_RGB666_LOOSE           (0x2 << 16)
11460 #define  PIX_FMT_RGB888                 (0x3 << 16)
11461 #define  PIX_FMT_RGB101010              (0x4 << 16)
11462 #define  PIX_FMT_RGB121212              (0x5 << 16)
11463 #define  PIX_FMT_COMPRESSED             (0x6 << 16)
11464 #define  BGR_TRANSMISSION               (1 << 15)
11465 #define  PIX_VIRT_CHAN(x)               ((x) << 12)
11466 #define  PIX_VIRT_CHAN_MASK             (0x3 << 12)
11467 #define  PIX_VIRT_CHAN_SHIFT            12
11468 #define  PIX_BUF_THRESHOLD_MASK         (0x3 << 10)
11469 #define  PIX_BUF_THRESHOLD_SHIFT        10
11470 #define  PIX_BUF_THRESHOLD_1_4          (0x0 << 10)
11471 #define  PIX_BUF_THRESHOLD_1_2          (0x1 << 10)
11472 #define  PIX_BUF_THRESHOLD_3_4          (0x2 << 10)
11473 #define  PIX_BUF_THRESHOLD_FULL         (0x3 << 10)
11474 #define  CONTINUOUS_CLK_MASK            (0x3 << 8)
11475 #define  CONTINUOUS_CLK_SHIFT           8
11476 #define  CLK_ENTER_LP_AFTER_DATA        (0x0 << 8)
11477 #define  CLK_HS_OR_LP                   (0x2 << 8)
11478 #define  CLK_HS_CONTINUOUS              (0x3 << 8)
11479 #define  LINK_CALIBRATION_MASK          (0x3 << 4)
11480 #define  LINK_CALIBRATION_SHIFT         4
11481 #define  CALIBRATION_DISABLED           (0x0 << 4)
11482 #define  CALIBRATION_ENABLED_INITIAL_ONLY       (0x2 << 4)
11483 #define  CALIBRATION_ENABLED_INITIAL_PERIODIC   (0x3 << 4)
11484 #define  BLANKING_PACKET_ENABLE         (1 << 2)
11485 #define  S3D_ORIENTATION_LANDSCAPE      (1 << 1)
11486 #define  EOTP_DISABLED                  (1 << 0)
11487
11488 #define _DSI_CMD_RXCTL_0                0x6b0d4
11489 #define _DSI_CMD_RXCTL_1                0x6b8d4
11490 #define DSI_CMD_RXCTL(tc)               _MMIO_DSI(tc,   \
11491                                                   _DSI_CMD_RXCTL_0,\
11492                                                   _DSI_CMD_RXCTL_1)
11493 #define  READ_UNLOADS_DW                (1 << 16)
11494 #define  RECEIVED_UNASSIGNED_TRIGGER    (1 << 15)
11495 #define  RECEIVED_ACKNOWLEDGE_TRIGGER   (1 << 14)
11496 #define  RECEIVED_TEAR_EFFECT_TRIGGER   (1 << 13)
11497 #define  RECEIVED_RESET_TRIGGER         (1 << 12)
11498 #define  RECEIVED_PAYLOAD_WAS_LOST      (1 << 11)
11499 #define  RECEIVED_CRC_WAS_LOST          (1 << 10)
11500 #define  NUMBER_RX_PLOAD_DW_MASK        (0xff << 0)
11501 #define  NUMBER_RX_PLOAD_DW_SHIFT       0
11502
11503 #define _DSI_CMD_TXCTL_0                0x6b0d0
11504 #define _DSI_CMD_TXCTL_1                0x6b8d0
11505 #define DSI_CMD_TXCTL(tc)               _MMIO_DSI(tc,   \
11506                                                   _DSI_CMD_TXCTL_0,\
11507                                                   _DSI_CMD_TXCTL_1)
11508 #define  KEEP_LINK_IN_HS                (1 << 24)
11509 #define  FREE_HEADER_CREDIT_MASK        (0x1f << 8)
11510 #define  FREE_HEADER_CREDIT_SHIFT       0x8
11511 #define  FREE_PLOAD_CREDIT_MASK         (0xff << 0)
11512 #define  FREE_PLOAD_CREDIT_SHIFT        0
11513 #define  MAX_HEADER_CREDIT              0x10
11514 #define  MAX_PLOAD_CREDIT               0x40
11515
11516 #define _DSI_CMD_TXHDR_0                0x6b100
11517 #define _DSI_CMD_TXHDR_1                0x6b900
11518 #define DSI_CMD_TXHDR(tc)               _MMIO_DSI(tc,   \
11519                                                   _DSI_CMD_TXHDR_0,\
11520                                                   _DSI_CMD_TXHDR_1)
11521 #define  PAYLOAD_PRESENT                (1 << 31)
11522 #define  LP_DATA_TRANSFER               (1 << 30)
11523 #define  VBLANK_FENCE                   (1 << 29)
11524 #define  PARAM_WC_MASK                  (0xffff << 8)
11525 #define  PARAM_WC_LOWER_SHIFT           8
11526 #define  PARAM_WC_UPPER_SHIFT           16
11527 #define  VC_MASK                        (0x3 << 6)
11528 #define  VC_SHIFT                       6
11529 #define  DT_MASK                        (0x3f << 0)
11530 #define  DT_SHIFT                       0
11531
11532 #define _DSI_CMD_TXPYLD_0               0x6b104
11533 #define _DSI_CMD_TXPYLD_1               0x6b904
11534 #define DSI_CMD_TXPYLD(tc)              _MMIO_DSI(tc,   \
11535                                                   _DSI_CMD_TXPYLD_0,\
11536                                                   _DSI_CMD_TXPYLD_1)
11537
11538 #define _DSI_LP_MSG_0                   0x6b0d8
11539 #define _DSI_LP_MSG_1                   0x6b8d8
11540 #define DSI_LP_MSG(tc)                  _MMIO_DSI(tc,   \
11541                                                   _DSI_LP_MSG_0,\
11542                                                   _DSI_LP_MSG_1)
11543 #define  LPTX_IN_PROGRESS               (1 << 17)
11544 #define  LINK_IN_ULPS                   (1 << 16)
11545 #define  LINK_ULPS_TYPE_LP11            (1 << 8)
11546 #define  LINK_ENTER_ULPS                (1 << 0)
11547
11548 /* DSI timeout registers */
11549 #define _DSI_HSTX_TO_0                  0x6b044
11550 #define _DSI_HSTX_TO_1                  0x6b844
11551 #define DSI_HSTX_TO(tc)                 _MMIO_DSI(tc,   \
11552                                                   _DSI_HSTX_TO_0,\
11553                                                   _DSI_HSTX_TO_1)
11554 #define  HSTX_TIMEOUT_VALUE_MASK        (0xffff << 16)
11555 #define  HSTX_TIMEOUT_VALUE_SHIFT       16
11556 #define  HSTX_TIMEOUT_VALUE(x)          ((x) << 16)
11557 #define  HSTX_TIMED_OUT                 (1 << 0)
11558
11559 #define _DSI_LPRX_HOST_TO_0             0x6b048
11560 #define _DSI_LPRX_HOST_TO_1             0x6b848
11561 #define DSI_LPRX_HOST_TO(tc)            _MMIO_DSI(tc,   \
11562                                                   _DSI_LPRX_HOST_TO_0,\
11563                                                   _DSI_LPRX_HOST_TO_1)
11564 #define  LPRX_TIMED_OUT                 (1 << 16)
11565 #define  LPRX_TIMEOUT_VALUE_MASK        (0xffff << 0)
11566 #define  LPRX_TIMEOUT_VALUE_SHIFT       0
11567 #define  LPRX_TIMEOUT_VALUE(x)          ((x) << 0)
11568
11569 #define _DSI_PWAIT_TO_0                 0x6b040
11570 #define _DSI_PWAIT_TO_1                 0x6b840
11571 #define DSI_PWAIT_TO(tc)                _MMIO_DSI(tc,   \
11572                                                   _DSI_PWAIT_TO_0,\
11573                                                   _DSI_PWAIT_TO_1)
11574 #define  PRESET_TIMEOUT_VALUE_MASK      (0xffff << 16)
11575 #define  PRESET_TIMEOUT_VALUE_SHIFT     16
11576 #define  PRESET_TIMEOUT_VALUE(x)        ((x) << 16)
11577 #define  PRESPONSE_TIMEOUT_VALUE_MASK   (0xffff << 0)
11578 #define  PRESPONSE_TIMEOUT_VALUE_SHIFT  0
11579 #define  PRESPONSE_TIMEOUT_VALUE(x)     ((x) << 0)
11580
11581 #define _DSI_TA_TO_0                    0x6b04c
11582 #define _DSI_TA_TO_1                    0x6b84c
11583 #define DSI_TA_TO(tc)                   _MMIO_DSI(tc,   \
11584                                                   _DSI_TA_TO_0,\
11585                                                   _DSI_TA_TO_1)
11586 #define  TA_TIMED_OUT                   (1 << 16)
11587 #define  TA_TIMEOUT_VALUE_MASK          (0xffff << 0)
11588 #define  TA_TIMEOUT_VALUE_SHIFT         0
11589 #define  TA_TIMEOUT_VALUE(x)            ((x) << 0)
11590
11591 /* bits 31:0 */
11592 #define _MIPIA_DBI_BW_CTRL              (dev_priv->mipi_mmio_base + 0xb084)
11593 #define _MIPIC_DBI_BW_CTRL              (dev_priv->mipi_mmio_base + 0xb884)
11594 #define MIPI_DBI_BW_CTRL(port)          _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
11595
11596 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT         (dev_priv->mipi_mmio_base + 0xb088)
11597 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT         (dev_priv->mipi_mmio_base + 0xb888)
11598 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)     _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
11599 #define  LP_HS_SSW_CNT_SHIFT                            16
11600 #define  LP_HS_SSW_CNT_MASK                             (0xffff << 16)
11601 #define  HS_LP_PWR_SW_CNT_SHIFT                         0
11602 #define  HS_LP_PWR_SW_CNT_MASK                          (0xffff << 0)
11603
11604 #define _MIPIA_STOP_STATE_STALL         (dev_priv->mipi_mmio_base + 0xb08c)
11605 #define _MIPIC_STOP_STATE_STALL         (dev_priv->mipi_mmio_base + 0xb88c)
11606 #define MIPI_STOP_STATE_STALL(port)     _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
11607 #define  STOP_STATE_STALL_COUNTER_SHIFT                 0
11608 #define  STOP_STATE_STALL_COUNTER_MASK                  (0xff << 0)
11609
11610 #define _MIPIA_INTR_STAT_REG_1          (dev_priv->mipi_mmio_base + 0xb090)
11611 #define _MIPIC_INTR_STAT_REG_1          (dev_priv->mipi_mmio_base + 0xb890)
11612 #define MIPI_INTR_STAT_REG_1(port)      _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
11613 #define _MIPIA_INTR_EN_REG_1            (dev_priv->mipi_mmio_base + 0xb094)
11614 #define _MIPIC_INTR_EN_REG_1            (dev_priv->mipi_mmio_base + 0xb894)
11615 #define MIPI_INTR_EN_REG_1(port)        _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
11616 #define  RX_CONTENTION_DETECTED                         (1 << 0)
11617
11618 /* XXX: only pipe A ?!? */
11619 #define MIPIA_DBI_TYPEC_CTRL            (dev_priv->mipi_mmio_base + 0xb100)
11620 #define  DBI_TYPEC_ENABLE                               (1 << 31)
11621 #define  DBI_TYPEC_WIP                                  (1 << 30)
11622 #define  DBI_TYPEC_OPTION_SHIFT                         28
11623 #define  DBI_TYPEC_OPTION_MASK                          (3 << 28)
11624 #define  DBI_TYPEC_FREQ_SHIFT                           24
11625 #define  DBI_TYPEC_FREQ_MASK                            (0xf << 24)
11626 #define  DBI_TYPEC_OVERRIDE                             (1 << 8)
11627 #define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT               0
11628 #define  DBI_TYPEC_OVERRIDE_COUNTER_MASK                (0xff << 0)
11629
11630
11631 /* MIPI adapter registers */
11632
11633 #define _MIPIA_CTRL                     (dev_priv->mipi_mmio_base + 0xb104)
11634 #define _MIPIC_CTRL                     (dev_priv->mipi_mmio_base + 0xb904)
11635 #define MIPI_CTRL(port)                 _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
11636 #define  ESCAPE_CLOCK_DIVIDER_SHIFT                     5 /* A only */
11637 #define  ESCAPE_CLOCK_DIVIDER_MASK                      (3 << 5)
11638 #define  ESCAPE_CLOCK_DIVIDER_1                         (0 << 5)
11639 #define  ESCAPE_CLOCK_DIVIDER_2                         (1 << 5)
11640 #define  ESCAPE_CLOCK_DIVIDER_4                         (2 << 5)
11641 #define  READ_REQUEST_PRIORITY_SHIFT                    3
11642 #define  READ_REQUEST_PRIORITY_MASK                     (3 << 3)
11643 #define  READ_REQUEST_PRIORITY_LOW                      (0 << 3)
11644 #define  READ_REQUEST_PRIORITY_HIGH                     (3 << 3)
11645 #define  RGB_FLIP_TO_BGR                                (1 << 2)
11646
11647 #define  BXT_PIPE_SELECT_SHIFT                          7
11648 #define  BXT_PIPE_SELECT_MASK                           (7 << 7)
11649 #define  BXT_PIPE_SELECT(pipe)                          ((pipe) << 7)
11650 #define  GLK_PHY_STATUS_PORT_READY                      (1 << 31) /* RO */
11651 #define  GLK_ULPS_NOT_ACTIVE                            (1 << 30) /* RO */
11652 #define  GLK_MIPIIO_RESET_RELEASED                      (1 << 28)
11653 #define  GLK_CLOCK_LANE_STOP_STATE                      (1 << 27) /* RO */
11654 #define  GLK_DATA_LANE_STOP_STATE                       (1 << 26) /* RO */
11655 #define  GLK_LP_WAKE                                    (1 << 22)
11656 #define  GLK_LP11_LOW_PWR_MODE                          (1 << 21)
11657 #define  GLK_LP00_LOW_PWR_MODE                          (1 << 20)
11658 #define  GLK_FIREWALL_ENABLE                            (1 << 16)
11659 #define  BXT_PIXEL_OVERLAP_CNT_MASK                     (0xf << 10)
11660 #define  BXT_PIXEL_OVERLAP_CNT_SHIFT                    10
11661 #define  BXT_DSC_ENABLE                                 (1 << 3)
11662 #define  BXT_RGB_FLIP                                   (1 << 2)
11663 #define  GLK_MIPIIO_PORT_POWERED                        (1 << 1) /* RO */
11664 #define  GLK_MIPIIO_ENABLE                              (1 << 0)
11665
11666 #define _MIPIA_DATA_ADDRESS             (dev_priv->mipi_mmio_base + 0xb108)
11667 #define _MIPIC_DATA_ADDRESS             (dev_priv->mipi_mmio_base + 0xb908)
11668 #define MIPI_DATA_ADDRESS(port)         _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
11669 #define  DATA_MEM_ADDRESS_SHIFT                         5
11670 #define  DATA_MEM_ADDRESS_MASK                          (0x7ffffff << 5)
11671 #define  DATA_VALID                                     (1 << 0)
11672
11673 #define _MIPIA_DATA_LENGTH              (dev_priv->mipi_mmio_base + 0xb10c)
11674 #define _MIPIC_DATA_LENGTH              (dev_priv->mipi_mmio_base + 0xb90c)
11675 #define MIPI_DATA_LENGTH(port)          _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
11676 #define  DATA_LENGTH_SHIFT                              0
11677 #define  DATA_LENGTH_MASK                               (0xfffff << 0)
11678
11679 #define _MIPIA_COMMAND_ADDRESS          (dev_priv->mipi_mmio_base + 0xb110)
11680 #define _MIPIC_COMMAND_ADDRESS          (dev_priv->mipi_mmio_base + 0xb910)
11681 #define MIPI_COMMAND_ADDRESS(port)      _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
11682 #define  COMMAND_MEM_ADDRESS_SHIFT                      5
11683 #define  COMMAND_MEM_ADDRESS_MASK                       (0x7ffffff << 5)
11684 #define  AUTO_PWG_ENABLE                                (1 << 2)
11685 #define  MEMORY_WRITE_DATA_FROM_PIPE_RENDERING          (1 << 1)
11686 #define  COMMAND_VALID                                  (1 << 0)
11687
11688 #define _MIPIA_COMMAND_LENGTH           (dev_priv->mipi_mmio_base + 0xb114)
11689 #define _MIPIC_COMMAND_LENGTH           (dev_priv->mipi_mmio_base + 0xb914)
11690 #define MIPI_COMMAND_LENGTH(port)       _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
11691 #define  COMMAND_LENGTH_SHIFT(n)                        (8 * (n)) /* n: 0...3 */
11692 #define  COMMAND_LENGTH_MASK(n)                         (0xff << (8 * (n)))
11693
11694 #define _MIPIA_READ_DATA_RETURN0        (dev_priv->mipi_mmio_base + 0xb118)
11695 #define _MIPIC_READ_DATA_RETURN0        (dev_priv->mipi_mmio_base + 0xb918)
11696 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
11697
11698 #define _MIPIA_READ_DATA_VALID          (dev_priv->mipi_mmio_base + 0xb138)
11699 #define _MIPIC_READ_DATA_VALID          (dev_priv->mipi_mmio_base + 0xb938)
11700 #define MIPI_READ_DATA_VALID(port)      _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
11701 #define  READ_DATA_VALID(n)                             (1 << (n))
11702
11703 /* MOCS (Memory Object Control State) registers */
11704 #define GEN9_LNCFCMOCS(i)       _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
11705
11706 #define __GEN9_RCS0_MOCS0       0xc800
11707 #define GEN9_GFX_MOCS(i)        _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
11708 #define __GEN9_VCS0_MOCS0       0xc900
11709 #define GEN9_MFX0_MOCS(i)       _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
11710 #define __GEN9_VCS1_MOCS0       0xca00
11711 #define GEN9_MFX1_MOCS(i)       _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
11712 #define __GEN9_VECS0_MOCS0      0xcb00
11713 #define GEN9_VEBOX_MOCS(i)      _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
11714 #define __GEN9_BCS0_MOCS0       0xcc00
11715 #define GEN9_BLT_MOCS(i)        _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
11716 #define __GEN11_VCS2_MOCS0      0x10000
11717 #define GEN11_MFX2_MOCS(i)      _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
11718
11719 #define GEN10_SCRATCH_LNCF2             _MMIO(0xb0a0)
11720 #define   PMFLUSHDONE_LNICRSDROP        (1 << 20)
11721 #define   PMFLUSH_GAPL3UNBLOCK          (1 << 21)
11722 #define   PMFLUSHDONE_LNEBLK            (1 << 22)
11723
11724 #define GEN12_GLOBAL_MOCS(i)    _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
11725
11726 /* gamt regs */
11727 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
11728 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
11729 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
11730 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
11731 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
11732
11733 #define MMCD_MISC_CTRL          _MMIO(0x4ddc) /* skl+ */
11734 #define  MMCD_PCLA              (1 << 31)
11735 #define  MMCD_HOTSPOT_EN        (1 << 27)
11736
11737 #define _ICL_PHY_MISC_A         0x64C00
11738 #define _ICL_PHY_MISC_B         0x64C04
11739 #define ICL_PHY_MISC(port)      _MMIO_PORT(port, _ICL_PHY_MISC_A, \
11740                                                  _ICL_PHY_MISC_B)
11741 #define  ICL_PHY_MISC_MUX_DDID                  (1 << 28)
11742 #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN       (1 << 23)
11743
11744 /* Icelake Display Stream Compression Registers */
11745 #define DSCA_PICTURE_PARAMETER_SET_0            _MMIO(0x6B200)
11746 #define DSCC_PICTURE_PARAMETER_SET_0            _MMIO(0x6BA00)
11747 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB    0x78270
11748 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB    0x78370
11749 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC    0x78470
11750 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC    0x78570
11751 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11752                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
11753                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
11754 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11755                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
11756                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
11757 #define  DSC_VBR_ENABLE                 (1 << 19)
11758 #define  DSC_422_ENABLE                 (1 << 18)
11759 #define  DSC_COLOR_SPACE_CONVERSION     (1 << 17)
11760 #define  DSC_BLOCK_PREDICTION           (1 << 16)
11761 #define  DSC_LINE_BUF_DEPTH_SHIFT       12
11762 #define  DSC_BPC_SHIFT                  8
11763 #define  DSC_VER_MIN_SHIFT              4
11764 #define  DSC_VER_MAJ                    (0x1 << 0)
11765
11766 #define DSCA_PICTURE_PARAMETER_SET_1            _MMIO(0x6B204)
11767 #define DSCC_PICTURE_PARAMETER_SET_1            _MMIO(0x6BA04)
11768 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB    0x78274
11769 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB    0x78374
11770 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC    0x78474
11771 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC    0x78574
11772 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11773                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
11774                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
11775 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11776                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
11777                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
11778 #define  DSC_BPP(bpp)                           ((bpp) << 0)
11779
11780 #define DSCA_PICTURE_PARAMETER_SET_2            _MMIO(0x6B208)
11781 #define DSCC_PICTURE_PARAMETER_SET_2            _MMIO(0x6BA08)
11782 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB    0x78278
11783 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB    0x78378
11784 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC    0x78478
11785 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC    0x78578
11786 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11787                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
11788                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
11789 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11790                                             _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
11791                                             _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
11792 #define  DSC_PIC_WIDTH(pic_width)       ((pic_width) << 16)
11793 #define  DSC_PIC_HEIGHT(pic_height)     ((pic_height) << 0)
11794
11795 #define DSCA_PICTURE_PARAMETER_SET_3            _MMIO(0x6B20C)
11796 #define DSCC_PICTURE_PARAMETER_SET_3            _MMIO(0x6BA0C)
11797 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB    0x7827C
11798 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB    0x7837C
11799 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC    0x7847C
11800 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC    0x7857C
11801 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11802                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
11803                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
11804 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11805                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
11806                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
11807 #define  DSC_SLICE_WIDTH(slice_width)   ((slice_width) << 16)
11808 #define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
11809
11810 #define DSCA_PICTURE_PARAMETER_SET_4            _MMIO(0x6B210)
11811 #define DSCC_PICTURE_PARAMETER_SET_4            _MMIO(0x6BA10)
11812 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB    0x78280
11813 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB    0x78380
11814 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC    0x78480
11815 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC    0x78580
11816 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11817                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
11818                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
11819 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11820                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
11821                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
11822 #define  DSC_INITIAL_DEC_DELAY(dec_delay)       ((dec_delay) << 16)
11823 #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
11824
11825 #define DSCA_PICTURE_PARAMETER_SET_5            _MMIO(0x6B214)
11826 #define DSCC_PICTURE_PARAMETER_SET_5            _MMIO(0x6BA14)
11827 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB    0x78284
11828 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB    0x78384
11829 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC    0x78484
11830 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC    0x78584
11831 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11832                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
11833                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
11834 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11835                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
11836                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
11837 #define  DSC_SCALE_DEC_INT(scale_dec)   ((scale_dec) << 16)
11838 #define  DSC_SCALE_INC_INT(scale_inc)           ((scale_inc) << 0)
11839
11840 #define DSCA_PICTURE_PARAMETER_SET_6            _MMIO(0x6B218)
11841 #define DSCC_PICTURE_PARAMETER_SET_6            _MMIO(0x6BA18)
11842 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB    0x78288
11843 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB    0x78388
11844 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC    0x78488
11845 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC    0x78588
11846 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11847                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
11848                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
11849 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11850                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
11851                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
11852 #define  DSC_FLATNESS_MAX_QP(max_qp)            ((max_qp) << 24)
11853 #define  DSC_FLATNESS_MIN_QP(min_qp)            ((min_qp) << 16)
11854 #define  DSC_FIRST_LINE_BPG_OFFSET(offset)      ((offset) << 8)
11855 #define  DSC_INITIAL_SCALE_VALUE(value)         ((value) << 0)
11856
11857 #define DSCA_PICTURE_PARAMETER_SET_7            _MMIO(0x6B21C)
11858 #define DSCC_PICTURE_PARAMETER_SET_7            _MMIO(0x6BA1C)
11859 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB    0x7828C
11860 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB    0x7838C
11861 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC    0x7848C
11862 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC    0x7858C
11863 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11864                                                             _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
11865                                                             _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
11866 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11867                                                             _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
11868                                                             _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
11869 #define  DSC_NFL_BPG_OFFSET(bpg_offset)         ((bpg_offset) << 16)
11870 #define  DSC_SLICE_BPG_OFFSET(bpg_offset)       ((bpg_offset) << 0)
11871
11872 #define DSCA_PICTURE_PARAMETER_SET_8            _MMIO(0x6B220)
11873 #define DSCC_PICTURE_PARAMETER_SET_8            _MMIO(0x6BA20)
11874 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB    0x78290
11875 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB    0x78390
11876 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC    0x78490
11877 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC    0x78590
11878 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11879                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
11880                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
11881 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11882                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
11883                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
11884 #define  DSC_INITIAL_OFFSET(initial_offset)             ((initial_offset) << 16)
11885 #define  DSC_FINAL_OFFSET(final_offset)                 ((final_offset) << 0)
11886
11887 #define DSCA_PICTURE_PARAMETER_SET_9            _MMIO(0x6B224)
11888 #define DSCC_PICTURE_PARAMETER_SET_9            _MMIO(0x6BA24)
11889 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB    0x78294
11890 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB    0x78394
11891 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC    0x78494
11892 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC    0x78594
11893 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11894                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
11895                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
11896 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe)  _MMIO_PIPE((pipe) - PIPE_B, \
11897                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
11898                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
11899 #define  DSC_RC_EDGE_FACTOR(rc_edge_fact)       ((rc_edge_fact) << 16)
11900 #define  DSC_RC_MODEL_SIZE(rc_model_size)       ((rc_model_size) << 0)
11901
11902 #define DSCA_PICTURE_PARAMETER_SET_10           _MMIO(0x6B228)
11903 #define DSCC_PICTURE_PARAMETER_SET_10           _MMIO(0x6BA28)
11904 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB   0x78298
11905 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB   0x78398
11906 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC   0x78498
11907 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC   0x78598
11908 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11909                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
11910                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
11911 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11912                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
11913                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
11914 #define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)          ((rc_tgt_off_low) << 20)
11915 #define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)        ((rc_tgt_off_high) << 16)
11916 #define  DSC_RC_QUANT_INC_LIMIT1(lim)                   ((lim) << 8)
11917 #define  DSC_RC_QUANT_INC_LIMIT0(lim)                   ((lim) << 0)
11918
11919 #define DSCA_PICTURE_PARAMETER_SET_11           _MMIO(0x6B22C)
11920 #define DSCC_PICTURE_PARAMETER_SET_11           _MMIO(0x6BA2C)
11921 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB   0x7829C
11922 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB   0x7839C
11923 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC   0x7849C
11924 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC   0x7859C
11925 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11926                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
11927                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
11928 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11929                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
11930                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
11931
11932 #define DSCA_PICTURE_PARAMETER_SET_12           _MMIO(0x6B260)
11933 #define DSCC_PICTURE_PARAMETER_SET_12           _MMIO(0x6BA60)
11934 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB   0x782A0
11935 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB   0x783A0
11936 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC   0x784A0
11937 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC   0x785A0
11938 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11939                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
11940                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
11941 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11942                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
11943                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
11944
11945 #define DSCA_PICTURE_PARAMETER_SET_13           _MMIO(0x6B264)
11946 #define DSCC_PICTURE_PARAMETER_SET_13           _MMIO(0x6BA64)
11947 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB   0x782A4
11948 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB   0x783A4
11949 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC   0x784A4
11950 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC   0x785A4
11951 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11952                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
11953                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
11954 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11955                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
11956                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
11957
11958 #define DSCA_PICTURE_PARAMETER_SET_14           _MMIO(0x6B268)
11959 #define DSCC_PICTURE_PARAMETER_SET_14           _MMIO(0x6BA68)
11960 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB   0x782A8
11961 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB   0x783A8
11962 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC   0x784A8
11963 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC   0x785A8
11964 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11965                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
11966                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
11967 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11968                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
11969                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
11970
11971 #define DSCA_PICTURE_PARAMETER_SET_15           _MMIO(0x6B26C)
11972 #define DSCC_PICTURE_PARAMETER_SET_15           _MMIO(0x6BA6C)
11973 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB   0x782AC
11974 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB   0x783AC
11975 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC   0x784AC
11976 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC   0x785AC
11977 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11978                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
11979                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
11980 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11981                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
11982                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
11983
11984 #define DSCA_PICTURE_PARAMETER_SET_16           _MMIO(0x6B270)
11985 #define DSCC_PICTURE_PARAMETER_SET_16           _MMIO(0x6BA70)
11986 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB   0x782B0
11987 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB   0x783B0
11988 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC   0x784B0
11989 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC   0x785B0
11990 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11991                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
11992                                                            _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
11993 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11994                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
11995                                                            _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
11996 #define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)   ((slice_row_per_frame) << 20)
11997 #define  DSC_SLICE_PER_LINE(slice_per_line)             ((slice_per_line) << 16)
11998 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)         ((slice_chunk_size) << 0)
11999
12000 /* Icelake Rate Control Buffer Threshold Registers */
12001 #define DSCA_RC_BUF_THRESH_0                    _MMIO(0x6B230)
12002 #define DSCA_RC_BUF_THRESH_0_UDW                _MMIO(0x6B230 + 4)
12003 #define DSCC_RC_BUF_THRESH_0                    _MMIO(0x6BA30)
12004 #define DSCC_RC_BUF_THRESH_0_UDW                _MMIO(0x6BA30 + 4)
12005 #define _ICL_DSC0_RC_BUF_THRESH_0_PB            (0x78254)
12006 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB        (0x78254 + 4)
12007 #define _ICL_DSC1_RC_BUF_THRESH_0_PB            (0x78354)
12008 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB        (0x78354 + 4)
12009 #define _ICL_DSC0_RC_BUF_THRESH_0_PC            (0x78454)
12010 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC        (0x78454 + 4)
12011 #define _ICL_DSC1_RC_BUF_THRESH_0_PC            (0x78554)
12012 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC        (0x78554 + 4)
12013 #define ICL_DSC0_RC_BUF_THRESH_0(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
12014                                                 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
12015                                                 _ICL_DSC0_RC_BUF_THRESH_0_PC)
12016 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
12017                                                 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
12018                                                 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
12019 #define ICL_DSC1_RC_BUF_THRESH_0(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
12020                                                 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
12021                                                 _ICL_DSC1_RC_BUF_THRESH_0_PC)
12022 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
12023                                                 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
12024                                                 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
12025
12026 #define DSCA_RC_BUF_THRESH_1                    _MMIO(0x6B238)
12027 #define DSCA_RC_BUF_THRESH_1_UDW                _MMIO(0x6B238 + 4)
12028 #define DSCC_RC_BUF_THRESH_1                    _MMIO(0x6BA38)
12029 #define DSCC_RC_BUF_THRESH_1_UDW                _MMIO(0x6BA38 + 4)
12030 #define _ICL_DSC0_RC_BUF_THRESH_1_PB            (0x7825C)
12031 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB        (0x7825C + 4)
12032 #define _ICL_DSC1_RC_BUF_THRESH_1_PB            (0x7835C)
12033 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB        (0x7835C + 4)
12034 #define _ICL_DSC0_RC_BUF_THRESH_1_PC            (0x7845C)
12035 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC        (0x7845C + 4)
12036 #define _ICL_DSC1_RC_BUF_THRESH_1_PC            (0x7855C)
12037 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC        (0x7855C + 4)
12038 #define ICL_DSC0_RC_BUF_THRESH_1(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
12039                                                 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
12040                                                 _ICL_DSC0_RC_BUF_THRESH_1_PC)
12041 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
12042                                                 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
12043                                                 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
12044 #define ICL_DSC1_RC_BUF_THRESH_1(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
12045                                                 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
12046                                                 _ICL_DSC1_RC_BUF_THRESH_1_PC)
12047 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
12048                                                 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
12049                                                 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
12050
12051 #define PORT_TX_DFLEXDPSP(fia)                  _MMIO_FIA((fia), 0x008A0)
12052 #define   MODULAR_FIA_MASK                      (1 << 4)
12053 #define   TC_LIVE_STATE_TBT(idx)                (1 << ((idx) * 8 + 6))
12054 #define   TC_LIVE_STATE_TC(idx)                 (1 << ((idx) * 8 + 5))
12055 #define   DP_LANE_ASSIGNMENT_SHIFT(idx)         ((idx) * 8)
12056 #define   DP_LANE_ASSIGNMENT_MASK(idx)          (0xf << ((idx) * 8))
12057 #define   DP_LANE_ASSIGNMENT(idx, x)            ((x) << ((idx) * 8))
12058
12059 #define PORT_TX_DFLEXDPPMS(fia)                 _MMIO_FIA((fia), 0x00890)
12060 #define   DP_PHY_MODE_STATUS_COMPLETED(idx)     (1 << (idx))
12061
12062 #define PORT_TX_DFLEXDPCSSS(fia)                _MMIO_FIA((fia), 0x00894)
12063 #define   DP_PHY_MODE_STATUS_NOT_SAFE(idx)      (1 << (idx))
12064
12065 #define PORT_TX_DFLEXPA1(fia)                   _MMIO_FIA((fia), 0x00880)
12066 #define   DP_PIN_ASSIGNMENT_SHIFT(idx)          ((idx) * 4)
12067 #define   DP_PIN_ASSIGNMENT_MASK(idx)           (0xf << ((idx) * 4))
12068 #define   DP_PIN_ASSIGNMENT(idx, x)             ((x) << ((idx) * 4))
12069
12070 /* This register controls the Display State Buffer (DSB) engines. */
12071 #define _DSBSL_INSTANCE_BASE            0x70B00
12072 #define DSBSL_INSTANCE(pipe, id)        (_DSBSL_INSTANCE_BASE + \
12073                                          (pipe) * 0x1000 + (id) * 0x100)
12074 #define DSB_HEAD(pipe, id)              _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
12075 #define DSB_TAIL(pipe, id)              _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
12076 #define DSB_CTRL(pipe, id)              _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
12077 #define   DSB_ENABLE                    (1 << 31)
12078 #define   DSB_STATUS                    (1 << 0)
12079
12080 #endif /* _I915_REG_H_ */