drivers/gpu/drm/rockchip/rk3066_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   4  *    Zheng Yang <zhengyang@rock-chips.com>
   5  */
   6
   7 #include <drm/drm_of.h>
   8 #include <drm/drm_probe_helper.h>
   9
  10 #include <linux/clk.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/regmap.h>
  14
  15 #include "rk3066_hdmi.h"
  16
  17 #include "rockchip_drm_drv.h"
  18 #include "rockchip_drm_vop.h"
  19
  20 #define DEFAULT_PLLA_RATE 30000000
  21
  22 struct hdmi_data_info {
  23         int vic; /* The CEA Video ID (VIC) of the current drm display mode. */
  24         bool sink_is_hdmi;
  25         unsigned int enc_out_format;
  26         unsigned int colorimetry;
  27 };
  28
  29 struct rk3066_hdmi_i2c {
  30         struct i2c_adapter adap;
  31
  32         u8 ddc_addr;
  33         u8 segment_addr;
  34         u8 stat;
  35
  36         struct mutex i2c_lock; /* For i2c operation. */
  37         struct completion cmpltn;
  38 };
  39
  40 struct rk3066_hdmi {
  41         struct device *dev;
  42         struct drm_device *drm_dev;
  43         struct regmap *grf_regmap;
  44         int irq;
  45         struct clk *hclk;
  46         void __iomem *regs;
  47
  48         struct drm_connector connector;
  49         struct drm_encoder encoder;
  50
  51         struct rk3066_hdmi_i2c *i2c;
  52         struct i2c_adapter *ddc;
  53
  54         unsigned int tmdsclk;
  55
  56         struct hdmi_data_info hdmi_data;
  57         struct drm_display_mode previous_mode;
  58 };
  59
  60 #define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x)
  61
  62 static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset)
  63 {
  64         return readl_relaxed(hdmi->regs + offset);
  65 }
  66
  67 static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val)
  68 {
  69         writel_relaxed(val, hdmi->regs + offset);
  70 }
  71
  72 static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset,
  73                              u32 msk, u32 val)
  74 {
  75         u8 temp = hdmi_readb(hdmi, offset) & ~msk;
  76
  77         temp |= val & msk;
  78         hdmi_writeb(hdmi, offset, temp);
  79 }
  80
  81 static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi)
  82 {
  83         int ddc_bus_freq;
  84
  85         ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE;
  86
  87         hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
  88         hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
  89
  90         /* Clear the EDID interrupt flag and mute the interrupt. */
  91         hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
  92         hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK);
  93 }
  94
  95 static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi)
  96 {
  97         return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK;
  98 }
  99
 100 static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode)
 101 {
 102         u8 current_mode, next_mode;
 103         u8 i = 0;
 104
 105         current_mode = rk3066_hdmi_get_power_mode(hdmi);
 106
 107         DRM_DEV_DEBUG(hdmi->dev, "mode         :%d\n", mode);
 108         DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode);
 109
 110         if (current_mode == mode)
 111                 return;
 112
 113         do {
 114                 if (current_mode > mode) {
 115                         next_mode = current_mode / 2;
 116                 } else {
 117                         if (current_mode < HDMI_SYS_POWER_MODE_A)
 118                                 next_mode = HDMI_SYS_POWER_MODE_A;
 119                         else
 120                                 next_mode = current_mode * 2;
 121                 }
 122
 123                 DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode);
 124
 125                 if (next_mode != HDMI_SYS_POWER_MODE_D) {
 126                         hdmi_modb(hdmi, HDMI_SYS_CTRL,
 127                                   HDMI_SYS_POWER_MODE_MASK, next_mode);
 128                 } else {
 129                         hdmi_writeb(hdmi, HDMI_SYS_CTRL,
 130                                     HDMI_SYS_POWER_MODE_D |
 131                                     HDMI_SYS_PLL_RESET_MASK);
 132                         usleep_range(90, 100);
 133                         hdmi_writeb(hdmi, HDMI_SYS_CTRL,
 134                                     HDMI_SYS_POWER_MODE_D |
 135                                     HDMI_SYS_PLLB_RESET);
 136                         usleep_range(90, 100);
 137                         hdmi_writeb(hdmi, HDMI_SYS_CTRL,
 138                                     HDMI_SYS_POWER_MODE_D);
 139                 }
 140                 current_mode = next_mode;
 141                 i = i + 1;
 142         } while ((next_mode != mode) && (i < 5));
 143
 144         /*
 145          * When the IP controller isn't configured with accurate video timing,
 146          * DDC_CLK should be equal to the PLLA frequency, which is 30MHz,
 147          * so we need to init the TMDS rate to the PCLK rate and reconfigure
 148          * the DDC clock.
 149          */
 150         if (mode < HDMI_SYS_POWER_MODE_D)
 151                 hdmi->tmdsclk = DEFAULT_PLLA_RATE;
 152 }
 153
 154 static int
 155 rk3066_hdmi_upload_frame(struct rk3066_hdmi *hdmi, int setup_rc,
 156                          union hdmi_infoframe *frame, u32 frame_index,
 157                          u32 mask, u32 disable, u32 enable)
 158 {
 159         if (mask)
 160                 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, disable);
 161
 162         hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, frame_index);
 163
 164         if (setup_rc >= 0) {
 165                 u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
 166                 ssize_t rc, i;
 167
 168                 rc = hdmi_infoframe_pack(frame, packed_frame,
 169                                          sizeof(packed_frame));
 170                 if (rc < 0)
 171                         return rc;
 172
 173                 for (i = 0; i < rc; i++)
 174                         hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4,
 175                                     packed_frame[i]);
 176
 177                 if (mask)
 178                         hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, enable);
 179         }
 180
 181         return setup_rc;
 182 }
 183
 184 static int rk3066_hdmi_config_avi(struct rk3066_hdmi *hdmi,
 185                                   struct drm_display_mode *mode)
 186 {
 187         union hdmi_infoframe frame;
 188         int rc;
 189
 190         rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 191                                                       &hdmi->connector, mode);
 192
 193         if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444)
 194                 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
 195         else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422)
 196                 frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
 197         else
 198                 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 199
 200         frame.avi.colorimetry = hdmi->hdmi_data.colorimetry;
 201         frame.avi.scan_mode = HDMI_SCAN_MODE_NONE;
 202
 203         return rk3066_hdmi_upload_frame(hdmi, rc, &frame,
 204                                         HDMI_INFOFRAME_AVI, 0, 0, 0);
 205 }
 206
 207 static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi,
 208                                            struct drm_display_mode *mode)
 209 {
 210         int value, vsync_offset;
 211
 212         /* Set the details for the external polarity and interlace mode. */
 213         value = HDMI_EXT_VIDEO_SET_EN;
 214         value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
 215                  HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW;
 216         value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
 217                  HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW;
 218         value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
 219                  HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE;
 220
 221         if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3)
 222                 vsync_offset = 6;
 223         else
 224                 vsync_offset = 0;
 225
 226         value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT;
 227         hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value);
 228
 229         /* Set the details for the external video timing. */
 230         value = mode->htotal;
 231         hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF);
 232         hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF);
 233
 234         value = mode->htotal - mode->hdisplay;
 235         hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF);
 236         hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 8) & 0xFF);
 237
 238         value = mode->htotal - mode->hsync_start;
 239         hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF);
 240         hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 8) & 0xFF);
 241
 242         value = mode->hsync_end - mode->hsync_start;
 243         hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF);
 244         hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 8) & 0xFF);
 245
 246         value = mode->vtotal;
 247         hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF);
 248         hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 8) & 0xFF);
 249
 250         value = mode->vtotal - mode->vdisplay;
 251         hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF);
 252
 253         value = mode->vtotal - mode->vsync_start + vsync_offset;
 254         hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF);
 255
 256         value = mode->vsync_end - mode->vsync_start;
 257         hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF);
 258
 259         return 0;
 260 }
 261
 262 static void
 263 rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value)
 264 {
 265         hdmi_writeb(hdmi, offset, value);
 266         hdmi_modb(hdmi, HDMI_SYS_CTRL,
 267                   HDMI_SYS_PLL_RESET_MASK, HDMI_SYS_PLL_RESET);
 268         usleep_range(90, 100);
 269         hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0);
 270         usleep_range(900, 1000);
 271 }
 272
 273 static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi)
 274 {
 275         /* TMDS uses the same frequency as dclk. */
 276         hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22);
 277
 278         /*
 279          * The semi-public documentation does not describe the hdmi registers
 280          * used by the function rk3066_hdmi_phy_write(), so we keep using
 281          * these magic values for now.
 282          */
 283         if (hdmi->tmdsclk > 100000000) {
 284                 rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E);
 285                 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
 286                 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
 287                 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
 288                 rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA);
 289                 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1);
 290                 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
 291                 rk3066_hdmi_phy_write(hdmi, 0x174, 0x22);
 292                 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
 293         } else if (hdmi->tmdsclk > 50000000) {
 294                 rk3066_hdmi_phy_write(hdmi, 0x158, 0x06);
 295                 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
 296                 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
 297                 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
 298                 rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA);
 299                 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3);
 300                 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
 301                 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
 302                 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
 303         } else {
 304                 rk3066_hdmi_phy_write(hdmi, 0x158, 0x02);
 305                 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
 306                 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
 307                 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
 308                 rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2);
 309                 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2);
 310                 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
 311                 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
 312                 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
 313         }
 314 }
 315
 316 static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi,
 317                              struct drm_display_mode *mode)
 318 {
 319         hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
 320         hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB;
 321
 322         if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 ||
 323             hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 ||
 324             hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 ||
 325             hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18)
 326                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
 327         else
 328                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
 329
 330         hdmi->tmdsclk = mode->clock * 1000;
 331
 332         /* Mute video and audio output. */
 333         hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK,
 334                   HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE);
 335
 336         /* Set power state to mode B. */
 337         if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B)
 338                 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
 339
 340         /* Input video mode is RGB 24 bit. Use external data enable signal. */
 341         hdmi_modb(hdmi, HDMI_AV_CTRL1,
 342                   HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE);
 343         hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1,
 344                     HDMI_VIDEO_OUTPUT_RGB444 |
 345                     HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT |
 346                     HDMI_VIDEO_INPUT_COLOR_RGB);
 347         hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20);
 348
 349         rk3066_hdmi_config_video_timing(hdmi, mode);
 350
 351         if (hdmi->hdmi_data.sink_is_hdmi) {
 352                 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK,
 353                           HDMI_VIDEO_MODE_HDMI);
 354                 rk3066_hdmi_config_avi(hdmi, mode);
 355         } else {
 356                 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0);
 357         }
 358
 359         rk3066_hdmi_config_phy(hdmi);
 360
 361         rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E);
 362
 363         /*
 364          * When the IP controller is configured with accurate video
 365          * timing, the TMDS clock source should be switched to
 366          * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode
 367          * clock rate and reconfigure the DDC clock.
 368          */
 369         rk3066_hdmi_i2c_init(hdmi);
 370
 371         /* Unmute video output. */
 372         hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
 373                   HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE);
 374         return 0;
 375 }
 376
 377 static void
 378 rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder,
 379                              struct drm_display_mode *mode,
 380                              struct drm_display_mode *adj_mode)
 381 {
 382         struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
 383
 384         /* Store the display mode for plugin/DPMS poweron events. */
 385         memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode));
 386 }
 387
 388 static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder)
 389 {
 390         struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
 391         int mux, val;
 392
 393         mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
 394         if (mux)
 395                 val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL;
 396         else
 397                 val = HDMI_VIDEO_SEL << 16;
 398
 399         regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val);
 400
 401         DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n",
 402                       (mux) ? "1" : "0");
 403
 404         rk3066_hdmi_setup(hdmi, &hdmi->previous_mode);
 405 }
 406
 407 static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder)
 408 {
 409         struct rk3066_hdmi *hdmi = to_rk3066_hdmi(encoder);
 410
 411         DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n");
 412
 413         if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) {
 414                 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2,
 415                             HDMI_VIDEO_AUDIO_DISABLE_MASK);
 416                 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
 417                           HDMI_AUDIO_CP_LOGIC_RESET_MASK,
 418                           HDMI_AUDIO_CP_LOGIC_RESET);
 419                 usleep_range(500, 510);
 420         }
 421         rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
 422 }
 423
 424 static bool
 425 rk3066_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
 426                                const struct drm_display_mode *mode,
 427                                struct drm_display_mode *adj_mode)
 428 {
 429         return true;
 430 }
 431
 432 static int
 433 rk3066_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
 434                                  struct drm_crtc_state *crtc_state,
 435                                  struct drm_connector_state *conn_state)
 436 {
 437         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 438
 439         s->output_mode = ROCKCHIP_OUT_MODE_P888;
 440         s->output_type = DRM_MODE_CONNECTOR_HDMIA;
 441
 442         return 0;
 443 }
 444
 445 static const
 446 struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = {
 447         .enable       = rk3066_hdmi_encoder_enable,
 448         .disable      = rk3066_hdmi_encoder_disable,
 449         .mode_fixup   = rk3066_hdmi_encoder_mode_fixup,
 450         .mode_set     = rk3066_hdmi_encoder_mode_set,
 451         .atomic_check = rk3066_hdmi_encoder_atomic_check,
 452 };
 453
 454 static const struct drm_encoder_funcs rk3066_hdmi_encoder_funcs = {
 455         .destroy = drm_encoder_cleanup,
 456 };
 457
 458 static enum drm_connector_status
 459 rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force)
 460 {
 461         struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
 462
 463         return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ?
 464                 connector_status_connected : connector_status_disconnected;
 465 }
 466
 467 static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector)
 468 {
 469         struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
 470         struct edid *edid;
 471         int ret = 0;
 472
 473         if (!hdmi->ddc)
 474                 return 0;
 475
 476         edid = drm_get_edid(connector, hdmi->ddc);
 477         if (edid) {
 478                 hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
 479                 drm_connector_update_edid_property(connector, edid);
 480                 ret = drm_add_edid_modes(connector, edid);
 481                 kfree(edid);
 482         }
 483
 484         return ret;
 485 }
 486
 487 static enum drm_mode_status
 488 rk3066_hdmi_connector_mode_valid(struct drm_connector *connector,
 489                                  struct drm_display_mode *mode)
 490 {
 491         u32 vic = drm_match_cea_mode(mode);
 492
 493         if (vic > 1)
 494                 return MODE_OK;
 495         else
 496                 return MODE_BAD;
 497 }
 498
 499 static struct drm_encoder *
 500 rk3066_hdmi_connector_best_encoder(struct drm_connector *connector)
 501 {
 502         struct rk3066_hdmi *hdmi = to_rk3066_hdmi(connector);
 503
 504         return &hdmi->encoder;
 505 }
 506
 507 static int
 508 rk3066_hdmi_probe_single_connector_modes(struct drm_connector *connector,
 509                                          uint32_t maxX, uint32_t maxY)
 510 {
 511         if (maxX > 1920)
 512                 maxX = 1920;
 513         if (maxY > 1080)
 514                 maxY = 1080;
 515
 516         return drm_helper_probe_single_connector_modes(connector, maxX, maxY);
 517 }
 518
 519 static void rk3066_hdmi_connector_destroy(struct drm_connector *connector)
 520 {
 521         drm_connector_unregister(connector);
 522         drm_connector_cleanup(connector);
 523 }
 524
 525 static const struct drm_connector_funcs rk3066_hdmi_connector_funcs = {
 526         .fill_modes = rk3066_hdmi_probe_single_connector_modes,
 527         .detect = rk3066_hdmi_connector_detect,
 528         .destroy = rk3066_hdmi_connector_destroy,
 529         .reset = drm_atomic_helper_connector_reset,
 530         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 531         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 532 };
 533
 534 static const
 535 struct drm_connector_helper_funcs rk3066_hdmi_connector_helper_funcs = {
 536         .get_modes = rk3066_hdmi_connector_get_modes,
 537         .mode_valid = rk3066_hdmi_connector_mode_valid,
 538         .best_encoder = rk3066_hdmi_connector_best_encoder,
 539 };
 540
 541 static int
 542 rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi)
 543 {
 544         struct drm_encoder *encoder = &hdmi->encoder;
 545         struct device *dev = hdmi->dev;
 546
 547         encoder->possible_crtcs =
 548                 drm_of_find_possible_crtcs(drm, dev->of_node);
 549
 550         /*
 551          * If we failed to find the CRTC(s) which this encoder is
 552          * supposed to be connected to, it's because the CRTC has
 553          * not been registered yet.  Defer probing, and hope that
 554          * the required CRTC is added later.
 555          */
 556         if (encoder->possible_crtcs == 0)
 557                 return -EPROBE_DEFER;
 558
 559         drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs);
 560         drm_encoder_init(drm, encoder, &rk3066_hdmi_encoder_funcs,
 561                          DRM_MODE_ENCODER_TMDS, NULL);
 562
 563         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
 564
 565         drm_connector_helper_add(&hdmi->connector,
 566                                  &rk3066_hdmi_connector_helper_funcs);
 567         drm_connector_init_with_ddc(drm, &hdmi->connector,
 568                                     &rk3066_hdmi_connector_funcs,
 569                                     DRM_MODE_CONNECTOR_HDMIA,
 570                                     hdmi->ddc);
 571
 572         drm_connector_attach_encoder(&hdmi->connector, encoder);
 573
 574         return 0;
 575 }
 576
 577 static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id)
 578 {
 579         struct rk3066_hdmi *hdmi = dev_id;
 580         irqreturn_t ret = IRQ_NONE;
 581         u8 interrupt;
 582
 583         if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A)
 584                 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B);
 585
 586         interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1);
 587         if (interrupt)
 588                 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt);
 589
 590         if (interrupt & HDMI_INTR_EDID_MASK) {
 591                 hdmi->i2c->stat = interrupt;
 592                 complete(&hdmi->i2c->cmpltn);
 593         }
 594
 595         if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS))
 596                 ret = IRQ_WAKE_THREAD;
 597
 598         return ret;
 599 }
 600
 601 static irqreturn_t rk3066_hdmi_irq(int irq, void *dev_id)
 602 {
 603         struct rk3066_hdmi *hdmi = dev_id;
 604
 605         drm_helper_hpd_irq_event(hdmi->connector.dev);
 606
 607         return IRQ_HANDLED;
 608 }
 609
 610 static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
 611 {
 612         int length = msgs->len;
 613         u8 *buf = msgs->buf;
 614         int ret;
 615
 616         ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10);
 617         if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR)
 618                 return -EAGAIN;
 619
 620         while (length--)
 621                 *buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR);
 622
 623         return 0;
 624 }
 625
 626 static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
 627 {
 628         /*
 629          * The DDC module only supports read EDID message, so
 630          * we assume that each word write to this i2c adapter
 631          * should be the offset of the EDID word address.
 632          */
 633         if (msgs->len != 1 ||
 634             (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR))
 635                 return -EINVAL;
 636
 637         reinit_completion(&hdmi->i2c->cmpltn);
 638
 639         if (msgs->addr == DDC_SEGMENT_ADDR)
 640                 hdmi->i2c->segment_addr = msgs->buf[0];
 641         if (msgs->addr == DDC_ADDR)
 642                 hdmi->i2c->ddc_addr = msgs->buf[0];
 643
 644         /* Set edid fifo first address. */
 645         hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00);
 646
 647         /* Set edid word address 0x00/0x80. */
 648         hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
 649
 650         /* Set edid segment pointer. */
 651         hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
 652
 653         return 0;
 654 }
 655
 656 static int rk3066_hdmi_i2c_xfer(struct i2c_adapter *adap,
 657                                 struct i2c_msg *msgs, int num)
 658 {
 659         struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap);
 660         struct rk3066_hdmi_i2c *i2c = hdmi->i2c;
 661         int i, ret = 0;
 662
 663         mutex_lock(&i2c->i2c_lock);
 664
 665         rk3066_hdmi_i2c_init(hdmi);
 666
 667         /* Unmute HDMI EDID interrupt. */
 668         hdmi_modb(hdmi, HDMI_INTR_MASK1,
 669                   HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK);
 670         i2c->stat = 0;
 671
 672         for (i = 0; i < num; i++) {
 673                 DRM_DEV_DEBUG(hdmi->dev,
 674                               "xfer: num: %d/%d, len: %d, flags: %#x\n",
 675                               i + 1, num, msgs[i].len, msgs[i].flags);
 676
 677                 if (msgs[i].flags & I2C_M_RD)
 678                         ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]);
 679                 else
 680                         ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]);
 681
 682                 if (ret < 0)
 683                         break;
 684         }
 685
 686         if (!ret)
 687                 ret = num;
 688
 689         /* Mute HDMI EDID interrupt. */
 690         hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
 691
 692         mutex_unlock(&i2c->i2c_lock);
 693
 694         return ret;
 695 }
 696
 697 static u32 rk3066_hdmi_i2c_func(struct i2c_adapter *adapter)
 698 {
 699         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 700 }
 701
 702 static const struct i2c_algorithm rk3066_hdmi_algorithm = {
 703         .master_xfer   = rk3066_hdmi_i2c_xfer,
 704         .functionality = rk3066_hdmi_i2c_func,
 705 };
 706
 707 static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi)
 708 {
 709         struct i2c_adapter *adap;
 710         struct rk3066_hdmi_i2c *i2c;
 711         int ret;
 712
 713         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 714         if (!i2c)
 715                 return ERR_PTR(-ENOMEM);
 716
 717         mutex_init(&i2c->i2c_lock);
 718         init_completion(&i2c->cmpltn);
 719
 720         adap = &i2c->adap;
 721         adap->class = I2C_CLASS_DDC;
 722         adap->owner = THIS_MODULE;
 723         adap->dev.parent = hdmi->dev;
 724         adap->dev.of_node = hdmi->dev->of_node;
 725         adap->algo = &rk3066_hdmi_algorithm;
 726         strlcpy(adap->name, "RK3066 HDMI", sizeof(adap->name));
 727         i2c_set_adapdata(adap, hdmi);
 728
 729         ret = i2c_add_adapter(adap);
 730         if (ret) {
 731                 DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n",
 732                               adap->name);
 733                 devm_kfree(hdmi->dev, i2c);
 734                 return ERR_PTR(ret);
 735         }
 736
 737         hdmi->i2c = i2c;
 738
 739         DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 740
 741         return adap;
 742 }
 743
 744 static int rk3066_hdmi_bind(struct device *dev, struct device *master,
 745                             void *data)
 746 {
 747         struct platform_device *pdev = to_platform_device(dev);
 748         struct drm_device *drm = data;
 749         struct rk3066_hdmi *hdmi;
 750         int irq;
 751         int ret;
 752
 753         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
 754         if (!hdmi)
 755                 return -ENOMEM;
 756
 757         hdmi->dev = dev;
 758         hdmi->drm_dev = drm;
 759         hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
 760         if (IS_ERR(hdmi->regs))
 761                 return PTR_ERR(hdmi->regs);
 762
 763         irq = platform_get_irq(pdev, 0);
 764         if (irq < 0)
 765                 return irq;
 766
 767         hdmi->hclk = devm_clk_get(dev, "hclk");
 768         if (IS_ERR(hdmi->hclk)) {
 769                 DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n");
 770                 return PTR_ERR(hdmi->hclk);
 771         }
 772
 773         ret = clk_prepare_enable(hdmi->hclk);
 774         if (ret) {
 775                 DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret);
 776                 return ret;
 777         }
 778
 779         hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
 780                                                            "rockchip,grf");
 781         if (IS_ERR(hdmi->grf_regmap)) {
 782                 DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n");
 783                 ret = PTR_ERR(hdmi->grf_regmap);
 784                 goto err_disable_hclk;
 785         }
 786
 787         /* internal hclk = hdmi_hclk / 25 */
 788         hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25);
 789
 790         hdmi->ddc = rk3066_hdmi_i2c_adapter(hdmi);
 791         if (IS_ERR(hdmi->ddc)) {
 792                 ret = PTR_ERR(hdmi->ddc);
 793                 hdmi->ddc = NULL;
 794                 goto err_disable_hclk;
 795         }
 796
 797         rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
 798         usleep_range(999, 1000);
 799         hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG);
 800         hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0);
 801         hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0);
 802         hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0);
 803         rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
 804
 805         ret = rk3066_hdmi_register(drm, hdmi);
 806         if (ret)
 807                 goto err_disable_i2c;
 808
 809         dev_set_drvdata(dev, hdmi);
 810
 811         ret = devm_request_threaded_irq(dev, irq, rk3066_hdmi_hardirq,
 812                                         rk3066_hdmi_irq, IRQF_SHARED,
 813                                         dev_name(dev), hdmi);
 814         if (ret) {
 815                 DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret);
 816                 goto err_cleanup_hdmi;
 817         }
 818
 819         return 0;
 820
 821 err_cleanup_hdmi:
 822         hdmi->connector.funcs->destroy(&hdmi->connector);
 823         hdmi->encoder.funcs->destroy(&hdmi->encoder);
 824 err_disable_i2c:
 825         i2c_put_adapter(hdmi->ddc);
 826 err_disable_hclk:
 827         clk_disable_unprepare(hdmi->hclk);
 828
 829         return ret;
 830 }
 831
 832 static void rk3066_hdmi_unbind(struct device *dev, struct device *master,
 833                                void *data)
 834 {
 835         struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
 836
 837         hdmi->connector.funcs->destroy(&hdmi->connector);
 838         hdmi->encoder.funcs->destroy(&hdmi->encoder);
 839
 840         i2c_put_adapter(hdmi->ddc);
 841         clk_disable_unprepare(hdmi->hclk);
 842 }
 843
 844 static const struct component_ops rk3066_hdmi_ops = {
 845         .bind   = rk3066_hdmi_bind,
 846         .unbind = rk3066_hdmi_unbind,
 847 };
 848
 849 static int rk3066_hdmi_probe(struct platform_device *pdev)
 850 {
 851         return component_add(&pdev->dev, &rk3066_hdmi_ops);
 852 }
 853
 854 static int rk3066_hdmi_remove(struct platform_device *pdev)
 855 {
 856         component_del(&pdev->dev, &rk3066_hdmi_ops);
 857
 858         return 0;
 859 }
 860
 861 static const struct of_device_id rk3066_hdmi_dt_ids[] = {
 862         { .compatible = "rockchip,rk3066-hdmi" },
 863         { /* sentinel */ },
 864 };
 865 MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids);
 866
 867 struct platform_driver rk3066_hdmi_driver = {
 868         .probe  = rk3066_hdmi_probe,
 869         .remove = rk3066_hdmi_remove,
 870         .driver = {
 871                 .name = "rockchip-rk3066-hdmi",
 872                 .of_match_table = rk3066_hdmi_dt_ids,
 873         },
 874 };