[PATCH] unnecessary long index i in sched
[linux/fpc-iii.git] / arch / i386 / mach-visws / setup.c
blob8a9e1a6f745de17f9d28e9acfaf2e3f3d205994a
1 /*
2 * Unmaintained SGI Visual Workstation support.
3 * Split out from setup.c by davej@suse.de
4 */
6 #include <linux/smp.h>
7 #include <linux/init.h>
8 #include <linux/interrupt.h>
10 #include <asm/fixmap.h>
11 #include <asm/arch_hooks.h>
12 #include <asm/io.h>
13 #include <asm/e820.h>
14 #include <asm/setup.h>
15 #include "cobalt.h"
16 #include "piix4.h"
18 int no_broadcast;
20 char visws_board_type = -1;
21 char visws_board_rev = -1;
23 void __init visws_get_board_type_and_rev(void)
25 int raw;
27 visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
28 >> PIIX_GPI_BD_SHIFT;
30 * Get Board rev.
31 * First, we have to initialize the 307 part to allow us access
32 * to the GPIO registers. Let's map them at 0x0fc0 which is right
33 * after the PIIX4 PM section.
35 outb_p(SIO_DEV_SEL, SIO_INDEX);
36 outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */
38 outb_p(SIO_DEV_MSB, SIO_INDEX);
39 outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */
41 outb_p(SIO_DEV_LSB, SIO_INDEX);
42 outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */
44 outb_p(SIO_DEV_ENB, SIO_INDEX);
45 outb_p(1, SIO_DATA); /* Enable GPIO registers. */
48 * Now, we have to map the power management section to write
49 * a bit which enables access to the GPIO registers.
50 * What lunatic came up with this shit?
52 outb_p(SIO_DEV_SEL, SIO_INDEX);
53 outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */
55 outb_p(SIO_DEV_MSB, SIO_INDEX);
56 outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */
58 outb_p(SIO_DEV_LSB, SIO_INDEX);
59 outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */
61 outb_p(SIO_DEV_ENB, SIO_INDEX);
62 outb_p(1, SIO_DATA); /* Enable PM registers. */
65 * Now, write the PM register which enables the GPIO registers.
67 outb_p(SIO_PM_FER2, SIO_PM_INDEX);
68 outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
71 * Now, initialize the GPIO registers.
72 * We want them all to be inputs which is the
73 * power on default, so let's leave them alone.
74 * So, let's just read the board rev!
76 raw = inb_p(SIO_GP_DATA1);
77 raw &= 0x7f; /* 7 bits of valid board revision ID. */
79 if (visws_board_type == VISWS_320) {
80 if (raw < 0x6) {
81 visws_board_rev = 4;
82 } else if (raw < 0xc) {
83 visws_board_rev = 5;
84 } else {
85 visws_board_rev = 6;
87 } else if (visws_board_type == VISWS_540) {
88 visws_board_rev = 2;
89 } else {
90 visws_board_rev = raw;
93 printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
94 (visws_board_type == VISWS_320 ? "320" :
95 (visws_board_type == VISWS_540 ? "540" :
96 "unknown")), visws_board_rev);
99 void __init pre_intr_init_hook(void)
101 init_VISWS_APIC_irqs();
104 void __init intr_init_hook(void)
106 #ifdef CONFIG_X86_LOCAL_APIC
107 apic_intr_init();
108 #endif
111 void __init pre_setup_arch_hook()
113 visws_get_board_type_and_rev();
116 static struct irqaction irq0 = {
117 .handler = timer_interrupt,
118 .flags = SA_INTERRUPT,
119 .name = "timer",
122 void __init time_init_hook(void)
124 printk(KERN_INFO "Starting Cobalt Timer system clock\n");
126 /* Set the countdown value */
127 co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
129 /* Start the timer */
130 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
132 /* Enable (unmask) the timer interrupt */
133 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
135 /* Wire cpu IDT entry to s/w handler (and Cobalt APIC to IDT) */
136 setup_irq(0, &irq0);
139 /* Hook for machine specific memory setup. */
141 #define MB (1024 * 1024)
143 static unsigned long sgivwfb_mem_phys;
144 static unsigned long sgivwfb_mem_size;
146 long long mem_size __initdata = 0;
148 char * __init machine_specific_memory_setup(void)
150 long long gfx_mem_size = 8 * MB;
152 mem_size = ALT_MEM_K;
154 if (!mem_size) {
155 printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
156 mem_size = 128 * MB;
160 * this hardcodes the graphics memory to 8 MB
161 * it really should be sized dynamically (or at least
162 * set as a boot param)
164 if (!sgivwfb_mem_size) {
165 printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
166 sgivwfb_mem_size = 8 * MB;
170 * Trim to nearest MB
172 sgivwfb_mem_size &= ~((1 << 20) - 1);
173 sgivwfb_mem_phys = mem_size - gfx_mem_size;
175 add_memory_region(0, LOWMEMSIZE(), E820_RAM);
176 add_memory_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
177 add_memory_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
179 return "PROM";
181 /* Remove gcc warnings */
182 (void) sanitize_e820_map(NULL, NULL);
183 (void) copy_e820_map(NULL, 0);