4 * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved
6 * Author: David Paris <david.paris@st.com> for STMicroelectronics
7 * Lee Jones <lee.jones@linaro.org> for STMicroelectronics
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public Licence
11 * as published by the Free Software Foundation; either version
12 * 2 of the Licence, or (at your option) any later version.
15 #include <linux/clk.h>
16 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
22 #include <linux/of_platform.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/watchdog.h>
27 #include <dt-bindings/mfd/st-lpc.h>
30 #define LPC_LPA_LSB_OFF 0x410
31 #define LPC_LPA_START_OFF 0x418
34 #define LPC_WDT_OFF 0x510
36 static struct watchdog_device st_wdog_dev
;
38 struct st_wdog_syscfg
{
39 unsigned int reset_type_reg
;
40 unsigned int reset_type_mask
;
41 unsigned int enable_reg
;
42 unsigned int enable_mask
;
48 struct regmap
*regmap
;
49 struct st_wdog_syscfg
*syscfg
;
51 unsigned long clkrate
;
55 static struct st_wdog_syscfg stid127_syscfg
= {
56 .reset_type_reg
= 0x004,
57 .reset_type_mask
= BIT(2),
59 .enable_mask
= BIT(2),
62 static struct st_wdog_syscfg stih415_syscfg
= {
63 .reset_type_reg
= 0x0B8,
64 .reset_type_mask
= BIT(6),
66 .enable_mask
= BIT(7),
69 static struct st_wdog_syscfg stih416_syscfg
= {
70 .reset_type_reg
= 0x88C,
71 .reset_type_mask
= BIT(6),
73 .enable_mask
= BIT(7),
76 static struct st_wdog_syscfg stih407_syscfg
= {
78 .enable_mask
= BIT(19),
81 static const struct of_device_id st_wdog_match
[] = {
83 .compatible
= "st,stih407-lpc",
84 .data
= &stih407_syscfg
,
87 .compatible
= "st,stih416-lpc",
88 .data
= &stih416_syscfg
,
91 .compatible
= "st,stih415-lpc",
92 .data
= &stih415_syscfg
,
95 .compatible
= "st,stid127-lpc",
96 .data
= &stid127_syscfg
,
100 MODULE_DEVICE_TABLE(of
, st_wdog_match
);
102 static void st_wdog_setup(struct st_wdog
*st_wdog
, bool enable
)
104 /* Type of watchdog reset - 0: Cold 1: Warm */
105 if (st_wdog
->syscfg
->reset_type_reg
)
106 regmap_update_bits(st_wdog
->regmap
,
107 st_wdog
->syscfg
->reset_type_reg
,
108 st_wdog
->syscfg
->reset_type_mask
,
109 st_wdog
->warm_reset
);
111 /* Mask/unmask watchdog reset */
112 regmap_update_bits(st_wdog
->regmap
,
113 st_wdog
->syscfg
->enable_reg
,
114 st_wdog
->syscfg
->enable_mask
,
115 enable
? 0 : st_wdog
->syscfg
->enable_mask
);
118 static void st_wdog_load_timer(struct st_wdog
*st_wdog
, unsigned int timeout
)
120 unsigned long clkrate
= st_wdog
->clkrate
;
122 writel_relaxed(timeout
* clkrate
, st_wdog
->base
+ LPC_LPA_LSB_OFF
);
123 writel_relaxed(1, st_wdog
->base
+ LPC_LPA_START_OFF
);
126 static int st_wdog_start(struct watchdog_device
*wdd
)
128 struct st_wdog
*st_wdog
= watchdog_get_drvdata(wdd
);
130 writel_relaxed(1, st_wdog
->base
+ LPC_WDT_OFF
);
135 static int st_wdog_stop(struct watchdog_device
*wdd
)
137 struct st_wdog
*st_wdog
= watchdog_get_drvdata(wdd
);
139 writel_relaxed(0, st_wdog
->base
+ LPC_WDT_OFF
);
144 static int st_wdog_set_timeout(struct watchdog_device
*wdd
,
145 unsigned int timeout
)
147 struct st_wdog
*st_wdog
= watchdog_get_drvdata(wdd
);
149 wdd
->timeout
= timeout
;
150 st_wdog_load_timer(st_wdog
, timeout
);
155 static int st_wdog_keepalive(struct watchdog_device
*wdd
)
157 struct st_wdog
*st_wdog
= watchdog_get_drvdata(wdd
);
159 st_wdog_load_timer(st_wdog
, wdd
->timeout
);
164 static const struct watchdog_info st_wdog_info
= {
165 .options
= WDIOF_SETTIMEOUT
| WDIOF_KEEPALIVEPING
| WDIOF_MAGICCLOSE
,
166 .identity
= "ST LPC WDT",
169 static const struct watchdog_ops st_wdog_ops
= {
170 .owner
= THIS_MODULE
,
171 .start
= st_wdog_start
,
172 .stop
= st_wdog_stop
,
173 .ping
= st_wdog_keepalive
,
174 .set_timeout
= st_wdog_set_timeout
,
177 static struct watchdog_device st_wdog_dev
= {
178 .info
= &st_wdog_info
,
182 static int st_wdog_probe(struct platform_device
*pdev
)
184 const struct of_device_id
*match
;
185 struct device_node
*np
= pdev
->dev
.of_node
;
186 struct st_wdog
*st_wdog
;
187 struct regmap
*regmap
;
188 struct resource
*res
;
194 ret
= of_property_read_u32(np
, "st,lpc-mode", &mode
);
196 dev_err(&pdev
->dev
, "An LPC mode must be provided\n");
200 /* LPC can either run as a Clocksource or in RTC or WDT mode */
201 if (mode
!= ST_LPC_MODE_WDT
)
204 st_wdog
= devm_kzalloc(&pdev
->dev
, sizeof(*st_wdog
), GFP_KERNEL
);
208 match
= of_match_device(st_wdog_match
, &pdev
->dev
);
210 dev_err(&pdev
->dev
, "Couldn't match device\n");
213 st_wdog
->syscfg
= (struct st_wdog_syscfg
*)match
->data
;
215 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
216 base
= devm_ioremap_resource(&pdev
->dev
, res
);
218 return PTR_ERR(base
);
220 regmap
= syscon_regmap_lookup_by_phandle(np
, "st,syscfg");
221 if (IS_ERR(regmap
)) {
222 dev_err(&pdev
->dev
, "No syscfg phandle specified\n");
223 return PTR_ERR(regmap
);
226 clk
= devm_clk_get(&pdev
->dev
, NULL
);
228 dev_err(&pdev
->dev
, "Unable to request clock\n");
232 st_wdog
->dev
= &pdev
->dev
;
233 st_wdog
->base
= base
;
235 st_wdog
->regmap
= regmap
;
236 st_wdog
->warm_reset
= of_property_read_bool(np
, "st,warm_reset");
237 st_wdog
->clkrate
= clk_get_rate(st_wdog
->clk
);
239 if (!st_wdog
->clkrate
) {
240 dev_err(&pdev
->dev
, "Unable to fetch clock rate\n");
243 st_wdog_dev
.max_timeout
= 0xFFFFFFFF / st_wdog
->clkrate
;
244 st_wdog_dev
.parent
= &pdev
->dev
;
246 ret
= clk_prepare_enable(clk
);
248 dev_err(&pdev
->dev
, "Unable to enable clock\n");
252 watchdog_set_drvdata(&st_wdog_dev
, st_wdog
);
253 watchdog_set_nowayout(&st_wdog_dev
, WATCHDOG_NOWAYOUT
);
255 /* Init Watchdog timeout with value in DT */
256 ret
= watchdog_init_timeout(&st_wdog_dev
, 0, &pdev
->dev
);
258 dev_err(&pdev
->dev
, "Unable to initialise watchdog timeout\n");
259 clk_disable_unprepare(clk
);
263 ret
= watchdog_register_device(&st_wdog_dev
);
265 dev_err(&pdev
->dev
, "Unable to register watchdog\n");
266 clk_disable_unprepare(clk
);
270 st_wdog_setup(st_wdog
, true);
272 dev_info(&pdev
->dev
, "LPC Watchdog driver registered, reset type is %s",
273 st_wdog
->warm_reset
? "warm" : "cold");
278 static int st_wdog_remove(struct platform_device
*pdev
)
280 struct st_wdog
*st_wdog
= watchdog_get_drvdata(&st_wdog_dev
);
282 st_wdog_setup(st_wdog
, false);
283 watchdog_unregister_device(&st_wdog_dev
);
284 clk_disable_unprepare(st_wdog
->clk
);
289 #ifdef CONFIG_PM_SLEEP
290 static int st_wdog_suspend(struct device
*dev
)
292 struct st_wdog
*st_wdog
= watchdog_get_drvdata(&st_wdog_dev
);
294 if (watchdog_active(&st_wdog_dev
))
295 st_wdog_stop(&st_wdog_dev
);
297 st_wdog_setup(st_wdog
, false);
299 clk_disable(st_wdog
->clk
);
304 static int st_wdog_resume(struct device
*dev
)
306 struct st_wdog
*st_wdog
= watchdog_get_drvdata(&st_wdog_dev
);
309 ret
= clk_enable(st_wdog
->clk
);
311 dev_err(dev
, "Unable to re-enable clock\n");
312 watchdog_unregister_device(&st_wdog_dev
);
313 clk_unprepare(st_wdog
->clk
);
317 st_wdog_setup(st_wdog
, true);
319 if (watchdog_active(&st_wdog_dev
)) {
320 st_wdog_load_timer(st_wdog
, st_wdog_dev
.timeout
);
321 st_wdog_start(&st_wdog_dev
);
328 static SIMPLE_DEV_PM_OPS(st_wdog_pm_ops
,
332 static struct platform_driver st_wdog_driver
= {
334 .name
= "st-lpc-wdt",
335 .pm
= &st_wdog_pm_ops
,
336 .of_match_table
= st_wdog_match
,
338 .probe
= st_wdog_probe
,
339 .remove
= st_wdog_remove
,
341 module_platform_driver(st_wdog_driver
);
343 MODULE_AUTHOR("David Paris <david.paris@st.com>");
344 MODULE_DESCRIPTION("ST LPC Watchdog Driver");
345 MODULE_LICENSE("GPL");