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LiteX: driver for MMCM
[linux/fpc-iii.git] / drivers / cpufreq / intel_pstate.c
blobbe05e038d956c75bd910d4651e9fb08faf5ffa90
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * intel_pstate.c: Native P state management for Intel processors
4 *
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/kernel.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/ktime.h>
15 #include <linux/hrtimer.h>
16 #include <linux/tick.h>
17 #include <linux/slab.h>
18 #include <linux/sched/cpufreq.h>
19 #include <linux/list.h>
20 #include <linux/cpu.h>
21 #include <linux/cpufreq.h>
22 #include <linux/sysfs.h>
23 #include <linux/types.h>
24 #include <linux/fs.h>
25 #include <linux/acpi.h>
26 #include <linux/vmalloc.h>
27 #include <linux/pm_qos.h>
28 #include <trace/events/power.h>
29
30 #include <asm/div64.h>
31 #include <asm/msr.h>
32 #include <asm/cpu_device_id.h>
33 #include <asm/cpufeature.h>
34 #include <asm/intel-family.h>
35
36 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
37
38 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
39 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
40 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
41
42 #ifdef CONFIG_ACPI
43 #include <acpi/processor.h>
44 #include <acpi/cppc_acpi.h>
45 #endif
46
47 #define FRAC_BITS 8
48 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
49 #define fp_toint(X) ((X) >> FRAC_BITS)
50
51 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
52
53 #define EXT_BITS 6
54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
55 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
56 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
57
58 static inline int32_t mul_fp(int32_t x, int32_t y)
59 {
60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
61 }
62
63 static inline int32_t div_fp(s64 x, s64 y)
64 {
65 return div64_s64((int64_t)x << FRAC_BITS, y);
66 }
67
68 static inline int ceiling_fp(int32_t x)
69 {
70 int mask, ret;
71
72 ret = fp_toint(x);
73 mask = (1 << FRAC_BITS) - 1;
74 if (x & mask)
75 ret += 1;
76 return ret;
77 }
78
79 static inline u64 mul_ext_fp(u64 x, u64 y)
80 {
81 return (x * y) >> EXT_FRAC_BITS;
82 }
83
84 static inline u64 div_ext_fp(u64 x, u64 y)
85 {
86 return div64_u64(x << EXT_FRAC_BITS, y);
87 }
88
89 /**
90 * struct sample - Store performance sample
91 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
92 * performance during last sample period
93 * @busy_scaled: Scaled busy value which is used to calculate next
94 * P state. This can be different than core_avg_perf
95 * to account for cpu idle period
96 * @aperf: Difference of actual performance frequency clock count
97 * read from APERF MSR between last and current sample
98 * @mperf: Difference of maximum performance frequency clock count
99 * read from MPERF MSR between last and current sample
100 * @tsc: Difference of time stamp counter between last and
101 * current sample
102 * @time: Current time from scheduler
103 *
104 * This structure is used in the cpudata structure to store performance sample
105 * data for choosing next P State.
106 */
107 struct sample {
108 int32_t core_avg_perf;
109 int32_t busy_scaled;
110 u64 aperf;
111 u64 mperf;
112 u64 tsc;
113 u64 time;
114 };
115
116 /**
117 * struct pstate_data - Store P state data
118 * @current_pstate: Current requested P state
119 * @min_pstate: Min P state possible for this platform
120 * @max_pstate: Max P state possible for this platform
121 * @max_pstate_physical:This is physical Max P state for a processor
122 * This can be higher than the max_pstate which can
123 * be limited by platform thermal design power limits
124 * @scaling: Scaling factor to convert frequency to cpufreq
125 * frequency units
126 * @turbo_pstate: Max Turbo P state possible for this platform
127 * @max_freq: @max_pstate frequency in cpufreq units
128 * @turbo_freq: @turbo_pstate frequency in cpufreq units
129 *
130 * Stores the per cpu model P state limits and current P state.
131 */
132 struct pstate_data {
133 int current_pstate;
134 int min_pstate;
135 int max_pstate;
136 int max_pstate_physical;
137 int scaling;
138 int turbo_pstate;
139 unsigned int max_freq;
140 unsigned int turbo_freq;
141 };
142
143 /**
144 * struct vid_data - Stores voltage information data
145 * @min: VID data for this platform corresponding to
146 * the lowest P state
147 * @max: VID data corresponding to the highest P State.
148 * @turbo: VID data for turbo P state
149 * @ratio: Ratio of (vid max - vid min) /
150 * (max P state - Min P State)
151 *
152 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
153 * This data is used in Atom platforms, where in addition to target P state,
154 * the voltage data needs to be specified to select next P State.
155 */
156 struct vid_data {
157 int min;
158 int max;
159 int turbo;
160 int32_t ratio;
161 };
162
163 /**
164 * struct global_params - Global parameters, mostly tunable via sysfs.
165 * @no_turbo: Whether or not to use turbo P-states.
166 * @turbo_disabled: Whether or not turbo P-states are available at all,
167 * based on the MSR_IA32_MISC_ENABLE value and whether or
168 * not the maximum reported turbo P-state is different from
169 * the maximum reported non-turbo one.
170 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
171 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
172 * P-state capacity.
173 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
174 * P-state capacity.
175 */
176 struct global_params {
177 bool no_turbo;
178 bool turbo_disabled;
179 bool turbo_disabled_mf;
180 int max_perf_pct;
181 int min_perf_pct;
182 };
183
184 /**
185 * struct cpudata - Per CPU instance data storage
186 * @cpu: CPU number for this instance data
187 * @policy: CPUFreq policy value
188 * @update_util: CPUFreq utility callback information
189 * @update_util_set: CPUFreq utility callback is set
190 * @iowait_boost: iowait-related boost fraction
191 * @last_update: Time of the last update.
192 * @pstate: Stores P state limits for this CPU
193 * @vid: Stores VID limits for this CPU
194 * @last_sample_time: Last Sample time
195 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
196 * @prev_aperf: Last APERF value read from APERF MSR
197 * @prev_mperf: Last MPERF value read from MPERF MSR
198 * @prev_tsc: Last timestamp counter (TSC) value
199 * @prev_cummulative_iowait: IO Wait time difference from last and
200 * current sample
201 * @sample: Storage for storing last Sample data
202 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
203 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
204 * @acpi_perf_data: Stores ACPI perf information read from _PSS
205 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
206 * @epp_powersave: Last saved HWP energy performance preference
207 * (EPP) or energy performance bias (EPB),
208 * when policy switched to performance
209 * @epp_policy: Last saved policy used to set EPP/EPB
210 * @epp_default: Power on default HWP energy performance
211 * preference/bias
212 * @epp_cached Cached HWP energy-performance preference value
213 * @hwp_req_cached: Cached value of the last HWP Request MSR
214 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
215 * @last_io_update: Last time when IO wake flag was set
216 * @sched_flags: Store scheduler flags for possible cross CPU update
217 * @hwp_boost_min: Last HWP boosted min performance
218 * @suspended: Whether or not the driver has been suspended.
219 *
220 * This structure stores per CPU instance data for all CPUs.
221 */
222 struct cpudata {
223 int cpu;
224
225 unsigned int policy;
226 struct update_util_data update_util;
227 bool update_util_set;
228
229 struct pstate_data pstate;
230 struct vid_data vid;
231
232 u64 last_update;
233 u64 last_sample_time;
234 u64 aperf_mperf_shift;
235 u64 prev_aperf;
236 u64 prev_mperf;
237 u64 prev_tsc;
238 u64 prev_cummulative_iowait;
239 struct sample sample;
240 int32_t min_perf_ratio;
241 int32_t max_perf_ratio;
242 #ifdef CONFIG_ACPI
243 struct acpi_processor_performance acpi_perf_data;
244 bool valid_pss_table;
245 #endif
246 unsigned int iowait_boost;
247 s16 epp_powersave;
248 s16 epp_policy;
249 s16 epp_default;
250 s16 epp_cached;
251 u64 hwp_req_cached;
252 u64 hwp_cap_cached;
253 u64 last_io_update;
254 unsigned int sched_flags;
255 u32 hwp_boost_min;
256 bool suspended;
257 };
258
259 static struct cpudata **all_cpu_data;
260
261 /**
262 * struct pstate_funcs - Per CPU model specific callbacks
263 * @get_max: Callback to get maximum non turbo effective P state
264 * @get_max_physical: Callback to get maximum non turbo physical P state
265 * @get_min: Callback to get minimum P state
266 * @get_turbo: Callback to get turbo P state
267 * @get_scaling: Callback to get frequency scaling factor
268 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
269 * @get_val: Callback to convert P state to actual MSR write value
270 * @get_vid: Callback to get VID data for Atom platforms
271 *
272 * Core and Atom CPU models have different way to get P State limits. This
273 * structure is used to store those callbacks.
274 */
275 struct pstate_funcs {
276 int (*get_max)(void);
277 int (*get_max_physical)(void);
278 int (*get_min)(void);
279 int (*get_turbo)(void);
280 int (*get_scaling)(void);
281 int (*get_aperf_mperf_shift)(void);
282 u64 (*get_val)(struct cpudata*, int pstate);
283 void (*get_vid)(struct cpudata *);
284 };
285
286 static struct pstate_funcs pstate_funcs __read_mostly;
287
288 static int hwp_active __read_mostly;
289 static int hwp_mode_bdw __read_mostly;
290 static bool per_cpu_limits __read_mostly;
291 static bool hwp_boost __read_mostly;
292
293 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
294
295 #ifdef CONFIG_ACPI
296 static bool acpi_ppc;
297 #endif
298
299 static struct global_params global;
300
301 static DEFINE_MUTEX(intel_pstate_driver_lock);
302 static DEFINE_MUTEX(intel_pstate_limits_lock);
303
304 #ifdef CONFIG_ACPI
305
306 static bool intel_pstate_acpi_pm_profile_server(void)
307 {
308 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
309 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
310 return true;
311
312 return false;
313 }
314
315 static bool intel_pstate_get_ppc_enable_status(void)
316 {
317 if (intel_pstate_acpi_pm_profile_server())
318 return true;
319
320 return acpi_ppc;
321 }
322
323 #ifdef CONFIG_ACPI_CPPC_LIB
324
325 /* The work item is needed to avoid CPU hotplug locking issues */
326 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
327 {
328 sched_set_itmt_support();
329 }
330
331 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
332
333 static void intel_pstate_set_itmt_prio(int cpu)
334 {
335 struct cppc_perf_caps cppc_perf;
336 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
337 int ret;
338
339 ret = cppc_get_perf_caps(cpu, &cppc_perf);
340 if (ret)
341 return;
342
343 /*
344 * The priorities can be set regardless of whether or not
345 * sched_set_itmt_support(true) has been called and it is valid to
346 * update them at any time after it has been called.
347 */
348 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
349
350 if (max_highest_perf <= min_highest_perf) {
351 if (cppc_perf.highest_perf > max_highest_perf)
352 max_highest_perf = cppc_perf.highest_perf;
353
354 if (cppc_perf.highest_perf < min_highest_perf)
355 min_highest_perf = cppc_perf.highest_perf;
356
357 if (max_highest_perf > min_highest_perf) {
358 /*
359 * This code can be run during CPU online under the
360 * CPU hotplug locks, so sched_set_itmt_support()
361 * cannot be called from here. Queue up a work item
362 * to invoke it.
363 */
364 schedule_work(&sched_itmt_work);
365 }
366 }
367 }
368
369 static int intel_pstate_get_cppc_guranteed(int cpu)
370 {
371 struct cppc_perf_caps cppc_perf;
372 int ret;
373
374 ret = cppc_get_perf_caps(cpu, &cppc_perf);
375 if (ret)
376 return ret;
377
378 if (cppc_perf.guaranteed_perf)
379 return cppc_perf.guaranteed_perf;
380
381 return cppc_perf.nominal_perf;
382 }
383
384 #else /* CONFIG_ACPI_CPPC_LIB */
385 static void intel_pstate_set_itmt_prio(int cpu)
386 {
387 }
388 #endif /* CONFIG_ACPI_CPPC_LIB */
389
390 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
391 {
392 struct cpudata *cpu;
393 int ret;
394 int i;
395
396 if (hwp_active) {
397 intel_pstate_set_itmt_prio(policy->cpu);
398 return;
399 }
400
401 if (!intel_pstate_get_ppc_enable_status())
402 return;
403
404 cpu = all_cpu_data[policy->cpu];
405
406 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
407 policy->cpu);
408 if (ret)
409 return;
410
411 /*
412 * Check if the control value in _PSS is for PERF_CTL MSR, which should
413 * guarantee that the states returned by it map to the states in our
414 * list directly.
415 */
416 if (cpu->acpi_perf_data.control_register.space_id !=
417 ACPI_ADR_SPACE_FIXED_HARDWARE)
418 goto err;
419
420 /*
421 * If there is only one entry _PSS, simply ignore _PSS and continue as
422 * usual without taking _PSS into account
423 */
424 if (cpu->acpi_perf_data.state_count < 2)
425 goto err;
426
427 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
428 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
429 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
430 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
431 (u32) cpu->acpi_perf_data.states[i].core_frequency,
432 (u32) cpu->acpi_perf_data.states[i].power,
433 (u32) cpu->acpi_perf_data.states[i].control);
434 }
435
436 /*
437 * The _PSS table doesn't contain whole turbo frequency range.
438 * This just contains +1 MHZ above the max non turbo frequency,
439 * with control value corresponding to max turbo ratio. But
440 * when cpufreq set policy is called, it will call with this
441 * max frequency, which will cause a reduced performance as
442 * this driver uses real max turbo frequency as the max
443 * frequency. So correct this frequency in _PSS table to
444 * correct max turbo frequency based on the turbo state.
445 * Also need to convert to MHz as _PSS freq is in MHz.
446 */
447 if (!global.turbo_disabled)
448 cpu->acpi_perf_data.states[0].core_frequency =
449 policy->cpuinfo.max_freq / 1000;
450 cpu->valid_pss_table = true;
451 pr_debug("_PPC limits will be enforced\n");
452
453 return;
454
455 err:
456 cpu->valid_pss_table = false;
457 acpi_processor_unregister_performance(policy->cpu);
458 }
459
460 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
461 {
462 struct cpudata *cpu;
463
464 cpu = all_cpu_data[policy->cpu];
465 if (!cpu->valid_pss_table)
466 return;
467
468 acpi_processor_unregister_performance(policy->cpu);
469 }
470 #else /* CONFIG_ACPI */
471 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
472 {
473 }
474
475 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
476 {
477 }
478
479 static inline bool intel_pstate_acpi_pm_profile_server(void)
480 {
481 return false;
482 }
483 #endif /* CONFIG_ACPI */
484
485 #ifndef CONFIG_ACPI_CPPC_LIB
486 static int intel_pstate_get_cppc_guranteed(int cpu)
487 {
488 return -ENOTSUPP;
489 }
490 #endif /* CONFIG_ACPI_CPPC_LIB */
491
492 static inline void update_turbo_state(void)
493 {
494 u64 misc_en;
495 struct cpudata *cpu;
496
497 cpu = all_cpu_data[0];
498 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
499 global.turbo_disabled =
500 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
501 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
502 }
503
504 static int min_perf_pct_min(void)
505 {
506 struct cpudata *cpu = all_cpu_data[0];
507 int turbo_pstate = cpu->pstate.turbo_pstate;
508
509 return turbo_pstate ?
510 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
511 }
512
513 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
514 {
515 u64 epb;
516 int ret;
517
518 if (!boot_cpu_has(X86_FEATURE_EPB))
519 return -ENXIO;
520
521 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
522 if (ret)
523 return (s16)ret;
524
525 return (s16)(epb & 0x0f);
526 }
527
528 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
529 {
530 s16 epp;
531
532 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
533 /*
534 * When hwp_req_data is 0, means that caller didn't read
535 * MSR_HWP_REQUEST, so need to read and get EPP.
536 */
537 if (!hwp_req_data) {
538 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
539 &hwp_req_data);
540 if (epp)
541 return epp;
542 }
543 epp = (hwp_req_data >> 24) & 0xff;
544 } else {
545 /* When there is no EPP present, HWP uses EPB settings */
546 epp = intel_pstate_get_epb(cpu_data);
547 }
548
549 return epp;
550 }
551
552 static int intel_pstate_set_epb(int cpu, s16 pref)
553 {
554 u64 epb;
555 int ret;
556
557 if (!boot_cpu_has(X86_FEATURE_EPB))
558 return -ENXIO;
559
560 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
561 if (ret)
562 return ret;
563
564 epb = (epb & ~0x0f) | pref;
565 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
566
567 return 0;
568 }
569
570 /*
571 * EPP/EPB display strings corresponding to EPP index in the
572 * energy_perf_strings[]
573 * index String
574 *-------------------------------------
575 * 0 default
576 * 1 performance
577 * 2 balance_performance
578 * 3 balance_power
579 * 4 power
580 */
581 static const char * const energy_perf_strings[] = {
582 "default",
583 "performance",
584 "balance_performance",
585 "balance_power",
586 "power",
587 NULL
588 };
589 static const unsigned int epp_values[] = {
590 HWP_EPP_PERFORMANCE,
591 HWP_EPP_BALANCE_PERFORMANCE,
592 HWP_EPP_BALANCE_POWERSAVE,
593 HWP_EPP_POWERSAVE
594 };
595
596 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
597 {
598 s16 epp;
599 int index = -EINVAL;
600
601 *raw_epp = 0;
602 epp = intel_pstate_get_epp(cpu_data, 0);
603 if (epp < 0)
604 return epp;
605
606 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
607 if (epp == HWP_EPP_PERFORMANCE)
608 return 1;
609 if (epp == HWP_EPP_BALANCE_PERFORMANCE)
610 return 2;
611 if (epp == HWP_EPP_BALANCE_POWERSAVE)
612 return 3;
613 if (epp == HWP_EPP_POWERSAVE)
614 return 4;
615 *raw_epp = epp;
616 return 0;
617 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
618 /*
619 * Range:
620 * 0x00-0x03 : Performance
621 * 0x04-0x07 : Balance performance
622 * 0x08-0x0B : Balance power
623 * 0x0C-0x0F : Power
624 * The EPB is a 4 bit value, but our ranges restrict the
625 * value which can be set. Here only using top two bits
626 * effectively.
627 */
628 index = (epp >> 2) + 1;
629 }
630
631 return index;
632 }
633
634 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
635 {
636 int ret;
637
638 /*
639 * Use the cached HWP Request MSR value, because in the active mode the
640 * register itself may be updated by intel_pstate_hwp_boost_up() or
641 * intel_pstate_hwp_boost_down() at any time.
642 */
643 u64 value = READ_ONCE(cpu->hwp_req_cached);
644
645 value &= ~GENMASK_ULL(31, 24);
646 value |= (u64)epp << 24;
647 /*
648 * The only other updater of hwp_req_cached in the active mode,
649 * intel_pstate_hwp_set(), is called under the same lock as this
650 * function, so it cannot run in parallel with the update below.
651 */
652 WRITE_ONCE(cpu->hwp_req_cached, value);
653 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
654 if (!ret)
655 cpu->epp_cached = epp;
656
657 return ret;
658 }
659
660 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
661 int pref_index, bool use_raw,
662 u32 raw_epp)
663 {
664 int epp = -EINVAL;
665 int ret;
666
667 if (!pref_index)
668 epp = cpu_data->epp_default;
669
670 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
671 if (use_raw)
672 epp = raw_epp;
673 else if (epp == -EINVAL)
674 epp = epp_values[pref_index - 1];
675
676 /*
677 * To avoid confusion, refuse to set EPP to any values different
678 * from 0 (performance) if the current policy is "performance",
679 * because those values would be overridden.
680 */
681 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
682 return -EBUSY;
683
684 ret = intel_pstate_set_epp(cpu_data, epp);
685 } else {
686 if (epp == -EINVAL)
687 epp = (pref_index - 1) << 2;
688 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
689 }
690
691 return ret;
692 }
693
694 static ssize_t show_energy_performance_available_preferences(
695 struct cpufreq_policy *policy, char *buf)
696 {
697 int i = 0;
698 int ret = 0;
699
700 while (energy_perf_strings[i] != NULL)
701 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
702
703 ret += sprintf(&buf[ret], "\n");
704
705 return ret;
706 }
707
708 cpufreq_freq_attr_ro(energy_performance_available_preferences);
709
710 static struct cpufreq_driver intel_pstate;
711
712 static ssize_t store_energy_performance_preference(
713 struct cpufreq_policy *policy, const char *buf, size_t count)
714 {
715 struct cpudata *cpu = all_cpu_data[policy->cpu];
716 char str_preference[21];
717 bool raw = false;
718 ssize_t ret;
719 u32 epp = 0;
720
721 ret = sscanf(buf, "%20s", str_preference);
722 if (ret != 1)
723 return -EINVAL;
724
725 ret = match_string(energy_perf_strings, -1, str_preference);
726 if (ret < 0) {
727 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
728 return ret;
729
730 ret = kstrtouint(buf, 10, &epp);
731 if (ret)
732 return ret;
733
734 if (epp > 255)
735 return -EINVAL;
736
737 raw = true;
738 }
739
740 /*
741 * This function runs with the policy R/W semaphore held, which
742 * guarantees that the driver pointer will not change while it is
743 * running.
744 */
745 if (!intel_pstate_driver)
746 return -EAGAIN;
747
748 mutex_lock(&intel_pstate_limits_lock);
749
750 if (intel_pstate_driver == &intel_pstate) {
751 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
752 } else {
753 /*
754 * In the passive mode the governor needs to be stopped on the
755 * target CPU before the EPP update and restarted after it,
756 * which is super-heavy-weight, so make sure it is worth doing
757 * upfront.
758 */
759 if (!raw)
760 epp = ret ? epp_values[ret - 1] : cpu->epp_default;
761
762 if (cpu->epp_cached != epp) {
763 int err;
764
765 cpufreq_stop_governor(policy);
766 ret = intel_pstate_set_epp(cpu, epp);
767 err = cpufreq_start_governor(policy);
768 if (!ret)
769 ret = err;
770 }
771 }
772
773 mutex_unlock(&intel_pstate_limits_lock);
774
775 return ret ?: count;
776 }
777
778 static ssize_t show_energy_performance_preference(
779 struct cpufreq_policy *policy, char *buf)
780 {
781 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
782 int preference, raw_epp;
783
784 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
785 if (preference < 0)
786 return preference;
787
788 if (raw_epp)
789 return sprintf(buf, "%d\n", raw_epp);
790 else
791 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
792 }
793
794 cpufreq_freq_attr_rw(energy_performance_preference);
795
796 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
797 {
798 struct cpudata *cpu;
799 u64 cap;
800 int ratio;
801
802 ratio = intel_pstate_get_cppc_guranteed(policy->cpu);
803 if (ratio <= 0) {
804 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
805 ratio = HWP_GUARANTEED_PERF(cap);
806 }
807
808 cpu = all_cpu_data[policy->cpu];
809
810 return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling);
811 }
812
813 cpufreq_freq_attr_ro(base_frequency);
814
815 static struct freq_attr *hwp_cpufreq_attrs[] = {
816 &energy_performance_preference,
817 &energy_performance_available_preferences,
818 &base_frequency,
819 NULL,
820 };
821
822 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
823 int *current_max)
824 {
825 u64 cap;
826
827 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
828 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
829 if (global.no_turbo || global.turbo_disabled)
830 *current_max = HWP_GUARANTEED_PERF(cap);
831 else
832 *current_max = HWP_HIGHEST_PERF(cap);
833
834 *phy_max = HWP_HIGHEST_PERF(cap);
835 }
836
837 static void intel_pstate_hwp_set(unsigned int cpu)
838 {
839 struct cpudata *cpu_data = all_cpu_data[cpu];
840 int max, min;
841 u64 value;
842 s16 epp;
843
844 max = cpu_data->max_perf_ratio;
845 min = cpu_data->min_perf_ratio;
846
847 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
848 min = max;
849
850 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
851
852 value &= ~HWP_MIN_PERF(~0L);
853 value |= HWP_MIN_PERF(min);
854
855 value &= ~HWP_MAX_PERF(~0L);
856 value |= HWP_MAX_PERF(max);
857
858 if (cpu_data->epp_policy == cpu_data->policy)
859 goto skip_epp;
860
861 cpu_data->epp_policy = cpu_data->policy;
862
863 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
864 epp = intel_pstate_get_epp(cpu_data, value);
865 cpu_data->epp_powersave = epp;
866 /* If EPP read was failed, then don't try to write */
867 if (epp < 0)
868 goto skip_epp;
869
870 epp = 0;
871 } else {
872 /* skip setting EPP, when saved value is invalid */
873 if (cpu_data->epp_powersave < 0)
874 goto skip_epp;
875
876 /*
877 * No need to restore EPP when it is not zero. This
878 * means:
879 * - Policy is not changed
880 * - user has manually changed
881 * - Error reading EPB
882 */
883 epp = intel_pstate_get_epp(cpu_data, value);
884 if (epp)
885 goto skip_epp;
886
887 epp = cpu_data->epp_powersave;
888 }
889 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
890 value &= ~GENMASK_ULL(31, 24);
891 value |= (u64)epp << 24;
892 } else {
893 intel_pstate_set_epb(cpu, epp);
894 }
895 skip_epp:
896 WRITE_ONCE(cpu_data->hwp_req_cached, value);
897 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
898 }
899
900 static void intel_pstate_hwp_offline(struct cpudata *cpu)
901 {
902 u64 value = READ_ONCE(cpu->hwp_req_cached);
903 int min_perf;
904
905 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
906 /*
907 * In case the EPP has been set to "performance" by the
908 * active mode "performance" scaling algorithm, replace that
909 * temporary value with the cached EPP one.
910 */
911 value &= ~GENMASK_ULL(31, 24);
912 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
913 WRITE_ONCE(cpu->hwp_req_cached, value);
914 }
915
916 value &= ~GENMASK_ULL(31, 0);
917 min_perf = HWP_LOWEST_PERF(cpu->hwp_cap_cached);
918
919 /* Set hwp_max = hwp_min */
920 value |= HWP_MAX_PERF(min_perf);
921 value |= HWP_MIN_PERF(min_perf);
922
923 /* Set EPP to min */
924 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
925 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
926
927 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
928 }
929
930 #define POWER_CTL_EE_ENABLE 1
931 #define POWER_CTL_EE_DISABLE 2
932
933 static int power_ctl_ee_state;
934
935 static void set_power_ctl_ee_state(bool input)
936 {
937 u64 power_ctl;
938
939 mutex_lock(&intel_pstate_driver_lock);
940 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
941 if (input) {
942 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
943 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
944 } else {
945 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
946 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
947 }
948 wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
949 mutex_unlock(&intel_pstate_driver_lock);
950 }
951
952 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
953
954 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
955 {
956 intel_pstate_hwp_enable(cpu);
957 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
958 }
959
960 static int intel_pstate_suspend(struct cpufreq_policy *policy)
961 {
962 struct cpudata *cpu = all_cpu_data[policy->cpu];
963
964 pr_debug("CPU %d suspending\n", cpu->cpu);
965
966 cpu->suspended = true;
967
968 return 0;
969 }
970
971 static int intel_pstate_resume(struct cpufreq_policy *policy)
972 {
973 struct cpudata *cpu = all_cpu_data[policy->cpu];
974
975 pr_debug("CPU %d resuming\n", cpu->cpu);
976
977 /* Only restore if the system default is changed */
978 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
979 set_power_ctl_ee_state(true);
980 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
981 set_power_ctl_ee_state(false);
982
983 if (cpu->suspended && hwp_active) {
984 mutex_lock(&intel_pstate_limits_lock);
985
986 /* Re-enable HWP, because "online" has not done that. */
987 intel_pstate_hwp_reenable(cpu);
988
989 mutex_unlock(&intel_pstate_limits_lock);
990 }
991
992 cpu->suspended = false;
993
994 return 0;
995 }
996
997 static void intel_pstate_update_policies(void)
998 {
999 int cpu;
1000
1001 for_each_possible_cpu(cpu)
1002 cpufreq_update_policy(cpu);
1003 }
1004
1005 static void intel_pstate_update_max_freq(unsigned int cpu)
1006 {
1007 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1008 struct cpudata *cpudata;
1009
1010 if (!policy)
1011 return;
1012
1013 cpudata = all_cpu_data[cpu];
1014 policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1015 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1016
1017 refresh_frequency_limits(policy);
1018
1019 cpufreq_cpu_release(policy);
1020 }
1021
1022 static void intel_pstate_update_limits(unsigned int cpu)
1023 {
1024 mutex_lock(&intel_pstate_driver_lock);
1025
1026 update_turbo_state();
1027 /*
1028 * If turbo has been turned on or off globally, policy limits for
1029 * all CPUs need to be updated to reflect that.
1030 */
1031 if (global.turbo_disabled_mf != global.turbo_disabled) {
1032 global.turbo_disabled_mf = global.turbo_disabled;
1033 arch_set_max_freq_ratio(global.turbo_disabled);
1034 for_each_possible_cpu(cpu)
1035 intel_pstate_update_max_freq(cpu);
1036 } else {
1037 cpufreq_update_policy(cpu);
1038 }
1039
1040 mutex_unlock(&intel_pstate_driver_lock);
1041 }
1042
1043 /************************** sysfs begin ************************/
1044 #define show_one(file_name, object) \
1045 static ssize_t show_##file_name \
1046 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1047 { \
1048 return sprintf(buf, "%u\n", global.object); \
1049 }
1050
1051 static ssize_t intel_pstate_show_status(char *buf);
1052 static int intel_pstate_update_status(const char *buf, size_t size);
1053
1054 static ssize_t show_status(struct kobject *kobj,
1055 struct kobj_attribute *attr, char *buf)
1056 {
1057 ssize_t ret;
1058
1059 mutex_lock(&intel_pstate_driver_lock);
1060 ret = intel_pstate_show_status(buf);
1061 mutex_unlock(&intel_pstate_driver_lock);
1062
1063 return ret;
1064 }
1065
1066 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1067 const char *buf, size_t count)
1068 {
1069 char *p = memchr(buf, '\n', count);
1070 int ret;
1071
1072 mutex_lock(&intel_pstate_driver_lock);
1073 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1074 mutex_unlock(&intel_pstate_driver_lock);
1075
1076 return ret < 0 ? ret : count;
1077 }
1078
1079 static ssize_t show_turbo_pct(struct kobject *kobj,
1080 struct kobj_attribute *attr, char *buf)
1081 {
1082 struct cpudata *cpu;
1083 int total, no_turbo, turbo_pct;
1084 uint32_t turbo_fp;
1085
1086 mutex_lock(&intel_pstate_driver_lock);
1087
1088 if (!intel_pstate_driver) {
1089 mutex_unlock(&intel_pstate_driver_lock);
1090 return -EAGAIN;
1091 }
1092
1093 cpu = all_cpu_data[0];
1094
1095 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1096 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1097 turbo_fp = div_fp(no_turbo, total);
1098 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1099
1100 mutex_unlock(&intel_pstate_driver_lock);
1101
1102 return sprintf(buf, "%u\n", turbo_pct);
1103 }
1104
1105 static ssize_t show_num_pstates(struct kobject *kobj,
1106 struct kobj_attribute *attr, char *buf)
1107 {
1108 struct cpudata *cpu;
1109 int total;
1110
1111 mutex_lock(&intel_pstate_driver_lock);
1112
1113 if (!intel_pstate_driver) {
1114 mutex_unlock(&intel_pstate_driver_lock);
1115 return -EAGAIN;
1116 }
1117
1118 cpu = all_cpu_data[0];
1119 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1120
1121 mutex_unlock(&intel_pstate_driver_lock);
1122
1123 return sprintf(buf, "%u\n", total);
1124 }
1125
1126 static ssize_t show_no_turbo(struct kobject *kobj,
1127 struct kobj_attribute *attr, char *buf)
1128 {
1129 ssize_t ret;
1130
1131 mutex_lock(&intel_pstate_driver_lock);
1132
1133 if (!intel_pstate_driver) {
1134 mutex_unlock(&intel_pstate_driver_lock);
1135 return -EAGAIN;
1136 }
1137
1138 update_turbo_state();
1139 if (global.turbo_disabled)
1140 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1141 else
1142 ret = sprintf(buf, "%u\n", global.no_turbo);
1143
1144 mutex_unlock(&intel_pstate_driver_lock);
1145
1146 return ret;
1147 }
1148
1149 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1150 const char *buf, size_t count)
1151 {
1152 unsigned int input;
1153 int ret;
1154
1155 ret = sscanf(buf, "%u", &input);
1156 if (ret != 1)
1157 return -EINVAL;
1158
1159 mutex_lock(&intel_pstate_driver_lock);
1160
1161 if (!intel_pstate_driver) {
1162 mutex_unlock(&intel_pstate_driver_lock);
1163 return -EAGAIN;
1164 }
1165
1166 mutex_lock(&intel_pstate_limits_lock);
1167
1168 update_turbo_state();
1169 if (global.turbo_disabled) {
1170 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1171 mutex_unlock(&intel_pstate_limits_lock);
1172 mutex_unlock(&intel_pstate_driver_lock);
1173 return -EPERM;
1174 }
1175
1176 global.no_turbo = clamp_t(int, input, 0, 1);
1177
1178 if (global.no_turbo) {
1179 struct cpudata *cpu = all_cpu_data[0];
1180 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1181
1182 /* Squash the global minimum into the permitted range. */
1183 if (global.min_perf_pct > pct)
1184 global.min_perf_pct = pct;
1185 }
1186
1187 mutex_unlock(&intel_pstate_limits_lock);
1188
1189 intel_pstate_update_policies();
1190
1191 mutex_unlock(&intel_pstate_driver_lock);
1192
1193 return count;
1194 }
1195
1196 static void update_qos_request(enum freq_qos_req_type type)
1197 {
1198 int max_state, turbo_max, freq, i, perf_pct;
1199 struct freq_qos_request *req;
1200 struct cpufreq_policy *policy;
1201
1202 for_each_possible_cpu(i) {
1203 struct cpudata *cpu = all_cpu_data[i];
1204
1205 policy = cpufreq_cpu_get(i);
1206 if (!policy)
1207 continue;
1208
1209 req = policy->driver_data;
1210 cpufreq_cpu_put(policy);
1211
1212 if (!req)
1213 continue;
1214
1215 if (hwp_active)
1216 intel_pstate_get_hwp_max(i, &turbo_max, &max_state);
1217 else
1218 turbo_max = cpu->pstate.turbo_pstate;
1219
1220 if (type == FREQ_QOS_MIN) {
1221 perf_pct = global.min_perf_pct;
1222 } else {
1223 req++;
1224 perf_pct = global.max_perf_pct;
1225 }
1226
1227 freq = DIV_ROUND_UP(turbo_max * perf_pct, 100);
1228 freq *= cpu->pstate.scaling;
1229
1230 if (freq_qos_update_request(req, freq) < 0)
1231 pr_warn("Failed to update freq constraint: CPU%d\n", i);
1232 }
1233 }
1234
1235 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1236 const char *buf, size_t count)
1237 {
1238 unsigned int input;
1239 int ret;
1240
1241 ret = sscanf(buf, "%u", &input);
1242 if (ret != 1)
1243 return -EINVAL;
1244
1245 mutex_lock(&intel_pstate_driver_lock);
1246
1247 if (!intel_pstate_driver) {
1248 mutex_unlock(&intel_pstate_driver_lock);
1249 return -EAGAIN;
1250 }
1251
1252 mutex_lock(&intel_pstate_limits_lock);
1253
1254 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1255
1256 mutex_unlock(&intel_pstate_limits_lock);
1257
1258 if (intel_pstate_driver == &intel_pstate)
1259 intel_pstate_update_policies();
1260 else
1261 update_qos_request(FREQ_QOS_MAX);
1262
1263 mutex_unlock(&intel_pstate_driver_lock);
1264
1265 return count;
1266 }
1267
1268 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1269 const char *buf, size_t count)
1270 {
1271 unsigned int input;
1272 int ret;
1273
1274 ret = sscanf(buf, "%u", &input);
1275 if (ret != 1)
1276 return -EINVAL;
1277
1278 mutex_lock(&intel_pstate_driver_lock);
1279
1280 if (!intel_pstate_driver) {
1281 mutex_unlock(&intel_pstate_driver_lock);
1282 return -EAGAIN;
1283 }
1284
1285 mutex_lock(&intel_pstate_limits_lock);
1286
1287 global.min_perf_pct = clamp_t(int, input,
1288 min_perf_pct_min(), global.max_perf_pct);
1289
1290 mutex_unlock(&intel_pstate_limits_lock);
1291
1292 if (intel_pstate_driver == &intel_pstate)
1293 intel_pstate_update_policies();
1294 else
1295 update_qos_request(FREQ_QOS_MIN);
1296
1297 mutex_unlock(&intel_pstate_driver_lock);
1298
1299 return count;
1300 }
1301
1302 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1303 struct kobj_attribute *attr, char *buf)
1304 {
1305 return sprintf(buf, "%u\n", hwp_boost);
1306 }
1307
1308 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1309 struct kobj_attribute *b,
1310 const char *buf, size_t count)
1311 {
1312 unsigned int input;
1313 int ret;
1314
1315 ret = kstrtouint(buf, 10, &input);
1316 if (ret)
1317 return ret;
1318
1319 mutex_lock(&intel_pstate_driver_lock);
1320 hwp_boost = !!input;
1321 intel_pstate_update_policies();
1322 mutex_unlock(&intel_pstate_driver_lock);
1323
1324 return count;
1325 }
1326
1327 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1328 char *buf)
1329 {
1330 u64 power_ctl;
1331 int enable;
1332
1333 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1334 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1335 return sprintf(buf, "%d\n", !enable);
1336 }
1337
1338 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1339 const char *buf, size_t count)
1340 {
1341 bool input;
1342 int ret;
1343
1344 ret = kstrtobool(buf, &input);
1345 if (ret)
1346 return ret;
1347
1348 set_power_ctl_ee_state(input);
1349
1350 return count;
1351 }
1352
1353 show_one(max_perf_pct, max_perf_pct);
1354 show_one(min_perf_pct, min_perf_pct);
1355
1356 define_one_global_rw(status);
1357 define_one_global_rw(no_turbo);
1358 define_one_global_rw(max_perf_pct);
1359 define_one_global_rw(min_perf_pct);
1360 define_one_global_ro(turbo_pct);
1361 define_one_global_ro(num_pstates);
1362 define_one_global_rw(hwp_dynamic_boost);
1363 define_one_global_rw(energy_efficiency);
1364
1365 static struct attribute *intel_pstate_attributes[] = {
1366 &status.attr,
1367 &no_turbo.attr,
1368 &turbo_pct.attr,
1369 &num_pstates.attr,
1370 NULL
1371 };
1372
1373 static const struct attribute_group intel_pstate_attr_group = {
1374 .attrs = intel_pstate_attributes,
1375 };
1376
1377 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1378
1379 static struct kobject *intel_pstate_kobject;
1380
1381 static void __init intel_pstate_sysfs_expose_params(void)
1382 {
1383 int rc;
1384
1385 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1386 &cpu_subsys.dev_root->kobj);
1387 if (WARN_ON(!intel_pstate_kobject))
1388 return;
1389
1390 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1391 if (WARN_ON(rc))
1392 return;
1393
1394 /*
1395 * If per cpu limits are enforced there are no global limits, so
1396 * return without creating max/min_perf_pct attributes
1397 */
1398 if (per_cpu_limits)
1399 return;
1400
1401 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1402 WARN_ON(rc);
1403
1404 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1405 WARN_ON(rc);
1406
1407 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1408 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1409 WARN_ON(rc);
1410 }
1411 }
1412
1413 static void __init intel_pstate_sysfs_remove(void)
1414 {
1415 if (!intel_pstate_kobject)
1416 return;
1417
1418 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1419
1420 if (!per_cpu_limits) {
1421 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1422 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1423
1424 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1425 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1426 }
1427
1428 kobject_put(intel_pstate_kobject);
1429 }
1430
1431 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1432 {
1433 int rc;
1434
1435 if (!hwp_active)
1436 return;
1437
1438 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1439 WARN_ON_ONCE(rc);
1440 }
1441
1442 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1443 {
1444 if (!hwp_active)
1445 return;
1446
1447 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1448 }
1449
1450 /************************** sysfs end ************************/
1451
1452 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1453 {
1454 /* First disable HWP notification interrupt as we don't process them */
1455 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1456 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1457
1458 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1459 if (cpudata->epp_default == -EINVAL)
1460 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1461 }
1462
1463 static int atom_get_min_pstate(void)
1464 {
1465 u64 value;
1466
1467 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1468 return (value >> 8) & 0x7F;
1469 }
1470
1471 static int atom_get_max_pstate(void)
1472 {
1473 u64 value;
1474
1475 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1476 return (value >> 16) & 0x7F;
1477 }
1478
1479 static int atom_get_turbo_pstate(void)
1480 {
1481 u64 value;
1482
1483 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1484 return value & 0x7F;
1485 }
1486
1487 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1488 {
1489 u64 val;
1490 int32_t vid_fp;
1491 u32 vid;
1492
1493 val = (u64)pstate << 8;
1494 if (global.no_turbo && !global.turbo_disabled)
1495 val |= (u64)1 << 32;
1496
1497 vid_fp = cpudata->vid.min + mul_fp(
1498 int_tofp(pstate - cpudata->pstate.min_pstate),
1499 cpudata->vid.ratio);
1500
1501 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1502 vid = ceiling_fp(vid_fp);
1503
1504 if (pstate > cpudata->pstate.max_pstate)
1505 vid = cpudata->vid.turbo;
1506
1507 return val | vid;
1508 }
1509
1510 static int silvermont_get_scaling(void)
1511 {
1512 u64 value;
1513 int i;
1514 /* Defined in Table 35-6 from SDM (Sept 2015) */
1515 static int silvermont_freq_table[] = {
1516 83300, 100000, 133300, 116700, 80000};
1517
1518 rdmsrl(MSR_FSB_FREQ, value);
1519 i = value & 0x7;
1520 WARN_ON(i > 4);
1521
1522 return silvermont_freq_table[i];
1523 }
1524
1525 static int airmont_get_scaling(void)
1526 {
1527 u64 value;
1528 int i;
1529 /* Defined in Table 35-10 from SDM (Sept 2015) */
1530 static int airmont_freq_table[] = {
1531 83300, 100000, 133300, 116700, 80000,
1532 93300, 90000, 88900, 87500};
1533
1534 rdmsrl(MSR_FSB_FREQ, value);
1535 i = value & 0xF;
1536 WARN_ON(i > 8);
1537
1538 return airmont_freq_table[i];
1539 }
1540
1541 static void atom_get_vid(struct cpudata *cpudata)
1542 {
1543 u64 value;
1544
1545 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1546 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1547 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1548 cpudata->vid.ratio = div_fp(
1549 cpudata->vid.max - cpudata->vid.min,
1550 int_tofp(cpudata->pstate.max_pstate -
1551 cpudata->pstate.min_pstate));
1552
1553 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1554 cpudata->vid.turbo = value & 0x7f;
1555 }
1556
1557 static int core_get_min_pstate(void)
1558 {
1559 u64 value;
1560
1561 rdmsrl(MSR_PLATFORM_INFO, value);
1562 return (value >> 40) & 0xFF;
1563 }
1564
1565 static int core_get_max_pstate_physical(void)
1566 {
1567 u64 value;
1568
1569 rdmsrl(MSR_PLATFORM_INFO, value);
1570 return (value >> 8) & 0xFF;
1571 }
1572
1573 static int core_get_tdp_ratio(u64 plat_info)
1574 {
1575 /* Check how many TDP levels present */
1576 if (plat_info & 0x600000000) {
1577 u64 tdp_ctrl;
1578 u64 tdp_ratio;
1579 int tdp_msr;
1580 int err;
1581
1582 /* Get the TDP level (0, 1, 2) to get ratios */
1583 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1584 if (err)
1585 return err;
1586
1587 /* TDP MSR are continuous starting at 0x648 */
1588 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1589 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1590 if (err)
1591 return err;
1592
1593 /* For level 1 and 2, bits[23:16] contain the ratio */
1594 if (tdp_ctrl & 0x03)
1595 tdp_ratio >>= 16;
1596
1597 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1598 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1599
1600 return (int)tdp_ratio;
1601 }
1602
1603 return -ENXIO;
1604 }
1605
1606 static int core_get_max_pstate(void)
1607 {
1608 u64 tar;
1609 u64 plat_info;
1610 int max_pstate;
1611 int tdp_ratio;
1612 int err;
1613
1614 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1615 max_pstate = (plat_info >> 8) & 0xFF;
1616
1617 tdp_ratio = core_get_tdp_ratio(plat_info);
1618 if (tdp_ratio <= 0)
1619 return max_pstate;
1620
1621 if (hwp_active) {
1622 /* Turbo activation ratio is not used on HWP platforms */
1623 return tdp_ratio;
1624 }
1625
1626 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1627 if (!err) {
1628 int tar_levels;
1629
1630 /* Do some sanity checking for safety */
1631 tar_levels = tar & 0xff;
1632 if (tdp_ratio - 1 == tar_levels) {
1633 max_pstate = tar_levels;
1634 pr_debug("max_pstate=TAC %x\n", max_pstate);
1635 }
1636 }
1637
1638 return max_pstate;
1639 }
1640
1641 static int core_get_turbo_pstate(void)
1642 {
1643 u64 value;
1644 int nont, ret;
1645
1646 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1647 nont = core_get_max_pstate();
1648 ret = (value) & 255;
1649 if (ret <= nont)
1650 ret = nont;
1651 return ret;
1652 }
1653
1654 static inline int core_get_scaling(void)
1655 {
1656 return 100000;
1657 }
1658
1659 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1660 {
1661 u64 val;
1662
1663 val = (u64)pstate << 8;
1664 if (global.no_turbo && !global.turbo_disabled)
1665 val |= (u64)1 << 32;
1666
1667 return val;
1668 }
1669
1670 static int knl_get_aperf_mperf_shift(void)
1671 {
1672 return 10;
1673 }
1674
1675 static int knl_get_turbo_pstate(void)
1676 {
1677 u64 value;
1678 int nont, ret;
1679
1680 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1681 nont = core_get_max_pstate();
1682 ret = (((value) >> 8) & 0xFF);
1683 if (ret <= nont)
1684 ret = nont;
1685 return ret;
1686 }
1687
1688 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1689 {
1690 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1691 cpu->pstate.current_pstate = pstate;
1692 /*
1693 * Generally, there is no guarantee that this code will always run on
1694 * the CPU being updated, so force the register update to run on the
1695 * right CPU.
1696 */
1697 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1698 pstate_funcs.get_val(cpu, pstate));
1699 }
1700
1701 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1702 {
1703 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1704 }
1705
1706 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1707 {
1708 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1709
1710 update_turbo_state();
1711 intel_pstate_set_pstate(cpu, pstate);
1712 }
1713
1714 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1715 {
1716 cpu->pstate.min_pstate = pstate_funcs.get_min();
1717 cpu->pstate.max_pstate = pstate_funcs.get_max();
1718 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1719 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1720 cpu->pstate.scaling = pstate_funcs.get_scaling();
1721 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1722
1723 if (hwp_active && !hwp_mode_bdw) {
1724 unsigned int phy_max, current_max;
1725
1726 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, &current_max);
1727 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1728 cpu->pstate.turbo_pstate = phy_max;
1729 } else {
1730 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1731 }
1732
1733 if (pstate_funcs.get_aperf_mperf_shift)
1734 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1735
1736 if (pstate_funcs.get_vid)
1737 pstate_funcs.get_vid(cpu);
1738
1739 intel_pstate_set_min_pstate(cpu);
1740 }
1741
1742 /*
1743 * Long hold time will keep high perf limits for long time,
1744 * which negatively impacts perf/watt for some workloads,
1745 * like specpower. 3ms is based on experiements on some
1746 * workoads.
1747 */
1748 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1749
1750 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1751 {
1752 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1753 u32 max_limit = (hwp_req & 0xff00) >> 8;
1754 u32 min_limit = (hwp_req & 0xff);
1755 u32 boost_level1;
1756
1757 /*
1758 * Cases to consider (User changes via sysfs or boot time):
1759 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1760 * No boost, return.
1761 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1762 * Should result in one level boost only for P0.
1763 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1764 * Should result in two level boost:
1765 * (min + p1)/2 and P1.
1766 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1767 * Should result in three level boost:
1768 * (min + p1)/2, P1 and P0.
1769 */
1770
1771 /* If max and min are equal or already at max, nothing to boost */
1772 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1773 return;
1774
1775 if (!cpu->hwp_boost_min)
1776 cpu->hwp_boost_min = min_limit;
1777
1778 /* level at half way mark between min and guranteed */
1779 boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1780
1781 if (cpu->hwp_boost_min < boost_level1)
1782 cpu->hwp_boost_min = boost_level1;
1783 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1784 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1785 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1786 max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1787 cpu->hwp_boost_min = max_limit;
1788 else
1789 return;
1790
1791 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1792 wrmsrl(MSR_HWP_REQUEST, hwp_req);
1793 cpu->last_update = cpu->sample.time;
1794 }
1795
1796 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1797 {
1798 if (cpu->hwp_boost_min) {
1799 bool expired;
1800
1801 /* Check if we are idle for hold time to boost down */
1802 expired = time_after64(cpu->sample.time, cpu->last_update +
1803 hwp_boost_hold_time_ns);
1804 if (expired) {
1805 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1806 cpu->hwp_boost_min = 0;
1807 }
1808 }
1809 cpu->last_update = cpu->sample.time;
1810 }
1811
1812 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1813 u64 time)
1814 {
1815 cpu->sample.time = time;
1816
1817 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1818 bool do_io = false;
1819
1820 cpu->sched_flags = 0;
1821 /*
1822 * Set iowait_boost flag and update time. Since IO WAIT flag
1823 * is set all the time, we can't just conclude that there is
1824 * some IO bound activity is scheduled on this CPU with just
1825 * one occurrence. If we receive at least two in two
1826 * consecutive ticks, then we treat as boost candidate.
1827 */
1828 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1829 do_io = true;
1830
1831 cpu->last_io_update = time;
1832
1833 if (do_io)
1834 intel_pstate_hwp_boost_up(cpu);
1835
1836 } else {
1837 intel_pstate_hwp_boost_down(cpu);
1838 }
1839 }
1840
1841 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1842 u64 time, unsigned int flags)
1843 {
1844 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1845
1846 cpu->sched_flags |= flags;
1847
1848 if (smp_processor_id() == cpu->cpu)
1849 intel_pstate_update_util_hwp_local(cpu, time);
1850 }
1851
1852 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1853 {
1854 struct sample *sample = &cpu->sample;
1855
1856 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1857 }
1858
1859 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1860 {
1861 u64 aperf, mperf;
1862 unsigned long flags;
1863 u64 tsc;
1864
1865 local_irq_save(flags);
1866 rdmsrl(MSR_IA32_APERF, aperf);
1867 rdmsrl(MSR_IA32_MPERF, mperf);
1868 tsc = rdtsc();
1869 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1870 local_irq_restore(flags);
1871 return false;
1872 }
1873 local_irq_restore(flags);
1874
1875 cpu->last_sample_time = cpu->sample.time;
1876 cpu->sample.time = time;
1877 cpu->sample.aperf = aperf;
1878 cpu->sample.mperf = mperf;
1879 cpu->sample.tsc = tsc;
1880 cpu->sample.aperf -= cpu->prev_aperf;
1881 cpu->sample.mperf -= cpu->prev_mperf;
1882 cpu->sample.tsc -= cpu->prev_tsc;
1883
1884 cpu->prev_aperf = aperf;
1885 cpu->prev_mperf = mperf;
1886 cpu->prev_tsc = tsc;
1887 /*
1888 * First time this function is invoked in a given cycle, all of the
1889 * previous sample data fields are equal to zero or stale and they must
1890 * be populated with meaningful numbers for things to work, so assume
1891 * that sample.time will always be reset before setting the utilization
1892 * update hook and make the caller skip the sample then.
1893 */
1894 if (cpu->last_sample_time) {
1895 intel_pstate_calc_avg_perf(cpu);
1896 return true;
1897 }
1898 return false;
1899 }
1900
1901 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1902 {
1903 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1904 }
1905
1906 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1907 {
1908 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1909 cpu->sample.core_avg_perf);
1910 }
1911
1912 static inline int32_t get_target_pstate(struct cpudata *cpu)
1913 {
1914 struct sample *sample = &cpu->sample;
1915 int32_t busy_frac;
1916 int target, avg_pstate;
1917
1918 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1919 sample->tsc);
1920
1921 if (busy_frac < cpu->iowait_boost)
1922 busy_frac = cpu->iowait_boost;
1923
1924 sample->busy_scaled = busy_frac * 100;
1925
1926 target = global.no_turbo || global.turbo_disabled ?
1927 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1928 target += target >> 2;
1929 target = mul_fp(target, busy_frac);
1930 if (target < cpu->pstate.min_pstate)
1931 target = cpu->pstate.min_pstate;
1932
1933 /*
1934 * If the average P-state during the previous cycle was higher than the
1935 * current target, add 50% of the difference to the target to reduce
1936 * possible performance oscillations and offset possible performance
1937 * loss related to moving the workload from one CPU to another within
1938 * a package/module.
1939 */
1940 avg_pstate = get_avg_pstate(cpu);
1941 if (avg_pstate > target)
1942 target += (avg_pstate - target) >> 1;
1943
1944 return target;
1945 }
1946
1947 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1948 {
1949 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1950 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
1951
1952 return clamp_t(int, pstate, min_pstate, max_pstate);
1953 }
1954
1955 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1956 {
1957 if (pstate == cpu->pstate.current_pstate)
1958 return;
1959
1960 cpu->pstate.current_pstate = pstate;
1961 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1962 }
1963
1964 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1965 {
1966 int from = cpu->pstate.current_pstate;
1967 struct sample *sample;
1968 int target_pstate;
1969
1970 update_turbo_state();
1971
1972 target_pstate = get_target_pstate(cpu);
1973 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1974 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1975 intel_pstate_update_pstate(cpu, target_pstate);
1976
1977 sample = &cpu->sample;
1978 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1979 fp_toint(sample->busy_scaled),
1980 from,
1981 cpu->pstate.current_pstate,
1982 sample->mperf,
1983 sample->aperf,
1984 sample->tsc,
1985 get_avg_frequency(cpu),
1986 fp_toint(cpu->iowait_boost * 100));
1987 }
1988
1989 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1990 unsigned int flags)
1991 {
1992 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1993 u64 delta_ns;
1994
1995 /* Don't allow remote callbacks */
1996 if (smp_processor_id() != cpu->cpu)
1997 return;
1998
1999 delta_ns = time - cpu->last_update;
2000 if (flags & SCHED_CPUFREQ_IOWAIT) {
2001 /* Start over if the CPU may have been idle. */
2002 if (delta_ns > TICK_NSEC) {
2003 cpu->iowait_boost = ONE_EIGHTH_FP;
2004 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2005 cpu->iowait_boost <<= 1;
2006 if (cpu->iowait_boost > int_tofp(1))
2007 cpu->iowait_boost = int_tofp(1);
2008 } else {
2009 cpu->iowait_boost = ONE_EIGHTH_FP;
2010 }
2011 } else if (cpu->iowait_boost) {
2012 /* Clear iowait_boost if the CPU may have been idle. */
2013 if (delta_ns > TICK_NSEC)
2014 cpu->iowait_boost = 0;
2015 else
2016 cpu->iowait_boost >>= 1;
2017 }
2018 cpu->last_update = time;
2019 delta_ns = time - cpu->sample.time;
2020 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2021 return;
2022
2023 if (intel_pstate_sample(cpu, time))
2024 intel_pstate_adjust_pstate(cpu);
2025 }
2026
2027 static struct pstate_funcs core_funcs = {
2028 .get_max = core_get_max_pstate,
2029 .get_max_physical = core_get_max_pstate_physical,
2030 .get_min = core_get_min_pstate,
2031 .get_turbo = core_get_turbo_pstate,
2032 .get_scaling = core_get_scaling,
2033 .get_val = core_get_val,
2034 };
2035
2036 static const struct pstate_funcs silvermont_funcs = {
2037 .get_max = atom_get_max_pstate,
2038 .get_max_physical = atom_get_max_pstate,
2039 .get_min = atom_get_min_pstate,
2040 .get_turbo = atom_get_turbo_pstate,
2041 .get_val = atom_get_val,
2042 .get_scaling = silvermont_get_scaling,
2043 .get_vid = atom_get_vid,
2044 };
2045
2046 static const struct pstate_funcs airmont_funcs = {
2047 .get_max = atom_get_max_pstate,
2048 .get_max_physical = atom_get_max_pstate,
2049 .get_min = atom_get_min_pstate,
2050 .get_turbo = atom_get_turbo_pstate,
2051 .get_val = atom_get_val,
2052 .get_scaling = airmont_get_scaling,
2053 .get_vid = atom_get_vid,
2054 };
2055
2056 static const struct pstate_funcs knl_funcs = {
2057 .get_max = core_get_max_pstate,
2058 .get_max_physical = core_get_max_pstate_physical,
2059 .get_min = core_get_min_pstate,
2060 .get_turbo = knl_get_turbo_pstate,
2061 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2062 .get_scaling = core_get_scaling,
2063 .get_val = core_get_val,
2064 };
2065
2066 #define X86_MATCH(model, policy) \
2067 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2068 X86_FEATURE_APERFMPERF, &policy)
2069
2070 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2071 X86_MATCH(SANDYBRIDGE, core_funcs),
2072 X86_MATCH(SANDYBRIDGE_X, core_funcs),
2073 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs),
2074 X86_MATCH(IVYBRIDGE, core_funcs),
2075 X86_MATCH(HASWELL, core_funcs),
2076 X86_MATCH(BROADWELL, core_funcs),
2077 X86_MATCH(IVYBRIDGE_X, core_funcs),
2078 X86_MATCH(HASWELL_X, core_funcs),
2079 X86_MATCH(HASWELL_L, core_funcs),
2080 X86_MATCH(HASWELL_G, core_funcs),
2081 X86_MATCH(BROADWELL_G, core_funcs),
2082 X86_MATCH(ATOM_AIRMONT, airmont_funcs),
2083 X86_MATCH(SKYLAKE_L, core_funcs),
2084 X86_MATCH(BROADWELL_X, core_funcs),
2085 X86_MATCH(SKYLAKE, core_funcs),
2086 X86_MATCH(BROADWELL_D, core_funcs),
2087 X86_MATCH(XEON_PHI_KNL, knl_funcs),
2088 X86_MATCH(XEON_PHI_KNM, knl_funcs),
2089 X86_MATCH(ATOM_GOLDMONT, core_funcs),
2090 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs),
2091 X86_MATCH(SKYLAKE_X, core_funcs),
2092 {}
2093 };
2094 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2095
2096 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2097 X86_MATCH(BROADWELL_D, core_funcs),
2098 X86_MATCH(BROADWELL_X, core_funcs),
2099 X86_MATCH(SKYLAKE_X, core_funcs),
2100 {}
2101 };
2102
2103 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2104 X86_MATCH(KABYLAKE, core_funcs),
2105 {}
2106 };
2107
2108 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
2109 X86_MATCH(SKYLAKE_X, core_funcs),
2110 X86_MATCH(SKYLAKE, core_funcs),
2111 {}
2112 };
2113
2114 static int intel_pstate_init_cpu(unsigned int cpunum)
2115 {
2116 struct cpudata *cpu;
2117
2118 cpu = all_cpu_data[cpunum];
2119
2120 if (!cpu) {
2121 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2122 if (!cpu)
2123 return -ENOMEM;
2124
2125 all_cpu_data[cpunum] = cpu;
2126
2127 cpu->cpu = cpunum;
2128
2129 cpu->epp_default = -EINVAL;
2130
2131 if (hwp_active) {
2132 const struct x86_cpu_id *id;
2133
2134 intel_pstate_hwp_enable(cpu);
2135
2136 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
2137 if (id && intel_pstate_acpi_pm_profile_server())
2138 hwp_boost = true;
2139 }
2140 } else if (hwp_active) {
2141 /*
2142 * Re-enable HWP in case this happens after a resume from ACPI
2143 * S3 if the CPU was offline during the whole system/resume
2144 * cycle.
2145 */
2146 intel_pstate_hwp_reenable(cpu);
2147 }
2148
2149 cpu->epp_powersave = -EINVAL;
2150 cpu->epp_policy = 0;
2151
2152 intel_pstate_get_cpu_pstates(cpu);
2153
2154 pr_debug("controlling: cpu %d\n", cpunum);
2155
2156 return 0;
2157 }
2158
2159 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2160 {
2161 struct cpudata *cpu = all_cpu_data[cpu_num];
2162
2163 if (hwp_active && !hwp_boost)
2164 return;
2165
2166 if (cpu->update_util_set)
2167 return;
2168
2169 /* Prevent intel_pstate_update_util() from using stale data. */
2170 cpu->sample.time = 0;
2171 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2172 (hwp_active ?
2173 intel_pstate_update_util_hwp :
2174 intel_pstate_update_util));
2175 cpu->update_util_set = true;
2176 }
2177
2178 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2179 {
2180 struct cpudata *cpu_data = all_cpu_data[cpu];
2181
2182 if (!cpu_data->update_util_set)
2183 return;
2184
2185 cpufreq_remove_update_util_hook(cpu);
2186 cpu_data->update_util_set = false;
2187 synchronize_rcu();
2188 }
2189
2190 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2191 {
2192 return global.turbo_disabled || global.no_turbo ?
2193 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2194 }
2195
2196 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2197 unsigned int policy_min,
2198 unsigned int policy_max)
2199 {
2200 int32_t max_policy_perf, min_policy_perf;
2201 int max_state, turbo_max;
2202 int max_freq;
2203
2204 /*
2205 * HWP needs some special consideration, because on BDX the
2206 * HWP_REQUEST uses abstract value to represent performance
2207 * rather than pure ratios.
2208 */
2209 if (hwp_active) {
2210 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
2211 } else {
2212 max_state = global.no_turbo || global.turbo_disabled ?
2213 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2214 turbo_max = cpu->pstate.turbo_pstate;
2215 }
2216 max_freq = max_state * cpu->pstate.scaling;
2217
2218 max_policy_perf = max_state * policy_max / max_freq;
2219 if (policy_max == policy_min) {
2220 min_policy_perf = max_policy_perf;
2221 } else {
2222 min_policy_perf = max_state * policy_min / max_freq;
2223 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2224 0, max_policy_perf);
2225 }
2226
2227 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
2228 cpu->cpu, max_state, min_policy_perf, max_policy_perf);
2229
2230 /* Normalize user input to [min_perf, max_perf] */
2231 if (per_cpu_limits) {
2232 cpu->min_perf_ratio = min_policy_perf;
2233 cpu->max_perf_ratio = max_policy_perf;
2234 } else {
2235 int32_t global_min, global_max;
2236
2237 /* Global limits are in percent of the maximum turbo P-state. */
2238 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2239 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2240 global_min = clamp_t(int32_t, global_min, 0, global_max);
2241
2242 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2243 global_min, global_max);
2244
2245 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2246 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2247 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2248 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2249
2250 /* Make sure min_perf <= max_perf */
2251 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2252 cpu->max_perf_ratio);
2253
2254 }
2255 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2256 cpu->max_perf_ratio,
2257 cpu->min_perf_ratio);
2258 }
2259
2260 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2261 {
2262 struct cpudata *cpu;
2263
2264 if (!policy->cpuinfo.max_freq)
2265 return -ENODEV;
2266
2267 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2268 policy->cpuinfo.max_freq, policy->max);
2269
2270 cpu = all_cpu_data[policy->cpu];
2271 cpu->policy = policy->policy;
2272
2273 mutex_lock(&intel_pstate_limits_lock);
2274
2275 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2276
2277 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2278 /*
2279 * NOHZ_FULL CPUs need this as the governor callback may not
2280 * be invoked on them.
2281 */
2282 intel_pstate_clear_update_util_hook(policy->cpu);
2283 intel_pstate_max_within_limits(cpu);
2284 } else {
2285 intel_pstate_set_update_util_hook(policy->cpu);
2286 }
2287
2288 if (hwp_active) {
2289 /*
2290 * When hwp_boost was active before and dynamically it
2291 * was turned off, in that case we need to clear the
2292 * update util hook.
2293 */
2294 if (!hwp_boost)
2295 intel_pstate_clear_update_util_hook(policy->cpu);
2296 intel_pstate_hwp_set(policy->cpu);
2297 }
2298
2299 mutex_unlock(&intel_pstate_limits_lock);
2300
2301 return 0;
2302 }
2303
2304 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2305 struct cpufreq_policy_data *policy)
2306 {
2307 if (!hwp_active &&
2308 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2309 policy->max < policy->cpuinfo.max_freq &&
2310 policy->max > cpu->pstate.max_freq) {
2311 pr_debug("policy->max > max non turbo frequency\n");
2312 policy->max = policy->cpuinfo.max_freq;
2313 }
2314 }
2315
2316 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2317 struct cpufreq_policy_data *policy)
2318 {
2319 int max_freq;
2320
2321 update_turbo_state();
2322 if (hwp_active) {
2323 int max_state, turbo_max;
2324
2325 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
2326 max_freq = max_state * cpu->pstate.scaling;
2327 } else {
2328 max_freq = intel_pstate_get_max_freq(cpu);
2329 }
2330 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2331
2332 intel_pstate_adjust_policy_max(cpu, policy);
2333 }
2334
2335 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2336 {
2337 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2338
2339 return 0;
2340 }
2341
2342 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2343 {
2344 struct cpudata *cpu = all_cpu_data[policy->cpu];
2345
2346 pr_debug("CPU %d going offline\n", cpu->cpu);
2347
2348 if (cpu->suspended)
2349 return 0;
2350
2351 /*
2352 * If the CPU is an SMT thread and it goes offline with the performance
2353 * settings different from the minimum, it will prevent its sibling
2354 * from getting to lower performance levels, so force the minimum
2355 * performance on CPU offline to prevent that from happening.
2356 */
2357 if (hwp_active)
2358 intel_pstate_hwp_offline(cpu);
2359 else
2360 intel_pstate_set_min_pstate(cpu);
2361
2362 intel_pstate_exit_perf_limits(policy);
2363
2364 return 0;
2365 }
2366
2367 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2368 {
2369 struct cpudata *cpu = all_cpu_data[policy->cpu];
2370
2371 pr_debug("CPU %d going online\n", cpu->cpu);
2372
2373 intel_pstate_init_acpi_perf_limits(policy);
2374
2375 if (hwp_active) {
2376 /*
2377 * Re-enable HWP and clear the "suspended" flag to let "resume"
2378 * know that it need not do that.
2379 */
2380 intel_pstate_hwp_reenable(cpu);
2381 cpu->suspended = false;
2382 }
2383
2384 return 0;
2385 }
2386
2387 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2388 {
2389 pr_debug("CPU %d stopping\n", policy->cpu);
2390
2391 intel_pstate_clear_update_util_hook(policy->cpu);
2392 }
2393
2394 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2395 {
2396 pr_debug("CPU %d exiting\n", policy->cpu);
2397
2398 policy->fast_switch_possible = false;
2399
2400 return 0;
2401 }
2402
2403 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2404 {
2405 struct cpudata *cpu;
2406 int rc;
2407
2408 rc = intel_pstate_init_cpu(policy->cpu);
2409 if (rc)
2410 return rc;
2411
2412 cpu = all_cpu_data[policy->cpu];
2413
2414 cpu->max_perf_ratio = 0xFF;
2415 cpu->min_perf_ratio = 0;
2416
2417 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2418 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2419
2420 /* cpuinfo and default policy values */
2421 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2422 update_turbo_state();
2423 global.turbo_disabled_mf = global.turbo_disabled;
2424 policy->cpuinfo.max_freq = global.turbo_disabled ?
2425 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2426 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2427
2428 if (hwp_active) {
2429 unsigned int max_freq;
2430
2431 max_freq = global.turbo_disabled ?
2432 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2433 if (max_freq < policy->cpuinfo.max_freq)
2434 policy->cpuinfo.max_freq = max_freq;
2435 }
2436
2437 intel_pstate_init_acpi_perf_limits(policy);
2438
2439 policy->fast_switch_possible = true;
2440
2441 return 0;
2442 }
2443
2444 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2445 {
2446 int ret = __intel_pstate_cpu_init(policy);
2447
2448 if (ret)
2449 return ret;
2450
2451 /*
2452 * Set the policy to powersave to provide a valid fallback value in case
2453 * the default cpufreq governor is neither powersave nor performance.
2454 */
2455 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2456
2457 if (hwp_active) {
2458 struct cpudata *cpu = all_cpu_data[policy->cpu];
2459
2460 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2461 }
2462
2463 return 0;
2464 }
2465
2466 static struct cpufreq_driver intel_pstate = {
2467 .flags = CPUFREQ_CONST_LOOPS,
2468 .verify = intel_pstate_verify_policy,
2469 .setpolicy = intel_pstate_set_policy,
2470 .suspend = intel_pstate_suspend,
2471 .resume = intel_pstate_resume,
2472 .init = intel_pstate_cpu_init,
2473 .exit = intel_pstate_cpu_exit,
2474 .stop_cpu = intel_pstate_stop_cpu,
2475 .offline = intel_pstate_cpu_offline,
2476 .online = intel_pstate_cpu_online,
2477 .update_limits = intel_pstate_update_limits,
2478 .name = "intel_pstate",
2479 };
2480
2481 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2482 {
2483 struct cpudata *cpu = all_cpu_data[policy->cpu];
2484
2485 intel_pstate_verify_cpu_policy(cpu, policy);
2486 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2487
2488 return 0;
2489 }
2490
2491 /* Use of trace in passive mode:
2492 *
2493 * In passive mode the trace core_busy field (also known as the
2494 * performance field, and lablelled as such on the graphs; also known as
2495 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2496 * driver call was via the normal or fast switch path. Various graphs
2497 * output from the intel_pstate_tracer.py utility that include core_busy
2498 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2499 * so we use 10 to indicate the the normal path through the driver, and
2500 * 90 to indicate the fast switch path through the driver.
2501 * The scaled_busy field is not used, and is set to 0.
2502 */
2503
2504 #define INTEL_PSTATE_TRACE_TARGET 10
2505 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2506
2507 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2508 {
2509 struct sample *sample;
2510
2511 if (!trace_pstate_sample_enabled())
2512 return;
2513
2514 if (!intel_pstate_sample(cpu, ktime_get()))
2515 return;
2516
2517 sample = &cpu->sample;
2518 trace_pstate_sample(trace_type,
2519 0,
2520 old_pstate,
2521 cpu->pstate.current_pstate,
2522 sample->mperf,
2523 sample->aperf,
2524 sample->tsc,
2525 get_avg_frequency(cpu),
2526 fp_toint(cpu->iowait_boost * 100));
2527 }
2528
2529 static void intel_cpufreq_adjust_hwp(struct cpudata *cpu, u32 min, u32 max,
2530 u32 desired, bool fast_switch)
2531 {
2532 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2533
2534 value &= ~HWP_MIN_PERF(~0L);
2535 value |= HWP_MIN_PERF(min);
2536
2537 value &= ~HWP_MAX_PERF(~0L);
2538 value |= HWP_MAX_PERF(max);
2539
2540 value &= ~HWP_DESIRED_PERF(~0L);
2541 value |= HWP_DESIRED_PERF(desired);
2542
2543 if (value == prev)
2544 return;
2545
2546 WRITE_ONCE(cpu->hwp_req_cached, value);
2547 if (fast_switch)
2548 wrmsrl(MSR_HWP_REQUEST, value);
2549 else
2550 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2551 }
2552
2553 static void intel_cpufreq_adjust_perf_ctl(struct cpudata *cpu,
2554 u32 target_pstate, bool fast_switch)
2555 {
2556 if (fast_switch)
2557 wrmsrl(MSR_IA32_PERF_CTL,
2558 pstate_funcs.get_val(cpu, target_pstate));
2559 else
2560 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2561 pstate_funcs.get_val(cpu, target_pstate));
2562 }
2563
2564 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2565 int target_pstate, bool fast_switch)
2566 {
2567 struct cpudata *cpu = all_cpu_data[policy->cpu];
2568 int old_pstate = cpu->pstate.current_pstate;
2569
2570 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2571 if (hwp_active) {
2572 int max_pstate = policy->strict_target ?
2573 target_pstate : cpu->max_perf_ratio;
2574
2575 intel_cpufreq_adjust_hwp(cpu, target_pstate, max_pstate, 0,
2576 fast_switch);
2577 } else if (target_pstate != old_pstate) {
2578 intel_cpufreq_adjust_perf_ctl(cpu, target_pstate, fast_switch);
2579 }
2580
2581 cpu->pstate.current_pstate = target_pstate;
2582
2583 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2584 INTEL_PSTATE_TRACE_TARGET, old_pstate);
2585
2586 return target_pstate;
2587 }
2588
2589 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2590 unsigned int target_freq,
2591 unsigned int relation)
2592 {
2593 struct cpudata *cpu = all_cpu_data[policy->cpu];
2594 struct cpufreq_freqs freqs;
2595 int target_pstate;
2596
2597 update_turbo_state();
2598
2599 freqs.old = policy->cur;
2600 freqs.new = target_freq;
2601
2602 cpufreq_freq_transition_begin(policy, &freqs);
2603
2604 switch (relation) {
2605 case CPUFREQ_RELATION_L:
2606 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2607 break;
2608 case CPUFREQ_RELATION_H:
2609 target_pstate = freqs.new / cpu->pstate.scaling;
2610 break;
2611 default:
2612 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2613 break;
2614 }
2615
2616 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2617
2618 freqs.new = target_pstate * cpu->pstate.scaling;
2619
2620 cpufreq_freq_transition_end(policy, &freqs, false);
2621
2622 return 0;
2623 }
2624
2625 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2626 unsigned int target_freq)
2627 {
2628 struct cpudata *cpu = all_cpu_data[policy->cpu];
2629 int target_pstate;
2630
2631 update_turbo_state();
2632
2633 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2634
2635 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2636
2637 return target_pstate * cpu->pstate.scaling;
2638 }
2639
2640 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2641 unsigned long min_perf,
2642 unsigned long target_perf,
2643 unsigned long capacity)
2644 {
2645 struct cpudata *cpu = all_cpu_data[cpunum];
2646 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2647 int old_pstate = cpu->pstate.current_pstate;
2648 int cap_pstate, min_pstate, max_pstate, target_pstate;
2649
2650 update_turbo_state();
2651 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2652 HWP_HIGHEST_PERF(hwp_cap);
2653
2654 /* Optimization: Avoid unnecessary divisions. */
2655
2656 target_pstate = cap_pstate;
2657 if (target_perf < capacity)
2658 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2659
2660 min_pstate = cap_pstate;
2661 if (min_perf < capacity)
2662 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2663
2664 if (min_pstate < cpu->pstate.min_pstate)
2665 min_pstate = cpu->pstate.min_pstate;
2666
2667 if (min_pstate < cpu->min_perf_ratio)
2668 min_pstate = cpu->min_perf_ratio;
2669
2670 max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2671 if (max_pstate < min_pstate)
2672 max_pstate = min_pstate;
2673
2674 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2675
2676 intel_cpufreq_adjust_hwp(cpu, min_pstate, max_pstate, target_pstate, true);
2677
2678 cpu->pstate.current_pstate = target_pstate;
2679 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2680 }
2681
2682 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2683 {
2684 int max_state, turbo_max, min_freq, max_freq, ret;
2685 struct freq_qos_request *req;
2686 struct cpudata *cpu;
2687 struct device *dev;
2688
2689 dev = get_cpu_device(policy->cpu);
2690 if (!dev)
2691 return -ENODEV;
2692
2693 ret = __intel_pstate_cpu_init(policy);
2694 if (ret)
2695 return ret;
2696
2697 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2698 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2699 policy->cur = policy->cpuinfo.min_freq;
2700
2701 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
2702 if (!req) {
2703 ret = -ENOMEM;
2704 goto pstate_exit;
2705 }
2706
2707 cpu = all_cpu_data[policy->cpu];
2708
2709 if (hwp_active) {
2710 u64 value;
2711
2712 intel_pstate_get_hwp_max(policy->cpu, &turbo_max, &max_state);
2713 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
2714 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
2715 WRITE_ONCE(cpu->hwp_req_cached, value);
2716 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
2717 } else {
2718 turbo_max = cpu->pstate.turbo_pstate;
2719 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2720 }
2721
2722 min_freq = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2723 min_freq *= cpu->pstate.scaling;
2724 max_freq = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2725 max_freq *= cpu->pstate.scaling;
2726
2727 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
2728 min_freq);
2729 if (ret < 0) {
2730 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
2731 goto free_req;
2732 }
2733
2734 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
2735 max_freq);
2736 if (ret < 0) {
2737 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
2738 goto remove_min_req;
2739 }
2740
2741 policy->driver_data = req;
2742
2743 return 0;
2744
2745 remove_min_req:
2746 freq_qos_remove_request(req);
2747 free_req:
2748 kfree(req);
2749 pstate_exit:
2750 intel_pstate_exit_perf_limits(policy);
2751
2752 return ret;
2753 }
2754
2755 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
2756 {
2757 struct freq_qos_request *req;
2758
2759 req = policy->driver_data;
2760
2761 freq_qos_remove_request(req + 1);
2762 freq_qos_remove_request(req);
2763 kfree(req);
2764
2765 return intel_pstate_cpu_exit(policy);
2766 }
2767
2768 static struct cpufreq_driver intel_cpufreq = {
2769 .flags = CPUFREQ_CONST_LOOPS,
2770 .verify = intel_cpufreq_verify_policy,
2771 .target = intel_cpufreq_target,
2772 .fast_switch = intel_cpufreq_fast_switch,
2773 .init = intel_cpufreq_cpu_init,
2774 .exit = intel_cpufreq_cpu_exit,
2775 .offline = intel_pstate_cpu_offline,
2776 .online = intel_pstate_cpu_online,
2777 .suspend = intel_pstate_suspend,
2778 .resume = intel_pstate_resume,
2779 .update_limits = intel_pstate_update_limits,
2780 .name = "intel_cpufreq",
2781 };
2782
2783 static struct cpufreq_driver *default_driver;
2784
2785 static void intel_pstate_driver_cleanup(void)
2786 {
2787 unsigned int cpu;
2788
2789 get_online_cpus();
2790 for_each_online_cpu(cpu) {
2791 if (all_cpu_data[cpu]) {
2792 if (intel_pstate_driver == &intel_pstate)
2793 intel_pstate_clear_update_util_hook(cpu);
2794
2795 kfree(all_cpu_data[cpu]);
2796 all_cpu_data[cpu] = NULL;
2797 }
2798 }
2799 put_online_cpus();
2800
2801 intel_pstate_driver = NULL;
2802 }
2803
2804 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2805 {
2806 int ret;
2807
2808 if (driver == &intel_pstate)
2809 intel_pstate_sysfs_expose_hwp_dynamic_boost();
2810
2811 memset(&global, 0, sizeof(global));
2812 global.max_perf_pct = 100;
2813
2814 intel_pstate_driver = driver;
2815 ret = cpufreq_register_driver(intel_pstate_driver);
2816 if (ret) {
2817 intel_pstate_driver_cleanup();
2818 return ret;
2819 }
2820
2821 global.min_perf_pct = min_perf_pct_min();
2822
2823 return 0;
2824 }
2825
2826 static ssize_t intel_pstate_show_status(char *buf)
2827 {
2828 if (!intel_pstate_driver)
2829 return sprintf(buf, "off\n");
2830
2831 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2832 "active" : "passive");
2833 }
2834
2835 static int intel_pstate_update_status(const char *buf, size_t size)
2836 {
2837 if (size == 3 && !strncmp(buf, "off", size)) {
2838 if (!intel_pstate_driver)
2839 return -EINVAL;
2840
2841 if (hwp_active)
2842 return -EBUSY;
2843
2844 cpufreq_unregister_driver(intel_pstate_driver);
2845 intel_pstate_driver_cleanup();
2846 return 0;
2847 }
2848
2849 if (size == 6 && !strncmp(buf, "active", size)) {
2850 if (intel_pstate_driver) {
2851 if (intel_pstate_driver == &intel_pstate)
2852 return 0;
2853
2854 cpufreq_unregister_driver(intel_pstate_driver);
2855 }
2856
2857 return intel_pstate_register_driver(&intel_pstate);
2858 }
2859
2860 if (size == 7 && !strncmp(buf, "passive", size)) {
2861 if (intel_pstate_driver) {
2862 if (intel_pstate_driver == &intel_cpufreq)
2863 return 0;
2864
2865 cpufreq_unregister_driver(intel_pstate_driver);
2866 intel_pstate_sysfs_hide_hwp_dynamic_boost();
2867 }
2868
2869 return intel_pstate_register_driver(&intel_cpufreq);
2870 }
2871
2872 return -EINVAL;
2873 }
2874
2875 static int no_load __initdata;
2876 static int no_hwp __initdata;
2877 static int hwp_only __initdata;
2878 static unsigned int force_load __initdata;
2879
2880 static int __init intel_pstate_msrs_not_valid(void)
2881 {
2882 if (!pstate_funcs.get_max() ||
2883 !pstate_funcs.get_min() ||
2884 !pstate_funcs.get_turbo())
2885 return -ENODEV;
2886
2887 return 0;
2888 }
2889
2890 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2891 {
2892 pstate_funcs.get_max = funcs->get_max;
2893 pstate_funcs.get_max_physical = funcs->get_max_physical;
2894 pstate_funcs.get_min = funcs->get_min;
2895 pstate_funcs.get_turbo = funcs->get_turbo;
2896 pstate_funcs.get_scaling = funcs->get_scaling;
2897 pstate_funcs.get_val = funcs->get_val;
2898 pstate_funcs.get_vid = funcs->get_vid;
2899 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2900 }
2901
2902 #ifdef CONFIG_ACPI
2903
2904 static bool __init intel_pstate_no_acpi_pss(void)
2905 {
2906 int i;
2907
2908 for_each_possible_cpu(i) {
2909 acpi_status status;
2910 union acpi_object *pss;
2911 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2912 struct acpi_processor *pr = per_cpu(processors, i);
2913
2914 if (!pr)
2915 continue;
2916
2917 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2918 if (ACPI_FAILURE(status))
2919 continue;
2920
2921 pss = buffer.pointer;
2922 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2923 kfree(pss);
2924 return false;
2925 }
2926
2927 kfree(pss);
2928 }
2929
2930 pr_debug("ACPI _PSS not found\n");
2931 return true;
2932 }
2933
2934 static bool __init intel_pstate_no_acpi_pcch(void)
2935 {
2936 acpi_status status;
2937 acpi_handle handle;
2938
2939 status = acpi_get_handle(NULL, "\\_SB", &handle);
2940 if (ACPI_FAILURE(status))
2941 goto not_found;
2942
2943 if (acpi_has_method(handle, "PCCH"))
2944 return false;
2945
2946 not_found:
2947 pr_debug("ACPI PCCH not found\n");
2948 return true;
2949 }
2950
2951 static bool __init intel_pstate_has_acpi_ppc(void)
2952 {
2953 int i;
2954
2955 for_each_possible_cpu(i) {
2956 struct acpi_processor *pr = per_cpu(processors, i);
2957
2958 if (!pr)
2959 continue;
2960 if (acpi_has_method(pr->handle, "_PPC"))
2961 return true;
2962 }
2963 pr_debug("ACPI _PPC not found\n");
2964 return false;
2965 }
2966
2967 enum {
2968 PSS,
2969 PPC,
2970 };
2971
2972 /* Hardware vendor-specific info that has its own power management modes */
2973 static struct acpi_platform_list plat_info[] __initdata = {
2974 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
2975 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2976 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2977 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2978 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2979 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2980 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2981 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2982 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2983 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2984 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2985 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2986 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2987 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2988 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2989 { } /* End */
2990 };
2991
2992 #define BITMASK_OOB (BIT(8) | BIT(18))
2993
2994 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2995 {
2996 const struct x86_cpu_id *id;
2997 u64 misc_pwr;
2998 int idx;
2999
3000 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3001 if (id) {
3002 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3003 if (misc_pwr & BITMASK_OOB) {
3004 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3005 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3006 return true;
3007 }
3008 }
3009
3010 idx = acpi_match_platform_list(plat_info);
3011 if (idx < 0)
3012 return false;
3013
3014 switch (plat_info[idx].data) {
3015 case PSS:
3016 if (!intel_pstate_no_acpi_pss())
3017 return false;
3018
3019 return intel_pstate_no_acpi_pcch();
3020 case PPC:
3021 return intel_pstate_has_acpi_ppc() && !force_load;
3022 }
3023
3024 return false;
3025 }
3026
3027 static void intel_pstate_request_control_from_smm(void)
3028 {
3029 /*
3030 * It may be unsafe to request P-states control from SMM if _PPC support
3031 * has not been enabled.
3032 */
3033 if (acpi_ppc)
3034 acpi_processor_pstate_control();
3035 }
3036 #else /* CONFIG_ACPI not enabled */
3037 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3038 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3039 static inline void intel_pstate_request_control_from_smm(void) {}
3040 #endif /* CONFIG_ACPI */
3041
3042 #define INTEL_PSTATE_HWP_BROADWELL 0x01
3043
3044 #define X86_MATCH_HWP(model, hwp_mode) \
3045 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3046 X86_FEATURE_HWP, hwp_mode)
3047
3048 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3049 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3050 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3051 X86_MATCH_HWP(ANY, 0),
3052 {}
3053 };
3054
3055 static int __init intel_pstate_init(void)
3056 {
3057 const struct x86_cpu_id *id;
3058 int rc;
3059
3060 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3061 return -ENODEV;
3062
3063 if (no_load)
3064 return -ENODEV;
3065
3066 id = x86_match_cpu(hwp_support_ids);
3067 if (id) {
3068 copy_cpu_funcs(&core_funcs);
3069 /*
3070 * Avoid enabling HWP for processors without EPP support,
3071 * because that means incomplete HWP implementation which is a
3072 * corner case and supporting it is generally problematic.
3073 */
3074 if (!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) {
3075 hwp_active++;
3076 hwp_mode_bdw = id->driver_data;
3077 intel_pstate.attr = hwp_cpufreq_attrs;
3078 intel_cpufreq.attr = hwp_cpufreq_attrs;
3079 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3080 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3081 if (!default_driver)
3082 default_driver = &intel_pstate;
3083
3084 goto hwp_cpu_matched;
3085 }
3086 } else {
3087 id = x86_match_cpu(intel_pstate_cpu_ids);
3088 if (!id) {
3089 pr_info("CPU model not supported\n");
3090 return -ENODEV;
3091 }
3092
3093 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3094 }
3095
3096 if (intel_pstate_msrs_not_valid()) {
3097 pr_info("Invalid MSRs\n");
3098 return -ENODEV;
3099 }
3100 /* Without HWP start in the passive mode. */
3101 if (!default_driver)
3102 default_driver = &intel_cpufreq;
3103
3104 hwp_cpu_matched:
3105 /*
3106 * The Intel pstate driver will be ignored if the platform
3107 * firmware has its own power management modes.
3108 */
3109 if (intel_pstate_platform_pwr_mgmt_exists()) {
3110 pr_info("P-states controlled by the platform\n");
3111 return -ENODEV;
3112 }
3113
3114 if (!hwp_active && hwp_only)
3115 return -ENOTSUPP;
3116
3117 pr_info("Intel P-state driver initializing\n");
3118
3119 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3120 if (!all_cpu_data)
3121 return -ENOMEM;
3122
3123 intel_pstate_request_control_from_smm();
3124
3125 intel_pstate_sysfs_expose_params();
3126
3127 mutex_lock(&intel_pstate_driver_lock);
3128 rc = intel_pstate_register_driver(default_driver);
3129 mutex_unlock(&intel_pstate_driver_lock);
3130 if (rc) {
3131 intel_pstate_sysfs_remove();
3132 return rc;
3133 }
3134
3135 if (hwp_active) {
3136 const struct x86_cpu_id *id;
3137
3138 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3139 if (id) {
3140 set_power_ctl_ee_state(false);
3141 pr_info("Disabling energy efficiency optimization\n");
3142 }
3143
3144 pr_info("HWP enabled\n");
3145 }
3146
3147 return 0;
3148 }
3149 device_initcall(intel_pstate_init);
3150
3151 static int __init intel_pstate_setup(char *str)
3152 {
3153 if (!str)
3154 return -EINVAL;
3155
3156 if (!strcmp(str, "disable"))
3157 no_load = 1;
3158 else if (!strcmp(str, "active"))
3159 default_driver = &intel_pstate;
3160 else if (!strcmp(str, "passive"))
3161 default_driver = &intel_cpufreq;
3162
3163 if (!strcmp(str, "no_hwp")) {
3164 pr_info("HWP disabled\n");
3165 no_hwp = 1;
3166 }
3167 if (!strcmp(str, "force"))
3168 force_load = 1;
3169 if (!strcmp(str, "hwp_only"))
3170 hwp_only = 1;
3171 if (!strcmp(str, "per_cpu_perf_limits"))
3172 per_cpu_limits = true;
3173
3174 #ifdef CONFIG_ACPI
3175 if (!strcmp(str, "support_acpi_ppc"))
3176 acpi_ppc = true;
3177 #endif
3178
3179 return 0;
3180 }
3181 early_param("intel_pstate", intel_pstate_setup);
3182
3183 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3184 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
3185 MODULE_LICENSE("GPL");
Linux with added FPC-III support