Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[linux/fpc-iii.git] / arch / arm / mach-at91 / at91sam926x_time.c
blob0f04ffe9c5a87c2afb4f90b02d75b86b70fd722b
1 /*
2 * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
4 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
5 * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
6 * Converted to ClockSource/ClockEvents by David Brownell.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/clk.h>
16 #include <linux/clockchips.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
21 #include <asm/mach/time.h>
23 #define AT91_PIT_MR 0x00 /* Mode Register */
24 #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
25 #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
26 #define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
28 #define AT91_PIT_SR 0x04 /* Status Register */
29 #define AT91_PIT_PITS (1 << 0) /* Timer Status */
31 #define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
32 #define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
33 #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
34 #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
36 #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
37 #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
39 static u32 pit_cycle; /* write-once */
40 static u32 pit_cnt; /* access only w/system irq blocked */
41 static void __iomem *pit_base_addr __read_mostly;
42 static struct clk *mck;
44 static inline unsigned int pit_read(unsigned int reg_offset)
46 return __raw_readl(pit_base_addr + reg_offset);
49 static inline void pit_write(unsigned int reg_offset, unsigned long value)
51 __raw_writel(value, pit_base_addr + reg_offset);
55 * Clocksource: just a monotonic counter of MCK/16 cycles.
56 * We don't care whether or not PIT irqs are enabled.
58 static cycle_t read_pit_clk(struct clocksource *cs)
60 unsigned long flags;
61 u32 elapsed;
62 u32 t;
64 raw_local_irq_save(flags);
65 elapsed = pit_cnt;
66 t = pit_read(AT91_PIT_PIIR);
67 raw_local_irq_restore(flags);
69 elapsed += PIT_PICNT(t) * pit_cycle;
70 elapsed += PIT_CPIV(t);
71 return elapsed;
74 static struct clocksource pit_clk = {
75 .name = "pit",
76 .rating = 175,
77 .read = read_pit_clk,
78 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
83 * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
85 static void
86 pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
88 switch (mode) {
89 case CLOCK_EVT_MODE_PERIODIC:
90 /* update clocksource counter */
91 pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
92 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
93 | AT91_PIT_PITIEN);
94 break;
95 case CLOCK_EVT_MODE_ONESHOT:
96 BUG();
97 /* FALLTHROUGH */
98 case CLOCK_EVT_MODE_SHUTDOWN:
99 case CLOCK_EVT_MODE_UNUSED:
100 /* disable irq, leaving the clocksource active */
101 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
102 break;
103 case CLOCK_EVT_MODE_RESUME:
104 break;
108 static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
110 /* Disable timer */
111 pit_write(AT91_PIT_MR, 0);
114 static void at91sam926x_pit_reset(void)
116 /* Disable timer and irqs */
117 pit_write(AT91_PIT_MR, 0);
119 /* Clear any pending interrupts, wait for PIT to stop counting */
120 while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
121 cpu_relax();
123 /* Start PIT but don't enable IRQ */
124 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
127 static void at91sam926x_pit_resume(struct clock_event_device *cedev)
129 at91sam926x_pit_reset();
132 static struct clock_event_device pit_clkevt = {
133 .name = "pit",
134 .features = CLOCK_EVT_FEAT_PERIODIC,
135 .shift = 32,
136 .rating = 100,
137 .set_mode = pit_clkevt_mode,
138 .suspend = at91sam926x_pit_suspend,
139 .resume = at91sam926x_pit_resume,
144 * IRQ handler for the timer.
146 static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
149 * irqs should be disabled here, but as the irq is shared they are only
150 * guaranteed to be off if the timer irq is registered first.
152 WARN_ON_ONCE(!irqs_disabled());
154 /* The PIT interrupt may be disabled, and is shared */
155 if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
156 && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
157 unsigned nr_ticks;
159 /* Get number of ticks performed before irq, and ack it */
160 nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
161 do {
162 pit_cnt += pit_cycle;
163 pit_clkevt.event_handler(&pit_clkevt);
164 nr_ticks--;
165 } while (nr_ticks);
167 return IRQ_HANDLED;
170 return IRQ_NONE;
173 static struct irqaction at91sam926x_pit_irq = {
174 .name = "at91_tick",
175 .flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
176 .handler = at91sam926x_pit_interrupt,
177 .irq = NR_IRQS_LEGACY + AT91_ID_SYS,
180 #ifdef CONFIG_OF
181 static struct of_device_id pit_timer_ids[] = {
182 { .compatible = "atmel,at91sam9260-pit" },
183 { /* sentinel */ }
186 static int __init of_at91sam926x_pit_init(void)
188 struct device_node *np;
189 int ret;
191 np = of_find_matching_node(NULL, pit_timer_ids);
192 if (!np)
193 goto err;
195 pit_base_addr = of_iomap(np, 0);
196 if (!pit_base_addr)
197 goto node_err;
199 mck = of_clk_get(np, 0);
201 /* Get the interrupts property */
202 ret = irq_of_parse_and_map(np, 0);
203 if (!ret) {
204 pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
205 if (!IS_ERR(mck))
206 clk_put(mck);
207 goto ioremap_err;
209 at91sam926x_pit_irq.irq = ret;
211 of_node_put(np);
213 return 0;
215 ioremap_err:
216 iounmap(pit_base_addr);
217 node_err:
218 of_node_put(np);
219 err:
220 return -EINVAL;
222 #else
223 static int __init of_at91sam926x_pit_init(void)
225 return -EINVAL;
227 #endif
230 * Set up both clocksource and clockevent support.
232 void __init at91sam926x_pit_init(void)
234 unsigned long pit_rate;
235 unsigned bits;
236 int ret;
238 mck = ERR_PTR(-ENOENT);
240 /* For device tree enabled device: initialize here */
241 of_at91sam926x_pit_init();
244 * Use our actual MCK to figure out how many MCK/16 ticks per
245 * 1/HZ period (instead of a compile-time constant LATCH).
247 if (IS_ERR(mck))
248 mck = clk_get(NULL, "mck");
250 if (IS_ERR(mck))
251 panic("AT91: PIT: Unable to get mck clk\n");
252 pit_rate = clk_get_rate(mck) / 16;
253 pit_cycle = (pit_rate + HZ/2) / HZ;
254 WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
256 /* Initialize and enable the timer */
257 at91sam926x_pit_reset();
260 * Register clocksource. The high order bits of PIV are unused,
261 * so this isn't a 32-bit counter unless we get clockevent irqs.
263 bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
264 pit_clk.mask = CLOCKSOURCE_MASK(bits);
265 clocksource_register_hz(&pit_clk, pit_rate);
267 /* Set up irq handler */
268 ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
269 if (ret)
270 pr_crit("AT91: PIT: Unable to setup IRQ\n");
272 /* Set up and register clockevents */
273 pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
274 pit_clkevt.cpumask = cpumask_of(0);
275 clockevents_register_device(&pit_clkevt);
278 void __init at91sam926x_ioremap_pit(u32 addr)
280 #if defined(CONFIG_OF)
281 struct device_node *np =
282 of_find_matching_node(NULL, pit_timer_ids);
284 if (np) {
285 of_node_put(np);
286 return;
288 #endif
289 pit_base_addr = ioremap(addr, 16);
291 if (!pit_base_addr)
292 panic("Impossible to ioremap PIT\n");