2 * Cavium Networks CNS3420 Validation Board
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
11 * This file is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License, Version 2, as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/compiler.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial_8250.h>
23 #include <linux/platform_device.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/physmap.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/usb/ehci_pdriver.h>
28 #include <linux/usb/ohci_pdriver.h>
29 #include <asm/setup.h>
30 #include <asm/mach-types.h>
31 #include <asm/mach/arch.h>
32 #include <asm/mach/map.h>
33 #include <asm/mach/time.h>
42 static struct mtd_partition cns3420_nor_partitions
[] = {
47 .mask_flags
= MTD_WRITEABLE
,
51 .offset
= MTDPART_OFS_APPEND
,
55 .offset
= MTDPART_OFS_APPEND
,
57 .name
= "filesystem2",
59 .offset
= MTDPART_OFS_APPEND
,
62 .size
= MTDPART_SIZ_FULL
,
63 .offset
= MTDPART_OFS_APPEND
,
67 static struct physmap_flash_data cns3420_nor_pdata
= {
69 .parts
= cns3420_nor_partitions
,
70 .nr_parts
= ARRAY_SIZE(cns3420_nor_partitions
),
73 static struct resource cns3420_nor_res
= {
74 .start
= CNS3XXX_FLASH_BASE
,
75 .end
= CNS3XXX_FLASH_BASE
+ SZ_128M
- 1,
76 .flags
= IORESOURCE_MEM
| IORESOURCE_MEM_32BIT
,
79 static struct platform_device cns3420_nor_pdev
= {
80 .name
= "physmap-flash",
82 .resource
= &cns3420_nor_res
,
85 .platform_data
= &cns3420_nor_pdata
,
92 static void __init
cns3420_early_serial_setup(void)
94 #ifdef CONFIG_SERIAL_8250_CONSOLE
95 static struct uart_port cns3420_serial_port
= {
96 .membase
= (void __iomem
*)CNS3XXX_UART0_BASE_VIRT
,
97 .mapbase
= CNS3XXX_UART0_BASE
,
98 .irq
= IRQ_CNS3XXX_UART0
,
100 .flags
= UPF_BOOT_AUTOCONF
| UPF_FIXED_TYPE
,
108 early_serial_setup(&cns3420_serial_port
);
115 static struct resource cns3xxx_usb_ehci_resources
[] = {
117 .start
= CNS3XXX_USB_BASE
,
118 .end
= CNS3XXX_USB_BASE
+ SZ_16M
- 1,
119 .flags
= IORESOURCE_MEM
,
122 .start
= IRQ_CNS3XXX_USB_EHCI
,
123 .flags
= IORESOURCE_IRQ
,
127 static u64 cns3xxx_usb_ehci_dma_mask
= DMA_BIT_MASK(32);
129 static int csn3xxx_usb_power_on(struct platform_device
*pdev
)
132 * EHCI and OHCI share the same clock and power,
133 * resetting twice would cause the 1st controller been reset.
134 * Therefore only do power up at the first up device, and
135 * power down at the last down device.
137 * Set USB AHB INCR length to 16
139 if (atomic_inc_return(&usb_pwr_ref
) == 1) {
140 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB
);
141 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST
);
142 cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST
);
143 __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG
) | (0X2 << 24)),
144 MISC_CHIP_CONFIG_REG
);
150 static void csn3xxx_usb_power_off(struct platform_device
*pdev
)
153 * EHCI and OHCI share the same clock and power,
154 * resetting twice would cause the 1st controller been reset.
155 * Therefore only do power up at the first up device, and
156 * power down at the last down device.
158 if (atomic_dec_return(&usb_pwr_ref
) == 0)
159 cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST
);
162 static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata
= {
163 .power_on
= csn3xxx_usb_power_on
,
164 .power_off
= csn3xxx_usb_power_off
,
167 static struct platform_device cns3xxx_usb_ehci_device
= {
168 .name
= "ehci-platform",
169 .num_resources
= ARRAY_SIZE(cns3xxx_usb_ehci_resources
),
170 .resource
= cns3xxx_usb_ehci_resources
,
172 .dma_mask
= &cns3xxx_usb_ehci_dma_mask
,
173 .coherent_dma_mask
= DMA_BIT_MASK(32),
174 .platform_data
= &cns3xxx_usb_ehci_pdata
,
178 static struct resource cns3xxx_usb_ohci_resources
[] = {
180 .start
= CNS3XXX_USB_OHCI_BASE
,
181 .end
= CNS3XXX_USB_OHCI_BASE
+ SZ_16M
- 1,
182 .flags
= IORESOURCE_MEM
,
185 .start
= IRQ_CNS3XXX_USB_OHCI
,
186 .flags
= IORESOURCE_IRQ
,
190 static u64 cns3xxx_usb_ohci_dma_mask
= DMA_BIT_MASK(32);
192 static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata
= {
194 .power_on
= csn3xxx_usb_power_on
,
195 .power_off
= csn3xxx_usb_power_off
,
198 static struct platform_device cns3xxx_usb_ohci_device
= {
199 .name
= "ohci-platform",
200 .num_resources
= ARRAY_SIZE(cns3xxx_usb_ohci_resources
),
201 .resource
= cns3xxx_usb_ohci_resources
,
203 .dma_mask
= &cns3xxx_usb_ohci_dma_mask
,
204 .coherent_dma_mask
= DMA_BIT_MASK(32),
205 .platform_data
= &cns3xxx_usb_ohci_pdata
,
212 static struct platform_device
*cns3420_pdevs
[] __initdata
= {
214 &cns3xxx_usb_ehci_device
,
215 &cns3xxx_usb_ohci_device
,
218 static void __init
cns3420_init(void)
222 platform_add_devices(cns3420_pdevs
, ARRAY_SIZE(cns3420_pdevs
));
225 cns3xxx_sdhci_init();
227 pm_power_off
= cns3xxx_power_off
;
230 static struct map_desc cns3420_io_desc
[] __initdata
= {
232 .virtual = CNS3XXX_UART0_BASE_VIRT
,
233 .pfn
= __phys_to_pfn(CNS3XXX_UART0_BASE
),
239 static void __init
cns3420_map_io(void)
242 iotable_init(cns3420_io_desc
, ARRAY_SIZE(cns3420_io_desc
));
244 cns3420_early_serial_setup();
247 MACHINE_START(CNS3420VB
, "Cavium Networks CNS3420 Validation Board")
248 .atag_offset
= 0x100,
249 .nr_irqs
= NR_IRQS_CNS3XXX
,
250 .map_io
= cns3420_map_io
,
251 .init_irq
= cns3xxx_init_irq
,
252 .init_time
= cns3xxx_timer_init
,
253 .init_machine
= cns3420_init
,
254 .restart
= cns3xxx_restart
,