arch/arm/mach-hisi/hotplug.c

   1 /*
   2  * Copyright (c) 2013 Linaro Ltd.
   3  * Copyright (c) 2013 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/cpu.h>
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_platform.h>
  15 #include <asm/cacheflush.h>
  16 #include <asm/smp_plat.h>
  17 #include "core.h"
  18
  19 /* Sysctrl registers in Hi3620 SoC */
  20 #define SCISOEN                         0xc0
  21 #define SCISODIS                        0xc4
  22 #define SCPERPWREN                      0xd0
  23 #define SCPERPWRDIS                     0xd4
  24 #define SCCPUCOREEN                     0xf4
  25 #define SCCPUCOREDIS                    0xf8
  26 #define SCPERCTRL0                      0x200
  27 #define SCCPURSTEN                      0x410
  28 #define SCCPURSTDIS                     0x414
  29
  30 /*
  31  * bit definition in SCISOEN/SCPERPWREN/...
  32  *
  33  * CPU2_ISO_CTRL        (1 << 5)
  34  * CPU3_ISO_CTRL        (1 << 6)
  35  * ...
  36  */
  37 #define CPU2_ISO_CTRL                   (1 << 5)
  38
  39 /*
  40  * bit definition in SCPERCTRL0
  41  *
  42  * CPU0_WFI_MASK_CFG    (1 << 28)
  43  * CPU1_WFI_MASK_CFG    (1 << 29)
  44  * ...
  45  */
  46 #define CPU0_WFI_MASK_CFG               (1 << 28)
  47
  48 /*
  49  * bit definition in SCCPURSTEN/...
  50  *
  51  * CPU0_SRST_REQ_EN     (1 << 0)
  52  * CPU1_SRST_REQ_EN     (1 << 1)
  53  * ...
  54  */
  55 #define CPU0_HPM_SRST_REQ_EN            (1 << 22)
  56 #define CPU0_DBG_SRST_REQ_EN            (1 << 12)
  57 #define CPU0_NEON_SRST_REQ_EN           (1 << 4)
  58 #define CPU0_SRST_REQ_EN                (1 << 0)
  59
  60 enum {
  61         HI3620_CTRL,
  62         ERROR_CTRL,
  63 };
  64
  65 static void __iomem *ctrl_base;
  66 static int id;
  67
  68 static void set_cpu_hi3620(int cpu, bool enable)
  69 {
  70         u32 val = 0;
  71
  72         if (enable) {
  73                 /* MTCMOS set */
  74                 if ((cpu == 2) || (cpu == 3))
  75                         writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
  76                                        ctrl_base + SCPERPWREN);
  77                 udelay(100);
  78
  79                 /* Enable core */
  80                 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
  81
  82                 /* unreset */
  83                 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
  84                         | CPU0_SRST_REQ_EN;
  85                 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
  86                 /* reset */
  87                 val |= CPU0_HPM_SRST_REQ_EN;
  88                 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
  89
  90                 /* ISO disable */
  91                 if ((cpu == 2) || (cpu == 3))
  92                         writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
  93                                        ctrl_base + SCISODIS);
  94                 udelay(1);
  95
  96                 /* WFI Mask */
  97                 val = readl_relaxed(ctrl_base + SCPERCTRL0);
  98                 val &= ~(CPU0_WFI_MASK_CFG << cpu);
  99                 writel_relaxed(val, ctrl_base + SCPERCTRL0);
 100
 101                 /* Unreset */
 102                 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
 103                         | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
 104                 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
 105         } else {
 106                 /* wfi mask */
 107                 val = readl_relaxed(ctrl_base + SCPERCTRL0);
 108                 val |= (CPU0_WFI_MASK_CFG << cpu);
 109                 writel_relaxed(val, ctrl_base + SCPERCTRL0);
 110
 111                 /* disable core*/
 112                 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
 113
 114                 if ((cpu == 2) || (cpu == 3)) {
 115                         /* iso enable */
 116                         writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
 117                                        ctrl_base + SCISOEN);
 118                         udelay(1);
 119                 }
 120
 121                 /* reset */
 122                 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
 123                         | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
 124                 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
 125
 126                 if ((cpu == 2) || (cpu == 3)) {
 127                         /* MTCMOS unset */
 128                         writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
 129                                        ctrl_base + SCPERPWRDIS);
 130                         udelay(100);
 131                 }
 132         }
 133 }
 134
 135 static int hi3xxx_hotplug_init(void)
 136 {
 137         struct device_node *node;
 138
 139         node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
 140         if (node) {
 141                 ctrl_base = of_iomap(node, 0);
 142                 id = HI3620_CTRL;
 143                 return 0;
 144         }
 145         id = ERROR_CTRL;
 146         return -ENOENT;
 147 }
 148
 149 void hi3xxx_set_cpu(int cpu, bool enable)
 150 {
 151         if (!ctrl_base) {
 152                 if (hi3xxx_hotplug_init() < 0)
 153                         return;
 154         }
 155
 156         if (id == HI3620_CTRL)
 157                 set_cpu_hi3620(cpu, enable);
 158 }
 159
 160 static inline void cpu_enter_lowpower(void)
 161 {
 162         unsigned int v;
 163
 164         flush_cache_all();
 165
 166         /*
 167          * Turn off coherency and L1 D-cache
 168          */
 169         asm volatile(
 170         "       mrc     p15, 0, %0, c1, c0, 1\n"
 171         "       bic     %0, %0, #0x40\n"
 172         "       mcr     p15, 0, %0, c1, c0, 1\n"
 173         "       mrc     p15, 0, %0, c1, c0, 0\n"
 174         "       bic     %0, %0, #0x04\n"
 175         "       mcr     p15, 0, %0, c1, c0, 0\n"
 176           : "=&r" (v)
 177           : "r" (0)
 178           : "cc");
 179 }
 180
 181 void hi3xxx_cpu_die(unsigned int cpu)
 182 {
 183         cpu_enter_lowpower();
 184         hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));
 185         cpu_do_idle();
 186
 187         /* We should have never returned from idle */
 188         panic("cpu %d unexpectedly exit from shutdown\n", cpu);
 189 }
 190
 191 int hi3xxx_cpu_kill(unsigned int cpu)
 192 {
 193         unsigned long timeout = jiffies + msecs_to_jiffies(50);
 194
 195         while (hi3xxx_get_cpu_jump(cpu))
 196                 if (time_after(jiffies, timeout))
 197                         return 0;
 198         hi3xxx_set_cpu(cpu, false);
 199         return 1;
 200 }