arch/arm/mach-integrator/core.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/core.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2, as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/device.h>
  14 #include <linux/export.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18 #include <linux/memblock.h>
  19 #include <linux/sched.h>
  20 #include <linux/smp.h>
  21 #include <linux/amba/bus.h>
  22 #include <linux/amba/serial.h>
  23 #include <linux/io.h>
  24 #include <linux/stat.h>
  25 #include <linux/of.h>
  26 #include <linux/of_address.h>
  27
  28 #include <mach/hardware.h>
  29 #include <mach/platform.h>
  30
  31 #include <asm/mach-types.h>
  32 #include <asm/mach/time.h>
  33 #include <asm/pgtable.h>
  34
  35 #include "cm.h"
  36 #include "common.h"
  37
  38 static DEFINE_RAW_SPINLOCK(cm_lock);
  39 static void __iomem *cm_base;
  40
  41 /**
  42  * cm_get - get the value from the CM_CTRL register
  43  */
  44 u32 cm_get(void)
  45 {
  46         return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET);
  47 }
  48
  49 /**
  50  * cm_control - update the CM_CTRL register.
  51  * @mask: bits to change
  52  * @set: bits to set
  53  */
  54 void cm_control(u32 mask, u32 set)
  55 {
  56         unsigned long flags;
  57         u32 val;
  58
  59         raw_spin_lock_irqsave(&cm_lock, flags);
  60         val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask;
  61         writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET);
  62         raw_spin_unlock_irqrestore(&cm_lock, flags);
  63 }
  64
  65 static const char *integrator_arch_str(u32 id)
  66 {
  67         switch ((id >> 16) & 0xff) {
  68         case 0x00:
  69                 return "ASB little-endian";
  70         case 0x01:
  71                 return "AHB little-endian";
  72         case 0x03:
  73                 return "AHB-Lite system bus, bi-endian";
  74         case 0x04:
  75                 return "AHB";
  76         case 0x08:
  77                 return "AHB system bus, ASB processor bus";
  78         default:
  79                 return "Unknown";
  80         }
  81 }
  82
  83 static const char *integrator_fpga_str(u32 id)
  84 {
  85         switch ((id >> 12) & 0xf) {
  86         case 0x01:
  87                 return "XC4062";
  88         case 0x02:
  89                 return "XC4085";
  90         case 0x03:
  91                 return "XVC600";
  92         case 0x04:
  93                 return "EPM7256AE (Altera PLD)";
  94         default:
  95                 return "Unknown";
  96         }
  97 }
  98
  99 void cm_clear_irqs(void)
 100 {
 101         /* disable core module IRQs */
 102         writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET +
 103                 IRQ_ENABLE_CLEAR);
 104 }
 105
 106 static const struct of_device_id cm_match[] = {
 107         { .compatible = "arm,core-module-integrator"},
 108         { },
 109 };
 110
 111 void cm_init(void)
 112 {
 113         struct device_node *cm = of_find_matching_node(NULL, cm_match);
 114         u32 val;
 115
 116         if (!cm) {
 117                 pr_crit("no core module node found in device tree\n");
 118                 return;
 119         }
 120         cm_base = of_iomap(cm, 0);
 121         if (!cm_base) {
 122                 pr_crit("could not remap core module\n");
 123                 return;
 124         }
 125         cm_clear_irqs();
 126         val = readl(cm_base + INTEGRATOR_HDR_ID_OFFSET);
 127         pr_info("Detected ARM core module:\n");
 128         pr_info("    Manufacturer: %02x\n", (val >> 24));
 129         pr_info("    Architecture: %s\n", integrator_arch_str(val));
 130         pr_info("    FPGA: %s\n", integrator_fpga_str(val));
 131         pr_info("    Build: %02x\n", (val >> 4) & 0xFF);
 132         pr_info("    Rev: %c\n", ('A' + (val & 0x03)));
 133 }
 134
 135 /*
 136  * We need to stop things allocating the low memory; ideally we need a
 137  * better implementation of GFP_DMA which does not assume that DMA-able
 138  * memory starts at zero.
 139  */
 140 void __init integrator_reserve(void)
 141 {
 142         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 143 }
 144
 145 /*
 146  * To reset, we hit the on-board reset register in the system FPGA
 147  */
 148 void integrator_restart(enum reboot_mode mode, const char *cmd)
 149 {
 150         cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 151 }
 152
 153 static u32 integrator_id;
 154
 155 static ssize_t intcp_get_manf(struct device *dev,
 156                               struct device_attribute *attr,
 157                               char *buf)
 158 {
 159         return sprintf(buf, "%02x\n", integrator_id >> 24);
 160 }
 161
 162 static struct device_attribute intcp_manf_attr =
 163         __ATTR(manufacturer,  S_IRUGO, intcp_get_manf,  NULL);
 164
 165 static ssize_t intcp_get_arch(struct device *dev,
 166                               struct device_attribute *attr,
 167                               char *buf)
 168 {
 169         return sprintf(buf, "%s\n", integrator_arch_str(integrator_id));
 170 }
 171
 172 static struct device_attribute intcp_arch_attr =
 173         __ATTR(architecture,  S_IRUGO, intcp_get_arch,  NULL);
 174
 175 static ssize_t intcp_get_fpga(struct device *dev,
 176                               struct device_attribute *attr,
 177                               char *buf)
 178 {
 179         return sprintf(buf, "%s\n", integrator_fpga_str(integrator_id));
 180 }
 181
 182 static struct device_attribute intcp_fpga_attr =
 183         __ATTR(fpga,  S_IRUGO, intcp_get_fpga,  NULL);
 184
 185 static ssize_t intcp_get_build(struct device *dev,
 186                                struct device_attribute *attr,
 187                                char *buf)
 188 {
 189         return sprintf(buf, "%02x\n", (integrator_id >> 4) & 0xFF);
 190 }
 191
 192 static struct device_attribute intcp_build_attr =
 193         __ATTR(build,  S_IRUGO, intcp_get_build,  NULL);
 194
 195
 196
 197 void integrator_init_sysfs(struct device *parent, u32 id)
 198 {
 199         integrator_id = id;
 200         device_create_file(parent, &intcp_manf_attr);
 201         device_create_file(parent, &intcp_arch_attr);
 202         device_create_file(parent, &intcp_fpga_attr);
 203         device_create_file(parent, &intcp_build_attr);
 204 }