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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[linux/fpc-iii.git] / arch / arm / mach-integrator / pci_v3.c
blobc5e01b24d9fb37215deb8988d5bebcf454a252b9
1 /*
2 * linux/arch/arm/mach-integrator/pci_v3.c
3 *
4 * PCI functions for V3 host PCI bridge
5 *
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/ioport.h>
26 #include <linux/interrupt.h>
27 #include <linux/spinlock.h>
28 #include <linux/init.h>
29 #include <linux/io.h>
30 #include <linux/platform_device.h>
31 #include <linux/of.h>
32 #include <linux/of_address.h>
33 #include <linux/of_irq.h>
34 #include <linux/of_pci.h>
35 #include <video/vga.h>
36
37 #include <mach/hardware.h>
38 #include <mach/platform.h>
39
40 #include <asm/mach/map.h>
41 #include <asm/signal.h>
42 #include <asm/mach/pci.h>
43 #include <asm/irq_regs.h>
44
45 #include "pci_v3.h"
46
47 /*
48 * Where in the memory map does PCI live?
49 *
50 * This represents a fairly liberal usage of address space. Even though
51 * the V3 only has two windows (therefore we need to map stuff on the fly),
52 * we maintain the same addresses, even if they're not mapped.
53 */
54 #define PHYS_PCI_MEM_BASE 0x40000000 /* 256M */
55 #define PHYS_PCI_PRE_BASE 0x50000000 /* 256M */
56 #define PHYS_PCI_IO_BASE 0x60000000 /* 16M */
57 #define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M */
58 #define PHYS_PCI_V3_BASE 0x62000000 /* 64K */
59
60 #define PCI_MEMORY_VADDR IOMEM(0xe8000000)
61 #define PCI_CONFIG_VADDR IOMEM(0xec000000)
62
63 /*
64 * V3 Local Bus to PCI Bridge definitions
65 *
66 * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
67 * All V3 register names are prefaced by V3_ to avoid clashing with any other
68 * PCI definitions. Their names match the user's manual.
69 *
70 * I'm assuming that I20 is disabled.
71 *
72 */
73 #define V3_PCI_VENDOR 0x00000000
74 #define V3_PCI_DEVICE 0x00000002
75 #define V3_PCI_CMD 0x00000004
76 #define V3_PCI_STAT 0x00000006
77 #define V3_PCI_CC_REV 0x00000008
78 #define V3_PCI_HDR_CFG 0x0000000C
79 #define V3_PCI_IO_BASE 0x00000010
80 #define V3_PCI_BASE0 0x00000014
81 #define V3_PCI_BASE1 0x00000018
82 #define V3_PCI_SUB_VENDOR 0x0000002C
83 #define V3_PCI_SUB_ID 0x0000002E
84 #define V3_PCI_ROM 0x00000030
85 #define V3_PCI_BPARAM 0x0000003C
86 #define V3_PCI_MAP0 0x00000040
87 #define V3_PCI_MAP1 0x00000044
88 #define V3_PCI_INT_STAT 0x00000048
89 #define V3_PCI_INT_CFG 0x0000004C
90 #define V3_LB_BASE0 0x00000054
91 #define V3_LB_BASE1 0x00000058
92 #define V3_LB_MAP0 0x0000005E
93 #define V3_LB_MAP1 0x00000062
94 #define V3_LB_BASE2 0x00000064
95 #define V3_LB_MAP2 0x00000066
96 #define V3_LB_SIZE 0x00000068
97 #define V3_LB_IO_BASE 0x0000006E
98 #define V3_FIFO_CFG 0x00000070
99 #define V3_FIFO_PRIORITY 0x00000072
100 #define V3_FIFO_STAT 0x00000074
101 #define V3_LB_ISTAT 0x00000076
102 #define V3_LB_IMASK 0x00000077
103 #define V3_SYSTEM 0x00000078
104 #define V3_LB_CFG 0x0000007A
105 #define V3_PCI_CFG 0x0000007C
106 #define V3_DMA_PCI_ADR0 0x00000080
107 #define V3_DMA_PCI_ADR1 0x00000090
108 #define V3_DMA_LOCAL_ADR0 0x00000084
109 #define V3_DMA_LOCAL_ADR1 0x00000094
110 #define V3_DMA_LENGTH0 0x00000088
111 #define V3_DMA_LENGTH1 0x00000098
112 #define V3_DMA_CSR0 0x0000008B
113 #define V3_DMA_CSR1 0x0000009B
114 #define V3_DMA_CTLB_ADR0 0x0000008C
115 #define V3_DMA_CTLB_ADR1 0x0000009C
116 #define V3_DMA_DELAY 0x000000E0
117 #define V3_MAIL_DATA 0x000000C0
118 #define V3_PCI_MAIL_IEWR 0x000000D0
119 #define V3_PCI_MAIL_IERD 0x000000D2
120 #define V3_LB_MAIL_IEWR 0x000000D4
121 #define V3_LB_MAIL_IERD 0x000000D6
122 #define V3_MAIL_WR_STAT 0x000000D8
123 #define V3_MAIL_RD_STAT 0x000000DA
124 #define V3_QBA_MAP 0x000000DC
125
126 /* PCI COMMAND REGISTER bits
127 */
128 #define V3_COMMAND_M_FBB_EN (1 << 9)
129 #define V3_COMMAND_M_SERR_EN (1 << 8)
130 #define V3_COMMAND_M_PAR_EN (1 << 6)
131 #define V3_COMMAND_M_MASTER_EN (1 << 2)
132 #define V3_COMMAND_M_MEM_EN (1 << 1)
133 #define V3_COMMAND_M_IO_EN (1 << 0)
134
135 /* SYSTEM REGISTER bits
136 */
137 #define V3_SYSTEM_M_RST_OUT (1 << 15)
138 #define V3_SYSTEM_M_LOCK (1 << 14)
139
140 /* PCI_CFG bits
141 */
142 #define V3_PCI_CFG_M_I2O_EN (1 << 15)
143 #define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
144 #define V3_PCI_CFG_M_IO_DIS (1 << 13)
145 #define V3_PCI_CFG_M_EN3V (1 << 12)
146 #define V3_PCI_CFG_M_RETRY_EN (1 << 10)
147 #define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
148 #define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
149
150 /* PCI_BASE register bits (PCI -> Local Bus)
151 */
152 #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
153 #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
154 #define V3_PCI_BASE_M_PREFETCH (1 << 3)
155 #define V3_PCI_BASE_M_TYPE (3 << 1)
156 #define V3_PCI_BASE_M_IO (1 << 0)
157
158 /* PCI MAP register bits (PCI -> Local bus)
159 */
160 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
161 #define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
162 #define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
163 #define V3_PCI_MAP_M_SWAP (3 << 8)
164 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
165 #define V3_PCI_MAP_M_REG_EN (1 << 1)
166 #define V3_PCI_MAP_M_ENABLE (1 << 0)
167
168 /*
169 * LB_BASE0,1 register bits (Local bus -> PCI)
170 */
171 #define V3_LB_BASE_ADR_BASE 0xfff00000
172 #define V3_LB_BASE_SWAP (3 << 8)
173 #define V3_LB_BASE_ADR_SIZE (15 << 4)
174 #define V3_LB_BASE_PREFETCH (1 << 3)
175 #define V3_LB_BASE_ENABLE (1 << 0)
176
177 #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
178 #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
179 #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
180 #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
181 #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
182 #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
183 #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
184 #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
185 #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
186 #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
187 #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
188 #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
189
190 #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
191
192 /*
193 * LB_MAP0,1 register bits (Local bus -> PCI)
194 */
195 #define V3_LB_MAP_MAP_ADR 0xfff0
196 #define V3_LB_MAP_TYPE (7 << 1)
197 #define V3_LB_MAP_AD_LOW_EN (1 << 0)
198
199 #define V3_LB_MAP_TYPE_IACK (0 << 1)
200 #define V3_LB_MAP_TYPE_IO (1 << 1)
201 #define V3_LB_MAP_TYPE_MEM (3 << 1)
202 #define V3_LB_MAP_TYPE_CONFIG (5 << 1)
203 #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
204
205 #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
206
207 /*
208 * LB_BASE2 register bits (Local bus -> PCI IO)
209 */
210 #define V3_LB_BASE2_ADR_BASE 0xff00
211 #define V3_LB_BASE2_SWAP (3 << 6)
212 #define V3_LB_BASE2_ENABLE (1 << 0)
213
214 #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
215
216 /*
217 * LB_MAP2 register bits (Local bus -> PCI IO)
218 */
219 #define V3_LB_MAP2_MAP_ADR 0xff00
220
221 #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
222
223 /*
224 * The V3 PCI interface chip in Integrator provides several windows from
225 * local bus memory into the PCI memory areas. Unfortunately, there
226 * are not really enough windows for our usage, therefore we reuse
227 * one of the windows for access to PCI configuration space. The
228 * memory map is as follows:
229 *
230 * Local Bus Memory Usage
231 *
232 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
233 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
234 * 60000000 - 60FFFFFF PCI IO. 16M
235 * 61000000 - 61FFFFFF PCI Configuration. 16M
236 *
237 * There are three V3 windows, each described by a pair of V3 registers.
238 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
239 * Base0 and Base1 can be used for any type of PCI memory access. Base2
240 * can be used either for PCI I/O or for I20 accesses. By default, uHAL
241 * uses this only for PCI IO space.
242 *
243 * Normally these spaces are mapped using the following base registers:
244 *
245 * Usage Local Bus Memory Base/Map registers used
246 *
247 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
248 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
249 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
250 * Cfg 61000000 - 61FFFFFF
251 *
252 * This means that I20 and PCI configuration space accesses will fail.
253 * When PCI configuration accesses are needed (via the uHAL PCI
254 * configuration space primitives) we must remap the spaces as follows:
255 *
256 * Usage Local Bus Memory Base/Map registers used
257 *
258 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
259 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
260 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
261 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
262 *
263 * To make this work, the code depends on overlapping windows working.
264 * The V3 chip translates an address by checking its range within
265 * each of the BASE/MAP pairs in turn (in ascending register number
266 * order). It will use the first matching pair. So, for example,
267 * if the same address is mapped by both LB_BASE0/LB_MAP0 and
268 * LB_BASE1/LB_MAP1, the V3 will use the translation from
269 * LB_BASE0/LB_MAP0.
270 *
271 * To allow PCI Configuration space access, the code enlarges the
272 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
273 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
274 * be remapped for use by configuration cycles.
275 *
276 * At the end of the PCI Configuration space accesses,
277 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
278 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
279 * reveal the now restored LB_BASE1/LB_MAP1 window.
280 *
281 * NOTE: We do not set up I2O mapping. I suspect that this is only
282 * for an intelligent (target) device. Using I2O disables most of
283 * the mappings into PCI memory.
284 */
285
286 /* Filled in by probe */
287 static void __iomem *pci_v3_base;
288 /* CPU side memory ranges */
289 static struct resource conf_mem; /* FIXME: remap this instead of static map */
290 static struct resource io_mem;
291 static struct resource non_mem;
292 static struct resource pre_mem;
293 /* PCI side memory ranges */
294 static u64 non_mem_pci;
295 static u64 non_mem_pci_sz;
296 static u64 pre_mem_pci;
297 static u64 pre_mem_pci_sz;
298
299 // V3 access routines
300 #define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o))
301 #define v3_readb(o) (__raw_readb(pci_v3_base + (unsigned int)(o)))
302
303 #define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o))
304 #define v3_readw(o) (__raw_readw(pci_v3_base + (unsigned int)(o)))
305
306 #define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o))
307 #define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o)))
308
309 /*============================================================================
310 *
311 * routine: uHALir_PCIMakeConfigAddress()
312 *
313 * parameters: bus = which bus
314 * device = which device
315 * function = which function
316 * offset = configuration space register we are interested in
317 *
318 * description: this routine will generate a platform dependent config
319 * address.
320 *
321 * calls: none
322 *
323 * returns: configuration address to play on the PCI bus
324 *
325 * To generate the appropriate PCI configuration cycles in the PCI
326 * configuration address space, you present the V3 with the following pattern
327 * (which is very nearly a type 1 (except that the lower two bits are 00 and
328 * not 01). In order for this mapping to work you need to set up one of
329 * the local to PCI aperatures to 16Mbytes in length translating to
330 * PCI configuration space starting at 0x0000.0000.
331 *
332 * PCI configuration cycles look like this:
333 *
334 * Type 0:
335 *
336 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
337 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
338 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
339 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
340 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
341 *
342 * 31:11 Device select bit.
343 * 10:8 Function number
344 * 7:2 Register number
345 *
346 * Type 1:
347 *
348 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
349 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
350 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
351 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
352 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
353 *
354 * 31:24 reserved
355 * 23:16 bus number (8 bits = 128 possible buses)
356 * 15:11 Device number (5 bits)
357 * 10:8 function number
358 * 7:2 register number
359 *
360 */
361 static DEFINE_RAW_SPINLOCK(v3_lock);
362
363 #undef V3_LB_BASE_PREFETCH
364 #define V3_LB_BASE_PREFETCH 0
365
366 static void __iomem *v3_open_config_window(struct pci_bus *bus,
367 unsigned int devfn, int offset)
368 {
369 unsigned int address, mapaddress, busnr;
370
371 busnr = bus->number;
372
373 /*
374 * Trap out illegal values
375 */
376 BUG_ON(offset > 255);
377 BUG_ON(busnr > 255);
378 BUG_ON(devfn > 255);
379
380 if (busnr == 0) {
381 int slot = PCI_SLOT(devfn);
382
383 /*
384 * local bus segment so need a type 0 config cycle
385 *
386 * build the PCI configuration "address" with one-hot in
387 * A31-A11
388 *
389 * mapaddress:
390 * 3:1 = config cycle (101)
391 * 0 = PCI A1 & A0 are 0 (0)
392 */
393 address = PCI_FUNC(devfn) << 8;
394 mapaddress = V3_LB_MAP_TYPE_CONFIG;
395
396 if (slot > 12)
397 /*
398 * high order bits are handled by the MAP register
399 */
400 mapaddress |= 1 << (slot - 5);
401 else
402 /*
403 * low order bits handled directly in the address
404 */
405 address |= 1 << (slot + 11);
406 } else {
407 /*
408 * not the local bus segment so need a type 1 config cycle
409 *
410 * address:
411 * 23:16 = bus number
412 * 15:11 = slot number (7:3 of devfn)
413 * 10:8 = func number (2:0 of devfn)
414 *
415 * mapaddress:
416 * 3:1 = config cycle (101)
417 * 0 = PCI A1 & A0 from host bus (1)
418 */
419 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
420 address = (busnr << 16) | (devfn << 8);
421 }
422
423 /*
424 * Set up base0 to see all 512Mbytes of memory space (not
425 * prefetchable), this frees up base1 for re-use by
426 * configuration memory
427 */
428 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
429 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
430
431 /*
432 * Set up base1/map1 to point into configuration space.
433 */
434 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) |
435 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
436 v3_writew(V3_LB_MAP1, mapaddress);
437
438 return PCI_CONFIG_VADDR + address + offset;
439 }
440
441 static void v3_close_config_window(void)
442 {
443 /*
444 * Reassign base1 for use by prefetchable PCI memory
445 */
446 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
447 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
448 V3_LB_BASE_ENABLE);
449 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
450 V3_LB_MAP_TYPE_MEM_MULTIPLE);
451
452 /*
453 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
454 */
455 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
456 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
457 }
458
459 static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
460 int size, u32 *val)
461 {
462 void __iomem *addr;
463 unsigned long flags;
464 u32 v;
465
466 raw_spin_lock_irqsave(&v3_lock, flags);
467 addr = v3_open_config_window(bus, devfn, where);
468
469 switch (size) {
470 case 1:
471 v = __raw_readb(addr);
472 break;
473
474 case 2:
475 v = __raw_readw(addr);
476 break;
477
478 default:
479 v = __raw_readl(addr);
480 break;
481 }
482
483 v3_close_config_window();
484 raw_spin_unlock_irqrestore(&v3_lock, flags);
485
486 *val = v;
487 return PCIBIOS_SUCCESSFUL;
488 }
489
490 static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
491 int size, u32 val)
492 {
493 void __iomem *addr;
494 unsigned long flags;
495
496 raw_spin_lock_irqsave(&v3_lock, flags);
497 addr = v3_open_config_window(bus, devfn, where);
498
499 switch (size) {
500 case 1:
501 __raw_writeb((u8)val, addr);
502 __raw_readb(addr);
503 break;
504
505 case 2:
506 __raw_writew((u16)val, addr);
507 __raw_readw(addr);
508 break;
509
510 case 4:
511 __raw_writel(val, addr);
512 __raw_readl(addr);
513 break;
514 }
515
516 v3_close_config_window();
517 raw_spin_unlock_irqrestore(&v3_lock, flags);
518
519 return PCIBIOS_SUCCESSFUL;
520 }
521
522 static struct pci_ops pci_v3_ops = {
523 .read = v3_read_config,
524 .write = v3_write_config,
525 };
526
527 static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
528 {
529 if (request_resource(&iomem_resource, &non_mem)) {
530 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
531 "memory region\n");
532 return -EBUSY;
533 }
534 if (request_resource(&iomem_resource, &pre_mem)) {
535 release_resource(&non_mem);
536 printk(KERN_ERR "PCI: unable to allocate prefetchable "
537 "memory region\n");
538 return -EBUSY;
539 }
540
541 /*
542 * the mem resource for this bus
543 * the prefetch mem resource for this bus
544 */
545 pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
546 pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
547
548 return 1;
549 }
550
551 /*
552 * These don't seem to be implemented on the Integrator I have, which
553 * means I can't get additional information on the reason for the pm2fb
554 * problems. I suppose I'll just have to mind-meld with the machine. ;)
555 */
556 static void __iomem *ap_syscon_base;
557 #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
558 #define INTEGRATOR_SC_LBFADDR_OFFSET 0x20
559 #define INTEGRATOR_SC_LBFCODE_OFFSET 0x24
560
561 static int
562 v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
563 {
564 unsigned long pc = instruction_pointer(regs);
565 unsigned long instr = *(unsigned long *)pc;
566 #if 0
567 char buf[128];
568
569 sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
570 addr, fsr, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
571 v3_readb(V3_LB_ISTAT));
572 printk(KERN_DEBUG "%s", buf);
573 #endif
574
575 v3_writeb(V3_LB_ISTAT, 0);
576 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
577
578 /*
579 * If the instruction being executed was a read,
580 * make it look like it read all-ones.
581 */
582 if ((instr & 0x0c100000) == 0x04100000) {
583 int reg = (instr >> 12) & 15;
584 unsigned long val;
585
586 if (instr & 0x00400000)
587 val = 255;
588 else
589 val = -1;
590
591 regs->uregs[reg] = val;
592 regs->ARM_pc += 4;
593 return 0;
594 }
595
596 if ((instr & 0x0e100090) == 0x00100090) {
597 int reg = (instr >> 12) & 15;
598
599 regs->uregs[reg] = -1;
600 regs->ARM_pc += 4;
601 return 0;
602 }
603
604 return 1;
605 }
606
607 static irqreturn_t v3_irq(int irq, void *devid)
608 {
609 #ifdef CONFIG_DEBUG_LL
610 struct pt_regs *regs = get_irq_regs();
611 unsigned long pc = instruction_pointer(regs);
612 unsigned long instr = *(unsigned long *)pc;
613 char buf[128];
614 extern void printascii(const char *);
615
616 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
617 "ISTAT=%02x\n", irq, pc, instr,
618 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET),
619 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
620 v3_readb(V3_LB_ISTAT));
621 printascii(buf);
622 #endif
623
624 v3_writew(V3_PCI_STAT, 0xf000);
625 v3_writeb(V3_LB_ISTAT, 0);
626 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
627
628 #ifdef CONFIG_DEBUG_LL
629 /*
630 * If the instruction being executed was a read,
631 * make it look like it read all-ones.
632 */
633 if ((instr & 0x0c100000) == 0x04100000) {
634 int reg = (instr >> 16) & 15;
635 sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]);
636 printascii(buf);
637 }
638 #endif
639 return IRQ_HANDLED;
640 }
641
642 static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
643 {
644 int ret = 0;
645
646 if (!ap_syscon_base)
647 return -EINVAL;
648
649 if (nr == 0) {
650 sys->mem_offset = non_mem.start;
651 ret = pci_v3_setup_resources(sys);
652 }
653
654 return ret;
655 }
656
657 /*
658 * V3_LB_BASE? - local bus address
659 * V3_LB_MAP? - pci bus address
660 */
661 static void __init pci_v3_preinit(void)
662 {
663 unsigned long flags;
664 unsigned int temp;
665
666 pcibios_min_mem = 0x00100000;
667
668 /*
669 * Hook in our fault handler for PCI errors
670 */
671 hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
672 hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
673 hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
674 hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
675
676 raw_spin_lock_irqsave(&v3_lock, flags);
677
678 /*
679 * Unlock V3 registers, but only if they were previously locked.
680 */
681 if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
682 v3_writew(V3_SYSTEM, 0xa05f);
683
684 /*
685 * Setup window 0 - PCI non-prefetchable memory
686 * Local: 0x40000000 Bus: 0x00000000 Size: 256MB
687 */
688 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
689 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
690 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(non_mem_pci) |
691 V3_LB_MAP_TYPE_MEM);
692
693 /*
694 * Setup window 1 - PCI prefetchable memory
695 * Local: 0x50000000 Bus: 0x10000000 Size: 256MB
696 */
697 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
698 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
699 V3_LB_BASE_ENABLE);
700 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
701 V3_LB_MAP_TYPE_MEM_MULTIPLE);
702
703 /*
704 * Setup window 2 - PCI IO
705 */
706 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) |
707 V3_LB_BASE_ENABLE);
708 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
709
710 /*
711 * Disable PCI to host IO cycles
712 */
713 temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
714 temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
715 v3_writew(V3_PCI_CFG, temp);
716
717 printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n",
718 v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
719
720 /*
721 * Set the V3 FIFO such that writes have higher priority than
722 * reads, and local bus write causes local bus read fifo flush.
723 * Same for PCI.
724 */
725 v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
726
727 /*
728 * Re-lock the system register.
729 */
730 temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
731 v3_writew(V3_SYSTEM, temp);
732
733 /*
734 * Clear any error conditions, and enable write errors.
735 */
736 v3_writeb(V3_LB_ISTAT, 0);
737 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
738 v3_writeb(V3_LB_IMASK, 0x28);
739 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
740
741 raw_spin_unlock_irqrestore(&v3_lock, flags);
742 }
743
744 static void __init pci_v3_postinit(void)
745 {
746 unsigned int pci_cmd;
747
748 pci_cmd = PCI_COMMAND_MEMORY |
749 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
750
751 v3_writew(V3_PCI_CMD, pci_cmd);
752
753 v3_writeb(V3_LB_ISTAT, ~0x40);
754 v3_writeb(V3_LB_IMASK, 0x68);
755
756 #if 0
757 ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
758 if (ret)
759 printk(KERN_ERR "PCI: unable to grab local bus timeout "
760 "interrupt: %d\n", ret);
761 #endif
762
763 register_isa_ports(non_mem.start, io_mem.start, 0);
764 }
765
766 /*
767 * A small note about bridges and interrupts. The DECchip 21050 (and
768 * later) adheres to the PCI-PCI bridge specification. This says that
769 * the interrupts on the other side of a bridge are swizzled in the
770 * following manner:
771 *
772 * Dev Interrupt Interrupt
773 * Pin on Pin on
774 * Device Connector
775 *
776 * 4 A A
777 * B B
778 * C C
779 * D D
780 *
781 * 5 A B
782 * B C
783 * C D
784 * D A
785 *
786 * 6 A C
787 * B D
788 * C A
789 * D B
790 *
791 * 7 A D
792 * B A
793 * C B
794 * D C
795 *
796 * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
797 * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
798 */
799
800 /*
801 * This routine handles multiple bridges.
802 */
803 static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
804 {
805 if (*pinp == 0)
806 *pinp = 1;
807
808 return pci_common_swizzle(dev, pinp);
809 }
810
811 static struct hw_pci pci_v3 __initdata = {
812 .swizzle = pci_v3_swizzle,
813 .setup = pci_v3_setup,
814 .nr_controllers = 1,
815 .ops = &pci_v3_ops,
816 .preinit = pci_v3_preinit,
817 .postinit = pci_v3_postinit,
818 };
819
820 static int __init pci_v3_probe(struct platform_device *pdev)
821 {
822 struct device_node *np = pdev->dev.of_node;
823 struct of_pci_range_parser parser;
824 struct of_pci_range range;
825 struct resource *res;
826 int irq, ret;
827
828 /* Remap the Integrator system controller */
829 ap_syscon_base = devm_ioremap(&pdev->dev, INTEGRATOR_SC_BASE, 0x100);
830 if (!ap_syscon_base) {
831 dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
832 return -ENODEV;
833 }
834
835 /* Device tree probe path */
836 if (!np) {
837 dev_err(&pdev->dev, "no device tree node for PCIv3\n");
838 return -ENODEV;
839 }
840
841 if (of_pci_range_parser_init(&parser, np))
842 return -EINVAL;
843
844 /* Get base for bridge registers */
845 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
846 if (!res) {
847 dev_err(&pdev->dev, "unable to obtain PCIv3 base\n");
848 return -ENODEV;
849 }
850 pci_v3_base = devm_ioremap(&pdev->dev, res->start,
851 resource_size(res));
852 if (!pci_v3_base) {
853 dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
854 return -ENODEV;
855 }
856
857 /* Get and request error IRQ resource */
858 irq = platform_get_irq(pdev, 0);
859 if (irq <= 0) {
860 dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n");
861 return -ENODEV;
862 }
863 ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0,
864 "PCIv3 error", NULL);
865 if (ret < 0) {
866 dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret);
867 return ret;
868 }
869
870 for_each_of_pci_range(&parser, &range) {
871 if (!range.flags) {
872 of_pci_range_to_resource(&range, np, &conf_mem);
873 conf_mem.name = "PCIv3 config";
874 }
875 if (range.flags & IORESOURCE_IO) {
876 of_pci_range_to_resource(&range, np, &io_mem);
877 io_mem.name = "PCIv3 I/O";
878 }
879 if ((range.flags & IORESOURCE_MEM) &&
880 !(range.flags & IORESOURCE_PREFETCH)) {
881 non_mem_pci = range.pci_addr;
882 non_mem_pci_sz = range.size;
883 of_pci_range_to_resource(&range, np, &non_mem);
884 non_mem.name = "PCIv3 non-prefetched mem";
885 }
886 if ((range.flags & IORESOURCE_MEM) &&
887 (range.flags & IORESOURCE_PREFETCH)) {
888 pre_mem_pci = range.pci_addr;
889 pre_mem_pci_sz = range.size;
890 of_pci_range_to_resource(&range, np, &pre_mem);
891 pre_mem.name = "PCIv3 prefetched mem";
892 }
893 }
894
895 if (!conf_mem.start || !io_mem.start ||
896 !non_mem.start || !pre_mem.start) {
897 dev_err(&pdev->dev, "missing ranges in device node\n");
898 return -EINVAL;
899 }
900
901 pci_v3.map_irq = of_irq_parse_and_map_pci;
902 pci_common_init_dev(&pdev->dev, &pci_v3);
903
904 return 0;
905 }
906
907 static const struct of_device_id pci_ids[] = {
908 { .compatible = "v3,v360epc-pci", },
909 {},
910 };
911
912 static struct platform_driver pci_v3_driver = {
913 .driver = {
914 .name = "pci-v3",
915 .of_match_table = pci_ids,
916 },
917 };
918
919 static int __init pci_v3_init(void)
920 {
921 return platform_driver_probe(&pci_v3_driver, pci_v3_probe);
922 }
923
924 subsys_initcall(pci_v3_init);
925
926 /*
927 * Static mappings for the PCIv3 bridge
928 *
929 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
930 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
931 * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
932 */
933 static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = {
934 {
935 .virtual = (unsigned long)PCI_MEMORY_VADDR,
936 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
937 .length = SZ_16M,
938 .type = MT_DEVICE
939 }, {
940 .virtual = (unsigned long)PCI_CONFIG_VADDR,
941 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
942 .length = SZ_16M,
943 .type = MT_DEVICE
944 }
945 };
946
947 int __init pci_v3_early_init(void)
948 {
949 iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc));
950 vga_base = (unsigned long)PCI_MEMORY_VADDR;
951 pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
952 return 0;
953 }
Linux with added FPC-III support