arch/arm/mach-omap2/clockdomains54xx_data.c

   1 /*
   2  * OMAP54XX Clock domains framework
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * Abhijit Pagare (abhijitpagare@ti.com)
   7  * Benoit Cousson (b-cousson@ti.com)
   8  * Paul Walmsley (paul@pwsan.com)
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/io.h>
  23
  24 #include "clockdomain.h"
  25 #include "cm1_54xx.h"
  26 #include "cm2_54xx.h"
  27
  28 #include "cm-regbits-54xx.h"
  29 #include "prm54xx.h"
  30 #include "prcm44xx.h"
  31 #include "prcm_mpu54xx.h"
  32
  33 /* Static Dependencies for OMAP4 Clock Domains */
  34
  35 static struct clkdm_dep c2c_wkup_sleep_deps[] = {
  36         { .clkdm_name = "abe_clkdm" },
  37         { .clkdm_name = "emif_clkdm" },
  38         { .clkdm_name = "iva_clkdm" },
  39         { .clkdm_name = "l3init_clkdm" },
  40         { .clkdm_name = "l3main1_clkdm" },
  41         { .clkdm_name = "l3main2_clkdm" },
  42         { .clkdm_name = "l4cfg_clkdm" },
  43         { .clkdm_name = "l4per_clkdm" },
  44         { NULL },
  45 };
  46
  47 static struct clkdm_dep cam_wkup_sleep_deps[] = {
  48         { .clkdm_name = "emif_clkdm" },
  49         { .clkdm_name = "iva_clkdm" },
  50         { .clkdm_name = "l3main1_clkdm" },
  51         { NULL },
  52 };
  53
  54 static struct clkdm_dep dma_wkup_sleep_deps[] = {
  55         { .clkdm_name = "abe_clkdm" },
  56         { .clkdm_name = "dss_clkdm" },
  57         { .clkdm_name = "emif_clkdm" },
  58         { .clkdm_name = "ipu_clkdm" },
  59         { .clkdm_name = "iva_clkdm" },
  60         { .clkdm_name = "l3init_clkdm" },
  61         { .clkdm_name = "l3main1_clkdm" },
  62         { .clkdm_name = "l4cfg_clkdm" },
  63         { .clkdm_name = "l4per_clkdm" },
  64         { .clkdm_name = "l4sec_clkdm" },
  65         { .clkdm_name = "wkupaon_clkdm" },
  66         { NULL },
  67 };
  68
  69 static struct clkdm_dep dsp_wkup_sleep_deps[] = {
  70         { .clkdm_name = "abe_clkdm" },
  71         { .clkdm_name = "emif_clkdm" },
  72         { .clkdm_name = "iva_clkdm" },
  73         { .clkdm_name = "l3init_clkdm" },
  74         { .clkdm_name = "l3main1_clkdm" },
  75         { .clkdm_name = "l3main2_clkdm" },
  76         { .clkdm_name = "l4cfg_clkdm" },
  77         { .clkdm_name = "l4per_clkdm" },
  78         { .clkdm_name = "wkupaon_clkdm" },
  79         { NULL },
  80 };
  81
  82 static struct clkdm_dep dss_wkup_sleep_deps[] = {
  83         { .clkdm_name = "emif_clkdm" },
  84         { .clkdm_name = "iva_clkdm" },
  85         { .clkdm_name = "l3main2_clkdm" },
  86         { NULL },
  87 };
  88
  89 static struct clkdm_dep gpu_wkup_sleep_deps[] = {
  90         { .clkdm_name = "emif_clkdm" },
  91         { .clkdm_name = "iva_clkdm" },
  92         { .clkdm_name = "l3main1_clkdm" },
  93         { NULL },
  94 };
  95
  96 static struct clkdm_dep ipu_wkup_sleep_deps[] = {
  97         { .clkdm_name = "abe_clkdm" },
  98         { .clkdm_name = "dsp_clkdm" },
  99         { .clkdm_name = "dss_clkdm" },
 100         { .clkdm_name = "emif_clkdm" },
 101         { .clkdm_name = "gpu_clkdm" },
 102         { .clkdm_name = "iva_clkdm" },
 103         { .clkdm_name = "l3init_clkdm" },
 104         { .clkdm_name = "l3main1_clkdm" },
 105         { .clkdm_name = "l3main2_clkdm" },
 106         { .clkdm_name = "l4cfg_clkdm" },
 107         { .clkdm_name = "l4per_clkdm" },
 108         { .clkdm_name = "l4sec_clkdm" },
 109         { .clkdm_name = "wkupaon_clkdm" },
 110         { NULL },
 111 };
 112
 113 static struct clkdm_dep iva_wkup_sleep_deps[] = {
 114         { .clkdm_name = "emif_clkdm" },
 115         { .clkdm_name = "l3main1_clkdm" },
 116         { NULL },
 117 };
 118
 119 static struct clkdm_dep l3init_wkup_sleep_deps[] = {
 120         { .clkdm_name = "abe_clkdm" },
 121         { .clkdm_name = "emif_clkdm" },
 122         { .clkdm_name = "iva_clkdm" },
 123         { .clkdm_name = "l4cfg_clkdm" },
 124         { .clkdm_name = "l4per_clkdm" },
 125         { .clkdm_name = "l4sec_clkdm" },
 126         { .clkdm_name = "wkupaon_clkdm" },
 127         { NULL },
 128 };
 129
 130 static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
 131         { .clkdm_name = "emif_clkdm" },
 132         { .clkdm_name = "l3main1_clkdm" },
 133         { .clkdm_name = "l4per_clkdm" },
 134         { NULL },
 135 };
 136
 137 static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
 138         { .clkdm_name = "abe_clkdm" },
 139         { .clkdm_name = "emif_clkdm" },
 140         { .clkdm_name = "iva_clkdm" },
 141         { .clkdm_name = "l3init_clkdm" },
 142         { .clkdm_name = "l3main1_clkdm" },
 143         { .clkdm_name = "l3main2_clkdm" },
 144         { .clkdm_name = "l4cfg_clkdm" },
 145         { .clkdm_name = "l4per_clkdm" },
 146         { NULL },
 147 };
 148
 149 static struct clkdm_dep mpu_wkup_sleep_deps[] = {
 150         { .clkdm_name = "abe_clkdm" },
 151         { .clkdm_name = "dsp_clkdm" },
 152         { .clkdm_name = "dss_clkdm" },
 153         { .clkdm_name = "emif_clkdm" },
 154         { .clkdm_name = "gpu_clkdm" },
 155         { .clkdm_name = "ipu_clkdm" },
 156         { .clkdm_name = "iva_clkdm" },
 157         { .clkdm_name = "l3init_clkdm" },
 158         { .clkdm_name = "l3main1_clkdm" },
 159         { .clkdm_name = "l3main2_clkdm" },
 160         { .clkdm_name = "l4cfg_clkdm" },
 161         { .clkdm_name = "l4per_clkdm" },
 162         { .clkdm_name = "l4sec_clkdm" },
 163         { .clkdm_name = "wkupaon_clkdm" },
 164         { NULL },
 165 };
 166
 167 static struct clockdomain l4sec_54xx_clkdm = {
 168         .name             = "l4sec_clkdm",
 169         .pwrdm            = { .name = "core_pwrdm" },
 170         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 171         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 172         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
 173         .dep_bit          = OMAP54XX_L4SEC_STATDEP_SHIFT,
 174         .wkdep_srcs       = l4sec_wkup_sleep_deps,
 175         .sleepdep_srcs    = l4sec_wkup_sleep_deps,
 176         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 177 };
 178
 179 static struct clockdomain iva_54xx_clkdm = {
 180         .name             = "iva_clkdm",
 181         .pwrdm            = { .name = "iva_pwrdm" },
 182         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 183         .cm_inst          = OMAP54XX_CM_CORE_IVA_INST,
 184         .clkdm_offs       = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
 185         .dep_bit          = OMAP54XX_IVA_STATDEP_SHIFT,
 186         .wkdep_srcs       = iva_wkup_sleep_deps,
 187         .sleepdep_srcs    = iva_wkup_sleep_deps,
 188         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 189 };
 190
 191 static struct clockdomain mipiext_54xx_clkdm = {
 192         .name             = "mipiext_clkdm",
 193         .pwrdm            = { .name = "core_pwrdm" },
 194         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 195         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 196         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
 197         .wkdep_srcs       = mipiext_wkup_sleep_deps,
 198         .sleepdep_srcs    = mipiext_wkup_sleep_deps,
 199         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 200 };
 201
 202 static struct clockdomain l3main2_54xx_clkdm = {
 203         .name             = "l3main2_clkdm",
 204         .pwrdm            = { .name = "core_pwrdm" },
 205         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 206         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 207         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
 208         .dep_bit          = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
 209         .flags            = CLKDM_CAN_HWSUP,
 210 };
 211
 212 static struct clockdomain l3main1_54xx_clkdm = {
 213         .name             = "l3main1_clkdm",
 214         .pwrdm            = { .name = "core_pwrdm" },
 215         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 216         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 217         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
 218         .dep_bit          = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
 219         .flags            = CLKDM_CAN_HWSUP,
 220 };
 221
 222 static struct clockdomain custefuse_54xx_clkdm = {
 223         .name             = "custefuse_clkdm",
 224         .pwrdm            = { .name = "custefuse_pwrdm" },
 225         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 226         .cm_inst          = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
 227         .clkdm_offs       = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
 228         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 229 };
 230
 231 static struct clockdomain ipu_54xx_clkdm = {
 232         .name             = "ipu_clkdm",
 233         .pwrdm            = { .name = "core_pwrdm" },
 234         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 235         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 236         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
 237         .dep_bit          = OMAP54XX_IPU_STATDEP_SHIFT,
 238         .wkdep_srcs       = ipu_wkup_sleep_deps,
 239         .sleepdep_srcs    = ipu_wkup_sleep_deps,
 240         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 241 };
 242
 243 static struct clockdomain l4cfg_54xx_clkdm = {
 244         .name             = "l4cfg_clkdm",
 245         .pwrdm            = { .name = "core_pwrdm" },
 246         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 247         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 248         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
 249         .dep_bit          = OMAP54XX_L4CFG_STATDEP_SHIFT,
 250         .flags            = CLKDM_CAN_HWSUP,
 251 };
 252
 253 static struct clockdomain abe_54xx_clkdm = {
 254         .name             = "abe_clkdm",
 255         .pwrdm            = { .name = "abe_pwrdm" },
 256         .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
 257         .cm_inst          = OMAP54XX_CM_CORE_AON_ABE_INST,
 258         .clkdm_offs       = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
 259         .dep_bit          = OMAP54XX_ABE_STATDEP_SHIFT,
 260         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 261 };
 262
 263 static struct clockdomain dss_54xx_clkdm = {
 264         .name             = "dss_clkdm",
 265         .pwrdm            = { .name = "dss_pwrdm" },
 266         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 267         .cm_inst          = OMAP54XX_CM_CORE_DSS_INST,
 268         .clkdm_offs       = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
 269         .dep_bit          = OMAP54XX_DSS_STATDEP_SHIFT,
 270         .wkdep_srcs       = dss_wkup_sleep_deps,
 271         .sleepdep_srcs    = dss_wkup_sleep_deps,
 272         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 273 };
 274
 275 static struct clockdomain dsp_54xx_clkdm = {
 276         .name             = "dsp_clkdm",
 277         .pwrdm            = { .name = "dsp_pwrdm" },
 278         .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
 279         .cm_inst          = OMAP54XX_CM_CORE_AON_DSP_INST,
 280         .clkdm_offs       = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
 281         .dep_bit          = OMAP54XX_DSP_STATDEP_SHIFT,
 282         .wkdep_srcs       = dsp_wkup_sleep_deps,
 283         .sleepdep_srcs    = dsp_wkup_sleep_deps,
 284         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 285 };
 286
 287 static struct clockdomain c2c_54xx_clkdm = {
 288         .name             = "c2c_clkdm",
 289         .pwrdm            = { .name = "core_pwrdm" },
 290         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 291         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 292         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
 293         .wkdep_srcs       = c2c_wkup_sleep_deps,
 294         .sleepdep_srcs    = c2c_wkup_sleep_deps,
 295         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 296 };
 297
 298 static struct clockdomain l4per_54xx_clkdm = {
 299         .name             = "l4per_clkdm",
 300         .pwrdm            = { .name = "core_pwrdm" },
 301         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 302         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 303         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
 304         .dep_bit          = OMAP54XX_L4PER_STATDEP_SHIFT,
 305         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 306 };
 307
 308 static struct clockdomain gpu_54xx_clkdm = {
 309         .name             = "gpu_clkdm",
 310         .pwrdm            = { .name = "gpu_pwrdm" },
 311         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 312         .cm_inst          = OMAP54XX_CM_CORE_GPU_INST,
 313         .clkdm_offs       = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
 314         .dep_bit          = OMAP54XX_GPU_STATDEP_SHIFT,
 315         .wkdep_srcs       = gpu_wkup_sleep_deps,
 316         .sleepdep_srcs    = gpu_wkup_sleep_deps,
 317         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 318 };
 319
 320 static struct clockdomain wkupaon_54xx_clkdm = {
 321         .name             = "wkupaon_clkdm",
 322         .pwrdm            = { .name = "wkupaon_pwrdm" },
 323         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 324         .cm_inst          = OMAP54XX_PRM_WKUPAON_CM_INST,
 325         .clkdm_offs       = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
 326         .dep_bit          = OMAP54XX_WKUPAON_STATDEP_SHIFT,
 327         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 328 };
 329
 330 static struct clockdomain mpu0_54xx_clkdm = {
 331         .name             = "mpu0_clkdm",
 332         .pwrdm            = { .name = "cpu0_pwrdm" },
 333         .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
 334         .cm_inst          = OMAP54XX_PRCM_MPU_CM_C0_INST,
 335         .clkdm_offs       = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
 336         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 337 };
 338
 339 static struct clockdomain mpu1_54xx_clkdm = {
 340         .name             = "mpu1_clkdm",
 341         .pwrdm            = { .name = "cpu1_pwrdm" },
 342         .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
 343         .cm_inst          = OMAP54XX_PRCM_MPU_CM_C1_INST,
 344         .clkdm_offs       = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
 345         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 346 };
 347
 348 static struct clockdomain coreaon_54xx_clkdm = {
 349         .name             = "coreaon_clkdm",
 350         .pwrdm            = { .name = "coreaon_pwrdm" },
 351         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 352         .cm_inst          = OMAP54XX_CM_CORE_COREAON_INST,
 353         .clkdm_offs       = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
 354         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 355 };
 356
 357 static struct clockdomain mpu_54xx_clkdm = {
 358         .name             = "mpu_clkdm",
 359         .pwrdm            = { .name = "mpu_pwrdm" },
 360         .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
 361         .cm_inst          = OMAP54XX_CM_CORE_AON_MPU_INST,
 362         .clkdm_offs       = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
 363         .wkdep_srcs       = mpu_wkup_sleep_deps,
 364         .sleepdep_srcs    = mpu_wkup_sleep_deps,
 365         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 366 };
 367
 368 static struct clockdomain l3init_54xx_clkdm = {
 369         .name             = "l3init_clkdm",
 370         .pwrdm            = { .name = "l3init_pwrdm" },
 371         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 372         .cm_inst          = OMAP54XX_CM_CORE_L3INIT_INST,
 373         .clkdm_offs       = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
 374         .dep_bit          = OMAP54XX_L3INIT_STATDEP_SHIFT,
 375         .wkdep_srcs       = l3init_wkup_sleep_deps,
 376         .sleepdep_srcs    = l3init_wkup_sleep_deps,
 377         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 378 };
 379
 380 static struct clockdomain dma_54xx_clkdm = {
 381         .name             = "dma_clkdm",
 382         .pwrdm            = { .name = "core_pwrdm" },
 383         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 384         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 385         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
 386         .wkdep_srcs       = dma_wkup_sleep_deps,
 387         .sleepdep_srcs    = dma_wkup_sleep_deps,
 388         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 389 };
 390
 391 static struct clockdomain l3instr_54xx_clkdm = {
 392         .name             = "l3instr_clkdm",
 393         .pwrdm            = { .name = "core_pwrdm" },
 394         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 395         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 396         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
 397 };
 398
 399 static struct clockdomain emif_54xx_clkdm = {
 400         .name             = "emif_clkdm",
 401         .pwrdm            = { .name = "core_pwrdm" },
 402         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 403         .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
 404         .clkdm_offs       = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
 405         .dep_bit          = OMAP54XX_EMIF_STATDEP_SHIFT,
 406         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 407 };
 408
 409 static struct clockdomain emu_54xx_clkdm = {
 410         .name             = "emu_clkdm",
 411         .pwrdm            = { .name = "emu_pwrdm" },
 412         .prcm_partition   = OMAP54XX_PRM_PARTITION,
 413         .cm_inst          = OMAP54XX_PRM_EMU_CM_INST,
 414         .clkdm_offs       = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
 415         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 416 };
 417
 418 static struct clockdomain cam_54xx_clkdm = {
 419         .name             = "cam_clkdm",
 420         .pwrdm            = { .name = "cam_pwrdm" },
 421         .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
 422         .cm_inst          = OMAP54XX_CM_CORE_CAM_INST,
 423         .clkdm_offs       = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
 424         .wkdep_srcs       = cam_wkup_sleep_deps,
 425         .sleepdep_srcs    = cam_wkup_sleep_deps,
 426         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 427 };
 428
 429 /* As clockdomains are added or removed above, this list must also be changed */
 430 static struct clockdomain *clockdomains_omap54xx[] __initdata = {
 431         &l4sec_54xx_clkdm,
 432         &iva_54xx_clkdm,
 433         &mipiext_54xx_clkdm,
 434         &l3main2_54xx_clkdm,
 435         &l3main1_54xx_clkdm,
 436         &custefuse_54xx_clkdm,
 437         &ipu_54xx_clkdm,
 438         &l4cfg_54xx_clkdm,
 439         &abe_54xx_clkdm,
 440         &dss_54xx_clkdm,
 441         &dsp_54xx_clkdm,
 442         &c2c_54xx_clkdm,
 443         &l4per_54xx_clkdm,
 444         &gpu_54xx_clkdm,
 445         &wkupaon_54xx_clkdm,
 446         &mpu0_54xx_clkdm,
 447         &mpu1_54xx_clkdm,
 448         &coreaon_54xx_clkdm,
 449         &mpu_54xx_clkdm,
 450         &l3init_54xx_clkdm,
 451         &dma_54xx_clkdm,
 452         &l3instr_54xx_clkdm,
 453         &emif_54xx_clkdm,
 454         &emu_54xx_clkdm,
 455         &cam_54xx_clkdm,
 456         NULL
 457 };
 458
 459 void __init omap54xx_clockdomains_init(void)
 460 {
 461         clkdm_register_platform_funcs(&omap4_clkdm_operations);
 462         clkdm_register_clkdms(clockdomains_omap54xx);
 463         clkdm_complete_init();
 464 }