4 * Copyright (C) 2009 Texas Instruments
5 * Vimal Singh <vimalsingh@ti.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/platform_device.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/platform_data/mtd-nand-omap2.h>
18 #include <asm/mach/flash.h>
22 #include "gpmc-nand.h"
24 /* minimum size for IO mapping */
25 #define NAND_IO_SIZE 4
27 static struct resource gpmc_nand_resource
[] = {
29 .flags
= IORESOURCE_MEM
,
32 .flags
= IORESOURCE_IRQ
,
35 .flags
= IORESOURCE_IRQ
,
39 static struct platform_device gpmc_nand_device
= {
42 .num_resources
= ARRAY_SIZE(gpmc_nand_resource
),
43 .resource
= gpmc_nand_resource
,
46 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt
)
48 /* support only OMAP3 class */
49 if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
50 pr_err("BCH ecc is not supported on this CPU\n");
55 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
56 * and AM33xx derivates. Other chips may be added if confirmed to work.
58 if ((ecc_opt
== OMAP_ECC_BCH4_CODE_HW
) &&
59 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
61 pr_err("BCH 4-bit mode is not supported on this CPU\n");
68 /* This function will go away once the device-tree convertion is complete */
69 static void gpmc_set_legacy(struct omap_nand_platform_data
*gpmc_nand_data
,
70 struct gpmc_settings
*s
)
72 /* Enable RD PIN Monitoring Reg */
73 if (gpmc_nand_data
->dev_ready
) {
74 s
->wait_on_read
= true;
75 s
->wait_on_write
= true;
78 if (gpmc_nand_data
->devsize
== NAND_BUSWIDTH_16
)
79 s
->device_width
= GPMC_DEVWIDTH_16BIT
;
81 s
->device_width
= GPMC_DEVWIDTH_8BIT
;
84 int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data
,
85 struct gpmc_timings
*gpmc_t
)
88 struct gpmc_settings s
;
89 struct device
*dev
= &gpmc_nand_device
.dev
;
91 memset(&s
, 0, sizeof(struct gpmc_settings
));
93 gpmc_nand_device
.dev
.platform_data
= gpmc_nand_data
;
95 err
= gpmc_cs_request(gpmc_nand_data
->cs
, NAND_IO_SIZE
,
96 (unsigned long *)&gpmc_nand_resource
[0].start
);
98 dev_err(dev
, "Cannot request GPMC CS %d, error %d\n",
99 gpmc_nand_data
->cs
, err
);
103 gpmc_nand_resource
[0].end
= gpmc_nand_resource
[0].start
+
106 gpmc_nand_resource
[1].start
=
107 gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE
);
108 gpmc_nand_resource
[2].start
=
109 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT
);
112 err
= gpmc_cs_set_timings(gpmc_nand_data
->cs
, gpmc_t
);
114 dev_err(dev
, "Unable to set gpmc timings: %d\n", err
);
119 if (gpmc_nand_data
->of_node
)
120 gpmc_read_settings_dt(gpmc_nand_data
->of_node
, &s
);
122 gpmc_set_legacy(gpmc_nand_data
, &s
);
124 s
.device_nand
= true;
126 err
= gpmc_cs_program_settings(gpmc_nand_data
->cs
, &s
);
130 err
= gpmc_configure(GPMC_CONFIG_WP
, 0);
134 gpmc_update_nand_reg(&gpmc_nand_data
->reg
, gpmc_nand_data
->cs
);
136 if (!gpmc_hwecc_bch_capable(gpmc_nand_data
->ecc_opt
))
139 err
= platform_device_register(&gpmc_nand_device
);
141 dev_err(dev
, "Unable to register NAND device\n");
148 gpmc_cs_free(gpmc_nand_data
->cs
);