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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[linux/fpc-iii.git] / arch / arm / mach-omap2 / gpmc.c
blobd24926e6340fa714cf0aeacca14a6578e5b481a4
1 /*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #undef DEBUG
16
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
24 #include <linux/io.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_mtd.h>
31 #include <linux/of_device.h>
32 #include <linux/mtd/nand.h>
33 #include <linux/pm_runtime.h>
34
35 #include <linux/platform_data/mtd-nand-omap2.h>
36
37 #include <asm/mach-types.h>
38
39 #include "soc.h"
40 #include "common.h"
41 #include "omap_device.h"
42 #include "gpmc.h"
43 #include "gpmc-nand.h"
44 #include "gpmc-onenand.h"
45
46 #define DEVICE_NAME "omap-gpmc"
47
48 /* GPMC register offsets */
49 #define GPMC_REVISION 0x00
50 #define GPMC_SYSCONFIG 0x10
51 #define GPMC_SYSSTATUS 0x14
52 #define GPMC_IRQSTATUS 0x18
53 #define GPMC_IRQENABLE 0x1c
54 #define GPMC_TIMEOUT_CONTROL 0x40
55 #define GPMC_ERR_ADDRESS 0x44
56 #define GPMC_ERR_TYPE 0x48
57 #define GPMC_CONFIG 0x50
58 #define GPMC_STATUS 0x54
59 #define GPMC_PREFETCH_CONFIG1 0x1e0
60 #define GPMC_PREFETCH_CONFIG2 0x1e4
61 #define GPMC_PREFETCH_CONTROL 0x1ec
62 #define GPMC_PREFETCH_STATUS 0x1f0
63 #define GPMC_ECC_CONFIG 0x1f4
64 #define GPMC_ECC_CONTROL 0x1f8
65 #define GPMC_ECC_SIZE_CONFIG 0x1fc
66 #define GPMC_ECC1_RESULT 0x200
67 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
68 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
69 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
70 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
71
72 /* GPMC ECC control settings */
73 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
74 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
75 #define GPMC_ECC_CTRL_ECCREG1 0x001
76 #define GPMC_ECC_CTRL_ECCREG2 0x002
77 #define GPMC_ECC_CTRL_ECCREG3 0x003
78 #define GPMC_ECC_CTRL_ECCREG4 0x004
79 #define GPMC_ECC_CTRL_ECCREG5 0x005
80 #define GPMC_ECC_CTRL_ECCREG6 0x006
81 #define GPMC_ECC_CTRL_ECCREG7 0x007
82 #define GPMC_ECC_CTRL_ECCREG8 0x008
83 #define GPMC_ECC_CTRL_ECCREG9 0x009
84
85 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
86 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
87 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
88 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
89 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
90 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
91
92 #define GPMC_CS0_OFFSET 0x60
93 #define GPMC_CS_SIZE 0x30
94 #define GPMC_BCH_SIZE 0x10
95
96 #define GPMC_MEM_END 0x3FFFFFFF
97
98 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
99 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
100
101 #define CS_NUM_SHIFT 24
102 #define ENABLE_PREFETCH (0x1 << 7)
103 #define DMA_MPU_MODE 2
104
105 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
106 #define GPMC_REVISION_MINOR(l) (l & 0xf)
107
108 #define GPMC_HAS_WR_ACCESS 0x1
109 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
110 #define GPMC_HAS_MUX_AAD 0x4
111
112 #define GPMC_NR_WAITPINS 4
113
114 /* XXX: Only NAND irq has been considered,currently these are the only ones used
115 */
116 #define GPMC_NR_IRQ 2
117
118 struct gpmc_client_irq {
119 unsigned irq;
120 u32 bitmask;
121 };
122
123 /* Structure to save gpmc cs context */
124 struct gpmc_cs_config {
125 u32 config1;
126 u32 config2;
127 u32 config3;
128 u32 config4;
129 u32 config5;
130 u32 config6;
131 u32 config7;
132 int is_valid;
133 };
134
135 /*
136 * Structure to save/restore gpmc context
137 * to support core off on OMAP3
138 */
139 struct omap3_gpmc_regs {
140 u32 sysconfig;
141 u32 irqenable;
142 u32 timeout_ctrl;
143 u32 config;
144 u32 prefetch_config1;
145 u32 prefetch_config2;
146 u32 prefetch_control;
147 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
148 };
149
150 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
151 static struct irq_chip gpmc_irq_chip;
152 static int gpmc_irq_start;
153
154 static struct resource gpmc_mem_root;
155 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
156 static DEFINE_SPINLOCK(gpmc_mem_lock);
157 /* Define chip-selects as reserved by default until probe completes */
158 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
159 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
160 static unsigned int gpmc_nr_waitpins;
161 static struct device *gpmc_dev;
162 static int gpmc_irq;
163 static resource_size_t phys_base, mem_size;
164 static unsigned gpmc_capability;
165 static void __iomem *gpmc_base;
166
167 static struct clk *gpmc_l3_clk;
168
169 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
170
171 static void gpmc_write_reg(int idx, u32 val)
172 {
173 __raw_writel(val, gpmc_base + idx);
174 }
175
176 static u32 gpmc_read_reg(int idx)
177 {
178 return __raw_readl(gpmc_base + idx);
179 }
180
181 void gpmc_cs_write_reg(int cs, int idx, u32 val)
182 {
183 void __iomem *reg_addr;
184
185 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
186 __raw_writel(val, reg_addr);
187 }
188
189 static u32 gpmc_cs_read_reg(int cs, int idx)
190 {
191 void __iomem *reg_addr;
192
193 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
194 return __raw_readl(reg_addr);
195 }
196
197 /* TODO: Add support for gpmc_fck to clock framework and use it */
198 static unsigned long gpmc_get_fclk_period(void)
199 {
200 unsigned long rate = clk_get_rate(gpmc_l3_clk);
201
202 if (rate == 0) {
203 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
204 return 0;
205 }
206
207 rate /= 1000;
208 rate = 1000000000 / rate; /* In picoseconds */
209
210 return rate;
211 }
212
213 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
214 {
215 unsigned long tick_ps;
216
217 /* Calculate in picosecs to yield more exact results */
218 tick_ps = gpmc_get_fclk_period();
219
220 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
221 }
222
223 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
224 {
225 unsigned long tick_ps;
226
227 /* Calculate in picosecs to yield more exact results */
228 tick_ps = gpmc_get_fclk_period();
229
230 return (time_ps + tick_ps - 1) / tick_ps;
231 }
232
233 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
234 {
235 return ticks * gpmc_get_fclk_period() / 1000;
236 }
237
238 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
239 {
240 return ticks * gpmc_get_fclk_period();
241 }
242
243 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
244 {
245 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
246
247 return ticks * gpmc_get_fclk_period();
248 }
249
250 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
251 {
252 u32 l;
253
254 l = gpmc_cs_read_reg(cs, reg);
255 if (value)
256 l |= mask;
257 else
258 l &= ~mask;
259 gpmc_cs_write_reg(cs, reg, l);
260 }
261
262 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
263 {
264 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
265 GPMC_CONFIG1_TIME_PARA_GRAN,
266 p->time_para_granularity);
267 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
268 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
269 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
270 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
271 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
272 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
273 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
274 GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
275 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
276 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
277 p->cycle2cyclesamecsen);
278 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
279 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
280 p->cycle2cyclediffcsen);
281 }
282
283 #ifdef DEBUG
284 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
285 int time, const char *name)
286 #else
287 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
288 int time)
289 #endif
290 {
291 u32 l;
292 int ticks, mask, nr_bits;
293
294 if (time == 0)
295 ticks = 0;
296 else
297 ticks = gpmc_ns_to_ticks(time);
298 nr_bits = end_bit - st_bit + 1;
299 if (ticks >= 1 << nr_bits) {
300 #ifdef DEBUG
301 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
302 cs, name, time, ticks, 1 << nr_bits);
303 #endif
304 return -1;
305 }
306
307 mask = (1 << nr_bits) - 1;
308 l = gpmc_cs_read_reg(cs, reg);
309 #ifdef DEBUG
310 printk(KERN_INFO
311 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
312 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
313 (l >> st_bit) & mask, time);
314 #endif
315 l &= ~(mask << st_bit);
316 l |= ticks << st_bit;
317 gpmc_cs_write_reg(cs, reg, l);
318
319 return 0;
320 }
321
322 #ifdef DEBUG
323 #define GPMC_SET_ONE(reg, st, end, field) \
324 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
325 t->field, #field) < 0) \
326 return -1
327 #else
328 #define GPMC_SET_ONE(reg, st, end, field) \
329 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
330 return -1
331 #endif
332
333 int gpmc_calc_divider(unsigned int sync_clk)
334 {
335 int div;
336 u32 l;
337
338 l = sync_clk + (gpmc_get_fclk_period() - 1);
339 div = l / gpmc_get_fclk_period();
340 if (div > 4)
341 return -1;
342 if (div <= 0)
343 div = 1;
344
345 return div;
346 }
347
348 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
349 {
350 int div;
351 u32 l;
352
353 div = gpmc_calc_divider(t->sync_clk);
354 if (div < 0)
355 return div;
356
357 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
358 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
359 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
360
361 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
362 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
363 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
364
365 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
366 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
367 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
368 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
369
370 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
371 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
372 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
373
374 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
375
376 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
377 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
378
379 GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
380 GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
381
382 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
383 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
384 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
385 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
386
387 /* caller is expected to have initialized CONFIG1 to cover
388 * at least sync vs async
389 */
390 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
391 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
392 #ifdef DEBUG
393 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
394 cs, (div * gpmc_get_fclk_period()) / 1000, div);
395 #endif
396 l &= ~0x03;
397 l |= (div - 1);
398 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
399 }
400
401 gpmc_cs_bool_timings(cs, &t->bool_timings);
402
403 return 0;
404 }
405
406 static int gpmc_cs_enable_mem(int cs, u32 base, u32 size)
407 {
408 u32 l;
409 u32 mask;
410
411 /*
412 * Ensure that base address is aligned on a
413 * boundary equal to or greater than size.
414 */
415 if (base & (size - 1))
416 return -EINVAL;
417
418 mask = (1 << GPMC_SECTION_SHIFT) - size;
419 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
420 l &= ~0x3f;
421 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
422 l &= ~(0x0f << 8);
423 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
424 l |= GPMC_CONFIG7_CSVALID;
425 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
426
427 return 0;
428 }
429
430 static void gpmc_cs_disable_mem(int cs)
431 {
432 u32 l;
433
434 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
435 l &= ~GPMC_CONFIG7_CSVALID;
436 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
437 }
438
439 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
440 {
441 u32 l;
442 u32 mask;
443
444 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
445 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
446 mask = (l >> 8) & 0x0f;
447 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
448 }
449
450 static int gpmc_cs_mem_enabled(int cs)
451 {
452 u32 l;
453
454 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
455 return l & GPMC_CONFIG7_CSVALID;
456 }
457
458 static void gpmc_cs_set_reserved(int cs, int reserved)
459 {
460 gpmc_cs_map &= ~(1 << cs);
461 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
462 }
463
464 static bool gpmc_cs_reserved(int cs)
465 {
466 return gpmc_cs_map & (1 << cs);
467 }
468
469 static unsigned long gpmc_mem_align(unsigned long size)
470 {
471 int order;
472
473 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
474 order = GPMC_CHUNK_SHIFT - 1;
475 do {
476 size >>= 1;
477 order++;
478 } while (size);
479 size = 1 << order;
480 return size;
481 }
482
483 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
484 {
485 struct resource *res = &gpmc_cs_mem[cs];
486 int r;
487
488 size = gpmc_mem_align(size);
489 spin_lock(&gpmc_mem_lock);
490 res->start = base;
491 res->end = base + size - 1;
492 r = request_resource(&gpmc_mem_root, res);
493 spin_unlock(&gpmc_mem_lock);
494
495 return r;
496 }
497
498 static int gpmc_cs_delete_mem(int cs)
499 {
500 struct resource *res = &gpmc_cs_mem[cs];
501 int r;
502
503 spin_lock(&gpmc_mem_lock);
504 r = release_resource(&gpmc_cs_mem[cs]);
505 res->start = 0;
506 res->end = 0;
507 spin_unlock(&gpmc_mem_lock);
508
509 return r;
510 }
511
512 /**
513 * gpmc_cs_remap - remaps a chip-select physical base address
514 * @cs: chip-select to remap
515 * @base: physical base address to re-map chip-select to
516 *
517 * Re-maps a chip-select to a new physical base address specified by
518 * "base". Returns 0 on success and appropriate negative error code
519 * on failure.
520 */
521 static int gpmc_cs_remap(int cs, u32 base)
522 {
523 int ret;
524 u32 old_base, size;
525
526 if (cs > gpmc_cs_num) {
527 pr_err("%s: requested chip-select is disabled\n", __func__);
528 return -ENODEV;
529 }
530 gpmc_cs_get_memconf(cs, &old_base, &size);
531 if (base == old_base)
532 return 0;
533 gpmc_cs_disable_mem(cs);
534 ret = gpmc_cs_delete_mem(cs);
535 if (ret < 0)
536 return ret;
537 ret = gpmc_cs_insert_mem(cs, base, size);
538 if (ret < 0)
539 return ret;
540 ret = gpmc_cs_enable_mem(cs, base, size);
541 if (ret < 0)
542 return ret;
543
544 return 0;
545 }
546
547 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
548 {
549 struct resource *res = &gpmc_cs_mem[cs];
550 int r = -1;
551
552 if (cs > gpmc_cs_num) {
553 pr_err("%s: requested chip-select is disabled\n", __func__);
554 return -ENODEV;
555 }
556 size = gpmc_mem_align(size);
557 if (size > (1 << GPMC_SECTION_SHIFT))
558 return -ENOMEM;
559
560 spin_lock(&gpmc_mem_lock);
561 if (gpmc_cs_reserved(cs)) {
562 r = -EBUSY;
563 goto out;
564 }
565 if (gpmc_cs_mem_enabled(cs))
566 r = adjust_resource(res, res->start & ~(size - 1), size);
567 if (r < 0)
568 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
569 size, NULL, NULL);
570 if (r < 0)
571 goto out;
572
573 r = gpmc_cs_enable_mem(cs, res->start, resource_size(res));
574 if (r < 0) {
575 release_resource(res);
576 goto out;
577 }
578
579 *base = res->start;
580 gpmc_cs_set_reserved(cs, 1);
581 out:
582 spin_unlock(&gpmc_mem_lock);
583 return r;
584 }
585 EXPORT_SYMBOL(gpmc_cs_request);
586
587 void gpmc_cs_free(int cs)
588 {
589 spin_lock(&gpmc_mem_lock);
590 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
591 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
592 BUG();
593 spin_unlock(&gpmc_mem_lock);
594 return;
595 }
596 gpmc_cs_disable_mem(cs);
597 release_resource(&gpmc_cs_mem[cs]);
598 gpmc_cs_set_reserved(cs, 0);
599 spin_unlock(&gpmc_mem_lock);
600 }
601 EXPORT_SYMBOL(gpmc_cs_free);
602
603 /**
604 * gpmc_configure - write request to configure gpmc
605 * @cmd: command type
606 * @wval: value to write
607 * @return status of the operation
608 */
609 int gpmc_configure(int cmd, int wval)
610 {
611 u32 regval;
612
613 switch (cmd) {
614 case GPMC_ENABLE_IRQ:
615 gpmc_write_reg(GPMC_IRQENABLE, wval);
616 break;
617
618 case GPMC_SET_IRQ_STATUS:
619 gpmc_write_reg(GPMC_IRQSTATUS, wval);
620 break;
621
622 case GPMC_CONFIG_WP:
623 regval = gpmc_read_reg(GPMC_CONFIG);
624 if (wval)
625 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
626 else
627 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
628 gpmc_write_reg(GPMC_CONFIG, regval);
629 break;
630
631 default:
632 pr_err("%s: command not supported\n", __func__);
633 return -EINVAL;
634 }
635
636 return 0;
637 }
638 EXPORT_SYMBOL(gpmc_configure);
639
640 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
641 {
642 int i;
643
644 reg->gpmc_status = gpmc_base + GPMC_STATUS;
645 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
646 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
647 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
648 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
649 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
650 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
651 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
652 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
653 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
654 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
655 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
656 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
657 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
658 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
659
660 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
661 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
662 GPMC_BCH_SIZE * i;
663 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
664 GPMC_BCH_SIZE * i;
665 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
666 GPMC_BCH_SIZE * i;
667 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
668 GPMC_BCH_SIZE * i;
669 }
670 }
671
672 int gpmc_get_client_irq(unsigned irq_config)
673 {
674 int i;
675
676 if (hweight32(irq_config) > 1)
677 return 0;
678
679 for (i = 0; i < GPMC_NR_IRQ; i++)
680 if (gpmc_client_irq[i].bitmask & irq_config)
681 return gpmc_client_irq[i].irq;
682
683 return 0;
684 }
685
686 static int gpmc_irq_endis(unsigned irq, bool endis)
687 {
688 int i;
689 u32 regval;
690
691 for (i = 0; i < GPMC_NR_IRQ; i++)
692 if (irq == gpmc_client_irq[i].irq) {
693 regval = gpmc_read_reg(GPMC_IRQENABLE);
694 if (endis)
695 regval |= gpmc_client_irq[i].bitmask;
696 else
697 regval &= ~gpmc_client_irq[i].bitmask;
698 gpmc_write_reg(GPMC_IRQENABLE, regval);
699 break;
700 }
701
702 return 0;
703 }
704
705 static void gpmc_irq_disable(struct irq_data *p)
706 {
707 gpmc_irq_endis(p->irq, false);
708 }
709
710 static void gpmc_irq_enable(struct irq_data *p)
711 {
712 gpmc_irq_endis(p->irq, true);
713 }
714
715 static void gpmc_irq_noop(struct irq_data *data) { }
716
717 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
718
719 static int gpmc_setup_irq(void)
720 {
721 int i;
722 u32 regval;
723
724 if (!gpmc_irq)
725 return -EINVAL;
726
727 gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
728 if (gpmc_irq_start < 0) {
729 pr_err("irq_alloc_descs failed\n");
730 return gpmc_irq_start;
731 }
732
733 gpmc_irq_chip.name = "gpmc";
734 gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
735 gpmc_irq_chip.irq_enable = gpmc_irq_enable;
736 gpmc_irq_chip.irq_disable = gpmc_irq_disable;
737 gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
738 gpmc_irq_chip.irq_ack = gpmc_irq_noop;
739 gpmc_irq_chip.irq_mask = gpmc_irq_noop;
740 gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
741
742 gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
743 gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
744
745 for (i = 0; i < GPMC_NR_IRQ; i++) {
746 gpmc_client_irq[i].irq = gpmc_irq_start + i;
747 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
748 &gpmc_irq_chip, handle_simple_irq);
749 set_irq_flags(gpmc_client_irq[i].irq,
750 IRQF_VALID | IRQF_NOAUTOEN);
751 }
752
753 /* Disable interrupts */
754 gpmc_write_reg(GPMC_IRQENABLE, 0);
755
756 /* clear interrupts */
757 regval = gpmc_read_reg(GPMC_IRQSTATUS);
758 gpmc_write_reg(GPMC_IRQSTATUS, regval);
759
760 return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
761 }
762
763 static int gpmc_free_irq(void)
764 {
765 int i;
766
767 if (gpmc_irq)
768 free_irq(gpmc_irq, NULL);
769
770 for (i = 0; i < GPMC_NR_IRQ; i++) {
771 irq_set_handler(gpmc_client_irq[i].irq, NULL);
772 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
773 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
774 }
775
776 irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
777
778 return 0;
779 }
780
781 static void gpmc_mem_exit(void)
782 {
783 int cs;
784
785 for (cs = 0; cs < gpmc_cs_num; cs++) {
786 if (!gpmc_cs_mem_enabled(cs))
787 continue;
788 gpmc_cs_delete_mem(cs);
789 }
790
791 }
792
793 static void gpmc_mem_init(void)
794 {
795 int cs;
796
797 /*
798 * The first 1MB of GPMC address space is typically mapped to
799 * the internal ROM. Never allocate the first page, to
800 * facilitate bug detection; even if we didn't boot from ROM.
801 */
802 gpmc_mem_root.start = SZ_1M;
803 gpmc_mem_root.end = GPMC_MEM_END;
804
805 /* Reserve all regions that has been set up by bootloader */
806 for (cs = 0; cs < gpmc_cs_num; cs++) {
807 u32 base, size;
808
809 if (!gpmc_cs_mem_enabled(cs))
810 continue;
811 gpmc_cs_get_memconf(cs, &base, &size);
812 if (gpmc_cs_insert_mem(cs, base, size)) {
813 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
814 __func__, cs, base, base + size);
815 gpmc_cs_disable_mem(cs);
816 }
817 }
818 }
819
820 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
821 {
822 u32 temp;
823 int div;
824
825 div = gpmc_calc_divider(sync_clk);
826 temp = gpmc_ps_to_ticks(time_ps);
827 temp = (temp + div - 1) / div;
828 return gpmc_ticks_to_ps(temp * div);
829 }
830
831 /* XXX: can the cycles be avoided ? */
832 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
833 struct gpmc_device_timings *dev_t,
834 bool mux)
835 {
836 u32 temp;
837
838 /* adv_rd_off */
839 temp = dev_t->t_avdp_r;
840 /* XXX: mux check required ? */
841 if (mux) {
842 /* XXX: t_avdp not to be required for sync, only added for tusb
843 * this indirectly necessitates requirement of t_avdp_r and
844 * t_avdp_w instead of having a single t_avdp
845 */
846 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
847 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
848 }
849 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
850
851 /* oe_on */
852 temp = dev_t->t_oeasu; /* XXX: remove this ? */
853 if (mux) {
854 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
855 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
856 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
857 }
858 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
859
860 /* access */
861 /* XXX: any scope for improvement ?, by combining oe_on
862 * and clk_activation, need to check whether
863 * access = clk_activation + round to sync clk ?
864 */
865 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
866 temp += gpmc_t->clk_activation;
867 if (dev_t->cyc_oe)
868 temp = max_t(u32, temp, gpmc_t->oe_on +
869 gpmc_ticks_to_ps(dev_t->cyc_oe));
870 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
871
872 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
873 gpmc_t->cs_rd_off = gpmc_t->oe_off;
874
875 /* rd_cycle */
876 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
877 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
878 gpmc_t->access;
879 /* XXX: barter t_ce_rdyz with t_cez_r ? */
880 if (dev_t->t_ce_rdyz)
881 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
882 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
883
884 return 0;
885 }
886
887 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
888 struct gpmc_device_timings *dev_t,
889 bool mux)
890 {
891 u32 temp;
892
893 /* adv_wr_off */
894 temp = dev_t->t_avdp_w;
895 if (mux) {
896 temp = max_t(u32, temp,
897 gpmc_t->clk_activation + dev_t->t_avdh);
898 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
899 }
900 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
901
902 /* wr_data_mux_bus */
903 temp = max_t(u32, dev_t->t_weasu,
904 gpmc_t->clk_activation + dev_t->t_rdyo);
905 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
906 * and in that case remember to handle we_on properly
907 */
908 if (mux) {
909 temp = max_t(u32, temp,
910 gpmc_t->adv_wr_off + dev_t->t_aavdh);
911 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
912 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
913 }
914 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
915
916 /* we_on */
917 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
918 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
919 else
920 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
921
922 /* wr_access */
923 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
924 gpmc_t->wr_access = gpmc_t->access;
925
926 /* we_off */
927 temp = gpmc_t->we_on + dev_t->t_wpl;
928 temp = max_t(u32, temp,
929 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
930 temp = max_t(u32, temp,
931 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
932 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
933
934 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
935 dev_t->t_wph);
936
937 /* wr_cycle */
938 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
939 temp += gpmc_t->wr_access;
940 /* XXX: barter t_ce_rdyz with t_cez_w ? */
941 if (dev_t->t_ce_rdyz)
942 temp = max_t(u32, temp,
943 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
944 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
945
946 return 0;
947 }
948
949 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
950 struct gpmc_device_timings *dev_t,
951 bool mux)
952 {
953 u32 temp;
954
955 /* adv_rd_off */
956 temp = dev_t->t_avdp_r;
957 if (mux)
958 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
959 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
960
961 /* oe_on */
962 temp = dev_t->t_oeasu;
963 if (mux)
964 temp = max_t(u32, temp,
965 gpmc_t->adv_rd_off + dev_t->t_aavdh);
966 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
967
968 /* access */
969 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
970 gpmc_t->oe_on + dev_t->t_oe);
971 temp = max_t(u32, temp,
972 gpmc_t->cs_on + dev_t->t_ce);
973 temp = max_t(u32, temp,
974 gpmc_t->adv_on + dev_t->t_aa);
975 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
976
977 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
978 gpmc_t->cs_rd_off = gpmc_t->oe_off;
979
980 /* rd_cycle */
981 temp = max_t(u32, dev_t->t_rd_cycle,
982 gpmc_t->cs_rd_off + dev_t->t_cez_r);
983 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
984 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
985
986 return 0;
987 }
988
989 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
990 struct gpmc_device_timings *dev_t,
991 bool mux)
992 {
993 u32 temp;
994
995 /* adv_wr_off */
996 temp = dev_t->t_avdp_w;
997 if (mux)
998 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
999 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1000
1001 /* wr_data_mux_bus */
1002 temp = dev_t->t_weasu;
1003 if (mux) {
1004 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1005 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1006 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1007 }
1008 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1009
1010 /* we_on */
1011 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1012 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1013 else
1014 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1015
1016 /* we_off */
1017 temp = gpmc_t->we_on + dev_t->t_wpl;
1018 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1019
1020 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1021 dev_t->t_wph);
1022
1023 /* wr_cycle */
1024 temp = max_t(u32, dev_t->t_wr_cycle,
1025 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1026 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1027
1028 return 0;
1029 }
1030
1031 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1032 struct gpmc_device_timings *dev_t)
1033 {
1034 u32 temp;
1035
1036 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1037 gpmc_get_fclk_period();
1038
1039 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1040 dev_t->t_bacc,
1041 gpmc_t->sync_clk);
1042
1043 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1044 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1045
1046 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1047 return 0;
1048
1049 if (dev_t->ce_xdelay)
1050 gpmc_t->bool_timings.cs_extra_delay = true;
1051 if (dev_t->avd_xdelay)
1052 gpmc_t->bool_timings.adv_extra_delay = true;
1053 if (dev_t->oe_xdelay)
1054 gpmc_t->bool_timings.oe_extra_delay = true;
1055 if (dev_t->we_xdelay)
1056 gpmc_t->bool_timings.we_extra_delay = true;
1057
1058 return 0;
1059 }
1060
1061 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1062 struct gpmc_device_timings *dev_t,
1063 bool sync)
1064 {
1065 u32 temp;
1066
1067 /* cs_on */
1068 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1069
1070 /* adv_on */
1071 temp = dev_t->t_avdasu;
1072 if (dev_t->t_ce_avd)
1073 temp = max_t(u32, temp,
1074 gpmc_t->cs_on + dev_t->t_ce_avd);
1075 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1076
1077 if (sync)
1078 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1079
1080 return 0;
1081 }
1082
1083 /* TODO: remove this function once all peripherals are confirmed to
1084 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1085 * has to be modified to handle timings in ps instead of ns
1086 */
1087 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1088 {
1089 t->cs_on /= 1000;
1090 t->cs_rd_off /= 1000;
1091 t->cs_wr_off /= 1000;
1092 t->adv_on /= 1000;
1093 t->adv_rd_off /= 1000;
1094 t->adv_wr_off /= 1000;
1095 t->we_on /= 1000;
1096 t->we_off /= 1000;
1097 t->oe_on /= 1000;
1098 t->oe_off /= 1000;
1099 t->page_burst_access /= 1000;
1100 t->access /= 1000;
1101 t->rd_cycle /= 1000;
1102 t->wr_cycle /= 1000;
1103 t->bus_turnaround /= 1000;
1104 t->cycle2cycle_delay /= 1000;
1105 t->wait_monitoring /= 1000;
1106 t->clk_activation /= 1000;
1107 t->wr_access /= 1000;
1108 t->wr_data_mux_bus /= 1000;
1109 }
1110
1111 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1112 struct gpmc_settings *gpmc_s,
1113 struct gpmc_device_timings *dev_t)
1114 {
1115 bool mux = false, sync = false;
1116
1117 if (gpmc_s) {
1118 mux = gpmc_s->mux_add_data ? true : false;
1119 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1120 }
1121
1122 memset(gpmc_t, 0, sizeof(*gpmc_t));
1123
1124 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1125
1126 if (gpmc_s && gpmc_s->sync_read)
1127 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1128 else
1129 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1130
1131 if (gpmc_s && gpmc_s->sync_write)
1132 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1133 else
1134 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1135
1136 /* TODO: remove, see function definition */
1137 gpmc_convert_ps_to_ns(gpmc_t);
1138
1139 return 0;
1140 }
1141
1142 /**
1143 * gpmc_cs_program_settings - programs non-timing related settings
1144 * @cs: GPMC chip-select to program
1145 * @p: pointer to GPMC settings structure
1146 *
1147 * Programs non-timing related settings for a GPMC chip-select, such as
1148 * bus-width, burst configuration, etc. Function should be called once
1149 * for each chip-select that is being used and must be called before
1150 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1151 * register will be initialised to zero by this function. Returns 0 on
1152 * success and appropriate negative error code on failure.
1153 */
1154 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1155 {
1156 u32 config1;
1157
1158 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1159 pr_err("%s: invalid width %d!", __func__, p->device_width);
1160 return -EINVAL;
1161 }
1162
1163 /* Address-data multiplexing not supported for NAND devices */
1164 if (p->device_nand && p->mux_add_data) {
1165 pr_err("%s: invalid configuration!\n", __func__);
1166 return -EINVAL;
1167 }
1168
1169 if ((p->mux_add_data > GPMC_MUX_AD) ||
1170 ((p->mux_add_data == GPMC_MUX_AAD) &&
1171 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1172 pr_err("%s: invalid multiplex configuration!\n", __func__);
1173 return -EINVAL;
1174 }
1175
1176 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1177 if (p->burst_read || p->burst_write) {
1178 switch (p->burst_len) {
1179 case GPMC_BURST_4:
1180 case GPMC_BURST_8:
1181 case GPMC_BURST_16:
1182 break;
1183 default:
1184 pr_err("%s: invalid page/burst-length (%d)\n",
1185 __func__, p->burst_len);
1186 return -EINVAL;
1187 }
1188 }
1189
1190 if ((p->wait_on_read || p->wait_on_write) &&
1191 (p->wait_pin > gpmc_nr_waitpins)) {
1192 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1193 return -EINVAL;
1194 }
1195
1196 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1197
1198 if (p->sync_read)
1199 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1200 if (p->sync_write)
1201 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1202 if (p->wait_on_read)
1203 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1204 if (p->wait_on_write)
1205 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1206 if (p->wait_on_read || p->wait_on_write)
1207 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1208 if (p->device_nand)
1209 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1210 if (p->mux_add_data)
1211 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1212 if (p->burst_read)
1213 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1214 if (p->burst_write)
1215 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1216 if (p->burst_read || p->burst_write) {
1217 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1218 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1219 }
1220
1221 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1222
1223 return 0;
1224 }
1225
1226 #ifdef CONFIG_OF
1227 static struct of_device_id gpmc_dt_ids[] = {
1228 { .compatible = "ti,omap2420-gpmc" },
1229 { .compatible = "ti,omap2430-gpmc" },
1230 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1231 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1232 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1233 { }
1234 };
1235 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1236
1237 /**
1238 * gpmc_read_settings_dt - read gpmc settings from device-tree
1239 * @np: pointer to device-tree node for a gpmc child device
1240 * @p: pointer to gpmc settings structure
1241 *
1242 * Reads the GPMC settings for a GPMC child device from device-tree and
1243 * stores them in the GPMC settings structure passed. The GPMC settings
1244 * structure is initialised to zero by this function and so any
1245 * previously stored settings will be cleared.
1246 */
1247 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1248 {
1249 memset(p, 0, sizeof(struct gpmc_settings));
1250
1251 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1252 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1253 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1254 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1255
1256 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1257 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1258 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1259 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1260 if (!p->burst_read && !p->burst_write)
1261 pr_warn("%s: page/burst-length set but not used!\n",
1262 __func__);
1263 }
1264
1265 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1266 p->wait_on_read = of_property_read_bool(np,
1267 "gpmc,wait-on-read");
1268 p->wait_on_write = of_property_read_bool(np,
1269 "gpmc,wait-on-write");
1270 if (!p->wait_on_read && !p->wait_on_write)
1271 pr_warn("%s: read/write wait monitoring not enabled!\n",
1272 __func__);
1273 }
1274 }
1275
1276 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1277 struct gpmc_timings *gpmc_t)
1278 {
1279 struct gpmc_bool_timings *p;
1280
1281 if (!np || !gpmc_t)
1282 return;
1283
1284 memset(gpmc_t, 0, sizeof(*gpmc_t));
1285
1286 /* minimum clock period for syncronous mode */
1287 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1288
1289 /* chip select timtings */
1290 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1291 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1292 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1293
1294 /* ADV signal timings */
1295 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1296 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1297 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1298
1299 /* WE signal timings */
1300 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1301 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1302
1303 /* OE signal timings */
1304 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1305 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1306
1307 /* access and cycle timings */
1308 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1309 &gpmc_t->page_burst_access);
1310 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1311 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1312 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1313 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1314 &gpmc_t->bus_turnaround);
1315 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1316 &gpmc_t->cycle2cycle_delay);
1317 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1318 &gpmc_t->wait_monitoring);
1319 of_property_read_u32(np, "gpmc,clk-activation-ns",
1320 &gpmc_t->clk_activation);
1321
1322 /* only applicable to OMAP3+ */
1323 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1324 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1325 &gpmc_t->wr_data_mux_bus);
1326
1327 /* bool timing parameters */
1328 p = &gpmc_t->bool_timings;
1329
1330 p->cycle2cyclediffcsen =
1331 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1332 p->cycle2cyclesamecsen =
1333 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1334 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1335 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1336 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1337 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1338 p->time_para_granularity =
1339 of_property_read_bool(np, "gpmc,time-para-granularity");
1340 }
1341
1342 #ifdef CONFIG_MTD_NAND
1343
1344 static const char * const nand_xfer_types[] = {
1345 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1346 [NAND_OMAP_POLLED] = "polled",
1347 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1348 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1349 };
1350
1351 static int gpmc_probe_nand_child(struct platform_device *pdev,
1352 struct device_node *child)
1353 {
1354 u32 val;
1355 const char *s;
1356 struct gpmc_timings gpmc_t;
1357 struct omap_nand_platform_data *gpmc_nand_data;
1358
1359 if (of_property_read_u32(child, "reg", &val) < 0) {
1360 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1361 child->full_name);
1362 return -ENODEV;
1363 }
1364
1365 gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1366 GFP_KERNEL);
1367 if (!gpmc_nand_data)
1368 return -ENOMEM;
1369
1370 gpmc_nand_data->cs = val;
1371 gpmc_nand_data->of_node = child;
1372
1373 /* Detect availability of ELM module */
1374 gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1375 if (gpmc_nand_data->elm_of_node == NULL)
1376 gpmc_nand_data->elm_of_node =
1377 of_parse_phandle(child, "elm_id", 0);
1378 if (gpmc_nand_data->elm_of_node == NULL)
1379 pr_warn("%s: ti,elm-id property not found\n", __func__);
1380
1381 /* select ecc-scheme for NAND */
1382 if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1383 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1384 return -ENODEV;
1385 }
1386 if (!strcmp(s, "ham1") || !strcmp(s, "sw") ||
1387 !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1388 gpmc_nand_data->ecc_opt =
1389 OMAP_ECC_HAM1_CODE_HW;
1390 else if (!strcmp(s, "bch4"))
1391 if (gpmc_nand_data->elm_of_node)
1392 gpmc_nand_data->ecc_opt =
1393 OMAP_ECC_BCH4_CODE_HW;
1394 else
1395 gpmc_nand_data->ecc_opt =
1396 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1397 else if (!strcmp(s, "bch8"))
1398 if (gpmc_nand_data->elm_of_node)
1399 gpmc_nand_data->ecc_opt =
1400 OMAP_ECC_BCH8_CODE_HW;
1401 else
1402 gpmc_nand_data->ecc_opt =
1403 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1404 else
1405 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
1406
1407 /* select data transfer mode for NAND controller */
1408 if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1409 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1410 if (!strcasecmp(s, nand_xfer_types[val])) {
1411 gpmc_nand_data->xfer_type = val;
1412 break;
1413 }
1414
1415 val = of_get_nand_bus_width(child);
1416 if (val == 16)
1417 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1418
1419 gpmc_read_timings_dt(child, &gpmc_t);
1420 gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1421
1422 return 0;
1423 }
1424 #else
1425 static int gpmc_probe_nand_child(struct platform_device *pdev,
1426 struct device_node *child)
1427 {
1428 return 0;
1429 }
1430 #endif
1431
1432 #ifdef CONFIG_MTD_ONENAND
1433 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1434 struct device_node *child)
1435 {
1436 u32 val;
1437 struct omap_onenand_platform_data *gpmc_onenand_data;
1438
1439 if (of_property_read_u32(child, "reg", &val) < 0) {
1440 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1441 child->full_name);
1442 return -ENODEV;
1443 }
1444
1445 gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1446 GFP_KERNEL);
1447 if (!gpmc_onenand_data)
1448 return -ENOMEM;
1449
1450 gpmc_onenand_data->cs = val;
1451 gpmc_onenand_data->of_node = child;
1452 gpmc_onenand_data->dma_channel = -1;
1453
1454 if (!of_property_read_u32(child, "dma-channel", &val))
1455 gpmc_onenand_data->dma_channel = val;
1456
1457 gpmc_onenand_init(gpmc_onenand_data);
1458
1459 return 0;
1460 }
1461 #else
1462 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1463 struct device_node *child)
1464 {
1465 return 0;
1466 }
1467 #endif
1468
1469 /**
1470 * gpmc_probe_generic_child - configures the gpmc for a child device
1471 * @pdev: pointer to gpmc platform device
1472 * @child: pointer to device-tree node for child device
1473 *
1474 * Allocates and configures a GPMC chip-select for a child device.
1475 * Returns 0 on success and appropriate negative error code on failure.
1476 */
1477 static int gpmc_probe_generic_child(struct platform_device *pdev,
1478 struct device_node *child)
1479 {
1480 struct gpmc_settings gpmc_s;
1481 struct gpmc_timings gpmc_t;
1482 struct resource res;
1483 unsigned long base;
1484 int ret, cs;
1485
1486 if (of_property_read_u32(child, "reg", &cs) < 0) {
1487 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1488 child->full_name);
1489 return -ENODEV;
1490 }
1491
1492 if (of_address_to_resource(child, 0, &res) < 0) {
1493 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1494 child->full_name);
1495 return -ENODEV;
1496 }
1497
1498 ret = gpmc_cs_request(cs, resource_size(&res), &base);
1499 if (ret < 0) {
1500 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1501 return ret;
1502 }
1503
1504 /*
1505 * For some GPMC devices we still need to rely on the bootloader
1506 * timings because the devices can be connected via FPGA. So far
1507 * the list is smc91x on the omap2 SDP boards, and 8250 on zooms.
1508 * REVISIT: Add timing support from slls644g.pdf and from the
1509 * lan91c96 manual.
1510 */
1511 if (of_device_is_compatible(child, "ns16550a") ||
1512 of_device_is_compatible(child, "smsc,lan91c94") ||
1513 of_device_is_compatible(child, "smsc,lan91c111")) {
1514 dev_warn(&pdev->dev,
1515 "%s using bootloader timings on CS%d\n",
1516 child->name, cs);
1517 goto no_timings;
1518 }
1519
1520 /*
1521 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1522 * location in the gpmc address space. When booting with
1523 * device-tree we want the NOR flash to be mapped to the
1524 * location specified in the device-tree blob. So remap the
1525 * CS to this location. Once DT migration is complete should
1526 * just make gpmc_cs_request() map a specific address.
1527 */
1528 ret = gpmc_cs_remap(cs, res.start);
1529 if (ret < 0) {
1530 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1531 cs, &res.start);
1532 goto err;
1533 }
1534
1535 gpmc_read_settings_dt(child, &gpmc_s);
1536
1537 ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
1538 if (ret < 0)
1539 goto err;
1540
1541 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1542 if (ret < 0)
1543 goto err;
1544
1545 gpmc_read_timings_dt(child, &gpmc_t);
1546 gpmc_cs_set_timings(cs, &gpmc_t);
1547
1548 no_timings:
1549 if (of_platform_device_create(child, NULL, &pdev->dev))
1550 return 0;
1551
1552 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
1553 ret = -ENODEV;
1554
1555 err:
1556 gpmc_cs_free(cs);
1557
1558 return ret;
1559 }
1560
1561 static int gpmc_probe_dt(struct platform_device *pdev)
1562 {
1563 int ret;
1564 struct device_node *child;
1565 const struct of_device_id *of_id =
1566 of_match_device(gpmc_dt_ids, &pdev->dev);
1567
1568 if (!of_id)
1569 return 0;
1570
1571 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
1572 &gpmc_cs_num);
1573 if (ret < 0) {
1574 pr_err("%s: number of chip-selects not defined\n", __func__);
1575 return ret;
1576 } else if (gpmc_cs_num < 1) {
1577 pr_err("%s: all chip-selects are disabled\n", __func__);
1578 return -EINVAL;
1579 } else if (gpmc_cs_num > GPMC_CS_NUM) {
1580 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1581 __func__, GPMC_CS_NUM);
1582 return -EINVAL;
1583 }
1584
1585 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
1586 &gpmc_nr_waitpins);
1587 if (ret < 0) {
1588 pr_err("%s: number of wait pins not found!\n", __func__);
1589 return ret;
1590 }
1591
1592 for_each_child_of_node(pdev->dev.of_node, child) {
1593
1594 if (!child->name)
1595 continue;
1596
1597 if (of_node_cmp(child->name, "nand") == 0)
1598 ret = gpmc_probe_nand_child(pdev, child);
1599 else if (of_node_cmp(child->name, "onenand") == 0)
1600 ret = gpmc_probe_onenand_child(pdev, child);
1601 else if (of_node_cmp(child->name, "ethernet") == 0 ||
1602 of_node_cmp(child->name, "nor") == 0 ||
1603 of_node_cmp(child->name, "uart") == 0)
1604 ret = gpmc_probe_generic_child(pdev, child);
1605
1606 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
1607 __func__, child->full_name))
1608 of_node_put(child);
1609 }
1610
1611 return 0;
1612 }
1613 #else
1614 static int gpmc_probe_dt(struct platform_device *pdev)
1615 {
1616 return 0;
1617 }
1618 #endif
1619
1620 static int gpmc_probe(struct platform_device *pdev)
1621 {
1622 int rc;
1623 u32 l;
1624 struct resource *res;
1625
1626 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1627 if (res == NULL)
1628 return -ENOENT;
1629
1630 phys_base = res->start;
1631 mem_size = resource_size(res);
1632
1633 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
1634 if (IS_ERR(gpmc_base))
1635 return PTR_ERR(gpmc_base);
1636
1637 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1638 if (res == NULL)
1639 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
1640 else
1641 gpmc_irq = res->start;
1642
1643 gpmc_l3_clk = clk_get(&pdev->dev, "fck");
1644 if (IS_ERR(gpmc_l3_clk)) {
1645 dev_err(&pdev->dev, "error: clk_get\n");
1646 gpmc_irq = 0;
1647 return PTR_ERR(gpmc_l3_clk);
1648 }
1649
1650 pm_runtime_enable(&pdev->dev);
1651 pm_runtime_get_sync(&pdev->dev);
1652
1653 gpmc_dev = &pdev->dev;
1654
1655 l = gpmc_read_reg(GPMC_REVISION);
1656
1657 /*
1658 * FIXME: Once device-tree migration is complete the below flags
1659 * should be populated based upon the device-tree compatible
1660 * string. For now just use the IP revision. OMAP3+ devices have
1661 * the wr_access and wr_data_mux_bus register fields. OMAP4+
1662 * devices support the addr-addr-data multiplex protocol.
1663 *
1664 * GPMC IP revisions:
1665 * - OMAP24xx = 2.0
1666 * - OMAP3xxx = 5.0
1667 * - OMAP44xx/54xx/AM335x = 6.0
1668 */
1669 if (GPMC_REVISION_MAJOR(l) > 0x4)
1670 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
1671 if (GPMC_REVISION_MAJOR(l) > 0x5)
1672 gpmc_capability |= GPMC_HAS_MUX_AAD;
1673 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1674 GPMC_REVISION_MINOR(l));
1675
1676 gpmc_mem_init();
1677
1678 if (gpmc_setup_irq() < 0)
1679 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1680
1681 /* Now the GPMC is initialised, unreserve the chip-selects */
1682 gpmc_cs_map = 0;
1683
1684 if (!pdev->dev.of_node) {
1685 gpmc_cs_num = GPMC_CS_NUM;
1686 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
1687 }
1688
1689 rc = gpmc_probe_dt(pdev);
1690 if (rc < 0) {
1691 pm_runtime_put_sync(&pdev->dev);
1692 clk_put(gpmc_l3_clk);
1693 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1694 return rc;
1695 }
1696
1697 return 0;
1698 }
1699
1700 static int gpmc_remove(struct platform_device *pdev)
1701 {
1702 gpmc_free_irq();
1703 gpmc_mem_exit();
1704 pm_runtime_put_sync(&pdev->dev);
1705 pm_runtime_disable(&pdev->dev);
1706 gpmc_dev = NULL;
1707 return 0;
1708 }
1709
1710 #ifdef CONFIG_PM_SLEEP
1711 static int gpmc_suspend(struct device *dev)
1712 {
1713 omap3_gpmc_save_context();
1714 pm_runtime_put_sync(dev);
1715 return 0;
1716 }
1717
1718 static int gpmc_resume(struct device *dev)
1719 {
1720 pm_runtime_get_sync(dev);
1721 omap3_gpmc_restore_context();
1722 return 0;
1723 }
1724 #endif
1725
1726 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
1727
1728 static struct platform_driver gpmc_driver = {
1729 .probe = gpmc_probe,
1730 .remove = gpmc_remove,
1731 .driver = {
1732 .name = DEVICE_NAME,
1733 .owner = THIS_MODULE,
1734 .of_match_table = of_match_ptr(gpmc_dt_ids),
1735 .pm = &gpmc_pm_ops,
1736 },
1737 };
1738
1739 static __init int gpmc_init(void)
1740 {
1741 return platform_driver_register(&gpmc_driver);
1742 }
1743
1744 static __exit void gpmc_exit(void)
1745 {
1746 platform_driver_unregister(&gpmc_driver);
1747
1748 }
1749
1750 omap_postcore_initcall(gpmc_init);
1751 module_exit(gpmc_exit);
1752
1753 static int __init omap_gpmc_init(void)
1754 {
1755 struct omap_hwmod *oh;
1756 struct platform_device *pdev;
1757 char *oh_name = "gpmc";
1758
1759 /*
1760 * if the board boots up with a populated DT, do not
1761 * manually add the device from this initcall
1762 */
1763 if (of_have_populated_dt())
1764 return -ENODEV;
1765
1766 oh = omap_hwmod_lookup(oh_name);
1767 if (!oh) {
1768 pr_err("Could not look up %s\n", oh_name);
1769 return -ENODEV;
1770 }
1771
1772 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
1773 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1774
1775 return PTR_RET(pdev);
1776 }
1777 omap_postcore_initcall(omap_gpmc_init);
1778
1779 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1780 {
1781 int i;
1782 u32 regval;
1783
1784 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1785
1786 if (!regval)
1787 return IRQ_NONE;
1788
1789 for (i = 0; i < GPMC_NR_IRQ; i++)
1790 if (regval & gpmc_client_irq[i].bitmask)
1791 generic_handle_irq(gpmc_client_irq[i].irq);
1792
1793 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1794
1795 return IRQ_HANDLED;
1796 }
1797
1798 static struct omap3_gpmc_regs gpmc_context;
1799
1800 void omap3_gpmc_save_context(void)
1801 {
1802 int i;
1803
1804 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
1805 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
1806 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
1807 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
1808 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
1809 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
1810 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
1811 for (i = 0; i < gpmc_cs_num; i++) {
1812 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
1813 if (gpmc_context.cs_context[i].is_valid) {
1814 gpmc_context.cs_context[i].config1 =
1815 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
1816 gpmc_context.cs_context[i].config2 =
1817 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
1818 gpmc_context.cs_context[i].config3 =
1819 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
1820 gpmc_context.cs_context[i].config4 =
1821 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
1822 gpmc_context.cs_context[i].config5 =
1823 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
1824 gpmc_context.cs_context[i].config6 =
1825 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
1826 gpmc_context.cs_context[i].config7 =
1827 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
1828 }
1829 }
1830 }
1831
1832 void omap3_gpmc_restore_context(void)
1833 {
1834 int i;
1835
1836 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
1837 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
1838 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
1839 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
1840 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
1841 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
1842 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
1843 for (i = 0; i < gpmc_cs_num; i++) {
1844 if (gpmc_context.cs_context[i].is_valid) {
1845 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
1846 gpmc_context.cs_context[i].config1);
1847 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
1848 gpmc_context.cs_context[i].config2);
1849 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
1850 gpmc_context.cs_context[i].config3);
1851 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
1852 gpmc_context.cs_context[i].config4);
1853 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
1854 gpmc_context.cs_context[i].config5);
1855 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
1856 gpmc_context.cs_context[i].config6);
1857 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
1858 gpmc_context.cs_context[i].config7);
1859 }
1860 }
1861 }
Linux with added FPC-III support